Data Sheet

Cost-Effective I/O 8-Bit OTP MCU
HT48R002/HT48R003
Revision: V1.10
Date: ���������������
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Table of Contents
Features............................................................................................................. 5
CPU Features.......................................................................................................................... 5
Peripheral Features.................................................................................................................. 5
General Description ......................................................................................... 5
Selection Table.................................................................................................. 6
Block Diagram................................................................................................... 6
Pin Assignment................................................................................................. 6
Pin Description................................................................................................. 7
HT48R002................................................................................................................................ 7
HT48R003................................................................................................................................ 8
Absolute Maximum Ratings............................................................................. 8
D.C. Characteristics.......................................................................................... 9
A.C. Characteristics.......................................................................................... 9
Power-on Reset Characteristics.................................................................... 10
System Architecture....................................................................................... 10
Clocking and Pipelining.......................................................................................................... 10
Program Counter – PC............................................................................................................11
Stack...................................................................................................................................... 12
Arithmetic and Logic Unit – ALU............................................................................................ 12
Program Memory............................................................................................ 13
Structure................................................................................................................................. 13
Special Vectors...................................................................................................................... 13
Look-up Table......................................................................................................................... 14
Table Program Example......................................................................................................... 14
RAM Data Memory.......................................................................................... 16
Structure................................................................................................................................. 16
Special Purpose Data Memory.............................................................................................. 17
Special Function Registers............................................................................ 18
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 18
Memory Pointers – MP0, MP1............................................................................................... 18
Accumulator – ACC................................................................................................................ 19
Program Counter Low Register – PCL................................................................................... 19
Status Register – STATUS..................................................................................................... 19
System Control Registers – CTRL0, CTRL1.......................................................................... 21
Oscillator......................................................................................................... 22
System Oscillator Overview................................................................................................... 22
System Clock Configurations................................................................................................. 22
Internal RC Oscillator – HIRC................................................................................................ 22
Internal 12kHz Oscillator – LIRC............................................................................................ 22
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Power Down Mode and Wake-up................................................................... 23
Power Down Mode................................................................................................................. 23
Entering the Power Down Mode............................................................................................ 23
Standby Current Considerations............................................................................................ 23
Wake-up................................................................................................................................. 24
Watchdog Timer.............................................................................................. 25
Watchdog Timer Clock Source............................................................................................... 25
Watchdog Timer Control Registers........................................................................................ 25
Watchdog Timer Operation.................................................................................................... 26
Reset and Initialization................................................................................... 27
Reset Functions..................................................................................................................... 27
Reset Initial Conditions.......................................................................................................... 30
Input/Output Ports.......................................................................................... 33
I/O Register List..................................................................................................................... 33
Pull-high Resistors................................................................................................................. 34
Port A Wake-up...................................................................................................................... 34
I/O Port Control Registers...................................................................................................... 35
Pin-shared Functions............................................................................................................. 36
I/O Pin Structures................................................................................................................... 36
Programming Considerations................................................................................................. 37
Timer/Event Counter...................................................................................... 38
Configuring the Timer/Event Counter Input Clock Source..................................................... 38
Timer Register – TMR0.......................................................................................................... 39
Timer Control Register – TMR0C........................................................................................... 39
Timer Mode............................................................................................................................ 40
Event Counter Mode.............................................................................................................. 41
Pulse Width Capture Mode.................................................................................................... 42
Prescaler................................................................................................................................ 43
PFD Function (for HT48R003)............................................................................................... 43
I/O Interfacing......................................................................................................................... 43
Programming Considerations................................................................................................. 44
Timer Program Example........................................................................................................ 45
Interrupts......................................................................................................... 46
Interrupt Register................................................................................................................... 46
Interrupt Operation................................................................................................................. 47
Interrupt Priority...................................................................................................................... 48
External Interrupt.................................................................................................................... 49
Timer/Event Counter Interrupt................................................................................................ 49
Interrupt Wake-up Function.................................................................................................... 49
Programming Considerations................................................................................................. 50
Application Circuits........................................................................................ 50
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Instruction Set................................................................................................. 51
Introduction............................................................................................................................ 51
Instruction Timing................................................................................................................... 51
Moving and Transferring Data................................................................................................ 51
Arithmetic Operations............................................................................................................. 51
Logical and Rotate Operation................................................................................................ 52
Branches and Control Transfer.............................................................................................. 52
Bit Operations........................................................................................................................ 52
Table Read Operations.......................................................................................................... 52
Other Operations.................................................................................................................... 52
Instruction Set Summary............................................................................... 53
Table Conventions.................................................................................................................. 53
Instruction Definition...................................................................................... 55
Package Information...................................................................................... 64
8-pin DIP (300mil) Outline Dimensions.................................................................................. 65
8-pin SOP (150mil) Outline Dimensions................................................................................ 66
10-pin MSOP Outline Dimensions......................................................................................... 67
16-pin DIP (300mil) Outline Dimensions................................................................................ 68
16-pin NSOP (150mil) Outline Dimensions............................................................................ 70
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Note that 8-pin MCU package types are not marketed in the following
countries: USA, UK, Germany, The Netherlands, France and Italy.
Features
CPU Features
• Operating voltage : fSYS=8MHz: 2.3V~5.5V
• Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V
• Power down and wake-up functions to reduce power consumption
• Two oscillators:
♦♦
Internal high speed RC -- HIRC
♦♦
Internal low speed RC -- LIRC
• Fully integrated internal 8MHz oscillator requires no external components
• All instructions executed in one or two instruction cycles
• Table read instruction
• 61 powerful instructions
• 2-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Program Memory: 1K×14
• RAM Data Memory: 64×8
• Watchdog Timer function
• Up to 14 bidirectional I/O lines
• External interrupt pin shared with I/O pin
• One 8-bit programmable Timer/Event Counter with overflow interrupt and prescaler
• Low voltage reset function
• Package types: 8-pin DIP/SOP, 10-pin MSOP and 16-pin DIP/NSOP
• Programmable Frequency Divider – PFD
General Description
The devices are 8-bit high performance RISC architecture microcontroller devices specifically
designed for the I/O control. The advantages of low power consumption, I/O flexibility, timer
functions, oscillator options, HALT and wake-up functions, watchdog timer, as well as low cost,
enhance the versatility of these devices to suit for a wide range of the I/O control application
possibilities such as industrial control, consumer products and subsystem controllers, etc.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Selection Table
Part No.
Operating
Voltage
HIRC 8-bit Interrupt
PFD Stack
(MHz) Timer Ext. Int.
ROM
RAM
I/O
Package
HT48R002 2.3V~5.5V 1K×14
64×8
8
8
1
1
1
×
2
8DIP/SOP
10MSOP
HT48R003 2.3V~5.5V 1K×14
64×8
14
8
1
1
1
√
2
16DIP/NSOP
Block Diagram
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        
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Note: Only the HT48R003 has a PFD function.
Pin Assignment
VDD
1
8
VSS
P�6
�
7
P�0
P�5
3
6
P�1/TMR
5
P��/INT
P�7/RES
�
HT48R002
8 DIP-A/SOP-A
1
16
P�5
PC5
�
15
P�6/PFD
PC�
3
1�
P�7/RES
VDD
1
10
VSS
PC3
�
13
P�6
�
9
P�0
VDD
PC�
5
1�
VSS
PC1
6
11
P�0
PC0
P�3
7
10
P�1/TMR
9
P��/INT
P�5
3
8
P�1/TMR
P�7/RES
�
7
P��/INT
P��
5
6
P�3
8
HT48R003
16 DIP-A/NSOP-A
HT48R002
10 MSOP-A
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Pin Description
HT48R002
Pin Name
Function
OPT
I/T
PA0
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA1
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TMR
TMR0C
ST
PA2
PAPU
PAWU
ST
INT
INTC0
CTRL1
ST
PA3~PA4
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PA5
PA5
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA6
PA6
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up.
NMOS General purpose I/O
PA0
PA1/TMR
PA2/INT
PA3~PA4
O/T
­—
Description
Timer/Event counter 0 input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
­—
External interrupt input
PA7
PAPU
ST
RES
—
ST
—
Reset input
VDD
VDD
—
PWR
—
Power supply
VSS
VSS
—
PWR
—
Ground
PA7/RES
Note: OPT: Optional by register option
I/T: Input type
O/T: Output type;
ST: Schmitt Trigger input;
CMOS: CMOS output;
NMOS: NMOS output;
PWR: Power
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
HT48R003
Pin Name
PA0
PA1/TMR
Function
OPT
I/T
PA0
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PA1
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TMR
TMR0C
ST
PA2
PAPU
PAWU
ST
INT
INTC0
CTRL1
ST
PA3~PA4
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PA5
PAPU
PAWU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS General purpose I/O. Register enabled pull-up.
PA2/INT
PA3~PA4
PA5
PA6/PFD
PA7/RES
PC0~PC5
O/T
­—
Description
Timer/Event counter 0 input
CMOS General purpose I/O. Register enabled pull-up and wake-up.
­—
External interrupt input
PA6
PAPU
ST
PFD
CTRL0
—
CMOS PFD output
PA7
PAPU
ST
NMOS General purpose I/O
RES
—
ST
—
Reset input
PC0~PC5
PCPU
ST
VDD
VDD
—
PWR
CMOS General purpose I/O. Register enabled pull-up.
—
Power supply
VSS
VSS
—
PWR
—
Ground
Note: OPT: Optional by register option
I/T: Input type;
O/T: Output type;
ST: Schmitt Trigger input;
CMOS: CMOS output;
NMOS: NMOS output
PWR: Power
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 125˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
D.C. Characteristics
Ta=25°C
Symbol
VDD
IDD1
ISTB1
Parameter
Operating Voltage (HIRC)
Operating Current (HIRC on)
Standby Current (LIRC on)
Test Conditions
Conditions
VDD
—
3V
5V
3V
5V
3V
fSYS=8MHz
No load, fSYS=8MHz
No load, system HALT
Min.
Typ.
Max.
Unit
2.3
—
5.5
V
—
1.2
1.8
mA
—
2.4
3.6
mA
—
—
5
μA
—
—
10
μA
—
—
1
μA
—
—
2
μA
0
—
1.5
V
0
—
0.2VDD
V
3.5
—
5
V
ISTB2
Standby Current (LIRC off)
VIL1
Input Low Voltage for I/O Ports,
TMR and INT pin
5V
VIH1
Input High Voltage for I/O Ports,
TMR and INT pin
5V
0.8VDD
—
VDD
V
VIL2
Input low voltage (RES)
—
—
0
—
0.4VDD
V
VIH2
Input high voltage (RES)
—
—
0.9VDD
—
VDD
V
VLVR
Low Voltage Reset Voltage
—
2.0
2.1
2.2
V
-2.5
-5
—
mA
IOH
I/O source current (PA)
IOL1
I/O sink current (PA)
IOL2
PA7 sink current
RPH
Pull-high Resistance for I/O Ports
5V
No load, system HALT
—
—
—
—
3V
5V
3V
5V
5V
LVR Enable, 2.1V
VOH=0.9VDD
VOL=0.1VDD
-5
-11
—
mA
7.5
15
—
mA
15
30
—
mA
2
3
—
mA
VOL=0.1VDD
3V
—
20
60
100
kΩ
5V
—
10
30
50
kΩ
A.C. Characteristics
Ta=25°C
Symbol
fCPU
fHIRC
Parameter
Operating Clock
System Clock (HIRC)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC
Watchdog oscillator period
tRES
Test Conditions
Conditions
VDD
—
2.3V~5.5V
Min.
Typ.
Max.
Unit
8
8
8
MHz
3/5V
—
-2%
8
+2%
MHz
3/5V
Ta=0°~70°C
-5%
8
+5%
MHz
3.0~5.5V Ta=0°~70°C
-8%
8
+8%
MHz
3.0~5.5V Ta=-40°~85°C
-12%
8
+12%
MHz
3.3~5.5V
—
0
—
8
MHz
3V
—
45
90
180
μs
5V
—
32
65
130
μs
External reset low pulse width
—
—
1
—
—
μs
tSST
System start-up timer period
—
—
16
—
tSYS
tLVR
Low Voltage Width to Reset
—
—
0.25
1
2
ms
tRSTD
System Reset Delay Time (All Reset)
—
—
25
50
100
ms
wake-up from halt
Note: 1. tSYS=1/fSYS
2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Power-on Reset Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRVDD
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to Ensure
Power-on Reset
—
—
1
—
—
ms
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the
exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations
of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and
can be directly or indirectly addressed. The simple addressing methods of these registers along
with additional architectural features ensure that a minimum of external components is required to
provide a functional I/O system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from HIRC oscillator is subdivided into four internally generated
non-overlapping clocks, T1~T4.The Program Counter is incremented at the beginning of the T1
clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the
decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle.
Although the fetching and execution of instructions takes place in consecutive instruction cycles, the
pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions where the contents of the Program Counter
are changed, such as subroutine calls or jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two instruction cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to firstly obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
 System Clocking and Pipelining
  €
€
 ­ €   
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Instruction Fetching
Program Counter – PC
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. It must be noted that only the lower 8 bits, known as the
Program Counter Low Register, are directly addressable by user.
When executing instructions requiring jumping to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc, the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is
obtained.
Program Counter
High Byte of Program
Low Byte of Program
PC9, PC8
PCL7~PCL0
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly. However, as only this low byte
is available for manipulation, the jumps are limited in the present page of memory, which have
256 locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. The lower byte of the Program Counter is fully accessible under program control.
Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch.
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is organized into 2 levels and neither part of the data nor part of the program space,
and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is
neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of
the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer will point to the top of the stack.
P ro g ra m
T o p o f S ta c k
S ta c k
P o in te r
S ta c k L e v e l 1
S ta c k L e v e l 2
B o tto m
C o u n te r
o f S ta c k
P ro g ra m
M e m o ry
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but
the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,
the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use
the structure more easily. However, when the stack is full, a CALL subroutine instruction can still
be executed which will result in a stack overflow. Precautions should be taken to avoid such cases
which might cause unpredictable program branching.
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI.
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Program Memory
The Program Memory is the location where the user code or program is stored. The device is
supplied with One-Time Programmable, OTP, memory where users can program their application
code into the device. By using the appropriate programming tools, OTP devices offer users the
flexibility to freely develop their applications which may be useful during debug or for products
requiring frequent upgrades or program changes.
Structure
The Program Memory has a capacity of 1k×14 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries information. Table
data which can be set in any location within the Program Memory is addressed by separate table
pointer registers.
     Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts.
Reset Vector
This vector is reserved for use by the device reset for program initialization. After a device reset is
initiated, the program will jump to this location and begin execution.
External interrupt vector
This vector is used by the external interrupt. If the external interrupt pin on the device receives an
edge transition, the program will jump to this location and begin execution if the external interrupt is
enabled and the stack is not full. The external interrupt active edge transition type, whether high to
low, low to high or both is specified in the CTRL1 register.
Timer/Event counter 0 interrupt vector
This internal vector is used by the Timer/Event Counter. If a Timer/Event Counter overflow occurs,
the program will jump to its respective location and begin execution if the associated Timer/Event
Counter 0 interrupt is enabled and the stack is not full.
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be set by placing the address
of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total
address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory
using the “TABRDC [m]” or “TABRDL [m]” instructions, respectively. When the instruction is
executed, the lower order table byte from the Program Memory will be transferred to the user
defined Data Memory register [m] as specified in the instruction. The higher order table data byte
from the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.
     Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved from
the device. This example uses raw table data located in the last page which is stored there using the
ORG statement. The value at this ORG statement is “0300H” which refers to the start address of the
last page within the 1K Program Memory of the microcontroller.
The table pointer is set here to have an initial value of “06H”. This will ensure that the first data read
from the data table will be at the Program Memory address “0306H” or 6 locations after the start of
the last page. Note that the value for the table pointer is referenced to the first address of the present
page if the “TABRDC [m]” instruction is being used. The high byte of the table data which in this
case is equal to zero will be transferred to the TBLH register automatically when the “TABRDL [m]”
instruction is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use the table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Instruction
Table Location Bits
b9
b8
b7
TABRDC [m]
@9
@8
@7
TABRDL [m]
1
1
@7
b6
b5
b4
b3
b2
b1
b0
@6
@5
@4
@3
@2
@1
@0
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: PC9~PC8: Current program Counter bits
@[email protected]: Table Pointer TBLP bits
Table Read Program Example
tempreg1 db? ; temporary register #1
tempreg2 db? ; temporary register #2
:
:
mov a,06h ; initialize table pointer - note that this address is referenced
mov tblp, a ; to the last page or present page
:
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempreg1
; data at prog. memory address “0306H” transferred to tempreg1 and
; TBLH
dec tblp ; reduce value of table pointer by one
tabrdl tempreg2 ; transfers value in table referenced by table pointer; to tempreg2
; data at prog. memory address “0305H” transferred to
; tempreg2 and TBLH
; in this example the data “1AH” is transferred to tempreg1 and
; data “0FH” to register tempreg2
; the value “00H” will be transferred to the high byte register TBLH
:
:
org 0300h ; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
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RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM where special function registers are
located. These registers have fixed locations and are necessary for correct operation of the device.
Many of these registers can be read from and written to directly under program control, however,
some remain protected from user manipulation. The second area of Data Memory is reserved for
general purpose use. All locations within this area are read and write accessible under program
control.
The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are
located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of
each memory section is dictated by the type of microcontroller chosen. The start address of the Data
Memory for all devices is the address “00H”.
All microcontroller programs require an area of read/write memory where temporary data can be
stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose
Data Memory. This area of Data Memory is fully accessible by the user program for both reading
and writing operations. By using the “SET [m].i” and “CLR [m].i” instructions individual bits can
be set or reset under program control giving the user a large range of flexibility for bit manipulation
in the Data Memory.
 Data Memory Structure
Note: Most of the Data Memory bits can be directly manipulated using the “SET [m].i” and
“CLR [m].i” with the exception of a few dedicated bits. The Data Memory can also be
accessed via the memory pointer registers.
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Special Purpose Data Memory
This area of Data Memory is where registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are both readable and writeable but some are
protected and are readable only, the details of which are located under the relevant Special Function
Register section. Note that for locations that are unused, any read instruction to these addresses will
return the value “00H”.
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          ­   ­   Special Purpose Data Memory
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Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in
the Data Memory area. These registers ensure correct operation of internal functions such as timer,
interrupts, etc., as well as external functions such as I/O data control. The locations of these registers
within the Data Memory begin at the address of “00H”. Any unused Data Memory locations
between these special function registers and the point where the General Purpose Memory begins is
reserved and attempting to read data from these locations will return a value of “00H”.
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation is using these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on
the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. As
the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing
Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in
no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to indirectly address and track data. When any
operation to the relevant Indirect Addressing Registers is carried out, the actual address which the
microcontroller is directed to is the address specified by the related Memory Pointer. Note that for
this device, the Memory Pointers, MP0 and MP1, are both 8-bit registers and used to access the Data
Memory together with their corresponding indirect addressing registers IAR0 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data . section ‘data’
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code. section at 0 code
org 00h
start:
mov a,04h;
mov block,a
mov a,offset adres1 ;
mov mp0,a ;
loop:
clr IAR0 ;
inc mp0;
sdz block ;
jmp loop
continue:
set size of block
Accumulator loaded with first RAM address
set memory pointer with first RAM address
clear the data at address defined by MP0
increment memory pointer
check if last memory location has been cleared
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
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Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however as the register is only 8-bit wide only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and
if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Note
that bits 0~3 of the STATUS register are both readable and writeable bits.
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STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
x
x
x
x
“x”: unknown
Bit 7~6
Unimplemented, read as “0”
Bit 5TO: Watchdog Time-Out flag
0: After power up or executing the “CLR WDT” or “HALT” instruction
1: A watchdog time-out occurred.
Bit 4PDF: Power down flag
0: After power up or executing the “CLR WDT” instruction
1: By executing the “HALT” instruction
Bit 3OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0C: Carry flag
0: No carry out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
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System Control Registers – CTRL0, CTRL1
These registers are used to provide control internal functions such as the PFD function and external
interrupt edge trigger type selection.
CTRL0 Register (for HT48R003)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
PFDC
—
—
R/W
—
—
—
—
—
R/W
—
—
POR
—
—
—
—
—
0
—
—
Bit 7~3
Unimplemented, read as "0"
Bit 2PFDC: PA6/PFD selection
0: PA6
1: PFD
Bit 1~0
Unimplemented, read as "0"
CTRL1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
INTES1
INTES0
—
—
—
—
—
—
R/W
R/W
R/W
—
—
—
—
—
—
POR
1
0
—
—
—
—
—
—
Bit 7, 6
INTES1, INTES0: External interrupt edge type selection
00: Disable
01: Rising edge trigger
10: Falling edge trigger
11: Dual edge trigger
Bit 5~0
Unimplemented, read as "0"
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimization can be achieved in terms of speed and power saving.
System Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer function and Timer/Event counter.
Type
Name
Freq.
Internal High Speed RC
HIRC
8MHz
Internal Low Speed RC
LIRC
12kHz
Oscillator Types
System Clock Configurations
There is one system oscillator implemented in these devices, internal 8MHz RC, HIRC. Also there
is an internal 12kHz RC oscillator LIRC used as the clock source for the WDT function and Timer/
Event counter. More details are described in the accompany sections.
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has the frequency of 8MHz .Device trimming during the manufacturing
process and the inclusion of internal frequency compensation circuit is used to ensure that the
influence of the power supply voltage, temperature and process variations on the oscillation
frequency are minimized. Note that this internal system clock option requires no external pins for its
operation. Refer to the A.C. Characteristics for more frequency accuracy details.
Internal 12kHz Oscillator – LIRC
The LIRC is a fully self-contained free running on-chip RC oscillator with a typical frequency of
12kHz at 5V, requiring no external components for its implementation. When the device enters the
Sleep Mode, the system clock will stop running but the LIRC oscillator continues to free-run and
to keep the watchdog active. However, to preserve power in certain applications the LIRC can be
disabled by disabling the WDT function and Timer/Event counter in the halt mode.
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Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the
HALT Mode or Sleep Mode. When the devices enter this mode, the normal operating current will
be reduced to an extremely low standby current level. This occurs because when the devices enter
the Power Down Mode, the system oscillator is stopped which reduces the power consumption to
extremely low levels. However, as the devices maintain their present internal condition, they can
be woken up at a later stage and continue running, without requiring a full reset. This feature is
extremely important in application areas where the MCUs must have their power supply constantly
maintained to keep the devices in a known condition.
Entering the Power Down Mode
There is only one way for the device to enter the Power Down Mode and that is to execute the
“HALT” instruction in the application program. When this instruction is executed, the following will
occur:
• The system oscillator will stop running and the application program will stop at the “HALT”
instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Standby Current Considerations
As the main reason for entering the Sleep Mode is to keep the current consumption of the
MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are
other considerations which must also be taken into account by the circuit designer if the power
consumption is to be minimized.
Special attention must be made to the I/O pins on the device. All high-impedance input pins must
be connected to either a fixed high or low level as any floating input pins could create internal
oscillations and result in increased current consumption. Care must also be taken with the loads,
which are connected to I/O pins, which are set as outputs. These should be placed in a condition in
which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
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Wake-up
After the system enters the Sleep Mode, it can be woken up from one of various sources listed as
follows:
• An external reset
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Although both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog Timer instructions and is set when executing the
“HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer, the other flags remain in their original status.
Pins PA0~PA2, PA5 can be set via the PAWU register to permit a negative transition on the pin
to wake-up the system. When a PA0~PA2 or PA5 pin wake-up occurs, the program will resume
execution at the instruction following the “HALT” instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where
the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the
program will resume execution at the instruction following the “HALT” instruction. In this situation,
the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced
later when the related interrupt is finally enabled or when a stack level becomes free. The other
situation is where the related interrupt is enabled and the stack is not full, in which case the regular
interrupt response takes place. If an interrupt request flag is set high before entering the Sleep Mode,
the wake-up function of the related interrupt will be ignored.
No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a
time delay before normal program execution resumes. Consult the table for the related time
Wake-up Source
Oscillator Type
HIRC,LIRC
External RES
tRSTD + tSST
PA Port
Interrupt
tSST
WDT Overflow
Note: 1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=50ms
3. tSST=16tSYS
Wake-up Delay Time
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Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to prevent program malfunctions or
sequences from jumping to unknown locations, due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the LIRC and the system clock fSYS which is
sourced from the HIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio
of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the
WDTS register. The LIRC internal oscillator has an approximate period frequency of 12kHz at a
supply voltage of 5V. However, it should be noted that this specified internal clock period can vary
with VDD, temperature and process variations.
Watchdog Timer Control Registers
WDTS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
WS2
WS1
WS0
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
1
1
1
Bit 7~3
Unimplemented, read as “0”
Bit 2~0WS2~WS0: WDT Time-out period selection
000: 28/fS
001: 29/fS
010: 210/fS
011: 211/fS
100: 212/fS
101: 213/fS
110: 214/fS
111: 215/fS
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
WDTC Register
Bit
Name
7
6
5
4
3
2
1
0
WDTCLS1 WDTCLS0 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6WDTCLS1~WDTCLS0: WDT/Timer clock source
00: fLIRC
01: fSYS/4
10: fSYS
11: fSYS
Bit 5~0WDTEN5~WDTEN0: WDT enable control
000000: Enable
101101: Disable
Other values: MCU reset
When these bits are changed by the environmental noise to reset the microcontroller,
the reset operation will be activated after 2~3 LIRC clock cycles.
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Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instruction. Note that if the Watchdog Timer function is not enabled,
then any instruction related to the Watchdog Timer will result in no operation.
Setting the various Watchdog Timer options are controlled via the internal registers WDTC and
WDTS. Enabling the Watchdog Timer can be controlled by the WDTEN bits in the internal WDTC
register in the Data Memory.
The Watchdog Timer will be disabled if bits WDTEN5~WDTEN0 in the WDTC register are written
with the binary value 101101B while the WDT Timer will be enabled if these bits are written
with the binary value 000000B. If these bits are written with the other values except 000000B and
101101B, the MCU will be reset.
The Watchdog Timer clock can emanate from three different sources, selected by the
WDTCLS1~WDTCLS0 bits in the WDTC register. These sources are fSYS, fSYS/4 or LIRC. It is
important to note that when the system enters the Sleep Mode the instruction clock is stopped,
therefore if it has selected fSYS or fSYS/4 as the Watchdog Timer clock source, the Watchdog Timer
will stop. For systems that operate in noisy environments, it’s recommended to use the LIRC as
the clock source. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and
with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler division ratio will
be 1:32768, which will give a maximum time-out period.
Under normal program operation, a Watchdog Timer time-out will initialize a device reset and set
the status bit TO. However, if the system is in the Sleep Mode, when a Watchdog Timer time-out
occurs, the device will be woken up, the TO bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Four methods can be adopted to clear the contents of the
Watchdog Timer. The first is a WDT software reset, which means a certain value except 101101B
and 000000B written into the WDTEN bit filed, the second is an external hardware reset, which
means a low level on the external reset pin, the third is using the Clear Watchdog Timer software
instructions and the fourth is via a “HALT” instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the “CLR WDT” instruction to clear the WDT.
WDTEN bits
Reset MCU
RES pin reset
“H�LT”Instr�ction
“CLR WDT”Instr�ction
fSYS
fSYS/�
LIRC
M
U
X
WDTCLS1�
WDTCLS0
CLR
fS 8-sta�e Prescaler fS/8
WDT Divider
8-to-1 MUX
WS�~WS0
WDT Time-o�t
(�8/fS ~ �15/fS)
Watchdog Timer
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Reset and Initialization
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a
reset condition when the microcontroller is running. One example of this is where after power has
been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such
a case, known as a normal operation reset, some of the microcontroller registers remain unchanged
allowing the microcontroller to deal with normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller.
All types of reset operations result in different register conditions being set.
Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES
reset is implemented in situations where the power supply voltage falls below a certain threshold.
Reset Functions
There are five ways in which a microcontroller reset can occur, through events occurring both
internally and externally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
Although the microcontroller has an internal RC reset function, if the VDD power supply rise time
is not fast enough or does not stabilize quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin
remains low for an extended period to allow the power supply to stabilize. During this time delay,
normal operation of the microcontroller will be inhibited. After the RES line reaches a certain
voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the
microcontroller will begin normal operation. The abbreviation SST in the figures stands for System
Start-up Timer.
For most applications a resistor connected between VDD and the RES pin and a capacitor connected
between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to
the RES pin should be kept as short as possible to minimize any stray noise interference.
Note: tRSTD is power-on delay, typical time=50ms
Power-On Reset Timing Chart
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For applications that operate within an environment where more noise is present the reset circuit
shown is recommended.
Note: “*” It is recommended that this component is added for added ESD protection.
“**” It is recommended that this component is added in environments where power line
noise is significant.
External RES Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the
Holtek website.
RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other reset,
the Program Counter will reset to zero and program execution initiated from this point.
Note: tRSTD is power-on delay, typical time=50ms
RES Reset Timing Chart
• EXTRESB Register
Bit
7
6
5
Name
—
—
—
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
4
3
2
1
0
RESBEN4 RESBEN3 RESBEN2 RESBEN1 RESBEN0
Unimplemented, read as “0”
Bit 4~0RESBEN4~RESBEN0: External Reset Pin select
00000: I/O Pin
10101: External Reset Pin
Other: MCU reset
When these bits are changed by the environmental noise to reset the microcontroller,
the reset operation will be activated after 2~3 LIRC clock cycles.
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Low Voltage Reset – LVR
The microcontroller contains an always enabled low voltage reset circuit in order to monitor the
supply voltage of the device. This voltage is fixed at 2.1V (VLVR). If the supply voltage of the device
drops to within a range of 0.9V~VLVR such as might occur when changing a battery, the LVR will
automatically reset the device internally.
The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage
in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C.
characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not
perform a reset function. Note that the LVR function will automatically be disabled when the MCU
enters the Power Down Mode.
Note: tRSTD is power-on delay, typical time=50ms
Low Voltage Reset Timing Chart
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to “1”.
Note: tRSTD is power-on delay, typical time=50ms
WDT Time-out Reset during Normal Operation Timing Chart
Watchdog Time-out Reset during Sleep Mode
The Watchdog time-out Reset during Sleep Mode is a little different from other kinds of reset. Most
of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details.
Note: tSST is 16 clock cycles for the system clock source is provided by HIRC.
WDT Time-out Reset during Sleep Timing Chart
Rev. 1.10
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Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the Sleep Mode function or Watchdog Timer. The reset flags are shown in the
table:
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
RES or LVR reset during NORMAL Mode operation
1
u
WDT time-out reset during NORMAL Mode operation
1
1
WDT time-out reset during Sleep Mode operation
Note: “u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Event Counter
Timer Counter will be turned off
Precaler
The Timer Counter Prescaler will be cleared
Input/Output Ports
I/O ports will be set as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects the microcontroller internal registers.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
HT48R002
Register
Power-on Reset
RES Reset
WDT Time-out
RES Reset (HALT)
(Normal operation)
(Normal Operation)
WDT Time-out
(HALT)*
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MP0
1xxx xxxx
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
MP1
1xxx xxxx
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
- - uu uuuu
- - uu uuuu
- - uu uuuu
- - uu uuuu
WDTS
- - - - - 111
- - - - - 111
- - - - - 111
- - - - - 111
- - - - - uuu
STATUS
--00 xxxx
- - uu uuuu
- - 0 1 uuuu
- - 1 u uuuu
- - 1 1 uuuu
INTC0
--00 -000
--00 -000
--00 -000
--00 -000
- - uu - uuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu - u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWU
--0- -000
--0- -000
--0- -000
--0- -000
- - u - - uuu
PAPU
-000 0000
-000 0000
-000 0000
-000 0000
- uuu uuuu
CTRL1
10-- ----
10-- ----
10-- ----
10-- ----
uu - - - - - -
WDTC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
EXTRESB
---0 0000
---0 0000
---0 0000
---0 0000
- - - u uuuu
Note: “*” means “warm reset”
“-” not implement
“u” means “unchanged”
“x” means “unknown”
Rev. 1.10
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Cost-Effective I/O 8-Bit OTP MCU
HT48R003
Register
Power-on Reset
RES Reset
RES Reset (HALT)
(Normal operation)
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)*
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MP0
1xxx xxxx
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
MP1
1xxx xxxx
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
1 uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
- - uu uuuu
- - uu uuuu
- - uu uuuu
- - uu uuuu
WDTS
- - - - - 111
- - - - - 111
- - - - - 111
- - - - - 111
- - - - - uuu
STATUS
--00 xxxx
- - uu uuuu
- - 0 1 uuuu
- - 1 u uuuu
- - 1 1 uuuu
INTC0
--00 -000
--00 -000
--00 -000
--00 -000
- - uu - uuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu - u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWU
--0- -000
--0- -000
--0- -000
--0- -000
- - u - - uuu
PAPU
-000 0000
-000 0000
-000 0000
-000 0000
- uuu uuuu
PC
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
- - uu uuuu
PCC
- - 11 1111
- - 11 1111
- - 11 1111
- - 11 1111
- - uu uuuu
PCPU
--00 0000
--00 0000
--00 0000
--00 0000
- - uu uuuu
CTRL0
---- -0--
---- -0--
---- -0--
---- -0--
---- -u--
CTRL1
10-- ----
10-- ----
10-- ----
10-- ----
uu - - - - - -
WDTC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
EXTRESB
---0 0000
---0 0000
---0 0000
---0 0000
- - - u uuuu
Note: “*” means “warm reset”
“-” not implement
“u” means “unchanged”
“x” means “unknown”
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an
input or output designation under user program control. Additionally, as there are pull-high resistors
and wake-up software configurations, the user is provided with an I/O structure to meet the needs of
a wide range of application possibilities.
The devices provide bidirectional input/output lines labeled with port names PA and PC. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
I/O Register List
HT48R002
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
—
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU
—
—
PAWU5
—
—
PAWU2
PAWU1
PAWU0
Register
Name
7
6
5
4
3
2
1
0
PA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PAC
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
—
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PAWU0
HT48R003
Rev. 1.10
Bit
PAWU
—
—
PAWU5
—
—
PAWU2
PAWU1
PC
—
—
PC5
PC4
PC3
PC2
PC1
PC0
PCC
—
—
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
—
—
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
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Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using the registers PAPU and PCPU located in the Data Memory. The
pull-high resistors are implemented using weak PMOS transistors. Note that pin PA7 does not have
a pull-high resistor selection.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
—
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6~0PAPU6~PAPU0: Port A bit6~bit0 pull-high control
0: Disable
1: Enable
PCPU Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7, 6
Unimplemented, read as "0"
Bit 5~0PCPU5~PCPU0: Port C bit5~bit0 pull-high control
0: Disable
1: Enable
Port A Wake-up
If the HALT instruction is executed, the device will enter the Sleep Mode, where the system clock will
stop resulting in power being conserved, a feature that is important for battery and other low-power
applications. Various methods exist to wake-up the microcontroller, one of which is to change
the logic condition on one of the PA0~PA2, PA5pins from high to low. After a HALT instruction
forces the microcontroller into entering the Sleep Mode, the processor will remain in a low-power
state until the logic condition of the selected wake-up pin on Port A changes from high to low. This
function is especially suitable for applications that can be woken up via external switches. Note
that pins PA0~PA2, PA5 can be selected individually to have this wake-up feature using an internal
register known as PAWU, located in the Data Memory.
Rev. 1.10
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Cost-Effective I/O 8-Bit OTP MCU
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
PAWU5
—
—
PAWU2
PAWU1
PAWU0
R/W
—
—
R/W
—
—
R/W
R/W
R/W
POR
—
—
0
—
—
0
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5PAWU5: Port A bit 5 wake-up control
0: Disable
1: Enable
Bit 4~3
Unimplemented, read as "0"
Bit 2~0PAWU2~PAWU0: Port A bit 2~bit 0 wake-up control
0: Disable
1: Enable
I/O Port Control Registers
Each port has its own control register known as PAC, PCC, which control the input/output
configuration. With this control register, each I/O pin with or without pull-high resistors can be
reconfigured dynamically under software control. For the I/O pin to function as an input, the
corresponding bit of the control register must be written as a “1”. This will then allow the logic
state of the input pin to be directly read by instructions. When the corresponding bit of the control
register is written as a “0”, the I/O pin will be set as a CMOS output. If the pin is currently set as an
output, instructions can still be used to read the output register. However, it should be noted that the
program will in fact only read the status of the output data latch and not the actual logic status of the
output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~0
Port A bit 7~bit 0 Input/Output control
0: Output
1: Input
PCC Register – HT48R003 only
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
1
1
1
1
1
1
Bit 7~6
Unimplemented, read as "0"
Bit 5~0
Port C bit 5~bit 0 Input/Output control
0: Output
1: Input
35
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more
than one function. Limited numbers of pins can force serious design constraints on designers but by
supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the
chosen function of the multi-function I/O pins is set by application program control.
External Interrupt Input
The external interrupt pin, INT, is pin-shared with an I/O pin. To use the pin as an external interrupt
input the correct bits in the INTC0 register must be programmed. The pin must also be set as an
input by setting the PAC2 bit in the Port Control Register. A pull-high resistor can also be selected
via the appropriate port pull-high resistor register. Note that even if the pin is set as an external
interrupt input the I/O function still remains.
External Timer/Event Counter Input
The Timer/Event Counter pin TMR is pin-shared with I/O pins For this shared pin to be used as
Timer/Event Counter input, the Timer/Event Counter must be configured to be in the Event Counter
or Pulse Width Capture Mode. This is achieved by setting the appropriate bits in the Timer/Event
Counter Control Register. The pin must also be set as input by setting the appropriate bit in the Port
Control Register. Pull-high resistor options can also be selected using the port pull-high resistor
registers. Note that even if the pin is set as an external timer input the I/O function still remains.
PFD Output(for HT48R003)
The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen
using the CTRL0 register. Note that the corresponding bit of the port control register must be set
the pin as an output to enable the PFD output. If the port control register has set the pin as an input,
then the pin will function as a normal logic input with the usual pull-high selection, even if the PFD
function has been selected
I/O Pin Structures
The accompanying diagrams illustrate the I/O pin internal structures. As the exact logical
construction of the I/O pin may differ from these drawings, they are supplied as a guide only to
assist with the functional understanding of the I/O pins.
   
  Generic Input/Output Ports
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
       PA7 NMOS Input/Output Port
Programming Considerations
Within the user program, one of the things first to consider is port initialization. After a reset, all
of the I/O data and port control registers will be set to high. This means that all I/O pins will be
defaulted to an input state, the level of which depends on the other connected circuitry and whether
pull-high selections have been chosen. If the port control registers are then programmed to set some
pins as outputs, these output pins will have an initial high output value unless the associated port
data registers are first programmed. Selecting which pins are inputs and which are outputs can be
achieved byte-wide by loading the correct values into the appropriate port control register or by
programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”
instructions. Note that when using these bit control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on the entire port, modify it to the required new
bit values and then rewrite this data back to the output ports.
Read Modify Write Timing
Pins PA0~PA2, PA5 each have wake-up functions, selected via the PAWU register. When the device
is in the Sleep Mode, various methods are available to wake the device up. One of these is a high to
low transition of any pins. Single or multiple pins on Port A can be set to have this function.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Timer/Event Counter
The provision of timer form an important part of any microcontroller, giving the designer a means of
carrying out time related functions. The devices contain from an 8-bit count-up timer. As the timer
has three different operating modes, they can be configured to operate as a general timer, an external
event counter or as a pulse width capture device. The provision of an internal prescaler to the clock
circuitry on gives added range to the timer.
There are two types of registers related to the Timer/Event Counters. The first is the register that
contains the actual value of the timer and into which an initial value can be preloaded. Reading from
this register retrieves the contents of the Timer/Event Counter. The second type of associated register
is the Timer Control Register which defines the timer options and determines how the timer is to
be used. The device can have the timer clock configured to come from the internal clock source. In
addition, the timer clock source can also be configured to come from an external timer pin.
Configuring the Timer/Event Counter Input Clock Source
The Timer/Event Counter clock source can originate from various sources, an internal clock or an
external pin. The internal clock source is used when the timer is in the timer mode. For the Timer/
Event Counter 0, this internal clock source is first divided by a prescaler, the division ratio of which
is conditioned by the Timer Control Register bits T0PSC2~T0PSC0. The internal clock source can
be derived from the system clock fSYS or from the instruction clock fSYS/4 or the internal low speed
oscillator LIRC for Timer/Event Counter selected by the clock selection bits WDTCLS1~WDTCLS0
in the WDTC register.
An external clock source is used when the Timer/Event Counter is in the event counting mode, the
clock source being provided on an external timer pin TMR. Depending upon the condition of the
T0EG bit, each high to low, or low to high transition on the external timer pin will increment the
counter by one.
PWM
PWM Circ�itry
fSYS
fSYS/�
M f
S
U
X
LIRC
WDTCLS1�
WDTCLS0
8-to-1 MUX
7
8-sta�e Prescaler
8-to-1 MUX
fS/�8
WS�~WS0
WDT Divider
WDT Time-o�t
(�8/fS ~ �15/fS)
To Timer 0 internal clock
T0PSC�~T0PSC0
Clock Source for Timer/WDT
‚ ƒ 
 
  „
­  €

Note: “*” means for HT48R003 only.
8-bit Timer/Event Counter 0 Structure
Rev. 1.10
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August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Timer Register – TMR0
The timer register is special function register located in the Special Purpose Data Memory and is the
place where the actual timer value is stored. The register is known as TMR0. The value in the timer
register increases by one each time an internal clock pulse is received or an external transition occurs
on the external timer pin. The timer will count from the initial value loaded by the preload register to
the full count of FFH at which point the timer overflows and an internal interrupt signal is generated.
The timer value will then reset with the initial preload register value and continue counting.
Note that to achieve a maximum full range count of FFH, the preload register must first be cleared.
It should be noted that after power-on, the preload register will be in an unknown condition. Note
that if the Timer/Event Counter is in an OFF condition and data is written to its preload register,
this data will be immediately written into the actual counter. However, if the counter is enabled and
counting, any new data written into the preload data register during this period will remain in the
preload register and will only be written into the actual counter the next time an overflow occurs.
Timer Control Register – TMR0C
The flexible features of the Holtek microcontroller Timer/Event Counter enable it to operate in three
different modes, the options of which are determined by the contents of their respective control
register.
The Timer Control Register is known as TMR0C. It is the Timer Control Register together with
its corresponding timer register that controls the full operation of the Timer/Event Counter. Before
the timer can be used, it is essential that the Timer Control Register is fully programmed with the
right data to ensure its correct operation, a process that is normally carried out during program
initialization.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair T0M1/T0M0, must be set to the required logic levels. The timer-on bit,
which is bit 4 of the Timer Control Register and known as T0ON, provides the basic on/off control
of the respective timer. Setting the bit to high allows the counter to run. Clearing the bit stops the
counter. Bits 0~2 of the Timer Control Register determine the division ratio of the input clock
prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is
in the event count or pulse width capture mode, the active transition edge level type is selected by
the logic level of bit 3 of the Timer Control Register which is known as T0EG.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
TMR0C Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
—
T0ON
T0EG
T0PSC2
T0PSC1
T0PSC0
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
POR
0
0
—
0
1
0
0
0
Bit 7~6T0M1~T0M0: Timer operation mode selection
00: No mode available
01: Event counter mode
10: Timer mode
11: Pulse width capture mode
Bit 5
Unimplemented, read as "0"
Bit 4T0ON: Timer/event counter counting enable
0: Disable
1: Enable
Bit 3T0EG: Timer/Event Counter active edge selection
In event counter mode (T0M1~T0M0=01)
0: Count on rising edge
1: Count on falling edge
In pulse width measurement mode (T0M1~T0M0=11)
0: Start counting on falling edge, stop on the rising edge
1: Start counting on rising edge, stop on the falling edge
Bit 2~0T0PSC2~T0PSC0: Timer prescalar rate selection
000: fS
001: fS/2
010: fS/4
011: fS/8
100: fS/16
101: fS/32
110: fS/64
111: fS/128
Timer Mode
In this mode, the Timer/Event Counter can be utilized to measure fixed time intervals, providing
an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,
the Operating Mode Select bit pair, T0M1/T0M0, in the Timer Control Register must be set to the
correct value as shown.
Bit7
Bit6
1
0
Control Register Operating Mode Select Bits for the Timer Mode
In this mode the internal clock is used as the timer clock. The timer input clock source is fSYS or
fSYS/4. However, this timer clock source is further divided by a prescaler, the value of which is
determined by the bits T0PSC2~T0PSC0 in the Timer Control Register. The timer-on bit, T0ON
must be set high to enable the timer to run. Each time an internal clock high to low transition occurs,
the timer increments by one. When the timer is full and overflows, an interrupt signal is generated
and the timer will reload the value already loaded into the preload register and continue counting.
A timer overflow condition and corresponding internal interrupts are two of the wake-up sources.
However, the internal interrupts can be disabled by ensuring that the T0E bits of the INTC0 register
are reset to zero.
Rev. 1.10
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HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Timer Mode Timing Chart
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TMR
pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode
Select bit pair, T0M1/T0M0, in the Timer Control Register must be set to the correct value as
shown.
Bit7
Bit6
0
1
Control Register Operating Mode Select Bits for the Timer Mode
In this mode, the external timer TMR pin is used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been
set, the enable bit T0ON, which is bit 4 of the Timer Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit, T0EG, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a
low to high transition. If the T0EG is high, the counter will increment each time the external timer
pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated
and the Timer/Event Counter will reload the value already loaded into the preload register and
continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt
Enable bit in the corresponding Interrupt Control Register. It is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as
an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode
Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting
Mode. The second is to ensure that the port control register configures the pin as an input. It should
be noted that in the event counting mode, even if the microcontroller is in the Sleep Mode, the
Timer/Event Counter will continue to record externally changing logic events on the timer input
TMR pin. As a result when the timer overflows it will generate a timer interrupt and corresponding
wake-up source.
Event Counter Mode Timing Chart (T0EG=1)
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Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses
applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, T0M1/
T0M0, in the Timer Control Register must be set to the correct value as shown.
Bit7
Bit6
1
1
Control Register Operating Mode Select Bits for the Pulse Width Capture Mode
In this mode the internal clock, fSYS, fSYS/4 or fLIRC is used as the internal clock for the 8-bit Timer/
Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler,
the value of which is determined by the Prescaler Rate Select bits T0PSC2~T0PSC0, which are bit
2~0 of the Timer Control Register, After other bits in the Timer Control Register have been set, the
enable bit T0ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/
Event Counter, however it will not actually start counting until an active edge is received on the
external timer pin.
If the Active Edge Select bit T0EG which is bit 3 of the Timer Control Register is low, once a high
to low transition has been received on the external timer pin, the Timer/Event Counter will start
counting until the external timer pin returns to its original high level. At this point the enable bit will
be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge
Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has
been received on the external timer pin and stop counting when the external timer pin returns to its
original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in the pulse width capture mode, the enable
bit is automatically reset to zero when the external control signal on the external timer pin returns
to its original level, whereas in the other two modes the enable bit can only be reset to zero under
program control.
The residual value in the Timer/Event Counter, which can now be read by the program, therefore
represents the length of the pulse received on the TMR pin. As the enable bit has now been reset,
any further transitions on the external timer pin will be ignored. The timer cannot begin further pulse
width capture until the enable bit is set high again by the program. In this way, single shot pulse
measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is
controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/
Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter
will reload the value already loaded into the preload register and continue counting. The interrupt
can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding
Interrupt Control Register, it is reset to zero. As the TMR pin is shared with an I/O pin, to ensure
that the pin is configured to operate as a pulse width capture pin, two things have to be implemented.
The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the
Timer/Event Counter in the pulse width capture mode, the second is to ensure that the port control
register configure the pin as an input.
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               ­ € ‚  ‚  € ƒ
Pulse Width Capture Mode Timing Chart (T0EG=0)
Prescaler
Bits T0PSC2~T0PSC0 of the TMR0C register can be used to define a division ratio for the internal
clock source of the Timer/Event Counter enabling longer time out periods to be set.
PFD Function (for HT48R003)
The Programmable Frequency Divider provides a means of producing a variable frequency output
suitable for application, such as some interfaces requiring a precise frequency generator.
The Timer/Event Counter overflow signal is the clock source for the PFD function, which is
controlled by PFDC bit in CTRL0. For this device the clock source can come from Timer/Event
Counter 0. The output frequency is controlled by loading the required values into the timer prescaler
and timer registers to give the required division ratio. The counter will begin to count-up from this
preload register value until full, at which point an overflow signal is generated, causing both the PFD
outputs to change state. Then the counter will be automatically reloaded with the preload register
value and continue counting-up. If the CTRL0 register has selected the PFD function, then for PFD
output to operate, it is essential for the Port A control register PAC to set the PFD pins as outputs.
PA6 must be set high to activate the PFD. The output data bits can be used as the on/off control bit
for the PFD outputs. Note that the PFD outputs will all be low if the output data bit is cleared to
zero.
PFD Function
I/O Interfacing
The Timer/Event Counter, when configured to run in the event counter or pulse width capture
mode, requires the use of an external timer pin for its operation. As this pin is a shared pin it must
be configured correctly to ensure that it is set for use as a Timer/Event Counter input pin. This is
achieved by ensuring that the mode selects bits in the Timer/Event Counter control register, either
the event counter or pulse width capture mode. Additionally the corresponding Port Control Register
bit must be set high to ensure that the pin is set as an input. Any pull-high resistor connected to this
pin will remain valid even if the pin is used as a Timer/Event Counter input.
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Programming Considerations
When running in the timer mode, the internal system clock is used as the timer clock source and
is therefore synchronised with the overall operation of the microcontroller. In this mode when
the appropriate timer register is full, the microcontroller will generate an internal interrupt signal
directing the program flow to the respective internal interrupt vector. For the pulse width capture
mode, the internal system clock is also used as the timer clock source but the timer will only run
when the correct logic condition appears on the external timer input pin. As this is an external
event and not synchronised with the internal timer clock, the microcontroller will only see this
external event when the next timer clock pulse arrives. As a result, there may be small differences
in measured values requiring programmers to take this into account during programming. The same
applies if the timer is configured to be in the event counting mode, which again is an external event
and not synchronised with the internal system or timer clock.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is
inhibited to avoid errors, however as this may result in a counting error, this should be taken into
account by the programmer. Care must be taken to ensure that the timers are properly initialised
before using them for the first time. The associated timer enable bits in the interrupt control
register must be properly set otherwise the internal interrupt associated with the timer will remain
inactive. The edge select, timer mode and clock source control bits in timer control register must
also be correctly set to ensure the timer is properly configured for the required application. It is
also important to ensure that an initial value is first loaded into the timer registers before the timer
is switched on; this is because after power-on the initial values of the timer registers are unknown.
After the timer has been initialised the timer can be turned on and off by controlling the enable bit in
the timer control register.
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt
control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate
an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event
Counter overflow will also generate a wake-up signal if the device is in a Power-down condition.
This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the
external signal continues to change state. In such a case, the Timer/Event Counter will continue to
count these external events and if an overflow occurs the device will be woken up from its Powerdown condition. To prevent such a wake-up from occurring, the timer interrupt request flag should
first be set high before issuing the “HALT” instruction to enter the Sleep Mode.
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Timer Program Example
The program shows how the Timer/Event Counter registers are set along with how the interrupts are
enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer
Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same
bit. This example program sets the Timer/Event Counters to be in the timer mode, which uses the
internal system clock as their clock source.
PFD Programming Example
org 04h ;
org 08h ;
jmp tmr0int ;
:
:
org 20h ;
:
:
;
tmr0int:
:
;
:
:
begin:
;
mov a,09bh ;
mov tmr0,a
mov a,081h ;
mov tmr0c,a ;
mov a,0c0H ;
mov wdtc,a
;
mov a,05h ;
mov intc0,a
:
:
set tmr0c.4 ;
:
:
Rev. 1.10
external interrupt vector
Timer Counter 0 interrupt vector
jump here when Timer 0 overflows
main program
internal Timer 0 interrupt routine
Timer 0 main program placed here
set Timer 0 registers
set Timer 0 preload value
set Timer 0 control register
timer mode and prescaler set to /2
select fSYS for the TMR0 clock source
set interrupt register
enable master interrupt and both timer interrupts
start Timer 0
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Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal
function such as a Timer/Event Counter requires microcontroller attention, their corresponding
interrupt will enforce a temporary suspension of the main program allowing the microcontroller to
direct attention to their respective needs.
The device contains only one external interrupt and one internal interrupts. The external interrupts
are controlled by the action of the external interrupt pin, while the internal interrupt is controlled by
the Timer/Event Counter.
Interrupt Register
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by
using the register, INTC0. By controlling the appropriate enable bits in the register each individual
interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag
will be set by the microcontroller. The global enable flag cleared to zero will disable all interrupts.
Function
Enable Bit
Request Flag
Global
EMI
—
INT Pin
INTE
INTF
Timer
T0E
T0F
INTC0 Register
Bit
7
6
Name
—
R/W
—
POR
—
Bit 7~6
5
4
3
2
1
—
T0F
INTF
—
R/W
R/W
—
0
0
0
—
T0E
INTE
EMI
—
R/W
R/W
R/W
—
0
0
0
Unimplemented, read as "0"
Bit 5T0F: Timer/Event Counter 0 request flag
0: No request
1: Interrupt request
Bit 4INTF: INT pin interrupt request flag
0: No request
1: Interrupt request
Bit 3
Unimplemented, read as "0"
Bit 2T0E: Timer/Event Counter 0 interrupt control
0: Disable
1: Enable
Bit 1INTE: INT interrupt control
0: Disable
1: Enable
Bit 0EMI: Global interrupt control
0: Disable
1: Enable
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Interrupt Operation
A Timer/Event Counter overflow or an active edge on the external interrupt pin will all generate an
interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit
is set. When this happens, the Program Counter, which stores the address of the next instruction to
be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new
address which will be the value of the corresponding interrupt vector. The microcontroller will then
fetch its next instruction from this interrupt vector.
The instruction at this vector will usually be a JMP statement which will jump to another section
of program which is known as the interrupt service routine. Here is located the code to control the
appropriate interrupt. The interrupt service routine must be terminated with a RETI instruction,
which retrieves the original Program Counter address from the stack and allows the microcontroller
to continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
   
      ­ Interrupt Scheme
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will
be cleared automatically. This will prevent any further interrupt nesting from occurring. However,
if other interrupt requests occur during this interval, although the interrupt will not be immediately
serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the
program is already in another interrupt service routine, the EMI bit should be set after entering the
routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service
is desired, the stack must be prevented from becoming full.
When an interrupt request is generated it takes 2 or 3 instruction cycles before the program jumps to
the interrupt vector. If the device is in the Sleep Mode and is woken up by an interrupt request then
it will take 3 cycles before the program jumps to the interrupt vector.
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Main
Pro�ram
Interr�pt Req�est or
Interr�pt Fla� Set by Instr�ction
N
Enable Bit Set ?
Y
��tomatically Disable Interr�pt
Clear EMI & Req�est Fla�
Main
Pro�ram
Wait for � ~ 3 Instr�ction Cycles
ISR Entry
…
…
RETI
(it will set EMI a�tomatically)
Interrupt Flow
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
Interrupt Source
Priority
Vector
External interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
In cases where both external and internal interrupts are enabled and where an external and internal
interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
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External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt
request flag, INTF is set, a situation that will occur when an edge transition appears on the external
INT line. The type of transition that will trigger an external interrupt, whether high to low, low to
high or both is determined by the INTES0 and INTES1 bits, which are bits 6 and 7 respectively in
the CTRL1 control register. These two bits can also disable the external interrupt function.
INTES1
INTES0
Request Flag
0
0
External interrupt disable
0
1
Rising edge trigger
1
0
Falling edge trigger
1
1
Dual edge trigger
The external interrupt pin is pin-shared with the I/O pin PA2 and can only be used as an external
interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set
and the edge trigger type has been selected using the CTRL1 register. The pin must also be set as
an input by setting the corresponding PAC.2 bit in the port control register. When the interrupt is
enabled, the stack is not full and a transition appears on the external interrupt pin, a subroutine
call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced,
the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor connections on this
pin will remain valid even if the pin is used as an external interrupt input
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI and the
corresponding timer interrupt enable bit T0E must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag T0F is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter overflow occurs, a subroutine call to the relevant timer interrupt
vector, will take place. When the interrupt is serviced, the timer interrupt request flag T0F will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
Sleep Mode. A wake-up is generated when an interrupt request flag changes from low to high and
is independent of whether the interrupt is enabled or not. Therefore, even though the device is in
the Sleep Mode and its system oscillator is stopped, situations such as external edge transitions
on the external interrupt pins, a low power supply voltage or may cause their respective interrupt
flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious
wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the
corresponding interrupt request flag should be set high before the device enters the Sleep Mode. The
interrupt enable bits have no effect on the interrupt wake-up function.
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Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the microcontroller when it is in Sleep
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before entering the Sleep Mode.
As only the Program Counter is pushed onto the stack, then if the contents of the accumulator, status
register or other registers are altered by the interrupt service program, which may corrupt the desired
control sequence, then the contents should be saved in advance.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
Application Circuits
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Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5μs and branch or call instructions would be implemented within
1μs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Logical and Rotate Operation
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
which rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction
or to a subroutine using the CALL instruction. They differ in the sense that in the case of a
subroutine call, the program must return to the instruction immediately when the subroutine has
been carried out. This is done by placing a return instruction “RET” in the subroutine which will
cause the program to jump back to the address right after the CALL instruction. In the case of a JMP
instruction, the program simply jumps to the desired location. There is no requirement to jump back
to the original jumping off point as in the case of the CALL instruction. One special and extremely
useful set of branch instructions are the conditional branches. Here a decision is first made regarding
the condition of a certain data memory or individual bits. Depending upon the conditions, the
program will continue with the next instruction or skip over it and jump to the following instruction.
These instructions are the key to decision making and branching within the program perhaps
determined by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i”
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be set as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the “HALT” instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
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Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rev. 1.10
53
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (specific page) to TBLH and Data Memory
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
2Note
None
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch Operation
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read Operation
TABRD [m]
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
54
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.10
55
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Rev. 1.10
56
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.10
57
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Rev. 1.10
58
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rev. 1.10
59
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Rev. 1.10
60
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.10
61
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.10
62
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.10
63
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.10
64
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
8-pin DIP (300mil) Outline Dimensions
Symbol
Nom.
Max.
A
0.355
0.365
0.400
B
0.240
0.250
0.280
C
0.115
0.130
0.195
D
0.115
0.130
0.150
E
0.014
0.018
0.022
0.070
F
0.045
0.060
G
—
0.100 BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.02
9.27
10.16
B
6.10
6.35
7.11
C
2.92
3.30
4.95
D
2.92
3.30
3.81
E
0.36
0.46
0.56
1.78
F
1.14
1.52
G
—
2.54 BSC
—
H
7.26
7.87
8.26
I
—
—
10.92
65
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
8-pin SOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.012
—
0.020
C′
—
0.193 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
—
A
—F
6.00 BSC
B
—
3.90 BSC
—
C
0.31
—
0.51
C′
—
4.90 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
—
8°
66
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
10-pin MSOP Outline Dimensions
Symbol
Min.
Nom.
Max.
A
—
—
0.043
A1
0.000
—
0.006
A2
0.030
0.033
0.037
B
0.007
—
0.013
C
0.003
—
0.009
D
—
0.118 BSC
—
E
—
0.193 BSC
—
E1
—
0.118 BSC
—
e
—
0.020 BSC
—
L
0.016
0.024
0.031
L1
—
0.037 BSC
—
y
—
0.004
—
θ
0°
—
8°
Symbol
Rev. 1.10
Dimensions in inch
Dimensions in mm
Min.
Nom.
A
—
—
1.10
A1
0.00
—
0.15
A2
0.75
0.85
0.95
B
0.17
—
0.33
C
0.08
—
0.23
D
—
3.00 BSC
—
E
—
4.90 BSC
—
E1
—
3.00 BSC
—
e
—
0.50 BSC
—
L
0.40
0.60
0.80
L1
—
0.95 BSC
—
y
—
0.10
—
θ
0°
—
8°
67
Max.
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
16-pin DIP (300mil) Outline Dimensions
Fig1. Full Lead Packages
Fig2. 1/2 Lead Packages
See Fig 1
Symbol
Min.
Nom.
Max.
A
0.780
0.790
0.800
B
0.240
0.250
0.280
C
0.115
0.130
0.195
D
0.115
0.130
0.150
E
0.014
0.018
0.022
F
0.045
0.060
0.070
G
—
0.100 BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.10
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
20.32
A
19.81
20.07
B
6.10
6.35
7.11
C
2.92
3.30
4.95
D
2.92
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.52
1.78
G
—
2.54 BSC
—
H
7.62
7.87
8.26
I
—
—
10.92
68
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
See Fig 2 − Type 1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.745
0.765
0.785
B
0.275
0.285
0.295
C
0.120
0.135
0.150
D
0.110
0.130
0.150
E
0.014
0.018
0.022
0.060
F
0.045
0.050
G
—
0.1 BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Dimensions in mm
Min.
Nom.
Max.
A
18.92
19.43
19.94
7.49
B
6.99
7.24
C
3.05
3.43
3.81
D
2.79
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.27
1.52
G
—
2.54 BSC
—
H
7.62
7.87
8.26
I
—
—
10.92
See Fig 2 − Type 2
Symbol
Nom.
Max.
A
0.735
0.755
0.775
B
0.240
0.250
0.280
C
0.115
0.130
0.195
D
0.115
0.130
0.150
E
0.014
0.018
0.022
F
0.045
0.060
0.070
G
—
0.1 BSC
—
H
0.300
0.310
0.325
I
—
—
0.430
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
18.67
19.18
19.69
B
6.10
6.35
7.11
C
2.92
3.30
4.95
D
2.92
3.30
3.81
E
0.36
0.46
0.56
F
1.14
1.52
1.78
G
—
2.54 BSC
—
H
7.62
7.87
8.26
I
—
—
10.92
69
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
16-pin NSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
—
0.236 BSC
—
B
—
0.154 BSC
—
0.020
C
0.012
—
C'
—
0.390 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
0.010
F
0.004
—
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.0 BSC
B
—
3.9 BSC
—
C
0.31
—
0.51
C'
—
9.9 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
―
8°
70
August 01, 2014
HT48R002/HT48R003
Cost-Effective I/O 8-Bit OTP MCU
Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.10
71
August 01, 2014