USB Low Speed Flash Type MCU HT68FB240 Revision: V1.00 Date: �������������� April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Block Diagram................................................................................................... 7 Pin Assignment................................................................................................. 8 Pin Description................................................................................................. 8 Absolute Maximum Ratings........................................................................... 10 D.C. Characteristics........................................................................................ 10 A.C. Characteristics.........................................................................................11 LVD & LVR Electrical Characteristics........................................................... 12 Power on Reset Characteristics.................................................................... 12 System Architecture....................................................................................... 13 Clocking and Pipelining.......................................................................................................... 13 Program Counter.................................................................................................................... 14 Stack...................................................................................................................................... 15 Arithmetic and Logic Unit – ALU............................................................................................ 15 Flash Program Memory.................................................................................. 16 Structure................................................................................................................................. 16 Special Vectors...................................................................................................................... 16 Look-up Table......................................................................................................................... 16 Table Program Example......................................................................................................... 17 In System Programming – ISP............................................................................................... 18 Flash Memory Read/Write Page Size.................................................................................... 18 ISP Bootloader....................................................................................................................... 20 Flash Program Memory Registers......................................................................................... 20 In Application Program – IAP................................................................................................. 24 In Circuit Programming – ICP................................................................................................ 28 On-Chip Debug Support – OCDS.......................................................................................... 29 RAM Data Memory.......................................................................................... 29 Structure................................................................................................................................. 29 Special Function Register Description......................................................... 31 Indirect Addressing Register – IAR0, IAR1............................................................................ 31 Memory Pointers – MP0, MP1 .............................................................................................. 31 Bank Pointer – BP ................................................................................................................. 32 Accumulator – ACC................................................................................................................ 32 Program Counter Low Register – PCL .................................................................................. 32 Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 32 Status Register – STATUS .................................................................................................... 33 Rev. 1.00 2 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Oscillator......................................................................................................... 35 Oscillator Overview ............................................................................................................... 35 System Clock Configurations ................................................................................................ 35 Internal RC Oscillator – HIRC ............................................................................................... 37 Internal 32kHz Oscillator – LIRC ........................................................................................... 37 Operating Modes and System Clocks ......................................................... 37 System Clocks ...................................................................................................................... 37 System Operation Modes ...................................................................................................... 38 Control Register..................................................................................................................... 40 Operating Mode Switching .................................................................................................... 41 Standby Current Considerations ........................................................................................... 45 Wake-up ................................................................................................................................ 45 Programming Considerations ................................................................................................ 46 Watchdog Timer.............................................................................................. 46 Watchdog Timer Clock Source............................................................................................... 46 Watchdog Timer Control Register.......................................................................................... 46 Watchdog Timer Operation.................................................................................................... 47 WDT Enable/Disabled using the WDT Control Register........................................................ 47 Reset and Initialisation................................................................................... 48 Reset Overview...................................................................................................................... 48 Reset Functions .................................................................................................................... 49 Reset Initial Conditions ......................................................................................................... 53 Input/Output Ports.......................................................................................... 56 Pull-high Resistors................................................................................................................. 56 Port Wake-up......................................................................................................................... 57 I/O Port Control Registers...................................................................................................... 58 I/O Pin Structures................................................................................................................... 60 Programming Considerations ................................................................................................ 60 Timer Modules – TM....................................................................................... 61 Introduction............................................................................................................................ 61 TM Operation......................................................................................................................... 61 TM Clock Source.................................................................................................................... 61 TM Interrupts.......................................................................................................................... 62 TM External Pins ................................................................................................................... 62 TM Input/Output Pin Control Registers.................................................................................. 62 Programming Considerations................................................................................................. 64 Compact Type TM – CTM............................................................................... 65 Compact TM Operation ......................................................................................................... 65 Compact Type TM Register Description................................................................................ 66 Compact Type TM Operating Modes..................................................................................... 70 Compare Match Output Mode................................................................................................ 70 Timer/Counter Mode ............................................................................................................. 73 PWM Output Mode ................................................................................................................ 73 Rev. 1.00 3 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Serial Interface Module – SIM ....................................................................... 76 SPI Interface ......................................................................................................................... 76 SPI Interface Operation ......................................................................................................... 76 SPI Registers......................................................................................................................... 77 SPI Communication .............................................................................................................. 80 SPI Bus Enable/Disable......................................................................................................... 82 SPI Operation......................................................................................................................... 82 I2C Interface .................................................................................................... 84 I2C Interface Operation .......................................................................................................... 84 I2C Registers.......................................................................................................................... 85 I2C Bus Communication ........................................................................................................ 89 I2C Bus Start Signal ............................................................................................................... 89 I2C Bus Slave Address .......................................................................................................... 90 I2C Bus Read/Write Signal .................................................................................................... 90 I2C Bus Slave Address Acknowledge Signal ......................................................................... 90 I2C Bus Data and Acknowledge Signal ................................................................................. 90 I2C Time Out Operation.......................................................................................................... 92 Peripheral Clock Output................................................................................. 93 Peripheral Clock Operation.................................................................................................... 93 Pulse Width Modulator .................................................................................. 94 PWM Operation...................................................................................................................... 94 6+2 PWM Mode..................................................................................................................... 95 7+1 PWM Mode..................................................................................................................... 96 PWM Output Control.............................................................................................................. 97 PWM Programming Example................................................................................................. 97 Interrupts......................................................................................................... 98 Interrupt Registers.................................................................................................................. 98 Interrupt Operation............................................................................................................... 101 External Interrupt.................................................................................................................. 103 USB SIE Interrupt................................................................................................................. 103 USB Setup Token Interrupt.................................................................................................. 103 USB Endpoint 0 IN Token Interrupt...................................................................................... 103 USB Endpoint 0 OUT Token Interrupt.................................................................................. 104 Serial Interface Module Interrupt.......................................................................................... 104 LVD Interrupt ....................................................................................................................... 104 Multi-function Interrupt......................................................................................................... 104 TM Interrupts ....................................................................................................................... 105 Interrupt Wake-up Function.................................................................................................. 105 Programming Considerations............................................................................................... 105 Low Voltage Detector – LVD........................................................................ 106 LVD Register........................................................................................................................ 106 LVD Operation...................................................................................................................... 107 Rev. 1.00 4 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU USB Interface................................................................................................ 108 Power Plane......................................................................................................................... 108 USB Suspend Wake-Up Remote Wake-Up......................................................................... 108 USB Interface Operation...................................................................................................... 109 USB Interface Registers....................................................................................................... 109 Application Circuits.......................................................................................116 Instruction Set................................................................................................117 Introduction...........................................................................................................................117 Instruction Timing..................................................................................................................117 Moving and Transferring Data...............................................................................................117 Arithmetic Operations............................................................................................................117 Logical and Rotate Operation...............................................................................................118 Branches and Control Transfer.............................................................................................118 Bit Operations.......................................................................................................................118 Table Read Operations.........................................................................................................118 Other Operations...................................................................................................................118 Instruction Set Summary..............................................................................119 Table Conventions.................................................................................................................119 Instruction Definition.................................................................................... 121 Package Information.................................................................................... 130 SAW Type 46-pin QFN (6.5mm×4.5mm) Outline Dimensions............................................. 131 48-pin LQFP (7mm×7mm) Outline Dimensions................................................................... 132 Rev. 1.00 5 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Features CPU Features • Operating voltage: ♦♦ VDD (MCU) fSYS = 6MHz: 2.2V~5.5V fSYS = 12MHz: 3.3V~5.5V ♦♦ VDD (USB mode) fSYS = 6MHz/12MHz: 3.3V~5.5V fSYS = 16MHz: 4.5V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • HALT function and wake-up feature reduce power consumption • Oscillators: ♦♦ Internal 12MHz RC – HIRC ♦♦ Internal 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 4K × 16 • RAM Data Memory: 160 × 8 • USB 2.0 Low Speed compatible • Up to 3 endpoints supported including endpoint 0 • All endpoints except endpoint 0 support interrupt transfer • Endpoint 0 supports control transfer for Setup, In and Out token respectively • Endpoint 0 has 8 bytes FIFO size, supports DMA interface for configure USB descriptor • Support 3.3V LDO and integrate an internal 1.5K ohm pull-up resistor on UDN line • Internal 12MHz RC OSC with 1.5% accuracy for all USB modes • Watchdog Timer function • Up to 34 bidirectional I/O lines • Two pin-shared external interrupts • Two Compact Timer Modules for time measure, compare match output, PWM output functions • Serial Interface Modules with SPI and I2C interfaces • Low voltage reset function • Low voltage detect function • In-system programmable in 32 words sector • Support 3 channels 8-bit PWM • Support ISP/IAP function • Package types: 46-pin QFN, 48-pin LQFP • OCDS debug Interface for HT68VB240 only Rev. 1.00 6 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU General Description The HT68FB240 is Flash Memory I/O with USB type 8-bit high performance RISC architecture microcontrollers, designed for applications that interface directly to analog signals and which require an USB interface. Offering users the convenience of Flash Memory multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world is catered for by including fully integrated SPI, I2C and USB interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The external interrupt can be triggered with falling edges or both falling and rising edges. A full choice of two oscillator functions are provided including two fully integrated system oscillators which requires no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. The inclusion of flexible I/O programming features along with many other features ensure that the devices will find specific excellent use in a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. This device is fully supported by the Holtek range of fully functional development and programming tools, providing a means for fast and efficient product development cycles. Block Diagram 3.3V Regulator USB 2.0 XCVR USB 2.0 Low Speed Engine Flash Programming Circuitry (ICP) RAM Data Memory Flash Program Memory Low Voltage Reset Low Voltage Detect Watchdog Timer Reset Circuit 8-bit RISC MCU Core Stack Interrupt Controller LIRC Oscillator HIRC Oscillator I/O Rev. 1.00 PWM 8-bit × 3 SIM TMn 7 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Pin Assignment NC PB0 PB1/SDO/SDA PB2/SDI/SCL PB3/SCK PB4/SCS PB5/PCK PB6/INT0 PB7/INT1 NC NC NC PC5/PWM1 PC6/PWM2 PC7 PA0/OCDSDA PA1 PA2 PA3 NC PA4 PA5 PA6/TP0 PA7/TP1 NC NC PB0 PB1/SDO/SDA PB2/SDI/SCL PB3/SCK PB4/SCS PB5/PCK PB6/INT0 PB7/INT1 UBUS/VDD 1 2 3 4 5 6 7 8 9 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HT68FB240 46 QFN-A 10 11 1213 14 15 16 17 18 19 20 21 22 23 32 31 30 29 28 27 26 25 24 UBUS/VDD V33O UDN/GPIO0 UDP/GPIO1 PE0 PE1 VSS RES/OCDSCK NC NC NC PC0 PC4/PWM0 PD7/TP1B PD6/TP0B PD5/TCK1 PD4/TCK0 PD3 PD2 PD1 PD0 NC PA7/TP1 PA6/TP0 PA5 PA4 PA3 PA2 PA1 PA0/OCDSDA PC7 PC6/PWM2 PC5/PWM1 PC4/PWM0 PD7/TP1B PD6/TP0B PD5/TCK1 PD4/TCK0 PD3 PD2 PD1 PD0 PC3 PC2 PC1 PC3 PC2 PC1 PC0 RES/OCDSCK NC VSS PE1 PE0 UDP/GPIO1 UDN/GPIO0 V33O NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 4 33 5 32 31 6 HT68FB240 7 30 48 LQFP-A 29 8 28 9 27 10 26 11 25 12 13 14 1516 17 18 19 20 21 22 23 24 Pin Description The pins on this device can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/ OCDSDA PA1~PA5 PA6/TP0 PA7/TP1 PB0 PB1/SDO/ SDA PB2/SDI/SCL PB3/SCK Rev. 1.00 Function OPT I/T O/T Description PA0 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. OCDSDA — ST CMOS OCDS data input/output, for EV chip only. PAn PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PA6 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. TP0 TMPC ST CMOS TM0 output PA7 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. TP1 TMPC ST CMOS TM1 output PB0 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PB1 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. SDO — — CMOS SPI serial data output SDA — ST NMOS I2C data line PB2 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. SDI — ST SCL — ST NMOS I2C clock line PB3 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. SCK — ST CMOS SPI serial clock — SPI serial data input 8 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Pin Name Function OPT I/T PB4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. SCS — ST CMOS SPI slave select pin PB5 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PCK — — CMOS Peripheral output clock PB6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. INT0 — ST PB7 PXPU PXWU ST INT1 — ST PCn PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PC4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PWM0 PWMC — CMOS PWM0 output PC5 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PWM1 PWMC — CMOS PWM1 output PC6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PWM2 PWMC — CMOS PWM2 output PC7 PC7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PD0~PD3 PDn PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. PD4 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. TCK0 — ST PD5 PXPU PXWU ST TCK1 — ST PD6 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. TP0B TMPC ST CMOS TM0 inverter output PD7 PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. TP1B TMPC ST CMOS TM1 inverter output PE0~PE1 PEn PXPU PXWU ST CMOS General purpose I/O. Register enabled pull-high and wake-up. RES/ OCDSCK RES — ST PB4/SCS PB5/PCK PB6/INT0 PB7/INT1 PC0~PC3 PC4/PWM0 PC5/PWM1 PC6/PWM2 PD4/TCK0 PD5/TCK1 PD6/TP0B PD7/TP1B UDN/GPIO0 UDP/GPIO1 UBUS/VDD Rev. 1.00 O/T — Description External interrupt 0 CMOS General purpose I/O. Register enabled pull-high and wake-up. — — External interrupt 1 TM0 clock input CMOS General purpose I/O. Register enabled pull-high and wake-up. — TM1 clock input — Reset input — OCDS clock input, for EV chip only. OCDSCK — ST UDN — ST CMOS USB UDN line GPIO0 — ST CMOS General purpose I/O UDP — ST CMOS USB UDP line GPIO1 — ST CMOS General purpose I/O UBUS — PWR — USB SIE VDD VDD — PWR — Power supply 9 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Function OPT I/T O/T V33O Pin Name V33O — — PWR VSS VSS — PWR — Description 3.3V regulator output Ground Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOH Total...................................................................................................................................-100mA IOL Total.................................................................................................................................... 150mA Total Power Dissipation ......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. D.C. Characteristics Ta= 25°C Symbol Parameter VDD Operating Voltage (HIRC OSC) IDD1 Test Conditions VDD Conditions Min. Typ. Max. Unit ─ fSYS=12MHz 3.3 — 5.5 V Operating Current (HIRC OSC, fSYS=fH, fS=fSUB=fLIRC) 3V No load, fH=12MHz, WDT enable USB disable, LVR enable — 2.2 3.3 mA — 5.0 7.5 mA IDD2 Operating Current (LIRC OSC, fSYS=fL=fLIRC, fS=fSUB=fLIRC) 3V ─ 35 70 μA — 70 100 μA IDD3 Operating Current (HIRC OSC, fSYS=fH, fS=fSUB=fLIRC) 3V — 4.8 10 mA — 11 16 mA ISTB1 Standby Current (Idle 0) (HIRC OSC, fSYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT enable, fSYS=12MHz off (FSYSON=0), Clear CLK_ADJ (SYSC.7=0) — 1.5 3.0 μA — 3.0 6.0 μA ISTB2 Standby Current (Sleep 0) (HIRC OSC, fSYS=off, fS=fSUB=fLIRC) 3V No load, system HALT, WDT disable, fSYS=12MHz, Clear CLK_ADJ (SYSC.7=0) — 0.1 1 μA — 0.3 2 μA ISUS1 Suspend Current (Sleep 0) (HIRC OSC, fSYS=off, fS=fSUB=fLIRC) — 330 400 μA Rev. 1.00 5V 5V 5V 5V 5V 5V No load, WDT enable, fLIRC=32K, Clear CLK_ADJ (SYSC.7=0) USB disable, LVR enable No load, fH=12MHz, WDT enable, USB enable, V33O on, LVR enable No load, system HALT, WDT disable, LVR disable USB transceiver, 3.3V Regulator on, clr SUSP2 (UCC.4) and clr RCTRL (UCC.7),Clear CLK_ADJ (SYSC.7=0) 10 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Symbol Parameter Test Conditions VDD Conditions No load, system HALT, WDT disable, LVR disable USB transceiver, 3.3V Regulator off, set SUSP2 (UCC.4) and set RCTRL (UCC.7),Clear CLK_ADJ (SYSC.7=0) ISUS2 Suspend Current (Sleep 0) (HIRC OSC, fSYS=off, fS=fSUB=fLIRC) VIL1 Input Low Voltage for I/O Ports, TCK and INT 5V VIH1 Input High Voltage for I/O Ports, TCK and INT 5V VIL2 Input Low Voltage (RES) — VIH2 Input High Voltage (RES) — IOL I/O Port Sink Current 5V VOL=0.4V IOH I/O Port Source Current 5V VOH=3.4V VV33O 3.3V regulator output 5V IV33O=20mA RUDN Pull-high Resistance between UDN and V33O RPH Pull-high Resistance of I/O Ports 5V — — Min. Typ. Max. Unit — 220 300 μA — 0 ─ 0.3VDD V 0 ─ 0.2VDD V 0.7VDD ─ VDD V 0.8VDD ─ VDD V — 0 ─ 0.4VDD V — 0.9VDD ─ VDD V 2 4 ─ mA -2 -4 ─ mA 3.0 3.3 3.6 V (Except VDD=5V) — (Except VDD=5V) 3.3V — -5% 1.5 +5% kΩ 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ A.C. Characteristics Ta= 25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit -3% 12 +3% MHz -10% 32 +10% kHz -50% 32 +60% kHz fSYS System clock (HIRC OSC) USB mode (USB On) 4.2V~ Ta=25°C 5.5V fLIRC System clock (32K RC) 2.2V~ Ta=-40°C to 85°C 5.5V tTCK TCKn Input Pin Minimum Pulse Width — — 0.3 — — μs tRES External Reset Minimum Low Pulse Width — — 10 — — μs tINT Interrupt Minimum Pulse Width — — 10 — — μs — fSYS=HIRC 1024 — — tSYS tSST System Start-up Timer Period (Wake-up from HALT, fSYS off at HALT state, Slow Mode → Normal Mode) — fSYS=LIRC 2 — — tSYS 5V tRSTD Rev. 1.00 Ta=25°C System Start-up Timer Period (Wakeup from HALT, fSYS on at HALT state) — — 2 — — tSYS System Reset Delay Time (Power On Reset, LVR reset, LVR S/W (LVRC) reset, WDT S/W (WDTC) reset) — — 25 50 100 ms System Reset Delay Time (Any Reset except Power On Reset, LVR reset, LVR S/W (LVRC) reset, WDT S/W (WDTC) reset) — — 8.3 16.7 33.3 ms 11 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU LVD & LVR Electrical Characteristics Ta= 25°C Test Conditions Symbol Parameter VLVR1 Low Voltage Reset Voltage VDD Conditions — LVR Enable Min. Typ. Max. Unit -5% 2.1 +5% V VLVD1 LVDEN = 1, VLVD = 2.0V 2.0 V VLVD2 LVDEN = 1, VLVD = 2.2V 2.2 V VLVD3 LVDEN = 1, VLVD = 2.4V 2.4 V VLVD4 LVDEN = 1, VLVD = 2.7V 2.7 VLVD5 Low Voltage Detector Voltage — -5% LVDEN = 1, VLVD = 3.0V 3.0 +5% V V VLVD6 LVDEN = 1, VLVD = 3.3V 3.3 V VLVD7 LVDEN = 1, VLVD = 3.6V 3.6 V VLVD8 LVDEN = 1, VLVD = 4.0V 4.0 V ILVR Additional Power Consumption if LVR is used 3V LVR disable → LVR enable 5V 3V ILVD Additional Power Consumption if LVD is used 5V 3V 5V — 30 45 μA — 60 90 μA LVD disable → LVD enable (LVR disable) — 40 60 μA — 75 115 μA LVD disable → LVD enable (LVR enable) — 30 45 μA — 60 90 μA 480 μs tLVR Low Voltage Width to Reset — — 120 240 tLVD Low Voltage Width to Interrupt — — 20 45 90 μs tSRESET Software Reset Width to Reset — — 45 90 120 μs tLVDS LVDO stable time — For LVR enable, LVD off → on — — 15 μs — For LVR disable, LVD off → on — — 15 μs Power on Reset Characteristics Ta= 25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Rise Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 1.00 12 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.00 13 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is ex ecuted except for instructions, such as "JMP" or "CALL" that demands a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter High Byte Low Byte (PCL Register) PC11~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.00 14 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 8 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 15 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. HT68FB240 0000H Reset 0004H 0024H Interrupt Vector 0FFFH 16 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD [m]" or "TABRDL [m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. Rev. 1.00 16 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "F00H" which refers to the start address of the last page within the 4K Program Memory of the microcontroller. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db? ; temporary register #1 tempreg2 db? ; temporary register #2 : mov a, 06h ; initialise low table pointer - note that this address mov tblp, a; is referenced mov a, 0Fh; initialise high table pointer mov tbhp, a : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address F06H transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address F05H transferred to tempreg2 and TBLH in this ; example the data 1AH is transferred to tempreg1 and data 0FH to ; register tempreg2 : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 17 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU In System Programming – ISP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-system using a two-line USB interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Program Memory can be programmed serially in-system using the USB interface, namely using the UDN and UDP pins. The power is supplied by the UBUS pin. The technical details regarding the in-system programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. The Flash Program Memory Read/Write function is implemented using a series of registers. Flash Memory Read/Write Page Size The Flash memory page size is 32 words. The page and buffer size are assigned as 32 words. The following diagram illustrates the Read/Write page and buffer assignment. The write buffer is controlled by the CLWB bit in the FRCR register. The CLWB bit can be set high to enable the Clear Write Buffer procedure, as the procedure is finished, this bit will be cleared to low by hardware. The Write Buffer is filled when the FWEN bit is set to high, when this bit is set high, the data in the Write buffer will be written to the Flash ROM, the FWT bit is used to indicate the writing procedure. Setting this bit high and check if the write procedure is finished, this bit will be cleared by hardware. The Read Byte can be assigned by the address. The FDEN is used to enable the read function and the FRD is used to indicate the reading procedure. When the reading procedure is finished, this bit will be cleared by hardware. Rev. 1.00 Device Page Size (Words) Write Buffer (Words) HT68FB240 (4K×16) 32 32 18 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU F�ash Memo�y W�ite Buffe� F�RH FD0H CLWB F�RL FD0L Write one word to FD0L/FD0H F�ash Memo�y F�RH FD0H F�RL FD0L Read one word to FD0L/FD0H Note: 1. Writing a data into high byte, which means the High/Low byte Data is written into Write Buffer, will cause the Flash memory address increased by one automatically and the new address will be loaded to the FARH and FARL registers. However, the user can also fill the new address by filling the data into FARH and FARL registers in the same page, then the data will be written into the corresponding address. 2. If the address already reached the boundary of the flash memory, such as 11111b of the 32 words, at this moment, the address will not be increased and the address will stop at the last address of that page and the writing data is invalid. 3. At this point, the user has to set a new address again to fill a new data. 4. If the data is writing using the write buffer, the write buffer will be cleared by hardware automatically after the write procedure is ready in 2ms. 5. First time use the Write buffer or renew the data in the Write buffer, the user can use to Clear buffer bit (CLWB) to clear write buffer. Rev. 1.00 19 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU ISP Bootloader The devices provide the ISP Bootloader function to upgrade the software in the Flash memory. The user can select to use the ISP Bootloader application software provided by Holtek IDE tool or to create his own Bootloader software. When the Holtek Bootloader software is selected, that will occupy 0.5K words area in the Flash memory. The accompanyimg diagram illustrates the Flash memory structure with Holtek Bootloader software. HT68FB240 Bootloader 0000H 0D00H 0DFFH Last Page Flash Program Memory Registers There are two address registers, four 16-bit data registers and one control register. The control register is located in Bank 1 and the other registers are located in Bank 0. Read and Write operations to the Flash memory are carried out in 16-bit data operations using the address and data registers and the control register. Several registers control the overall operation of the internal Flash Program Memory. The address registers are named FARL and FARH, the data registers are named FDnL and FDnH, and the single control register is named FCR. As the FARL and FDnL registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The FARH, FDnH, FCR and FRCR registers however, being located in Bank 1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Program Memory Register List Rev. 1.00 Bit Register Name 7 6 5 4 3 2 1 0 FARL D7 D6 D5 D4 D3 D2 D1 D0 FARH — — — — D11 D10 D9 D8 FD0L D7 D6 D5 D4 D3 D2 D1 D0 FD0H D15 D14 D13 D12 D11 D10 D9 D8 FD1L D7 D6 D5 D4 D3 D2 D1 D0 FD1H D15 D14 D13 D12 D11 D10 D9 D8 FD2L D7 D6 D5 D4 D3 D2 D1 D0 FD2H D15 D14 D13 D12 D11 D10 D9 D8 FD3L D7 D6 D5 D4 D3 D2 D1 D0 FD3H D15 D14 D13 D12 D11 D10 D9 D8 FCR CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD FRCR — — — FSWRST — — — CLWB 20 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU • FARL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: Flash Program Memory address Flash Program Memory address bit 7 ~ bit 0 • FARH Register Bit 7 6 5 4 3 2 1 0 Name — — — — D11 D10 D9 D8 R/W — — — — R/W R/W R/W R/W POR — — — — x x x x "x" unknown Bit 7~4 Unimplemented, read as "0" Bit 3~0D11~D8: Flash Program Memory address Flash Program Memory address bit 11 ~ bit 8 • FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: The first Flash ROM data The first Flash ROM data 7~0 • FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D15~D8: The first Flash ROM data The first Flash ROM data 15~8 • FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: The second Flash ROM data The second Flash ROM data 7~0 Rev. 1.00 21 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU • FD1H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D15~D8: The second Flash ROM data The second Flash ROM data 15~8 • FD2L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: The third Flash ROM data The third Flash ROM data 7~0 • FD2H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D15~D8: The third Flash ROM data The third Flash ROM data bit 15~8 • FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D7~D0: The fourth Flash ROM data The fourth Flash ROM data 7~0 • FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~0D15~D8: The fourth Flash ROM data The fourth Flash ROM data 15~8 Rev. 1.00 22 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU • FCR Register Bit 7 6 5 4 3 2 1 0 Name CFWEN FMOD2 FMOD1 FMOD0 BWT FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7CFWEN: Flash ROM Write Enable bit, FWEN, control bit 0: disable 1: unimplemented This bit is used to control the FWEN bit enable or disable. When this bit is cleared to low by software, the Flash memory write enable control bit, FWEN will be cleared to low as well. It’s ineffective to set this bit to high. The user can check this bit to confirm the FWEN status. Bit 6~4 FMOD2~FMOD0: Flash Program memory, Configuration option memory operating mode control bits 000: write memory mode 001: page erase mode 010: reserved 011: read memory mode 100: reserved 101: reserved 110: FWEN (flash memory write enable) bit control mode 111: reserved Bit 3BWT: Mode change control 0: mode change cycle has finished 1: activate a mode change cycle This bit will be automatically reset to zero by the hardware after the mode change cycle has finished. Rev. 1.00 Bit 2 FWT: Flash memory Write Control 0: write cycle has finished 1: activate a write cycle This is the Flash memory Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Bit 1 FRDEN: Flash Memory Read Enable 0: disable 1: enable This is the Flash memory Read Enable Bit which must be set high before Flash memory read operations are carried out. Clearing this bit to zero will inhibit Flash memory read operations. Bit 0 FRD: Flash memory Read Control 0: read cycle has finished 1: activate a read cycle This is the Flash memory Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the FRDEN has not first been set high. Note: The FWT, FRDEN and FRD bits can not be set to "1" at the same time with a single instruction. 23 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU • FRCR Register Bit 7 6 5 4 3 2 1 0 Name — — — FSWRST — — — CLWB R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as "0" Bit 4 FSWRST: Software Reset MCU control bit Described elsewhere Bit 3~1 unimplemented, read as "0" Bit 0 CLWB: Flash Program memory Write buffer clear control bit 0: do not initiate clear Write Buffer or clear process 1: initiate clear Write Buffer process This bit is used to control the Flash Program memory clear Write buffer process. It will be set by software and cleared by hardware. In Application Program – IAP Offering users the convenience of Flash Memory multi-programming features, the device not only provides an ISP function, but also an additional IAP function. The convenience of the IAP function is that it can execute the updated program procedure using its internal firmware, without requiring an external Program Writer or PC. In addition, the IAP interface can also be any type of communication protocol, such as UART or SPI, using I/O pins. Designers can assign I/O pins to communicate with the external memory device, including the updated program. Regarding the internal firmware, the user can select versions provided by HOLTEK or create their own. The following section illustrates the procedures regarding how to implement IAP firmware. Enable Flash Write Control Procedure The first procedure to implement the IAP firmware is to enable the Flash Write control which includes the following steps. • Write data "110" to the FMOD[2:0] bits in the FCR register to enable the Flash write control bit, FWEN. • Set the BWT bit in the FCR register to "1". • The device will start a 1ms counter. The user should write the correct data pattern into the Flash data registers, namely FD1L~FD3L and FD1H~FD3H, during this period of time. • Once the 1ms counter has overflowed or if the written pattern is incorrect, the enable Flash write control procedure will be invalid and the user should repeat the above procedure. • No matter whether the procedure is valid or not, the devices will clear the BWT bit automatically. • The enable Flash write pattern data is (00H, 04H, 0DH, 09H, C3H and 40H) and it should be written into the Flash data registers. • Once the Flash write operation is enabled, the user can update the Flash memory using the Flash control registers. • To disable the Flash write procedure, the user can only clear the CFWEN bit in the FCR register. There is no need to execute the above procedure. Rev. 1.00 24 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Set FWEN FMOD[2:0]=110 : Set FWEN bit BWT=1,Hardware set a counter Wrtie the following pattern to Flash Data register FD1L= 00h , FD1H = 04h FD2L=0dh , FD2H = 09h FD3L=C3h , FD3H = 40h no Is counter overflow? BWT=0? yes Is pattern is correct ? no yes CFWEN=1 Set FWEN bit success CFWEN=0 Set FWEN bit fail END Rev. 1.00 25 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Flash Memory Write and Read Procedures The following flow charts illustrate the Write and Read Flash memory procedures. Write Flash ROM Set FWEN procedure Page Erase FAH=xxh, FAL=xxh FMOD[2:0]=001 FWT=1 No FWT=0 ? Yes Write FMOD[2:0]=000 Write data to Write Buffer [(ROM ≤ 8K → 1~32 Words data) or (ROM > 8K → 1~64 Words data)]: Flash address register: FAH=xxh, FAL=xxh Write the following data to register: FD0L=xxh, FD0H=xxh No Write next data Write Buffer Finish? Yes FWT=1 No FWT=0 ? Yes Write Finish ? No Write next Page Yes Clear CFWEN bit END Write Flash Program ROM Procedure Rev. 1.00 26 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Read Flash ROM FMOD[2:0]=011 FDEN=1 flash address register: FAH=xxh, FAL=xxh FRD=1 no FRD=0 ? yes Read value: FD0L=xxh, FD0H=xxh no Read Finish ? yes FDEN=0 Clear CFWEN bit END Read Flash Program Procedure Rev. 1.00 27 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins Pin Description ICPDA UDN Programming Serial Data/Address ICPCK RES Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the UDN and RES pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. Note: * may be resistor or capacitor. The resistance of * must be greater than 300Ω or the capacitance of * must be less than 1nF. Rev. 1.00 28 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU On-Chip Debug Support – OCDS An EV chip exists for the purposes of device emulation. This EV chip device also provides an "On-Chip Debug" function to debug the device during the development process. The EV chip and the actual MCU device are almost functionally compatible except for the "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For a more detailed OCDS description, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-chip Debug Support Data/Address input/output Pin Description OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the FRCR, FCR, FARH and FDnH registers at address from 40H to 46H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for the device is the address 00H. 00H Bank 0 Special Purpose Data Memory 40H~46H in Bank 1 5FH 60H General Purpose Data Memory FFH Bank 0 Data Memory Structure Rev. 1.00 29 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bank 0~1 Bank 0~1 Bank 1 00H IAR0 33H TMPC 01H MP0 34H TM0C0 02H IAR1 35H TM0C1 03H MP1 36H TM0DL 04H BP 37H TM0DH 05H ACC 38H TM0AL 06H PCL 39H TM0AH 07H TBLP 3AH TM1C0 08H TBLH 3BH TM1C1 09H TBHP 3CH TM1DL 0AH STATUS 3DH TM1DH 0BH SMOD 3EH TM1AL 0CH LVDC 3FH TM1AH 0DH INTEG 40H Unused 0EH WDTC 41H Unused 0FH Unused 42H FARL FARH 10H INTC0 43H FD0L FD0H 11H INTC1 44H FD1L FD1H 12H INTC2 45H FD2L FD2H 13H Unused 46H FD3L FD3H 14H MFI0 47H USB_STAT 15H PAWU 48H UINT 16H PAPU 49H USC 17H PA 4AH UCC AWR FRCR FCR 18H PAC 4BH 19H PXWU 4CH STL 1AH PXPU 4DH SIES 1BH PB 4EH MISC 1CH PBC 4FH UFEN 1DH PC 50H FIFO0 1EH PCC 51H FIFO1 1FH PD 52H FIFO2 20H PDC 53H URDCT 21H PE 54H 22H PEC 55H 23H 56H Unused 57H Unused 58H PWMC 59H PWM0 PWM1 2CH 2DH I2CTOC 5AH 2EH SIMC0 5BH PWM2 2FH SIMC1 5CH Unused 30H SIMD 5DH CTRL 31H SIMA/SIMC2 5EH LVRC 32H SBSC 5FH SYSC : Unused, read as 00H Special Purpose Data Memory Rev. 1.00 30 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections; however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 31 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bank Pointer – BP For this device, the Data Memory is divided into two banks, Bank 0 and Bank 1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank 1 must be implemented using Indirect Addressing. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7~1 Unimplemented, read as "0" Bit 0DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Rev. 1.00 32 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.00 33 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 34 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer Function. Fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Internal High Speed RC HIRC 12MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are several oscillator sources, a high speed oscillator and a low speed oscillator. The high speed system clock is sourced from the internal 12MHz RC oscillator and the automatic adjust clock. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for the high speed and the low speed oscillators is chosen via registers. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. In addition, the internal automatic adjust frequency clock, whose clock source is supplied by the internal 12MHz RC oscillator, can be enabled by a software control bit to generate various frequencies for the USB interface and system clock. USBCKEN bit To USBCK Circuits High Speed Oscillator HIRC ÷2 6MHz fH SYSCLK Bit 6-stage Prescaler fH /2 fH /4 fH /8 SYSCLK fSYS fH /16 fH /32 Low Speed Oscillator LIRC fL fH /64 HLCLK, CKS2~ CKS0 bits System Clock Configurations Rev. 1.00 35 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SYSC Register Bit 7 6 5 4 3 2 1 0 Name CLK_ADJ — — — — — — — R/W R/W — — — — — — — POR 1 — — — — — — — Bit 7 CLK_ADJ: Automatic Clock adjusts function 0: disable 1: enable (default) Note that if the user selects the HIRC as the system clock, the CLK_ADJ bit must be set to "1" to adjust the clock frequency automatically. Bit 6~0 Unimplemented, read as "0" UCC Register Bit 7 6 5 4 3 2 1 0 Name Rctrl SYSCLK — SUSP2 USBCKEN — EPS1 EPS0 R/W R/W R/W — R/W R/W — R/W R/W POR 0 0 — 0 0 — 0 0 Bit 7Rctrl: 7.5kΩ resistor between UDN and UBUS control bit Described elsewhere Bit 6 SYSCLK: Specify MCU oscillator frequency indication bit 0: 12MHz 1: 6MHz Bit 5 Unimplemented, read as "0" Bit 4 SUSP2: Reduce power consumption in suspend mode control bit Described elsewhere Bit 3 USBCKEN: USB clock control bit 0: disable 1: enable Bit 2 Unimplemented, read as "0" Bit 1~0 EPS1, EPS0: Accessing endpoint FIFO selection Described elsewhere USBCKEN USB SIE HIRC 12MHz 1/2 6MHz MUX (See Table) fH SYSCLK SYSCLK fH 0 12MHz 1 6MHz High frequency system clock fH configure Rev. 1.00 36 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins are free for use as normal I/O pins. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.00 37 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU USBCKEN bit To USBCK Circuits High Speed Oscillator HIRC ÷2 6MHz fH SYSCLK Bit 6-stage Prescaler fH /2 fH /4 fSYS fH /8 SYSCLK fH /16 fH /32 Low Speed Oscillator fH /64 fL LIRC HLCLK, CKS2~ CKS0 bits fSUB WDT System Clock Configuration Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode Rev. 1.00 Description CPU fSYS fSUB NORMAL Mode on fH~fH/64 on SLOW Mode on fL on IDLE0 Mode off off on IDLE1 Mode off on on SLEEP0 Mode off off off SLEEP1 Mode off off on 38 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator, LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB clock will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to "0". If the LVDEN is set to "1", it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB clock will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will be stopped, the low frequency clock fSUB will be on. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the low frequency clock fSUB will be on. Rev. 1.00 39 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5CKS2~CKS0: The system clock selection when HLCLK is "0" 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0" Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 2 clock cycles if the LIRC oscillator is used. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 32 clock cycles if the HIRC oscillator is used. Bit 1IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2~fH/64 or fL clock is used as the system clock. When the bit is high the f H clock will be selected and if low the fH/2~fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Rev. 1.00 40 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 1.00 41 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to "0" and set the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.00 42 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and WDT clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 43 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and fSUB clock will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 44 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator is enabled. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred microamps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external or USB reset • An external falling edge on Ports • A system interrupt • A WDT overflow If the system is woken up by an external or USB reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Ports can be setup using the PAWU and PXWU registers to permit a negative transition on the pin to wake-up the system. When a Port pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 45 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and the HIRC oscillator needs to start-up from an off state. The LIRC oscillator uses the SST counter after HIRC oscillator has finished its SST period. • If the device is woken up from the SLEEP0 Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is "1". • There are peripheral functions, such as WDT, TMs and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. • The on/off condition of fL depends upon whether the WDT is enabled or disabled as the WDT clock source is generated from fL. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fSUB, which is sourced from the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The WDT function is allowed to enable or disable by setting the WDTC register data. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. The WRF software reset flag will be indicated in the CTRL register. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control 10101: disable 01010: enable Other: reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1 to indicate the reset source. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the time-out period. Rev. 1.00 46 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode 0: disable 1: enable Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag Described elsewhere Bit 1LRF: LVR Control register software reset flag Described elsewhere Bit 0WRF: WDT Control register software reset flag 0: not occur 1: occurred This bit is set to 1 by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. WDT Enable/Disabled using the WDT Control Register The WDT is enabled/disabled using the WDT control register, the WE4~WE0 values can determine which mode the WDT operates in. The WDT will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bit value is equal to 01010B. If the WE4~WE0 bits are set to any other values other than 01010B and 10101B, it will reset the device after 2~3 LIRC clock cycles. After power on these bits will have the value of 01010B. WDT Configuration Option Controlled by WDT Control Register WE4~WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the Rev. 1.00 47 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Register WE4~WE0 bits Reset MCU CLR “HALT” Instruction “CLR WDT” Instruction LIRC fSUB fSUB/28 8-stage Divider WDT Prescaler 8-to-1 MUX WS2~WS0 WDT Time-out (28/fSUB~218/fSUB) Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. A hardware reset will of course be automatically implemented after the device is powered on, however there is a number of other hardware and software reset sources that can be implemented dynamically when the device is running. Reset Overview The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program instructions commence execution. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. The devices provide several reset sources to generate the internal reset signal, providing extended MCU protection. The different types of resets are listed in the accompanying table. Reset Name Abbreviation Indication Bit Register Notes Power-On Reset POR Reset Pin RES — — Hardware Reset Low-Voltage Reset LVR LRF CTRL Low VDD voltage Watchdog Reset — — Auto generated at power on WDT TO STATUS WDTC Register Setting Software Reset — WRF CTRL Write to WDTC register LVRC Register Setting Software Reset — LRF CTRL Write to LVRC register Reset Source Summary Rev. 1.00 48 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. Power-On Reset Timing Chart RES Pin Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. Rev. 1.00 49 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU External RES Circuit Note: * It is recommended that this component is added for added ESD protection. ** It is recommended that this component is added in environments where power line noise is significant. More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point. RES Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provide an MCU reset should the value fall below a certain predefined level. LVR Operation The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Low Voltage Reset Timing Chart Rev. 1.00 50 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V (default) 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Any other value: Generates MCU reset – LVRC register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock cycles. However in this situation the register contents will be reset to the POR value. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag 0: not occur 1: occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to 0 by the application program. Bit 1LRF: LVR Control register software reset flag 0: not occur 1: occurred This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to 0 by the application program. Bit 0WRF: WDT Control register software reset flag Described elsewhere Rev. 1.00 51 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to "1". WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during Sleep Timing Chart WDTC Register Software Reset A WDTC software reset will be generated when a value other than "10101" or "01010", exist in the highest five bits of the WDTC register. The WRF bit in the CTRL register will be set high when this occurs, thus indicating the generation of a WDTC software reset. • WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control 10101: disable 01010: enable (default) Other: reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the CTRL register will be set to 1 to indicate the reset source. Bit 2~0WS2~WS0: WDT time-out period selection Described elsewhere Rev. 1.00 52 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Software Reset Control The devices provide the ability to control the MCU reset function enable or not by software option. This function is managed by the FSWRST bit in the FRCR register. • FRCR Register Bit 7 6 5 4 3 2 1 0 Name — — — FSWRST — — — CLWB R/W — — — R/W — — — R/W POR — — — 0 — — — 0 Bit 7~5 Unimplemented, read as "0" Bit 4 FSWRST: Software Reset MCU control bit 0: MCU reset enable 1: MCU reset disable (except power on reset) This control bit is used to setup the reset action of MCU when there is a reset signal detected by the USB SIE. If this bit is set to "0", the MCU reset will happen and if this bit is set to "1", then the reset signal will be bypassed, the MCU will not be reset. Note that the power on reset will not be controlled by the FSWRST bit. Bit 3~1 unimplemented, read as "0" Bit 0 CLWB: Flash Program memory Write buffer clear control bit Described elsewhere Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF Reset Conditions 0 0 Power-on reset u u RES, LVR or USB reset during Normal or SLOW Mode operation 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.00 Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 53 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBHP - - - - STATUS - - 0 0 x x x x --1u uuuu --uu uuuu --01 uuuu --11 uuuu --uu uuuu --uu uuuu x x x x ---- - - 0 - - - - uuuu ---- uuuu ---- - - - 0 - - - - uuuu - - - - 0000 ---- - - - u - - - - uuuu ---- 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0 0 0 - 0 0 11 uuu- uuuu 0 0 0 - 0 0 11 0 0 0 - 0 0 11 0000 ---- - - - 0 - - - - uuuu ---- BP 0000 ---- - - - 0 - - - - uuuu ---- SMOD 0000 ---- - - - 0 - - - - uuuu ---- 0000 ---- - - - 0 INTEG ---- LVDC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu --00 -000 --00 -000 0000 WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 u u u u u u u u 0 1 0 1 0 0 11 0 1 0 1 0 0 11 INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 INTC1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 INTC2 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 MFI0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAWU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PAPU 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PXWU -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 PXPU -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PCC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PD 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PDC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 PE - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - u u - - - - - - 11 - - - - - - 11 PEC - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - 11 - - - - - - u u - - - - - - 11 - - - - - - 11 I2CTOC 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SIMC0 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - 111 0 0 0 0 - uuuu uuu- 111 0 0 0 0 - 111 0 0 0 0 - SIMC1 1000 0001 1000 0001 1000 0001 1000 0001 uuuu uuuu 1000 0001 1000 0001 SIMD xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx SIMA/ SIMC2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 SBSC 0 - 0 0 TMPC --01 - - - - 0 - 0 0 --01 --01 - - - - 0 - 0 0 --01 --01 - - - - 0 - 0 0 --01 --01 - - - - u - u u --01 --uu - - - - 0 - 0 0 --uu --01 - - - - 0 - 0 0 --01 --01 - - - --01 TM0C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0DH - - - - TM0AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM0AH - - - - Rev. 1.00 - - 0 0 - - - - - 0 0 - - - - - - 0 0 - - - - - 0 0 - - - - - - 0 0 - - - - - 0 0 - - - - 54 - - 0 0 - - - - - 0 0 - - - - - - u u - - - - - u u - - - - - - 0 0 - - - - - 0 0 - - - - - - 0 0 - - 0 0 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* USB-reset (Normal) USB-reset (HALT) TM1C0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1C1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 TM1DH - - - - TM1AL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 TM1AH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - u u - - - - - - 0 0 - - - - - - 0 0 FRCR - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - u - - - u - - - 0 - - - 0 - - - 0 - - - 0 FCR 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FARL xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FARH - - - - FD0L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx x x x x - - - - x x x x - - - - x x x x - - - - x x x x ---- uuuu - - - - x x x x - - - - x x x x FD0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD2H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx FD3H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx USB_ STAT 11 x x 0 0 0 - uuxx 00u- uuxx 00u- uuxx 00u- uuxx 00u- uuxx 00u- uuxx 00u- UINT -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu -000 -000 -000 -000 USC 10-0 x0xx uu-u xuxx uu-u xuxx uu-u xuxx uu-u xuxx uu-u 0100 uu-u 0100 UCC 00-0 0-xx uu-u u-xx uu-u u-xx uu-u u-xx uu-u u-uu uu-u u-00 uu-u u-00 AWR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 STL -xxx SIES xx-x xxxx xx-x xxxx xx-x xxxx xx-x xxxx xx-x xxxx 00-0 0000 00-0 0000 -xxx -xxx -xxx xxx- -xxx -xxx -xxx xxx- -xxx -xxx -xxx xxx- -xxx -xxx -xxx xxx- -xxx -000 -000 -000 -000 MISC xxx- UFEN -00- -000 -uu- -uuu -00- -000 -00- -000 -uu- -uuu -00- -000 -00- -000 -xxx 000- -000 000- -000 FIFO0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx FIFO2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx URDCT xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu 0000 0000 0000 0000 PWMC 0--- PWM0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 -000 0--- -000 0--- -000 0--- -000 u--- -uuu 0--- -000 0--- -000 PWM1 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 PWM2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 CTRL 0--- LVRC 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu 0101 0101 0101 0101 SYSC 1 - - - -x00 0--- - - - 1 - - - -x00 0--- - - - 1 - - - -x00 0--- - - - 1 - - - -x00 u--- - - - u - - - -xuu 0--- - - - 1 - - - -x00 0--- - - - 1 - - - -x00 - - - - Note: "u" stands for unchanged "x" stands for unknown "-" stands for unimplemented Rev. 1.00 55 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PE. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PXWU — PELWU PDHWU PDLWU PCHWU PCLWU PBHWU PBLWU PXPU — PELPU PDHPU PDLPU PCHPU PCLPU PBHPU PBLPU PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PE — — — — — — PE1 PE0 PEC — — — — — — PEC1 PEC0 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU and PXPU, and are implemented using weak PMOS transistors. PAPU Register Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAPU7~PAPU0: Port A bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable Rev. 1.00 56 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU PXPU Register Bit 7 6 5 4 3 2 1 0 Name — PELWU PDHWU PDLWU PCHWU PCLWU PBHWU PBLWU R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 PELPU: PE1~PE0 pins Pull-High control 0: Disable 1: Enable Bit 5PDHPU: PD7~PD4 pins Pull-High control 0: Disable 1: Enable Bit 4 PDLPU: PD3~PD0 pins Pull-High control 0: Disable 1: Enable Bit 3 PCHPU: PC7~PC4 pins Pull-High control 0: Disable 1: Enable Bit 2 PCLPU: PC3~PC0 pins Pull-High control 0: Disable 1: Enable Bit 1 PBHPU: PB7~PB4 pins Pull-High control 0: Disable 1: Enable Bit 0 PBLPU: PB3~PB0 pins Pull-High control 0: Disable 1: Enable Port Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A ~ Port E pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A ~ Port E can be selected respectively to have this wake-up feature using the PAWU and PXWU registers. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU7~PAWU0: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable Rev. 1.00 57 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU PXWU Register Bit 7 6 5 4 3 2 1 0 Name — PELPU PDHPU PDLPU PCHPU PCLPU PBHPU PBLPU R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 PELWU: PE1~PE0 pins Wake-up control 0: Disable 1: Enable Bit 5 PDHWU: PD7~PD4 pins Wake-up control 0: Disable 1: Enable Bit 4 PDLWU: PD3~PD0 pins Wake-up control 0: Disable 1: Enable Bit 3 PCHWU: PC7~PC4 pins Wake-up control 0: Disable 1: Enable Bit 2 PCLWU: PC3~PC0 pins Wake-up control 0: Disable 1: Enable Bit 1 PBHWU: PB7~PB4 pins Wake-up control 0: Disable 1: Enable Bit 0 PBLWU: PB3~PB0 pins Wake-up control 0: Disable 1: Enable Note: I/O port slew rate always 200ns in HT68FB240. If the SIM function is enabled, SPI/I2C function pin slew rate is kept 0 ns. I/O Port Control Registers Each I/O port has its own control register known as PAC~PEC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PAC7~PAC0: Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. 1.00 58 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU PBC Register Bit 7 6 5 4 3 2 1 0 Name PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PBC7~PBC0: Port B bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PCC Register Bit 7 6 5 4 3 2 1 0 Name PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PCC7~PCC0: Port C bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PDC Register Bit 7 6 5 4 3 2 1 0 Name PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PDC7~PDC0: Port D bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input PEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — PEC1 PEC0 R/W — — — — — — R/W R/W POR — — — — — — 1 1 Bit 7~2 Unimplemented, read as "0" Bit 1~0PEC1~PEC0: Port E bit 1 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. 1.00 59 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PEC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PE, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. All Ports provide the wake-up function which can be set by individual pin in the Port A while it has to be set by nibble pins in the Port B, Port C, Port D and Port E. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a voltage level transition on any of the Port pins. Single or multiple pins on Ports can be setup to have this function. Rev. 1.00 60 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Compare Match Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. Introduction The device contains two TMs having a reference name of TM0 and TM1. The TMs can be categorised as Compact Type TM. The main features of CTMs are summarised in the accompanying table. Function CTM Timer/Counter √ Compare Match Output √ PWM Channels 1 PWM Alignment Edge PWM Adjustment Period & Duty Duty or Period This chip contains a specific number of Compact Type TM unit which is shown in the table together with their individual reference names, TM0~TM1. Device TM0 TM1 HT68FB240 10-bit CTM 10-bit CTM TM Name/Type Reference TM Operation The TM offers a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fLIRC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. Rev. 1.00 61 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU TM Interrupts The Compact Type TMs have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have more output pins with the label TPn, TPnB. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn or TPnB output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. Device CTM Register HT68FB240 TP0, TP0B TP1, TP1B TMPC TM Output Pins TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared functions is implemented using one register with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output if reset to zero the pin will retain its original other functions. TMPC Register Bit 7 6 5 4 3 2 1 0 Name — — T1CP1 T1CP0 — — T0CP1 T0CP0 R/W — — R/W R/W — — R/W R/W POR — — 0 1 — — 0 1 Bit 7~6 Unimplemented, read as "0" Bit 5T1CP1: TP1B pin control 0: Disable 1: Enable Bit 4T1CP0: TP1 pin control 0: Disable 1: Enable Bit 3~2 Unimplemented, read as "0" Bit 1T0CP1: TP0B pin control 0: Disable 1: Enable Bit 0T0CP: TP0 pin control 0: Disable 1: Enable Rev. 1.00 62 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU TM0 & TM1 Function Pin Control Block Diagram Rev. 1.00 63 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA register is implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA low byte register, named TMxAL, using the following access procedures. Accessing the CCRA low byte register without following these access procedures will result in unpredictable values. The following steps show the read and write procedures: • Writing Data to CCRA ♦♦ Step 1. Write data to Low Byte TMxAL – Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte TMxAH – Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA ♦♦ Step 1. Read data from the High Byte TMxDH or TMxAH – Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte TMxDL or TMxAL – This step reads data from the 8-bit buffer. Rev. 1.00 64 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. These two external output pins can be the same signal or the inverse signal. Name TM No. TM Input Pin TM Output Pin 10-bit CTM 0, 1 TCK0, TCK1 TP0, TP0B TP1, TP1B Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared the highest three bits in the counter while the CCRA is the ten bits and therefore compares all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Block Digram (n=0, 1) Rev. 1.00 65 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH — — — — — — D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH — — — — — — D9 D8 Compact TM Register List (n=0, 1) TMnC0 Register (n=0, 1) Bit 7 6 5 4 3 2 1 0 Name TnPAU TnCK2 TnCK1 TnCK0 TnON TnRP2 TnRP1 TnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TnPAU: TMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fLIRC 101: Undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fLIRC are other internal clocks, the details of which can be found in the oscillator section. Bit 3TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM Rev. 1.00 66 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Bit 2~0 TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register (n=0, 1) Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnDPX TnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 TnM1, TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4 TnIO1, TnIO0: Select TPn, TPnB output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both 67 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the TnON bit from low to high. In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running. Bit 3TnOC: TPn, TPnB Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2TnPOL: TPn, TPnB Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn, TPnB output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Rev. 1.00 68 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU TMnDL Register (n=0, 1) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register (n=0, 1) Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 TMnAL Register (n=0, 1) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7~0D7~D0: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 TMnAH Register (n=0, 1) Bit Rev. 1.00 7 6 5 4 3 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 D9~D8: TMn CCRA High Byte Register bit 1 ~ bit 0 TMn 10-bit CCRA bit 9 ~ bit 8 69 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Rev. 1.00 70 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Counte� Va�ue Counte� ove�f�ow CCRP=0 0x3FF TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counte� c�ea�ed by CCRP va�ue CCRP > 0 Counte� Resta�t Resume CCRP Pause CCR� Sto� Time TnON TnP�U TnPOL CCRP Int. F�ag TnPF CCR� Int. F�ag Tn�F TM O/P Pin Out�ut �in set to initia� Leve� Low if TnOC=0 Out�ut not affected by Tn�F f�ag. Remains High unti� �eset by TnON bit Out�ut Togg�e with Tn�F f�ag He�e TnIO [1:0] = 11 Togg�e Out�ut se�ect Note TnIO [1:0] = 10 �ctive High Out�ut se�ect Out�ut Inve�ts when TnPOL is high Out�ut Pin Reset to Initia� va�ue Out�ut cont�o��ed by othe� �in-sha�ed function Compare Match Output Mode – TnCCLR = 0 (n=0, 1) Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.00 71 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Counte� Va�ue TnCCLR = 1; TnM [1:0] = 00 CCR� = 0 Counte� ove�f�ow CCR� > 0 Counte� c�ea�ed by CCR� va�ue 0x3FF CCR�=0 Resume CCR� Pause Sto� Counte� Resta�t CCRP Time TnON TnP�U TnPOL No Tn�F f�ag gene�ated on CCR� ove�f�ow CCR� Int. F�ag Tn�F CCRP Int. F�ag TnPF TnPF not gene�ated Out�ut does not change TM O/P Pin Out�ut �in set to initia� Leve� Low if TnOC=0 Out�ut not affected by Tn�F f�ag. Remains High unti� �eset by TnON bit Out�ut Togg�e with Tn�F f�ag He�e TnIO [1:0] = 11 Togg�e Out�ut se�ect Note TnIO [1:0] = 10 �ctive High Out�ut se�ect Out�ut Inve�ts when TnPOL is high Out�ut Pin Reset to Initia� va�ue Out�ut cont�o��ed by othe� �in-sha�ed function Compare Match Output Mode – TnCCLR = 1 (n=0, 1) Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.00 72 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to "11" respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to "10" respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b and CCRA = 128, The CTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. 10-bit CTM, PWM Mode, Edge-aligned Mode, TnDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.00 73 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Counte� Va�ue TnDPX = 0; TnM [1:0] = 10 Counte� c�ea�ed by CCRP Counte� Reset when TnON �etu�ns high CCRP Pause Resume CCR� Counte� Sto� if TnON bit �ow Time TnON TnP�U TnPOL CCR� Int. F�ag Tn�F CCRP Int. F�ag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cyc�e set by CCR� PWM Pe�iod set by CCRP PWM �esumes o�e�ation Out�ut cont�o��ed by Out�ut Inve�ts othe� �in-sha�ed function when TnPOL = 1 PWM Mode – TnDPX = 0 (n=0, 1) Note: 1. Here TnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.00 74 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Counte� Va�ue TnDPX = 1; TnM [1:0] = 10 Counte� c�ea�ed by CCR� Counte� Reset when TnON �etu�ns high CCR� Pause Resume CCRP Counte� Sto� if TnON bit �ow Time TnON TnP�U TnPOL CCRP Int. F�ag TnPF CCR� Int. F�ag Tn�F TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cyc�e set by CCRP PWM Pe�iod set by CCR� PWM �esumes o�e�ation Out�ut cont�o��ed by Out�ut Inve�ts othe� �in-sha�ed function when TnPOL = 1 PWM Mode – TnDPX = 1 (n=0, 1) Note: 1. Here TnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.00 75 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Serial Interface Module – SIM This device contains a Serial Interface Module, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pinshared I/O are selected using pull-high control registers, and also if the SIM function is enabled. There is one control register associated with the serial interface control, namely SBSC. This is used to enable the SIM WCOL function and I2C debounce selection. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMC0 and SIMC2 registers. After the SPI option has been selected, it can also be additionally disabled or enabled using the SIMEN bit in the SIMC0 register. SPI Master/Slave Connection Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. Rev. 1.00 76 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SPI Block Diagram The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge • WCOL and CSEN bit enabled or disable select The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. SPI Registers There are four internal registers which control the overall operation of the SPI interface. These are the SIMD data register and three registers SIMC0, SIMC2 and SBSC. Note that the SIMC1 register is only used by the I2C interface. Bit Register Name 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — — SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. The SIM_WCOL bit in the SBSC register is used to control the SPI WCOL function. Rev. 1.00 77 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown There are also three control registers for the SPI interface, SIMC0, SIMC2 and SBSC. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/ disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: I/O mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the 78 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as "0" SIMC2 Register Bit Rev. 1.00 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 D7, D6: Undefined bit This bit can be read or written by user software program. Bit 5 CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option. Bit 1 WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option. 79 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 0 TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set "1" automatically when an SPI data transmission is completed, but must set to "0" by the application program. It can be used to generate an interrupt. SBSC Register Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL — I2CDB1 I2CDB0 — — — — R/W R/W — R/W R/W — — — — POR 0 — 0 0 — — — — Bit 7 SIM_WCOL: SIM WCOL control bit 0: Disable 1: Enable Bit 6 Unimplemented, read as "0" Bit 5~4 I2CDB1~I2CDB0: I2C debounce selection bits Related to I2C function, described elsewhere Bit 3~0 Unimplemented, read as "0" SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing Rev. 1.00 80 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SPI Slave Mode Timing – CKEG=0 SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.00 81 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SPI Bus Enable/Disable To enable the SPI bus, set CSEN= 1 and SCS= 0, then wait for data to be written into the SIMD (TXRX buffer) register. For the Master Mode, after data has been written to the SIMD (TXRX buffer) register, then transmission or reception will start automatically. When all the data has been transferred, the TRF bit should be set. For the Slave Mode, when clock pulses are received on SCK, data in the TXRX buffer will be shifted out or data on SDI will be shifted in.To disable the SPI bus, the SCK, SDI, SDO and SCS will become I/O pins or the other functions. SPI Operation All communication is carried out using the 4-line interface for either Master or Slave Mode.The CSEN bit in the SIMC2 register controls the overall function of the SPI interface. Setting this bit high will enable the SPI interface by allowing the SCS line to be active, which can then be used to control the SPI interface. If the CSEN bit is low, the SPI interface will be disabled and the SCS line will be an I/O pin or the other functions and can therefore not be used for control of the SPI interface. If the CSEN bit and the SIMEN bit in the SIMC0 are set high, this will place the SDI line in a floating condition and the SDO line high. If in Master Mode the SCK line will be either high or low depending upon the clock polarity selection bit CKPOLB in the SIMC2 register. If in Slave Mode the SCK line will be in a floating condition. If the SIMEN bit is low, then the bus will be disabled and SCS, SDI, SDO and SCK will all become I/O pins or the other functions. In the Master Mode the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written into the SIMD register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission and reception. The following sequences show the order to be followed for data transfer in both Master and Slave Mode: Master Mode • Step 1 Select the SPI Master mode and clock source using the SIM2~SIM0 bits in the SIMC0 control register. • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Slave device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then use the SCK and SCS lines to output the data. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Rev. 1.00 82 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Slave Mode • Step 1 Select the SPI Slave mode using the SIM2~SIM0 bits in the SIMC0 control register • Step 2 Setup the CSEN bit and setup the MLS bit to choose if the data is MSB or LSB first, this setting must be the same with the Master device. • Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface. • Step 4 For write operations: write the data to the SIMD register, which will actually place the data into the TXRX buffer. Then wait for the master clock SCK and SCS signal. After this, go to step5. For read operations: the data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register. • Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4. If equal to zero then go to the following step. • Step 6 Check the TRF bit or wait for a SPI serial bus interrupt. • Step 7 Read data from the SIMD register. • Step 8 Clear TRF. • Step 9 Go to step 4. Error Detection The WCOL bit in the SIMC2 register is provided to indicate errors during data transfer. The bit is set by the SPI serial Interface but must be cleared by the application program. This bit indicates a data collision has occurred which happens if a write to the SIMD register takes place during a data transfer operation and will prevent the write operation from continuing. The overall function of the WCOL bit can be disabled or enabled by the SIM_WCOL bit in the SBSC register. Rev. 1.00 83 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For this device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will have no effect. A configuration option exists to allow a clock other than the system clock to drive the I2C interface. Another configuration option determines the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r Rev. 1.00 84 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SBSC, one address register SIMA and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. The I2CDB0 and I2CDB1 in the SBSC register are used to select the I2C debounce time. Bit Register Name 7 SIMC0 SIMC1 6 5 4 3 2 1 0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SBSC SIM_WCOL — I2CDB1 I2CDB0 — — — — I2C Registers List SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: I/O mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 85 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as "0" SIMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8 bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. 2 86 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 2 SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable This bit should be set to "1" to enable I2C address match wake up from SLEEP or IDLE Mode. Bit 0 RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1" . When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Rev. 1.00 87 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SIMA Register Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x 0 "x" unknown Bit 7~1 IICA6~IICA0: I2C slave address IICA6~ IICA0 is the I2C slave address bit 6 ~ bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. SBSC Register Bit 7 6 5 4 3 2 1 0 Name SIM_WCOL — I2CDB1 I2CDB0 — — — — R/W R/W — R/W R/W — — — — POR 0 — 0 0 — — — — Bit 7 SIM_WCOL: SIM WCOL control bit Related to SPI, described elsewhere Bit 6 Unimplemented, read as "0" Bit 5~4 I2CDB1~I2CDB0: I2C debounce selection bits 00: No debounce (default) 01: 1 system clock debounce 10: 2 system clocks debounce 11: 2 system clocks debounce Bit 3~0 Unimplemented, read as "0" I2C Block Diagram Rev. 1.00 88 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to "1" to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register SIMA. • Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. I2C Bus Initialisation Flow Chart I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Rev. 1.00 89 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Bus Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". I2C Bus Data and Acknowledge Signal The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Rev. 1.00 90 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Communication Timing Diagram Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus ISR Flow Chart Rev. 1.00 91 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU I2C Time Out Operation The time-out counter will start counting when the I2C interface received the START bit and address match. After that the counter will be cleared on each falling edge of the SCL pin. If the time counter is larger than the selected time-out time, then the anti-locked protection scheme will take place and the time-out counter will be stopped by hardware automatically, the I2CTOF bit will be set high and an I2C interrupt will also take place. Note that this scheme can also be stopped when the I2C received the STOP bit. There are several time-out periods can be selected by the I2CTOS0~I2CTOS5 bits in the I2CTOC register. I2CTOC Register Rev. 1.00 Bit 7 6 Name I2CTOEN I2CTOF 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0 Bit 7 I2CTOEN: I2C Time Out function control bit 0: Disable 1: Enable Bit 6 I2CTOF: I2C Time Out indication bit 0: Not occurred 1: Occurred Bit 5~0 I2CTOS5~I2CTOS0: I2C Time out time period select The I2C Time out clock is provided by the fL/32. The time out time period can be calculated from the accompanying equation. ([I2CTOS5:I2CTOS0] + 1) × (32/fL) 92 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to "1" enables the Peripheral Clock, setting PCKEN bit to "0" disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode, this will disable the Peripheral Clock output. SIMC0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN — R/W R/W R/W R/W R/W R/W R/W R/W — POR 1 1 1 0 0 0 0 — Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: I/O mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 PCKEN: PCK Output Pin Control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be in a floating condition and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program. Bit 0 Unimplemented, read as "0" 93 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Pulse Width Modulator The device contains three Pulse Width Modulation outputs, PWM0, PWM1 and PWM2. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. PWM Operation The device has three PWM registers, PWM0, PWM1 and PWM2, where the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modulation cycle is modulated into four/two individual modulation sub-sections, known as the 6+2/7+1 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. For the device, the PWM clock source is the system clock fSYS. This method of dividing the original modulation cycle into a further 2/4 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty fSYS/64 for (6+2) bits mode fSYS/128 for (7+1) bits mode fSYS/256 [PWM]/256 PWMC Register Bit 7 6 5 4 3 2 1 0 Name PWMM — — — — PWM2C PWM1C PWM0C R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7PWMM: PWM mode selection 0: (6+2) mode 1: (7+1) mode Bit 6~3 Unimplemented, read as "0" Bit 2PWM2C: PWM2 control bit 0: Disable 1: Enable Bit 1PWM1C: PWM1 control bit 0: Disable 1: Enable Bit 0PWM0C: PWM0 control bit 0: Disable 1: Enable Rev. 1.00 94 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU 6+2 PWM Mode Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as "i" in the table. Each one of these four subcycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM, PWM0, PWM1 or PWM2 register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit 2~bit 7 is denoted here as the DC value. The second group which consists of bit 0~bit 1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation subcycles is shown in the following table. The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. Parameter AC (0~3) DC (Duty Cycle) Modulation cycle i (i=0~3) i < AC (DC+1)/64 i ≥ AC DC/64 6+2 PWM Mode PWM Register for 6+2 Mode Rev. 1.00 95 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU 7+1 PWM Mode Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles known as modulation cycle 0 ~ modulation cycle 1, denoted as "i" in the table. Each one of these two subcycles contains 128 clock cycles. In this mode, a modulation frequency increase of two is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit 1~bit 7 is denoted here as the DC value. The second group which consists of bit 0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. Parameter AC (0~1) DC (Duty Cycle) Modulation cycle i (i=0~1) i < AC (DC+1)/128 i ≥ AC DC/128 7+1 PWM Mode PWM Register for 7+1 Mode Rev. 1.00 96 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU PWM Output Control On the device, the PWM outputs are pin-shared with pins PC4, PC5 and PC6. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be selected. A "0" must also be written to the corresponding bits in the I/O port control register PCC to ensure that the required PWM output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a "1" to the corresponding bit in the PC output data register will enable the PWM data to appear on the pin. Writing a "0" to the corresponding bit in the PC output data register will disable The PWM output function and force the output low. In this way, the Port C data output register can be used as an on/ off control for the PWM function. Note that if the configuration options have selected the PWM function, but a "1" has been written to its corresponding bit in the PCC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. PWM Programming Example The following sample program shows how the PWM outputs are setup and controlled. Before use the corresponding PWM output configuration options must first be selected. mov a,64h ; setup PWM value of 100 decimal which is 64H mov pwm0,a set pwmc.7 ; select the 7+1 PWM mode set pwmc.0 ; setup PWM0 shared with PC4 clr pcc.4; setup pin PC4 as an output set pc.4 ; PC.4=1; enable the PWM output : : clr pc.4 ; disable the PWM output _ PC4 will remain low Rev. 1.00 97 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INTn pin, while the internal interrupts are generated by various internal functions such as TMs, LVD, SIM and USB. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0 register which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Notes EMI — — Global INTn Pin INTnE INTnF n=0~1 Multi-function MF0E MF0F — SIM SIME SIMF — LVD LVE LVF — TnPE TnPF n=0~1 TnAE TnAF n=0~1 USB SIE USBE USBF — USB Setup Token USTE USTF — USB Endpoint 0 IN Token UITE UITF — USB Endpoint 0 OUT Token UOTE UOTF — TM Interrupt Register Bit Naming Conventions Interrupt Register Contents Rev. 1.00 Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — USBF INT1F INT0F USBE INT1E INT0E EMI INTC1 — UOTF UITF USTF — UOTE UITE USTE INTC2 — LVF SIMF MF0F — LVE SIME MF0E MFI0 T1AF T1PF T0AF T0PF T1AE T1PE T0AE T0PE 98 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2INT1S1~INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges Bit 1~0INT0S1~INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: both rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — USBF INT1F INT0F USBE INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 USBF: USB SIE Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 Interrupt Request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 USBE: USB SIE Interrupt Control 0: Disable 1: Enable Bit 2 INT1E: INT1 Interrupt Control 0: Disable 1: Enable Bit 1INT0E: INT0 Interrupt Control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable Rev. 1.00 99 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU INTC1 Register Bit 7 6 5 4 3 2 1 0 Name — UOTF UITF USTF — UOTE UITE USTE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 2 1 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unimplemented, read as "0" UOTF: USB Endpoint 0 OUT Token Interrupt Request Flag 0: No request 1: Interrupt request UITF: USB Endpoint 0 IN Token Interrupt Request Flag 0: No request 1: Interrupt request USTF: USB Setup Token Interrupt Request Flag 0: No request 1: Interrupt request Unimplemented, read as "0" UOTE: USB Endpoint 0 OUT Token Interrupt Control 0: Disable 1: Enable UITE: USB Endpoint 0 IN Token Interrupt Control 0: Disable 1: Enable USTE: USB Setup Token Interrupt Control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 Name — LVF SIMF MF0F — LVE SIME MF0E R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6LVF: LVD Interrupt Request Flag 0: No request 1: Interrupt request Bit 5 SIMF: SIM Interrupt Request Flag 0: No request 1: Interrupt request Bit 4MF0F: Multi-function Interrupt 0 Request Flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2LVE: LVD Interrupt Control 0: Disable 1: Enable Bit 1SIME: SIM Interrupt Control 0: Disable 1: Enable Bit 0MF0E: Multi-function Interrupt 0 Control 0: Disable 1: Enable Rev. 1.00 100 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name T1AF T1PF T0AF T0PF T1AE T1PE T0AE T0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7T1AF: TM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 6T1PF: TM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 5T0AF: TM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4T0PF: TM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3T1AE: TM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 2T1PE: TM1 Comparator P match interrupt control 0: Disable 1: Enable Bit 1T0AE: TM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0T0PE: TM0 Comparator P match interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector, if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Rev. 1.00 101 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU The various interrupt enable bits, together with their associated request flags, are shown in the Accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. EMI auto disabled in ISR Legend xxF Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits TM0P T0PF T0PE TM0A T0AF T0AE TM1P T1PF T1PE TM1A T1AF T1AE Interrupts contained within Multi-Function Interrupts Interrupt Name INT0 Pin Request Flags INT0F Enable Bits INT0E Master Enable EMI Vector INT1 Pin INT1F INT1E EMI 08H USB SIE USBF USBE EMI 0CH USB Setup Token USTF USTE EMI 10H USB Endpoint 0 UITF IN Token UITE EMI 14H USB Endpoint 0 UOTF OUT Token UOTE EMI 18H 04H M. Funct. 0 MF0F MF0E EMI 1CH SIM SIMF SIME EMI 20H LVD LVDF LVDE EMI 24H Priority High Low Interrupt Structure Rev. 1.00 102 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU External Interrupt The external interrupt is controlled by signal transitions on the INTn pins. An external interrupt request will take place when the external interrupt request flag, INTnF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTnE, must first be set. Additionally the correct interrupt edge type must be selected using the related register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. USB SIE Interrupt A USB SIE interrupt request will take place when the USB SIE interrupt request flags, USBF, is set, a situation that will occur when an endpoint except endpoint 0 is accessed. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB SIE interrupt enable bit, USBE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB SIE interrupt vector, will take place. When the interrupt is serviced, the USB SIE interrupt request flag, USBF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. USB Setup Token Interrupt A USB Setup Token interrupt request will take place when the USB Setup Token interrupt request flags, USTF, is set, a situation that will occur when the USB receives endpoint 0 Setup token signal from PC. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB Setup Token interrupt enable bit, USTE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB Setup Token interrupt vector, will take place. When the interrupt is serviced, the USB Setup Token interrupt request flag, USTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. USB Endpoint 0 IN Token Interrupt A USB Endpoint 0 IN Token interrupt request will take place when the USB Endpoint 0 IN Token interrupt request flags, UITF, is set, a situation that will occur when the USB receives endpoint 0 IN token signal from PC. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB Endpoint 0 IN Token interrupt enable bit, UITE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB Endpoint 0 IN Token interrupt vector, will take place. When the interrupt is serviced, the USB Endpoint 0 IN Token interrupt request flag, UITF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.00 103 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU USB Endpoint 0 OUT Token Interrupt A USB Endpoint 0 OUT Token interrupt request will take place when the USB Endpoint 0 OUT Token interrupt request flags, UOTF, is set, a situation that will occur when the USB receives endpoint 0 OUT token signal from PC. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and USB Endpoint 0 OUT Token interrupt enable bit, UOTE, must first be set. When the interrupt is enabled, the stack is not full and an endpoint is accessed, a subroutine call to the USB Endpoint 0 OUT Token interrupt vector, will take place. When the interrupt is serviced, the USB Endpoint 0 OUT Token interrupt request flag, UOTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Serial Interface Module Interrupt The Serial Interface Module interrupt, known as the SIM interrupt, will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the SIMF flag will be automatically cleared as well. LVD Interrupt The Low Voltage Detector interrupt, known as the LVD interrupt, will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI and Low Voltage Interrupt enable bit, LVE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the LVF flag will be automatically cleared as well. Multi-function Interrupt Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place the Multi-function interrupt request flag, MF0F is set. The Multi-function interrupt flag will be set when any of its included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to the Multi-function interrupt vector will take place. When the interrupt is serviced, the related Multi-Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, will not be automatically reset and must be manually reset by the application program. Rev. 1.00 104 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU TM Interrupts The Compact Type TMs have two interrupts each. All of the TM interrupts are contained within the Multifunction Interrupts. For each of the Compact Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 105 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as "0" Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.00 106 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. Rev. 1.00 107 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU USB Interface The USB interface is a 4-wire serial bus that allows communication between a host device and up to 127 max peripheral devices on the same bus. A token based protocol method is used by the host device for communication control. Other advantages of the USB bus include live plugging and unplugging and dynamic device configuration. As the complexity of USB data protocol does not permit comprehensive USB operation information to be provided in this datasheet, the reader should therefore consult other external information for a detailed USB understanding. The device includes a USB interface function allowing for the convenient design of USB peripheral products. Power Plane There is one power plane for HT68FB240: UBUS/VDD. For the UBUS/VDD will supply all the HT68FB240 circuits including USB SIE and be sourced from pin "UBUS/VDD". Once the USB is removed from the USB and there is no power in the UBUS/VDD pin, the HT68FB240 circuit is no longer operational. USB Suspend Wake-Up Remote Wake-Up If there is no signal on the USB bus for over 3ms, the device will go into a suspend mode. The Suspend flag, SUSP, in the USC register, will then be set high and an USB interrupt will be generated to indicate that the device should jump to the suspend state to meet the requirements of the USB suspend current spec. In order to meet the requirements of the suspend current, the firmware should disable the USB clock by clearing the USBCKEN bit to "0". The suspend current can be further decreased by setting the SUSP2 bit in the UCC register. When the resume signal is sent out by the host, the device will be woken up the by the USB interrupt and the RESUME bit in the USC register will be set. To ensure correct device operation, the program must set the USBCKEN bit in the UCC register high and clear the SUSP2 bit in the UCC register. The Resume signal will be cleared before the Idle signal is sent out by the host and the Suspend line in the USC register will change to zero. So when the MCU detects the Suspend bit in the USC register, the condition of the Resume line should be noted and taken into consideration. SUSPEND USB Resume Signa� USB_INT The device has a remote wake up function which can wake-up the USB Host by sending a wake-up pulse through RMWK in the USC register. Once the USB Host receives a wake-up signal from the device, it will send a Resume signal to the device. SUSPEND Min. 1 USB CLK RMWK USB Resume Signa� Min.�.5ms USB_INT Rev. 1.00 108 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU USB Interface Operation The device has 3 Endpoints (EP0~EP2). EP0 supports Control transfer for Setup, IN and OUT token respectively. EP1 and EP2 support Interrupt transfer. These registers, including USB_STAT, UINT, USC, UCC, AWR, STL, SIES, MISC, UFEN, URDCT and FIFO0~FIFO2 are used for the USB function. EP0, EP1 and EP2 each have 8-byte FIFO size respectively. EP0 supports DMA interface for Configure USB descriptor. Please reference the DMA for detail description. EP0~EP2 are equiped with independent registers and not shared with the general data memory RAM. The Serial Interface Engine (SIE) of the device is compatible with USB 2.0 Low speed protocol. The URD in the USC register is the USB reset signal control function definition bit. USB Interface Registers The USB interface has a series of registers associated with its operation. USB_STAT Register Bit 7 6 4 PS2_CKI PS2_DAI 3 2 1 0 SE1 SE0 PU ESD R/W W W R R R/W R/W R/W R/W POR 1 1 x x 0 0 0 — Name PS2_CKO PS2_DAO 5 "x" unknown "-" Hardware did not give ESD bit initial value in power on reset Bit 7PS2_CKO: Output for driving UDP/GPIO1 pin, when work under 3D PS2 mouse function. Default value is "1". Rev. 1.00 Bit 6 PS2_DAO: Output for driving UDN/GPIO0 pin, when work under 3D PS2 mouse function. Default value is "1". Bit 5 PS2_CKI: UDP/GPIO1 input. Bit 4 PS2_DAI: UDN/GPIO0 input. Bit 3 SE1: This bit is used to indicate the SIE has detected a SE1 noise in the USB bus. This bit is set by SIE and cleared by F/W. Bit 2 SE0: This bit is used to indicate the SIE has detected a SE0 noise in the USB bus. This bit is set by SIE and cleared by F/W. Bit 1 PU: Bit1=1, UDP and UDN have a 600kΩ pull-high. Bit1=0, no pull-high (default on MCU reset) Bit 0 ESD: This bit will set to "1" when there is ESD issue. This bit is set by SIE and cleared by F/W. Hardware did not give ESD bit initial value in power on reset. 109 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU The endpoint requestflags (EP0F, EP1F and EP2F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to "1" and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is serviced, the endpoint request flag has to be cleared to "0" by software. UINT Register Bit 7 6 5 4 3 2 1 0 Name — EP2F EP1F EP0F — EP2EN EP1EN EP0EN R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unimplemented, read as "0" EP2F: USB endpoint2 accessed detection 0: no accessed 1: accessed EP1F: USB endpoint1 accessed detection 0: no accessed 1: accessed EP0F: USB endpoint0 accessed detection 0: no accessed 1: accessed Unimplemented, read as "0" EP2EN: USB endpoint2 interrupt control bit 0: disable 1: enable EP1EN: USB endpoint1 interrupt control bit 0: disable 1: enable EP0EN: USB endpoint0 interrupt control bit 0: disable 1: enable USC Register Bit 7 6 5 Name URD SELPS2 — 4 R/W R/W R/W — R/W POR 1 0 — 0 3 2 1 0 URST RMWK SUSP R R/W R/W R x 0 x x SELUSB RESUME "x" unknown Bit 7URD: USB reset signal control function definition 0: USB reset signal cannot MCU 1: USB reset signal will reset MCU Rev. 1.00 Bit 6 SELPS2: PS2 mode select bit 0: not PS2 mode 1: PS2 mode When the SELPS2 bit is set high, the PS2 function is selected and the pin-shared pins, UDN/GPIO0 and UDP/GPIO1, will become the GPIO0 and GPIO1 general purpose I/O functions which can be used to be the DATA and CLK pins for the PS2. Bit 5 Unimplemented, read as "0" 110 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 4SELUSB: USB mode and V33O on/off select bit 0: not USB mode, turn-off V33O 1: USB mode, turn-on V33O When the V33C bit is set high, the USB and V33O functions is selected and the pin-shared pins, UDN/GPIO0 and UDP/GPIO1, will become the UDN and UDP pins for the USB. SELUSB SELPS2 USB and PS2 mode description 0 1.No mode supported 2.V33O pin not output and it will floating 3.UDN/GPIO0 and UDP/GPIO1 pins cann’t output 0 1 1.PS2 mode 2.V33O pin output VDD 3.UDN/GPIO0 and UDP/GPIO1 pins will become the GPIO0 and GPIO1 pins, which can output by firmware 1 x 1.USB mode 2.V33O output 3.3V 3.UDN/GPIO0 and UDP/GPIO1 pins will become the UDN and UDP pins 0 x: don’t care Bit 3 RESUME: USB resume indication bit 0: SUSP bit goes to "0" 1: leave the suspend mode When the USB leaves the suspend mode, this bit is set to "1" (set by SIE). When the RESUME is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detect the suspend state, the MCU should set USBCKEN and clear SUSP2 (in the UCC register) to enable the SIE detect function. RESUME will be cleared when the SUSP goes to "0". When the MCU is detecting the SUSP, the condition of RESUME (causes the MCU to wake-up) should be noted and taken into consideration. Bit 2 URST: USB reset indication bit 0: no USB reset 1: USB reset occurred This bit is set/cleared by the USB SIE. This bit is used to detect a USB reset event on the USB bus. When this bit is set to "1", this indicates that a USB reset has occurred and that a USB interrupt will be initialized. Bit 1 RMWK: USB remote wake-up command 0: no remote wake-up 1: remote wake-up It is set by MCU to leave the USB host leaving the suspend mode. Indicate that the USB host leaves the suspend mode. Bit 0SUSP: USB suspend indication 0: not in the suspend mode 1: enter the suspend mode When this bit is set to 1 (set by SIE), it indicates that the USB bus has entered the suspend mode. The USB interrupt is also triggered when this bit changes from low to high. Rev. 1.00 111 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU UCC Register Bit 7 6 5 4 3 2 1 0 Name Rctrl SYSCLK — SUSP2 USBCKEN — EPS1 EPS0 R/W R/W R/W — R/W R/W — R/W R/W POR 0 0 — 0 0 — x x "x" unknown Bit 7Rctrl: 7.5kΩ resistor between UDN and UBUS control bit 0: no 7.5kΩ resistor between UDN and UBUS 1: has 7.5kΩ resistor between UDN and UBUS Bit 6 SYSCLK: Specify MCU oscillator frequency indication bit 0: 12MHz crystal oscillator or resonator 1: 6MHz crystal oscillator or resonator Bit 5 Unimplemented, read as "0" Bit 4 SUSP2: Reduce power consumption in suspend mode control bit 0: in normal mode 1: in halt mode, set this bit to "1" for reducing power consumption Bit 3 USBCKEN: USB clock control bit 0: Disable 1: Enable Bit 2 Unimplemented, read as "0" Bit 1~0 EPS1, EPS0: Accessing endpoint FIFO selection 00: select endpoint 0 FIFO (control) 01: select endpoint 1 FIFO 10~11: select endpoint 2 FIFO AWR Register Bit 7 6 5 4 3 2 1 0 Name AD6 AD5 AD4 AD3 AD2 AD1 AD0 WKEN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x" unknown Bit 7~1AD6~AD0: USB device address Bit 0 Rev. 1.00 WKEN: USB remote-wake-up control bit 0: Disable 1: Enable The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is "00H". The address value extracted from the USB command has not to be loaded into this register until the SETUP stage has finished 112 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU STL Register Bit 7 6 5 4 3 2 1 0 Name — STLO2 STLO1 STLO0 — STLI2 STLI1 STLI0 R/W — R/W R/W R/W — R/W R/W R/W POR — x x x — x x x "x" unknown Bit 7 Unimplemented, read as "0" Bit 6~4STLO3~STLO0: FIFO OUT stall endpoints indication bits 0: not stall 1: stall The STL register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STL register has to be set high. The STL register bits will be cleared by a USB reset signal and a setup token event. Bit 3 Unimplemented, read as "0" Bit 2~0 STLI3~STLI0: FIFO IN stall endpoints indication bits 0: not stall 1: stall The STL register shows if the corresponding endpoint has worked properly or not. As soon as endpoint improper operation occurs, the related bit in the STL register has to be set high. The STL register bits will be cleared by a USB reset signal and a setup token event. SIES Register Bit 7 6 5 4 3 2 1 0 Name NMI R/W R/W CRCF — NAK IN OUT ERR ASET R/W — R R R/W R/W R/W POR x x — x x x x x "x" unknown Rev. 1.00 Bit 7 NMI: NAK token interrupt mask flag 0: interrupt enable 1: interrupt disable If this bit set, when the device sent a NAK token to the host, an interrupt will be disabled. Otherwise if this bit is cleared, when the device sends a NAK token to the host, it will enter the interrupt sub-routine. This bit is used for all endpoint. Bit 6 CRCF: CRC error detection flag 0: no error 1: error This bit will be set to "1" when there are the following three conditions happened: CRC error, PID error, Bit stuffing error. This bit is set by SIE and cleared by F/W. Bit 5 Unimplemented, read as "0" Bit 4 NAK: ACK error detection flag 0: no error 1: error This bit will set to "1" once SIE discover there are some error condition so the SIE is not response (NAK or ACK or DATA) for the USB token. This bit is set by SIE and cleared by F/W. Bit 3 IN: Current USB receiving signal indicator 0: low 1: high This bit is used to indicate the current USB receiving signal from PC host is IN token. 113 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 2 OUT: USB OUT token indicator 0: low 1: high This bit is used to indicate the OUT token (except the OUT zero length token) has been received. The firmware clears this bit after the OUT data has been read. Also, this bit will be cleared by SIE after the next valid SETUP token is received. Bit 1 ERR: FIFO accessed error indicator 0: no error 1: error This bit is used to indicate that some errors have occurred when the FIFO is accessed. This bit is set by SIE and should be cleared by firmware. This bit is used for all endpoint. Bit 0 ASET: device address updated method control bit 0: update address after an written address to the AWR register 1: update address after PC host read out data This bit is used to configure the SIE to automatically change the device address by the value stored in the AWR register. When this bit is set to "1" by firmware, the SIE will update the device address by the value stored in the AWR register after the PC host has successfully read the data from he device by an IN operation. Otherwise, when this bit is cleared to"0", the SIE will update the device address immediately after an address is written to the AWR register. So, in order to work properly, the firmware has to clear this bit after a next valid SETUP token is received. MISC Register Bit 7 6 5 4 3 2 1 0 Name LEN0 READY SETCMD — — CLEAR TX REQUEST R/W R R R/W — — R/W R/W R/W POR x x x — — x x x "x" unknown Bit 7LEN0: 0-sized packet indication flag 0: not 0-sized packet 1: 0-sized packet This bit is used to show that the host sent a 0-sized packet to the MCU. This bit must be cleared by a read action to the corresponding FIFO. Rev. 1.00 Bit 6 READY: Desired FIFO ready indication flag 0: not ready 1: ready Bit 5 SETCMD: Setup command indication flag 0: not setup command 1: setup command This bit is used to show that the data in the FIFO is a setup command. This bit is set by Hardware and cleared by Firmware. Bit 4~3 Unimplemented, read as "0" Bit 2 CLEAR: Clear FIFO function control bit 0: disable 1: enable MCU requests to clear the FIFO, even if the FIFO is not ready. After clearing the FIFO, the USB interface will send force_tx_err to tell the Host that data under-run if the Host wants to read data. 114 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Bit 1 TX: data writing to FIFO status indication flag 0: data writing finished 1: data writing to FIFO To represent the direction and transition end MCU access. When set to logic 1, the MCU desires to write data to the FIFO. After finishing, this bit must be set to logic 0 before terminating request to represent transition end. For an MCU read operation, this bit must be set to logic 0 and set to logic 1 after finishing. Bit 0 REQUEST: Desired FIFO request status indication flag 0: no request 1: request After setting the status of the desired one, FIFO can be requested by setting this bit high.After finishing, this bit must be set low. UFEN Register Bit 7 6 5 4 3 2 1 0 Name — SETO2 SETO1 — — SETI2 SETI1 DATATG R/W — R/W R/W — — R/W R/W R/W POR — 0 0 — — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6SETO2: EP2 output FIFO control bit 0: disable 1: enable Bit 5SETO1: EP1 output FIFO control bit 0: disable 1: enable Bit 4~3 Unimplemented, read as "0" Bit 2 SETI2: EP2 input FIFO control bit 0: disable 1: enable Bit 1 SETI1: EP1 input FIFO control bit 0: disable 1: enable Bit 0 DATATG: DATA token toggle bit 0: low 1: high Note: This register will be reset only by power-on reset. USB endpoint accessing registers Bit Register Name 7 6 5 4 3 2 1 0 FIFO0 D7 D6 D5 D4 D3 D2 D1 D0 FIFO1 D7 D6 D5 D4 D3 D2 D1 D0 FIFO2 D7 D6 D5 D4 D3 D2 D1 D0 7 6 5 4 3 2 1 0 URDCT Register Bit Name URDCT7 URDCT6 URDCT5 URDCT4 URDCT3 URDCT2 URDCT1 URDCT0 R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x R/W x "x" unknown Bit 7~0URDCT7~URDCT0: Used for counting the received data size of USB Setup or OUT token packets Rev. 1.00 115 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Application Circuits VDD VDD/UBUS I/O 100 KΩ 10µF 0.1µF 300Ω RES/ OCDSCK Key Matrix Input 0.1µF VSS VBUS DD+ VSS UDN UDP V33O 0.1µF ICP / OCDS Interface VDD RES/OCDSCK PA0/OCDSDA VSS UDN OCDS ICP HT68FB240 Rev. 1.00 116 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 117 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 118 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 119 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 120 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 121 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 122 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 123 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 124 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.00 125 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.00 126 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 127 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 128 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 129 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 130 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Package Information SAW Type QFN Outline Dimensions SAW Type 46-pin (6.5mm4.5mm) Outline Dimensions SAW Type 46-pin QFNQFN (6.5mm×4.5mm) Outline Dimensions OSET Symbol Symbol A1 A1 A3 A3 b b D D E E e e D2D2 — 0.197 0.197 0.016 BSC. 0.016 0.201 0.201 — 0.205 0.205 E2E2 0.118 0.118 0.122 0.122 0.126 0.126 L L 0.012 0.012 0.016 0.016 0.020 0.020 A A K Symbol Symbol A A1 A A3 A1 b A3 D b E e D D2 E E2 e L D2 Rev. 1.00 Dimensions in inch Dimensions in inch Nom. Nom. 0.033 0.033 0.001 0.001 0.08 REF 0.008 0.008 0.008 0.256 0.256 0.177 0.177 Min. Min. 0.031 0.031 0.000 0.000 — 0.006 0.006 0.254 0.254 0.175 0.175 — — Dimensions in mm Min. Nom. Dimensions in mm 0.85 Nom. 0.02 0.85 0.20 0.02 0.20 0.2 REF 6.50 0.2 4.50 0.406.5 0.80 Min. 0.00 0.8 0 0.15 — 6.45 0.15 4.45 6.45 4.45 5.00 5.104.5 0.4 BSC. 3.10 3.00— 0.30 5 Max. Max. 0.035 0.035 0.002 0.002 — 0.010 0.010 0.258 0.258 0.179 0.179 — Max. 0.90 Max. 0.04 0.9 0.04 0.25 — 6.55 0.25 4.55 6.55 4.55 5.20 0.405.1 3.20 — 0.505.2 E2 3 3.1 3.2 L 0.3 0.4 0.5 K — — — 1 131 May 12, 2011 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° ― 7° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° ― 7° 132 April 18, 2014 HT68FB240 USB Low Speed 8-Bit Flash MCU Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 133 April 18, 2014