HT16C24/HT16C24G RAM Mapping 72×4/68×8/60×16

HT16C24/HT16C24G
RAM Mapping 72×4/68×8/60×16
LCD Driver Controller
Features
Applications
• Operating voltage:2.4V ~ 5.5V
• Electronic meter
• Internal 32kHz RC oscillator
• Water meter
• Bias: 1/3, 1/4 or 1/5; Duty:1/4, 1/8 or 1/16
• Gas meter
• Internal LCD bias generation with voltage-follower
buffers
• Heat energy meter
• I2C-bus interface
• Games
• Household appliance
• Two Selectable LCD frame frequencies: 80Hz or
160Hz
• Telephone
• Consumer electronics
• Up to 60 x 16 bits RAM for display data storage
• Display patterns:
––72×4 patterns: 72 segments and 4 commons
––68×8 patterns: 68 segments and 8 commons
––60×16 patterns: 60 segments and 16 commons
General Description
The HT16C24/HT16C24G device is a memory
mapping and multi-function LCD controller driver.
The Display segments of the device may be 288
patterns (72 segments and 4 commons), 544 patterns
(68 segments and 8 commons) or 960 patterns
(60 segments and 16 commons). The software
configuration feature of the HT16C24/HT16C24G
device makes it suitable for multiple LCD applications
including LCD modules and display subsystems. The
HT16C24/HT16C24G device communicates with
most microprocessors / microcontrollers via a twoline bidirectional I2C-bus.
• Versatile blinking modes
• R/W address auto increment
• Internal 16-step voltage adjustment to adjust LCD
operating voltage
• Low power consumption
• Provides VLCD pin to adjust LCD operating voltage
• Manufactured in silicon gate CMOS process
• Package type: 64-pin LQFP, 80-pin LQFP, Chip
and COG.
Rev. 1.40
1
October 17, 2012
HT16C24/HT16C24G
Block Diagram
Power_on reset
VSS
COM0
SDA
SCL
Internal RC
Oscillator
Timing
generator
I2C
Controller
Column
/Segment
driver
output
Display RAM
60*16bits
8
COM3
COM4/SEG0
COM15/SEG11
VDD
－
OP4
Internal
voltage
adjustment
VLCD
SEG12
＋
R
－
OP3
＋
R
Segment
driver
output
－
OP2
＋
R
－
OP1
＋
LCD
Voltage
Selector
SEG71
R
－
OP0
＋
R
Rev. 1.40
LCD bias generator
2
October 17, 2012
HT16C24/HT16C24G
Pin Assignment
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG68
SEG69
SEG70
VLCD
64 63 62 6160 59 585756 5554 5352 51 50 49
48
1
2
47
3
46
4
45
5
44
6
43
7
42
8
41
HT16C24
9
40
64 LQFP-A
10
39
11
38
12
37
13
36
35
14
15
34
33
16
1718 19 2021 2223 2425 26 2728 29303132
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
COM12/SEG8
COM13/SEG9
COM14/SEG10
COM15/SEG11
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
VDD
SDA
SCL
VSS
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
COM8/SEG4
COM9/SEG5
COM10/SEG6
COM11/SEG7
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
VLCD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
HT16C24
10
51
11
40
80 LQFP-A
12
49
13
48
47
14
46
15
45
16
44
17
43
18
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
VDD
SDA
SCL
VSS
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
COM7/SEG3
COM8/SEG4
COM9/SEG5
COM10/SEG6
COM11/SEG7
COM12/SEG8
COM13/SEG9
COM14/SEG10
COM15/SEG11
Note: Application at VDD ≤ VLCD or VLCD ≤ VDD
Rev. 1.40
3
October 17, 2012
HT16C24/HT16C24G
Pad Assignment for COB
SEG54
68
SEG55
SEG57
71 70 69
SEG56
SEG58
72
SEG59
74 73
SEG60
SEG61
76 75
SEG62
SEG63
SEG64
78 77
SEG65
SEG66
81 80 79
SEG67
SEG68
SEG69
83 82
SEG70
SEG71
VDD
VLCD
VCCA2
1
67 66 65
2
SDA
3
64
SEG53
SCL
4
63
SEG52
VSS
5
62
SEG51
COM0
6
61
SEG50
COM1
7
60
SEG49
COM2
8
59
SEG48
COM3
9
58
SEG47
COM4/SEG0
10
57
SEG46
COM5/SEG1
11
56
SEG45
COM6/SEG2
12
55
SEG44
COM7/SEG3
13
54
SEG43
COM8/SEG4
14
53
SEG42
COM9/SEG5
15
52
SEG41
COM10/SEG6
17
51
SEG40
COM11/SEG7
18
50
SEG39
COM12/SEG8
19
49
SEG38
COM13/SEG9
20
48
SEG37
COM14/SEG10
21
47
SEG36
COM15/SEG11
22
46
SEG35
SEG12
23
45
SEG34
SEG13
24
44
SEG33
SEG14
25
43
SEG32
SEG15
26
42
SEG31
(0, 0)
16
N.C.
39 40
41
SEG30
SEG29
38
SEG28
SEG25
SEG24
37
SEG27
35 36
SEG26
34
SEG23
SEG22
SEG21
SEG19
31 32 33
SEG20
SEG16
SEG18
30
SEG17
27 28 29
Chip size: 2044 × 2438μm2
Notes: 1. The IC substrate should be connected to VSS in the PCB layout artwork.
2. VLCD (pad 83) and VCCA2 (pad 1) must be bonded together for the application at VDD ≤ VLCD
or VLCD ≤ VDD.
Internal Voltage Adjustment (IVA) Set Command
DE Bit
VE Bit
VLCD
(Pad 83)
SEG71
(Pad 82)
Note
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Input
Null
●●Internal Voltage Adjustment is null
●●VLCD support internal bias voltage
1
0
Input
Output
●●VLCD support internal bias voltage
1
1
Input
Output
●●VLCD support internal bias voltage
3. VDD (pad 2) and VCCA2 (pad 1) must be bonded together for the application at VLCD ≤ VDD.
Internal Voltage Adjustment (IVA) Set Command
DE Bit
VE Bit
VLCD
(Pad 83)
SEG71
(Pad 82)
Note
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Output
Null
●●Detect the internal bias voltage
●●VDD support internal bias voltage
1
0
Floating
Output
●●VDD support internal bias voltage
1
1
Floating
Output
●●VDD support internal bias voltage
Rev. 1.40
4
October 17, 2012
HT16C24/HT16C24G
Pad Coordinates for COB
Unit: μm
No
Name
X
Y
No
Name
X
Y
1
VCCA2
-734.6
1114.95
43
SEG32
917.7
-993.1
2
VDD
-918.4
889.55
44
SEG33
917.7
-908.1
3
SDA
-918.4
804.55
45
SEG34
917.7
-823.1
4
SCL
-918.4
719.55
46
SEG35
917.7
-738.1
5
VSS
-918.4
634.55
47
SEG36
917.7
-653.1
6
COM0
-918.4
549.55
48
SEG37
917.7
-568.1
7
COM1
-918.4
464.55
49
SEG38
917.7
-483.1
8
COM2
-918.4
379.55
50
SEG39
917.7
-398.1
9
COM3
-918.4
294.55
51
SEG40
917.7
-313.1
10
COM4/SEG0
-918.4
199.65
52
SEG41
917.7
-228.1
11
COM5/SEG1
-918.4
114.65
53
SEG42
917.7
-143.1
12
COM6/SEG2
-918.4
29.65
54
SEG43
917.7
-58.1
13
COM7/SEG3
-918.4
-55.35
55
SEG44
917.7
26.9
14
COM8/SEG4
-918.4
-140.35
56
SEG45
917.7
111.9
15
COM9/SEG5
-918.4
-225.35
57
SEG46
917.7
196.9
16
N.C.
-567.474
-161.846
58
SEG47
917.7
281.9
17
COM10/SEG6
-918.4
-310.35
59
SEG48
917.7
366.9
18
COM11/SEG7
-918.4
-395.35
60
SEG49
917.7
451.9
19
COM12/SEG8
-918.4
-480.35
61
SEG50
917.7
536.9
20
COM13/SEG9
-918.4
-565.35
62
SEG51
917.7
621.9
706.9
21
COM14/SEG10
-918.4
-650.35
63
SEG52
917.7
22
COM15/SEG11
-918.4
-735.35
64
SEG53
917.7
791.9
23
SEG12
-918.4
-823.1
65
SEG54
880.4
1114.95
24
SEG13
-918.4
-908.1
66
SEG55
795.4
1114.95
25
SEG14
-918.4
-993.1
67
SEG56
710.4
1114.95
26
SEG15
-918.4
-1078.1
68
SEG57
625.4
1114.95
27
SEG16
-595.35
-1115.4
69
SEG58
540.4
1114.95
28
SEG17
-510.35
-1115.4
70
SEG59
455.4
1114.95
29
SEG18
-425.35
-1115.4
71
SEG60
370.4
1114.95
30
SEG19
-340.35
-1115.4
72
SEG61
285.4
1114.95
31
SEG20
-255.35
-1115.4
73
SEG62
200.4
1114.95
32
SEG21
-170.35
-1115.4
74
SEG63
115.4
1114.95
1114.95
33
SEG22
-85.35
-1115.4
75
SEG64
30.4
34
SEG23
-0.35
-1115.4
76
SEG65
-54.6
1114.95
35
SEG24
84.65
-1115.4
77
SEG66
-139.6
1114.95
36
SEG25
169.65
-1115.4
78
SEG67
-224.6
1114.95
37
SEG26
254.65
-1115.4
79
SEG68
-309.6
1114.95
38
SEG27
339.65
-1115.4
80
SEG69
-394.6
1114.95
39
SEG28
424.65
-1115.4
81
SEG70
-479.6
1114.95
40
SEG29
509.65
-1115.4
82
SEG71
-564.6
1114.95
41
SEG30
594.65
-1115.4
83
VLCD
-649.6
1114.95
42
SEG31
917.7
-1078.1
Rev. 1.40
5
October 17, 2012
HT16C24/HT16C24G
Pad Assignment for COG
1
121 120 119 118
64 63 62 61 60
117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
2
59
3
58
4
5
57
56
6
55
(0, 0)
7
54
8
53
9
52
10
51
11
50
49
12
13
14
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
48
45
47
15
46
Note:
• VLCD (pad 20) must be connected to VCCA2 (pad 21) in the PCB layout for the application at VDD ≤ VLCD or
VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 20)
SEG71
(pad 13)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Input
Null
●●Internal Voltage Adjustment is null
●●VLCD support internal bias voltage
1
0
Input
Output
●●VLCD support internal bias voltage
1
1
Input
Output
●●VLCD support internal bias voltage
• VDD (pad 18) must be connected to VCCA2 (pad 21) in the PCB layout for the application at VLCD ≤ VDD.
Internal voltage adjustment (IVA)
set command
VLCD
(pad 20)
SEG71
(pad 13)
Note
DE bit
VE bit
0
0
Input
Null
●●VLCD support internal bias voltage.
0
1
Output
Null
●●Detect the internal bias voltage
●●VDD support internal bias voltage
1
0
Floating
Output
●●VDD support internal bias voltage
1
1
Floating
Output
●●VDD support internal bias voltage
Pad Dimensions for COG
Item
Chip size
－
Chip thickness
－
Pad pitch
X
3958
Rev. 1.40
1080
508
Unit
μm
μm
1.3~15, 46~58, 60~121
60
μm
87
μm
62~120
40
60
μm
5~13, 48~55
60
40
μm
16~21
67
67
μm
1, 60,61,121
40
60
μm
Dummy pad 3,4, 14,15, 46,47,56,57,58
60
40
μm
Input pad
22~45
Bump height
Y
16~45
Output pad
Bump size
Size
Number
67
All pad
67
18±3
6
μm
μm
October 17, 2012
HT16C24/HT16C24G
Alignment Mark Dimensions for COG
Item
Number
Size
Unit
(-1906, 362.5)
10um
10um
ALIGN_A
μm
2
10um
10um
20um
40um
(1886, 362.5)
10um
10um
ALIGN_B
59
μm
7
10um
10um
20um
Rev. 1.40
20um
20um
20um
October 17, 2012
HT16C24/HT16C24G
Pad Coordinates for COG
Unit: μm
No
Name
X
Y
No
Name
X
Y
1
DUMMY
-1866.85
444.5
63
COM9/SEG5
1673.15
444.5
3
DUMMY
-1884.5
269.566
64
COM10/SEG6
1613.15
444.5
4
DUMMY
-1884.5
209.566
65
COM11/SEG7
1553.15
444.5
5
SEG63
-1884.5
149.566
66
COM12/SEG8
1493.15
444.5
6
SEG64
-1884.5
89.566
67
COM13/SEG9
1433.15
444.5
7
SEG65
-1884.5
29.566
68
COM14/SEG10
1373.15
444.5
8
SEG66
-1884.5
-30.434
69
COM15/SEG11
1313.15
444.5
9
SEG67
-1884.5
-90.434
70
SEG12
1253.15
444.5
10
SEG68
-1884.5
-150.434
71
SEG13
1193.15
444.5
11
SEG69
-1884.5
-210.434
72
SEG14
1133.15
444.5
12
SEG70
-1884.5
-270.434
73
SEG15
1073.15
444.5
13
SEG71
-1884.5
-330.434
74
SEG16
1013.15
444.5
14
DUMMY
-1884.5
-390.434
75
SEG17
953.15
444.5
15
DUMMY
-1884.5
-450.434
76
SEG18
893.15
444.5
444.5
16
SDA
-1381.81
-436.691
77
SEG19
833.15
17
SCL
-1294.81
-436.691
78
SEG20
773.15
444.5
18
VDD
-1023.81
-436.691
79
SEG21
713.15
444.5
444.5
19
VSS
-936.81
-436.691
80
SEG22
653.15
20
VLCD
-750.81
-436.691
81
SEG23
593.15
444.5
21
VCCA2
-663.81
-436.691
82
SEG24
533.15
444.5
22
DUMMY
-477.81
-436.691
83
SEG25
473.15
444.5
23
DUMMY
-390.81
-436.691
84
SEG26
413.15
444.5
24
DUMMY
-303.81
-436.691
85
SEG27
353.15
444.5
25
DUMMY
-216.81
-436.691
86
SEG28
293.15
444.5
26
DUMMY
-129.81
-436.691
87
SEG29
233.15
444.5
27
DUMMY
-42.81
-436.691
88
SEG30
173.15
444.5
28
DUMMY
44.19
-436.691
89
SEG31
113.15
444.5
29
DUMMY
131.19
-436.691
90
SEG32
53.15
444.5
30
DUMMY
218.19
-436.691
91
SEG33
-6.85
444.5
31
DUMMY
305.19
-436.691
92
SEG34
-66.85
444.5
32
DUMMY
392.19
-436.691
93
SEG35
-126.85
444.5
33
DUMMY
479.19
-436.691
94
SEG36
-186.85
444.5
34
DUMMY
566.19
-436.691
95
SEG37
-246.85
444.5
35
DUMMY
653.19
-436.691
96
SEG38
-306.85
444.5
36
DUMMY
740.19
-436.691
97
SEG39
-366.85
444.5
37
DUMMY
827.19
-436.691
98
SEG40
-426.85
444.5
38
DUMMY
914.19
-436.691
99
SEG41
-486.85
444.5
39
DUMMY
1001.19
-436.691
100
SEG42
-546.85
444.5
40
DUMMY
1088.19
-436.691
101
SEG43
-606.85
444.5
41
DUMMY
1175.19
-436.691
102
SEG44
-666.85
444.5
42
DUMMY
1262.19
-436.691
103
SEG45
-726.85
444.5
43
DUMMY
1349.19
-436.691
104
SEG46
-786.85
444.5
44
DUMMY
1436.19
-436.691
105
SEG47
-846.85
444.5
45
DUMMY
1523.19
-436.691
106
SEG48
-906.85
444.5
46
DUMMY
1884.5
-450.434
107
SEG49
-966.85
444.5
47
DUMMY
1884.5
-390.434
108
SEG50
-1026.85
444.5
48
COM0
1884.5
-330.434
109
SEG51
-1086.85
444.5
Rev. 1.40
8
October 17, 2012
HT16C24/HT16C24G
No
Name
X
Y
No
Name
X
Y
49
COM1
1884.5
-270.434
110
SEG52
-1146.85
444.5
50
COM2
1884.5
-210.434
111
SEG53
-1206.85
444.5
51
COM3
1884.5
-150.434
112
SEG54
-1266.85
444.5
52
COM4/SEG0
1884.5
-90.434
113
SEG55
-1326.85
444.5
53
COM5/SEG1
1884.5
-30.434
114
SEG56
-1386.85
444.5
54
COM6/SEG2
1884.5
29.566
115
SEG57
-1446.85
444.5
55
COM7/SEG3
1884.5
89.566
116
SEG58
-1506.85
444.5
56
DUMMY
1884.5
149.566
117
SEG59
-1566.85
444.5
57
DUMMY
1884.5
209.566
118
SEG60
-1626.85
444.5
58
DUMMY
1884.5
269.566
119
SEG61
-1686.85
444.5
60
DUMMY
1853.15
444.5
120
SEG62
-1746.85
444.5
61
DUMMY
1793.15
444.5
121
DUMMY
-1806.85
444.5
62
COM8/SEG4
1733.15
444.5
Alignment Mark Coordinates for COG
No
Name
X
Y
No
Name
X
Y
2
ALIGN_A
-1906
362.5
59
ALIGN_B
1886
362.5
Pin Description
Pin Name
Type
SDA
I/O
SCL
I
VDD
—
Positive power supply.
VSS
—
Negative power supply, ground.
VCCA2
—
Power supply for LCD bias generator
VLCD
—
●●One external resistor is connected between the VLCD pin and the VDD pin to
determine the bias voltage for the package with a VLCD pin. Internal voltage
adjustment function is disabled.
●●Internal voltage adjustment function can be used to adjust the VLCD voltage. If the
VLCD pin is used as a voltage output detection pin, an external power supply
should not be applied to the VLCD pin.
●●An external MCU can detect the voltage of the VLCD pin and program the internal
voltage adjustment for the packages with a VLCD pin.
COM0~COM3
O
LCD Common outputs.
COM4/SEG0
~COM15/SEG11
O
LCD Common/Segment multiplexed driver outputs
SEG12~SEG71
O
LCD Segment outputs.
Rev. 1.40
Description
Serial Data Input/Output for I2C interface
Serial Clock Input for I2C interface
9
October 17, 2012
HT16C24/HT16C24G
Approximate Internal Connections
COM0~COM15; SEG0~SEG71
SCL, SDA (for schmit Trigger type)
VDD
Vselect-on
Vselect-off
VSS
Absolute Maximum Ratings
Supply Voltage ........................................................................................................................VSS-0.3V to VSS+6.5V
Input Voltage ..........................................................................................................................VSS-0.3V to VDD+0.3V
Storage Temperature ......................................................................................................................... -55°C to 150°C
Operating Temperature ....................................................................................................................... -40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect
device reliability.
Rev. 1.40
10
October 17, 2012
HT16C24/HT16C24G
D.C. Characteristics
VSS = 0V; VDD =2.4 to 5.5V; Ta = -40 to +85°C
Symbol
Parameter
Test Condition
VDD
Condition
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
—
2.4
—
5.5
V
VLCD
Operating Voltage
—
—
2.4
—
5.5
V
3V
No load, VLCD=VDD, 1/3bias,
fLCD=80Hz, LCD display on,
Internal system oscillator on,
DA0~DA3 are set to "0000"
—
30
45
μA
—
40
60
μA
No load, VLCD=VDD, 1/3bias
fLCD=80Hz, LCD display off,
Internal system oscillator on,
DA0~DA3 are set to ”0000”
—
2
5
μA
—
4
10
μA
—
—
1
μA
5V
No load, VLCD=VDD,
LCD display off,
Internal system oscillator off,
—
—
2
μA
0.7VDD
—
VDD
V
IDD
Operating Current
5V
3V
IDD1
Operating Current
5V
3V
ISTB
Standby Current
VIH
Input high Voltage
—
SDA ,SCL
VIL
Input low Voltage
—
SDA, SCL
0
—
0.3VDD
V
IIL
Input leakage current
—
VIN = VSS or VDD
-1
—
1
μA
IOL
Low level output current
3
—
—
mA
6
—
—
mA
IOL1
LCD COM Sink Current
IOH1
LCD COM Source Current
IOL2
LCD SEG Sink Current
IOH2
Rev. 1.40
LCD SEG Source Current
3V
5V
VOL=0.4V for SDA
3V
VLCD=3V, VOL=0.3V
250
400
—
μA
5V
VLCD=5V, VOL=0.5V
500
800
—
μA
3V
VLCD=3V, VOH=2.7V
-140
-230
—
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
—
μA
3V
VLCD=3V, VOL=0.3V
250
400
—
μA
5V
VLCD=5V, VOL=0.5V
500
800
—
μA
3V
VLCD=3V, VOH=2.7V
-140
-230
—
μA
5V
VLCD=5V, VOH=4.5V
-300
-500
—
μA
11
October 17, 2012
HT16C24/HT16C24G
A.C. Characteristics
Symbol
Parameter
VSS = 0V; VDD = 2.4 to 5.5V; Ta= -40 to +85°C
Test Condition
Condition
VDD
Min.
Typ.
Max.
Unit
fLCD1
LCD Frame Frequency
4V
1/4 duty, Ta =25°C
72
80
88
Hz
fLCD2
LCD Frame Frequency
4V
1/4 duty, Ta =25°C
144
160
176
Hz
fLCD3
LCD Frame Frequency
4V
1/4 duty,Ta=-40 to +85°C
52
80
124
Hz
fLCD4
LCD Frame Frequency
4V
1/4 duty, Ta=-40 to +85°C
104
160
248
Hz
tOFF
VDD OFF Times
—
VDD drop down to 0V
20
—
—
ms
tSR
VDD Slew Rate
—
0.05
—
—
V/ms
—
Note:
• If the conditions of Power on Reset timing are not satisfied during the power ON/OFF sequence, the internal
Power on Reset (POR) circuit will not operate normally.
• If the VDD voltage drops below the minimum voltage of operating voltage spec. during operating, the Power on
Reset timing conditions must also be satisfied. That is, the VDD voltage must drop to 0V and remain at 0V for
20ms (min.) before rising to the normal operating voltage.
A.C. Characteristics – I2C Interface
Symbol
Parameter
Condition
fSCL
Clock frequency
tBUF
bus free time
Time in which the bus
must be free before a new
transmission can start
Start condition hold time
After this period, the first
clock pulse is generated
tHD: STA
VDD=2.4V to 5.5V VDD=3.0V to 5.5V
—
Unit
Min.
Max.
Min.
Max.
—
100
—
400
KHZ
4.7
—
1.3
—
μs
4
—
0.6
—
μs
tLOW
SCL Low time
—
4.7
—
1.3
—
μs
tHIGH
SCL High time
—
4
—
0.6
—
μs
4.7
—
0.6
—
μs
Only relevant for repeated
START condition.
tSU: STA
Start condition setup time
tHD: DAT
Data hold time
—
0
—
0
—
ns
tSU: DAT
Data setup time
—
250
—
100
—
ns
tR
SDA and SCL rise time
Note
—
1
—
0.3
μs
tF
SDA and SCL fall time
Note
—
0.3
—
0.3
μs
Stop condition set-up time
—
4
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
(SDA and SCL Pins)
—
100
—
50
ns
tSU: STO
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.40
12
October 17, 2012
HT16C24/HT16C24G
Timing Diagrams
I2C Timing
SDA
tBUF
tSU:DAT
tf
tLOW
tHD:STA
tr
tSP
SCL
tHD:STA
S
tHD:DAT
tHIGH
tSU:STA
tAA
tSU:STO
Sr
P
S
SDA
OUT
Power On Reset Timing
Rev. 1.40
13
October 17, 2012
HT16C24/HT16C24G
Functional Description
Data transfers on the I2C-bus should be avoided for
1ms following power-on to allow completion of the
reset action.
Power-On Reset
When the power is applied, the device is initialized
by an internal power-on reset circuit. The status of the
internal circuits after initialization is as follows:
Display Memory – RAM Structure
The display RAM is static 60×16 bits RAM which
stores the LCD data. Logic “1” in the RAM bit-map
indicates the “on” state of the corresponding LCD
segment; similarly, logic 0 indicates the “off” state.
• All common/segment outputs are set to VDD when
VLCD ≤ VDD.
• All common/segment outputs are set to VLCD when
VDD ≤ VLCD.
The contents of the RAM data are directly mapped
to the LCD data. The first RAM column corresponds
to the segments operated with respect to COM0. In
multiplexed LCD applications the segment data from
2nd to 16th column of the display RAM are timemultiplexed from COM1 to COM15 respectively. The
following is a mapping from the RAM data to the
LCD pattern:
• The drive mode 1/4 duty output and 1/3 bias is
selected.
• The System Oscillator and the LCD bias generator
are off state.
• LCD Display is off state.
• Internal voltage adjustment function is enabled.
• The Segment/VLCD shared pin is set as the
Segment pin.
• Detection switch for the VLCD pin is disabled.
• Frame Frequency is set to 80Hz.
• Blinking function is switched off
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0
address
SEG1
SEG0
00H
SEG3
SEG2
01H
SEG5
SEG4
02H
SEG7
SEG6
03H
SEG9
SEG8
04H
SEG11
SEG10
05H
SEG71
SEG70
23H
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM Mapping of 72×4 Display Mode
Rev. 1.40
14
October 17, 2012
HT16C24/HT16C24G
COM7/
SEG3
Output
COM6/
SEG2
COM5/
SEG1
COM4/
SEG0
COM3
COM2
COM1
COM0
address
SEG4
00H
SEG5
01H
SEG6
02H
SEG7
03H
SEG8
04H
SEG9
05H
SEG71
43H
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM Mapping of 68×8 Display Mode
COM0
COM1
COM2
COM3
COM4/SEG0
COM5/SEG1
COM6/SEG2
Addr.
COM7/SEG3
COM8/SEG4
COM9/SEG5
COM10/SEG6
COM11/SEG7
COM12/SEG8
COM13/SEG9
COM14/SEG10
COM15/SEG11
Output
Addr.
SEG12
01H
00H
SEG13
03H
02H
SEG14
05H
04H
SEG15
07H
06H
SEG16
09H
08H
SEG17
0BH
0AH
SEG71
77H
D7
D6
D5
D4
D3
D2
D1
D0
Data
76H
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM Mapping of 60×16 Display Mode
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
Display Data Transfer format for I2C Bus
System Oscillator
The timing for the internal logic and the LCD drive signals are generated by an internal oscillator. The System
Clock frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator
will be in the stop state.
Rev. 1.40
15
October 17, 2012
HT16C24/HT16C24G
LCD Bias Generator
and VSS. The specific resistor can be switched out of
circuits to provide a 1/3, 1/4 or 1/5 bias voltage level
configuration.
The full-scale LCD voltage (VOP) is obtained from
(VLCD – VSS). The LCD voltage may be temperature
compensated externally through the Voltage supply to
the VLCD pin.
LCD Drive Mode Waveforms
• When the LCD drive mode is selected as 1/4 duty
and 1/3 bias, the waveform and LCD display is
shown as follows:
Fractional LCD biasing voltages, known as 1/3, 1/4 or
1/5 bias voltage, are obtained from an internal voltage
divider of five serial resistors connected between VLCD
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
COM0
COM0 VLCD- 2Vop/3
VLCD- 2Vop/3
State1
State1
(on)
(on)
VSS
VSS
VLCD
VLCD
COM1
COM1
State2
State2
(off)
(off)
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM2
COM2
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
COM3
COM3
VLCD- Vop/3
VLCD- Vop/3
VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n
SEG n VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+1
SEG n+1 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+2
SEG n+2 VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
VLCD
VLCD
VLCD- Vop/3
VLCD- Vop/3
SEG n+3
SEG n+3VLCD- 2Vop/3
VLCD- 2Vop/3
VSS
VSS
Note: tLCD=1/fLCD
Rev. 1.40
Waveforms for 1/4 Duty Drive Mode with 1/3 Bias (VOP=VLCD-VSS)
16
October 17, 2012
HT16C24/HT16C24G
• When the LCD drive mode is selected as 1/8 duty and 1/4 bias, the waveform and LCD display is shown as
follows:
tLCD
LCD segment
LCD segment
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM0
VLCD- 2Vop/4
COM0
State1
State1
(on)
(on)
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
State2
State2
(off)
(off)
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM1
VLCD- 2Vop/4
COM1
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM2
VLCD- 2Vop/4
COM2
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM3
VLCD- 2Vop/4
COM3
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM4
VLCD- 2Vop/4
COM4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM5
VLCD- 2Vop/4
COM5
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM6
VLCD- 2Vop/4
COM6
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
VLCD- 2Vop/4
COM7
VLCD- 2Vop/4
COM7
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n
SEG n
VLCD- 2Vop/4
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+1
VLCD- 2Vop/4
SEG n+1
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+2
VLCD- 2Vop/4
SEG n+2
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
VLCD
VLCD
VLCD- Vop/4
VLCD- Vop/4
SEG n+3
VLCD- 2Vop/4
SEG n+3
VLCD- 2Vop/4
VLCD- 3Vop/4
VLCD- 3Vop/4
VSS
VSS
Note: tLCD=1/fLCD
Rev. 1.40
Waveforms for 1/8 Duty Drive Mode with 1/4 Bias (VOP=VLCD-VSS)
17
October 17, 2012
HT16C24/HT16C24G
• When the LCD drive mode is selected as 1/16 duty and 1/5 bias, the waveform and LCD display is shown as
follows:
tLCD
COM0
COM0
COM1
COM1
COM2
COM2
COM3
COM3
COM4
COM4
COM5
COM5
COM6
COM6
COM7
COM7
COM8
COM8
COM9
COM9
COM10
COM10
COM11
COM11
COM12
COM12
COM13
COM13
COM14
COM14
COM15
COM15
SEG n
SEG n
SEG n+1
SEG n+1
SEG n+2
SEG n+2
SEG n+3
SEG n+3
LCD segment
LCD segment
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCD- Vop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD- 3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD- 3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD- 2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD- 2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCD- Vop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
State1
State1
(on)
(on)
State2
State2
(off)
(off)
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
VLCD
VLCD- Vop/5
VLCD
VLCD2Vop/5
VLCDVop/5
VLCD3Vop/5
VLCD2Vop/5
VLCD4Vop/5
VLCD3Vop/5
VSS
VLCD- 4Vop/5
VSS
Note: tLCD=1/fLCD
Rev. 1.40
Waveforms for 1/16 Duty Drive Mode with 1/5 Bias (VOP=VLCD-VSS)
18
October 17, 2012
HT16C24/HT16C24G
Segment Driver Outputs
series of display data bytes, into any location of the
display RAM. The sequence commences with the
initialization of the address pointer by the Address
pointer command.
The LCD drive section includes up to 72 segment
outputs which should be connected directly to the
LCD panel. The segment output signals are generated
in accordance with the multiplexed column signals
and with the data resident in the display latch. The
unused segment outputs should be left open-circuit.
Blinker Function
The LCD drive section includes up to 16 column
outputs which should be connected directly to the
LCD panel. The column output signals are generated
in accordance with the selected LCD drive mode. The
unused column outputs should be left open-circuit.
The device contains versatile blinking capabilities.
The whole display can be blinked at frequencies
selected by the Blink command. The blinking
frequency is a subdivided ratio of the system
frequency. The ratio between the system oscillator
and blinking frequencies depends on the blinking
mode in which the device is operating, as shown in
the following table.
Address Pointer
Frame Frequency
Column Driver Outputs
The HT16C24/HT16C24G device provides two frame
frequencies selected with Mode set command known
as 80Hz and 160Hz respectively.
The addressing mechanism for the display RAM is
implemented using the address pointer. This allows
the loading of an individual display data byte, or a
Blinking Mode
Operating Mode Ratio
Blinking Frequency (Hz)
0
0
Blink off
1
fsys / 16384Hz
2
2
fsys / 32768Hz
1
3
fsys / 65536Hz
0.5
Internal VLCD Voltage Adjustment
• The internal VLCD adjustment structure is shown in
the diagram:
• The internal VLCD adjustment contains four resistors
in series and a 4-bit programmable analog switch
which can provide sixteen voltage adjustment
options using the VLCD voltage adjustment
command.
VDD pad
VCCA2 pad
VE bit
DE bit
VLCD pad
R
Internal voltage adjustment
R
R
R
R
LCD Bias
generator
Rev. 1.40
19
October 17, 2012
HT16C24/HT16C24G
• The relationship between the programmable 4-bit analog switch and the VLCD output voltage is shown in the
table:
1. When VCCA2 pad is connected to VDD pad
DA3~DA0
00H
Bias
1/3
1/4
1/5
1.000×VDD
1.000×VDD
1.000×VDD
01H
0.944×VDD
0.957×VDD
0.966×VDD
02H
0.894×VDD
0.918×VDD
0.934×VDD
03H
0.849×VDD
0.882×VDD
0.904×VDD
04H
0.808×VDD
0.849×VDD
0.875×VDD
05H
0.771×VDD
0.818×VDD
0.849×VDD
06H
0.738×VDD
0.789×VDD
0.824×VDD
07H
0.707×VDD
0.763×VDD
0.801×VDD
08H
0.678×VDD
0.738×VDD
0.779×VDD
09H
0.652×VDD
0.714×VDD
0.758×VDD
0AH
0.628×VDD
0.692×VDD
0.738×VDD
0BH
0.605×VDD
0.672×VDD
0.719×VDD
0CH
0.584×VDD
0.652×VDD
0.701×VDD
0DH
0.565×VDD
0.634×VDD
0.684×VDD
0EH
0.547×VDD
0.616×VDD
0.668×VDD
0FH
0.529×VDD
0.600×VDD
0.652×VDD
Note
Default value
2. When VCCA2 pad is connected to VLCD pad
DA3~DA0
00H
Bias
1/3
1/4
1/5
1.000×VLCD
1.000×VLCD
1.000×VLCD
01H
0.944×VLCD
0.957×VLCD
0.966×VLCD
02H
0.894×VLCD
0.918×VLCD
0.934×VLCD
03H
0.849×VLCD
0.882×VLCD
0.904×VLCD
04H
0.808×VLCD
0.849×VLCD
0.875×VLCD
05H
0.771×VLCD
0.818×VLCD
0.849×VLCD
06H
0.738×VLCD
0.789×VLCD
0.824×VLCD
07H
0.707×VLCD
0.763×VLCD
0.801×VLCD
08H
0.678×VLCD
0.738×VLCD
0.779×VLCD
09H
0.652×VLCD
0.714×VLCD
0.758×VLCD
0AH
0.628×VLCD
0.692×VLCD
0.738×VLCD
0BH
0.605×VLCD
0.672×VLCD
0.719×VLCD
0CH
0.584×VLCD
0.652×VLCD
0.701×VLCD
0DH
0.565×VLCD
0.634×VLCD
0.684×VLCD
0EH
0.547×VLCD
0.616×VLCD
0.668×VLCD
0FH
0.529×VLCD
0.600×VLCD
0.652×VLCD
Rev. 1.40
20
Note
Default value
October 17, 2012
HT16C24/HT16C24G
I2C Serial Interface
The device supports I2C serial interface. The I2C bus is for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are
connected to the positive supply via pull-up resistors with a typical value of 4.7KΩ. When the bus is free, both
lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wiredor function. Data transfer is initiated only when the bus is not busy.
Data Validity
The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the
data line can only change when the clock signal on the SCL line is Low as shown in the diagram.
SDA
SCL
Data line stable,
Data valid
Chang of data
allowed
START and STOP Conditions
• A high to low transition on the SDA line while SCL is high defines a START condition.
• A low to high transition on the SDA line while SCL is high defines a STOP condition.
• START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
• The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte Format
Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit,
MSB, first.
P
SDA
Sr
SCL
Rev. 1.40
S
or
Sr
1
2
7
9
8
ACK
21
1
2
3-8
9
ACK
P
or
Sr
October 17, 2012
HT16C24/HT16C24G
Acknowledge
• Each bytes of eight bits is followed by one acknowledge bit. The acknowledge bit is a low level placed on the
bus by the receiver. The master generates an extra acknowledge related clock pulse.
• A slave receiver which is addressed must generate an acknowledge bit, ACK, after the reception of each byte.
• The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it
remains stable low during the high period of this clock pulse.
• A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the
last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high
during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
Data Output
by Transmitter
not acknowledge
Data Outptu
by Receiver
acknowledge
SCL From
Master
1
S
2
7
8
START
condition
9
clock pulse for
acknowledgement
Slave Addressing
• The slave address byte is the first byte received following the START condition form the master device. The
first seven bits of the first byte make up the slave address. The eighth bit defines a read or write operation to be
performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.
• The HT16C24/HT16C24G address bits are “0111101”. When an address byte is sent, the device compares the
first seven bits after the START condition. If they match, the device outputs an acknowledge signal on the SDA
line.
Slave Address
MSB
0
Rev. 1.40
LSB
1
1
1
1
22
0
1
R/W
October 17, 2012
HT16C24/HT16C24G
Write Operation
Byte Writes Operation
• Command Byte
A Command Byte write operation requires a START condition, a slave address with an R/W bit, a command byte,
a command setting byte and a STOP condition for a command byte write operation.
Command byte
Command setting
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
0
1
0
Write ACK
ACK
1st
P
ACK
2nd
Command Byte Write Operation
• Display RAM Single Data Byte
A display RAM data byte write operation requires a START condition, a slave address with an R/W bit, a
command byte, a valid Register Address byte, a Data byte and a STOP condition.
Command byte
Register Address byte
Data byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
D7 D6 D5 D4 D3 D2 D1 D0
Slave Address
S 0
1
1
1
1
0
1
0
Write ACK
ACK
1st
ACK
2nd
P
ACK
Display RAM Single Data Byte Write Operation
Display RAM Page Write Operation
After a START condition the slave address with the R/W bit is placed on the bus followed with a command
byte and the specified display RAM Register Address of which the contents are written to the internal address
pointer. The data to be written to the memory will be transmitted next and then the internal address pointer will be
incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse.
After the internal address point reaches the maximum memory address, which is 23H for 1/4 duty drive mode,
43H for 1/8 duty drive mode or 77H for 1/16 duty drive mode, the address pointer will be reset to 00H.
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Slave Address
S
0
1
1
1
1
0
1
0
Write
1st
Data byte
D7
D6
D5
D4
D3
2nd
ACK
ACK
ACK
Data byte
D2
D1
D0
D7
1st data
D6
D5
D4
D3
Data byte
D2
D1
D0
D7
2nd data
D6
D5
D4
D3
Nth data
ACK
ACK
ACK
D2
D1
P
D0
ACK
N Bytes Display RAM Data Write Operation
Rev. 1.40
23
October 17, 2012
HT16C24/HT16C24G
Display RAM Read Operation
• In this mode, the master reads theHT16C24/HT16C24G data after setting the slave address. Following the
R/W bit (=“0”) is an acknowledge bit, a command byte and the register address byte which is written to the
internal address pointer. After the start address of the Read Operation has been configured, another START
condition and the slave address transferred on the bus followed by the R/W bit (=“1”). Then the MSB of the
data which was addressed is transmitted first on the I2C bus. The address pointer is only incremented by 1 after
the reception of an acknowledge clock. That means that if the device is configured to transmit the data at the
address of AN+1, the master will read and acknowledge the transferred new data byte and the address pointer is
incremented to AN+2. After the internal address pointer reaches the maximum memory address, which is 23H
for 1/4 duty drive mode, 43H for 1/8 duty drive mode or 77H for 1/16 duty drive mode, the address pointer will
be reset to 00H.
• This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
Command byte
Register Address byte
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
1st
2nd
Slave Address
S
0
1
1
1
1
0
1
0
Write
Device Address
S
0
1
1
1
1
0
1
1
Read
Rev. 1.40
D7
D6
D5
ACK
ACK
Data byte
Data byte
D4
D3
D2
D1
D0
D7
1st data
ACK
D6
D5
D4
D3
ACK
Data byte
D2
D1
D0
D7
2nd data
ACK
24
P
D6
D5
D4
D3
Nth data
ACK
D2
D1
D0
P
NACK
ACK
October 17, 2012
HT16C24/HT16C24G
Command Summary
Display Data Input Command
This command sends data from MCU to memory MAP of the HT16C24/HT16C24G device.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Note
Display Data
Input/output
Command
1st
1
0
0
0
0
0
0
0
­
W
Address pointer
2nd
X
A6
A5
A4
A3
A2
A1
A0
Display data
start address of
memory map
W
Function
R/W Def
00H
Note:
●●Power on status: the address is set to 00H
●●If the programmed command is not defined, the function will not be affected.
●●For 1/4 duty drive mode after reaching the memory location 23H, the pointer will reset to 00H.
●●For 1/8 duty drive mode after reaching the memory location 43H, the pointer will reset to 00H.
●●For 1/16 duty drive mode after reaching the memory location 77H, the pointer will reset to 00H.
Drive Mode Command
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Driver mode
setting command
1st
1
0
0
0
0
0
1
0
Duty and Bias
setting
2nd
X
X
X
X
Function
Duty1 Bias1 Duty0 Bias0
Note
R/W Def
W
W
00H
Note:
Duty1
Duty0
Duty
0
0
1/4 duty
0
1
1/8 duty
1
X
1/16 duty
Bias1
Bias0
Bias
0
0
1/3 bias
0
1
1/4 bias
1
X
1/5 bias
●●Power on status: The drive mode 1/4 duty output and 1/3 bias is selected.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.40
25
October 17, 2012
HT16C24/HT16C24G
System Mode Command
This command controls the internal system oscillator on/off and display on/off.
Function
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
System mode setting
command
1st
1
0
0
0
0
1
0
0
W
System oscillator and
Display on/off Setting
2nd
X
X
X
X
X
X
S
E
W
Note
R/W Def
00H
Note:
Bit
DutyInternal System
oscillator
LCD Display
X
off
off
0
on
off
1
on
on
S
E
0
1
1
●●Power on status: Display off and disable the internal system oscillator.
●●If the programmed command is not defined, the function will not be affected.
Frame Frequency Command
This command selects the frame frequency.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Frame frequency
command
1st
1
0
0
0
0
1
1
0
W
Frame frequency
setting
2nd
X
X
X
X
X
X
X
F
W
Function
Note
R/W Def
00H
Note:
Bit
F
Frame Frequency
0
80Hz
1
160Hz
●●Power on status: Frame frequency is set to 80Hz.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.40
26
October 17, 2012
HT16C24/HT16C24G
Blinking Frequency Command
This command defines the blinking frequency of the display modes.
Byte
(MSB)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
(LSB)
Bit0
Blinking Frequency
command
1st
1
0
0
0
1
0
0
0
W
Blinking Frequency
setting
2nd
X
X
X
X
X
X
BK1
BK0
W
Function
Note
R/W Def
00H
Note:
Bit
Blinking Frequency
BK1
BK0
0
0
Blinking off
0
1
2Hz
1
0
1Hz
1
1
0.5Hz
●●Power on status: Blinking function is switched off.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.40
27
October 17, 2012
HT16C24/HT16C24G
Internal Voltage Adjustment (IVA) Setting Command
The internal voltage (VLCD) adjustment can provide sixteen kinds of regulator voltage adjustment options by
setting the LCD operating voltage adjustment command.
Function Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IVA
Command
IVA
Control
1st
2nd
1
X
0
X
0
DE
0
VE
1
0
1
Note
R/W
0
Def
W
●●The Segment/VLCD shared
pin can be programmed via
the “DE” bit.
●●The “VE” bit is used to enable
or disable the internal voltage
DA3 DA2 DA1 DA0
adjustment is supply voltage
to bias voltage.
●●The DA3~DA0 bits can be
used to adjust the VLCD output
voltage.
W
30H
Note:
Bit
DE
0
0
1
1
VE
0
1
0
1
Segment
71/ VLCD
shared pin
select
VLCD
VLCD
Segment 71
Segment 71
Internal
Voltage
Adjustment
Note
off
●●The bias voltage is supplied by the external VLCD pin when VCCA2
is connected to VLCD.
●●The bias voltage is supplied by the external VLCD pin when VCCA2
is connected to VDD.
●●If the VLCD pin is connected to the VDD pin, the internal voltage
follower (OP4) must be disabled by setting the DA3~DA0 bits as
“0000”.
on
●●When VCCA2 is connected to VLCD, internal voltage adjustment can
not be used to adjust internal bias voltage. (Bias voltage is supplied
by the external VLCD pin)
●●When VCCA2 is connected to VDD, internal voltage adjustment can
not be used to adjust internal bias voltage when VLCD pin is supplies
with external voltage.(Recommend: can not be used)
●●When VCCA2 is connected to VDD, internal voltage adjustment can
be used to adjust internal bias voltage when VLCD pin is floating and
internal voltage adjustment is enable.(Bias voltage is supplied by the
internal voltage adjustment)
off
●●The bias voltage is supplied by the external VLCD pin when VCCA2
is connected to VLCD.
●●The bias voltage is supplied by the external VDD power when VCCA2
is connected to VDD.
●●The internal voltage-follower (OP4) is disabled automatically and
DA3~DA0 don’t care.
on
●●When VCCA2 is connected to VLCD, internal voltage adjustment can
be used to adjust internal bias voltage when VLCD pin is supplies
with external voltage and internal voltage adjustment is enable. (Bias
voltage is supplied by the internal voltage adjustment)
●●When VCCA2 is connected to VDD, internal voltage adjustment
can be used to adjust internal bias voltage when internal voltage
adjustment is enable.(Bias voltage is supplied by the internal voltage
adjustment)
●●Power on status: Enable the internal voltage Adjustment and the Segment/VLCD pin is set as the segment pin.
●●When the DA0~DA3 bits are set to “0000”, the internal voltage-follower (OP4) is disabled. When the DA0~DA3
bits are set to other values except “0000”, the internal voltage follower (OP4) is enabled.
●●If the programmed command is not defined, the function will not be affected.
Rev. 1.40
28
October 17, 2012
HT16C24/HT16C24G
Operation Flow Chart
Display Data Read/Write
(Address Setting)
Access procedures are illustrated below by means of
the flowcharts.
Start
Initialization
Power On
Address setting
Internal LCD bias and duty setting
Display RAM data write
Internal LCD frame frequency setting
Display on and Internal system clock enabled
Segment / VLCD shared pin setting
Next processing
LCD blinking frequency setting
Next processing
Segment/VLCD Shared Pin and Internal Voltage Adjustment Setting
Start
Set as Segment pin
Internal
voltage adjustment
enable ?
yes
Segment / VLCD
share pin setting
The external MCU
can detect the
voltage of VLCD pin
The bias voltage is supplied
by Programmable Internal
voltage adjustment
no
The bias voltage is
supplied by internal VDD
power
Rev. 1.40
Set as VLCD pin
yes
Internal
voltage adjustment
enable ?
no
One external resistor must be
connected between to VLCD pin and
VDD pin to determine the bias voltage
Next processing
29
October 17, 2012
HT16C24/HT16C24G
Application Circuits
1/4 Duty
VLCD
0.1mF
VDD
0.1mF
VDD
4.7kW
VDD
4.7kW
VLCD
COM0~COM3
COM0~COM3
SCL
HT16C24
HOST
LCD Panel
SDA
SEG0~SEG70
SEG0~SEG70
VSS
VSS
VSS
1/8 Duty
VLCD
0.1mF
VDD
0.1mF
VDD
4.7kW
VLCD
VDD
4.7kW
COM0~COM7
COM0~COM7
SCL
HT16C24
HOST
LCD Panel
SDA
SEG4~SEG70
VSS
SEG0~SEG66
VSS
VSS
Rev. 1.40
30
October 17, 2012
HT16C24/HT16C24G
1/16 Duty
VLCD
0.1mF
VDD
0.1mF
VDD
4.7kW
VLCD
VDD
4.7kW
COM0~COM15
COM0~COM15
SCL
HT16C24
HOST
LCD Panel
SDA
SEG12~SEG70
VSS
SEG0~SEG58
VSS
VSS
Rev. 1.40
31
October 17, 2012
HT16C24/HT16C24G
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website Package
(http://www.holtek.com.tw/english/
Information
literature/package.pdf) for the latest version of the package information.
LQFP Outline Dimensions
80-pin LQFP
(10mm×10mm) Outline Dimensions
80-pin LQFP (10mm10mm) Outline Dimensions
Dimensions in inch
Symbol
Symbol
A
B
C
Nom. in inch
Dimensions
Max.
Nom.
0.476
Max.
―
0.476
A
Min. 0.469
B
0.390
0.469
0.398
0.390
0.469
0.476
0.390
0.398
C
D
E
―
0.469 0.390 ―
0.016
0.476
F
0.398
E
G
― 0.053
0.016
0.057
―
F
H
―
0.006
0.063
―
G
I
0.004
0.057
0.018
0.030
0.004
0.008
0.063
7
I
J
K
J
0.053 ―
―
0.018
Symbol
α
A
0° 11.90
B
9.90
C
―
―
0.004
0
K
Symbol
―
0.006
0.398
D
H
―
Dimensions in mm
0.004 Min.
Nom.
―
Max.
0.008
―
12.10
7°
10.10
Dimensions in mm
11.90
―
0.030
A
E
12.10
B
F
9.90 0.16
―
10.10
C
G
11.90 1.35
―
1.45
12.10
D
H
1.60
0.10
10.10
0.45
0.75
E
I
J
F
K
G
H
9.90
―
Nom.
12.10
Min. 9.90
11.90 D
Rev. 1.40
Min.
―
0.40
― 0.10
0.16
1.35 0
―
I
―
―
0.40
―
1
10.10
Max.
―
0.20
―
7
1.45
―
1.60
0.10
April 1,
―2010
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
32
October 17, 2012
HT16C24/HT16C24G
64-pin LQFP (7mm×7mm) Outline Dimensions
Symbol
A
Min.
Nom.
Max.
0.350
―
0.358
B
0.272
―
0.280
C
0.350
―
0.358
D
0.272
―
0.280
E
―
0.016
―
F
0.005
―
0.009
G
0.053
―
0.057
H
―
―
0.063
I
0.002
―
0.006
J
0.018
―
0.030
K
0.004
―
0.008
α
0°
―
7°
Symbol
Rev. 1.40
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
8.90
―
9.10
B
6.90
―
7.10
C
8.90
―
9.10
D
6.90
―
7.10
E
―
0.40
―
F
0.13
―
0.23
G
1.35
―
1.45
H
―
―
1.60
I
0.05
―
0.15
J
0.45
―
0.75
K
0.09
―
0.20
α
0°
―
7°
33
October 17, 2012
HT16C24/HT16C24G
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc.
Building No.10, Xinzhu Court, (No.1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2012 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication.
However, Holtek assumes no responsibility arising from the use of the specifications described.
The applications mentioned herein are used solely for the purpose of illustration and Holtek makes
no warranty or representation that such applications will be suitable without further modification,
nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For
the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
34
October 17, 2012