Small DC Motor 8-Bit Flash MCU with Driver HT45RM22/HT45RM23 Revision: V1.00 Date: ���������������� October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Table of Contents Features............................................................................................................. 5 CPU Features.......................................................................................................................... 5 Peripheral Features.................................................................................................................. 5 General Description.......................................................................................... 5 Selection Table.................................................................................................. 6 Block Diagram................................................................................................... 6 Pin Assignment................................................................................................. 6 Pin Description................................................................................................. 7 Absolute Maximum Ratings............................................................................. 7 D.C. Characteristics.......................................................................................... 8 A.C. Characteristics.......................................................................................... 8 LDO Electrical Characteristics........................................................................ 9 A/D Converter Electrical Characteristics........................................................ 9 H-Bridge Electrical Characteristics............................................................... 10 Power on Reset Characteristics.................................................................... 10 System Architecture........................................................................................11 Clocking and Pipelining...........................................................................................................11 Program Counter.................................................................................................................... 12 Stack...................................................................................................................................... 13 Arithmetic and Logic Unit – ALU............................................................................................ 13 Program Memory............................................................................................ 14 Structure................................................................................................................................. 14 Special Vectors...................................................................................................................... 14 Look-up Table......................................................................................................................... 15 Table Program Example......................................................................................................... 16 Data Memory................................................................................................... 17 Structure................................................................................................................................. 17 General Purpose Data Memory............................................................................................. 17 Special Purpose Data Memory.............................................................................................. 17 Special Function Register Description......................................................... 19 Indirect Addressing Register – IAR0, IAR1............................................................................ 19 Memory Pointers – MP0, MP1............................................................................................... 19 Accumulator – ACC................................................................................................................ 20 Program Counter Low Register – PCL................................................................................... 20 Look-up Table Registers – TBLP, TBLH................................................................................. 20 Status Register – STATUS..................................................................................................... 20 System Control Register........................................................................................................ 22 Input/Output Ports and Control Registers.............................................................................. 22 Rev. 1.00 2 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Oscillator......................................................................................................... 23 Oscillator Overview ............................................................................................................... 23 System Clock Configurations ................................................................................................ 23 Internal RC Oscillator – HIRC ............................................................................................... 23 Internal Low Speed Oscillator – LIRC.................................................................................... 23 Watchdog Timer.............................................................................................. 24 Watchdog Timer Operation.................................................................................................... 24 Reset and Initialisation................................................................................... 25 Reset Functions .................................................................................................................... 25 Reset Initial Conditions ......................................................................................................... 27 Input/Output Ports.......................................................................................... 29 Pull-high Resistors................................................................................................................. 29 Port A Wake-up...................................................................................................................... 29 I/O Port Control Registers...................................................................................................... 30 I/O Pin Structures................................................................................................................... 30 Pin-shared Functions............................................................................................................. 31 Programming Considerations................................................................................................. 32 Timer/Event Counters.................................................................................... 33 Configuring the Timer/Event Counter Input Clock Source..................................................... 33 Timer Registers – TMR0, TMR1L/TMR1H............................................................................. 33 Timer Control Registers – TMR0C, TMR1C........................................................................... 34 Timer Mode............................................................................................................................ 36 Event Counter Mode.............................................................................................................. 37 Pulse Width Measurement Mode........................................................................................... 38 Prescaler................................................................................................................................ 39 I/O Interfacing......................................................................................................................... 39 Programming Considerations................................................................................................. 39 Timer Program Example........................................................................................................ 40 Time Base.............................................................................................................................. 40 Motor Controller ............................................................................................. 41 Overview................................................................................................................................ 41 Motor Controller Register Description.................................................................................... 41 PWM Operation...................................................................................................................... 44 Complementary PWM Signals............................................................................................... 45 H-Bridge Driving Signal Control............................................................................................. 45 Dead Time Insertion............................................................................................................... 46 H-Bridge Driver...................................................................................................................... 49 H-Bridge Output Control......................................................................................................... 49 Rev. 1.00 3 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Analog to Digital Converter – ADC................................................................ 50 A/D Overview......................................................................................................................... 50 A/D Converter Data Registers – ADRL, ADRH...................................................................... 50 A/D Converter Control Register – ADCR, ACSR.................................................................... 51 A/D Operation........................................................................................................................ 52 A/D Input Pin.......................................................................................................................... 53 Summary of A/D Conversion Steps ....................................................................................... 53 Programming Considerations................................................................................................. 54 A/D Transfer Function............................................................................................................ 55 A/D Programming Example.................................................................................................... 56 Interrupts......................................................................................................... 58 Interrupt Registers.................................................................................................................. 58 Interrupt Operation................................................................................................................. 60 Interrupt Priority...................................................................................................................... 61 External Interrupt.................................................................................................................... 62 Timer/Event Counter Interrupts.............................................................................................. 62 A/D Converter Interrupt.......................................................................................................... 62 Time Base Interrupt................................................................................................................ 62 PWM Transition Interrupt....................................................................................................... 63 Programming Considerations................................................................................................. 63 Power Down Mode and Wake-up................................................................... 64 Entering the Power Down Mode............................................................................................ 64 Standby Current Considerations............................................................................................ 64 Wake-up................................................................................................................................. 64 LDO Function.................................................................................................. 65 Configuration Option...................................................................................... 66 Application Circuit.......................................................................................... 66 Instruction Set................................................................................................. 67 Introduction............................................................................................................................ 67 Instruction Timing................................................................................................................... 67 Moving and Transferring Data................................................................................................ 67 Arithmetic Operations............................................................................................................. 67 Logical and Rotate Operation................................................................................................ 68 Branches and Control Transfer.............................................................................................. 68 Bit Operations........................................................................................................................ 68 Table Read Operations.......................................................................................................... 68 Other Operations.................................................................................................................... 68 Instruction Set Summary............................................................................... 69 Table Conventions.................................................................................................................. 69 Instruction Definition...................................................................................... 71 Package Information...................................................................................... 80 10-pin MSOP Outline Dimensions......................................................................................... 81 Rev. 1.00 4 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Features CPU Features • Operating Voltage: fSYS = 4MHz: 2.2V~5.5V • Up to 1μs instruction cycle with 4MHz system clock at VDD=5V • Power Down mode and wake-up functions to reduce power consumption • Oscillator types ♦♦ Internal 4MHz RC – HIRC ♦♦ Internal RC – LIRC (for Watchdog Timer) • Fully integrated internal 4MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 4-level subroutine nesting • Bit manipulation instruction Peripheral Features • OTP Program Memory: 2K×15 • RAM Data Memory: 96×8 • 3 bidirectional I/O lines • Watchdog Timer function • 1-channel 12-bit resolution A/D converter • Motor control circuitry including H-Bridge driven by 10-bit PWM with dead time insertion • One external interrupt input shared with an I/O line • One 8-bit programmable Timer/Event Counter with overflow interrupt and prescaler • One 16-bit programmable Timer/Event Counter with overflow interrupt • Time Base function • LDO function • Low voltage reset function • Package type: 10-pin MSOP General Description The device is an 8-bit high performance RISC architecture microcontroller specifically designed for a wide range of applications. The usual Holtek microcontroller features of low power consumption, I/O flexibility, timer functions, oscillator options, Power down and wake-up functions, A/D converter, LDO function, watchdog timer and low voltage reset, combine to provide the device with a wide range of functional options while still maintaining a high level of cost effectiveness. The fully integrated system oscillator HIRC, which requires no external components and which has one fixed frequency, opens up a huge range of new application possibilities for this device, some of which may include industrial control, consumer products, household appliances subsystem controllers, etc. This device also includes integrated motor control circuitry in the way of an H-Bridge driver especially suitable for servo-motor control applications. Rev. 1.00 5 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Selection Table Part No. Program Memory VDD Data Memory IO External Interrupt A/D Timer Module 12-bit×1 8-bit TMR×1 16-bit TMR×1 10-bit PWM×1 HT45RM22 2.2V~ 5.5V 2K×15 96×8 4 1 HT45RM23 H-B Driving Stack Package 4 10MSOP 200mA 400mA Block Diagram OTP Programming Circuitry Watchdog Timer Low Voltage Reset OTP Program Memory RAM Data Memory Time Base Interrupt Controller 8-bit RISC MCU Core Reset Circuit Internal RC Oscillator 12-bit A/D Converter I/O Timers LDO Motor Driver Pin Assignment VSS PA�/AN0 NC VSS1 PA0/�UT0 1 10 � 9 3 8 � � 5 6 VCC VDD&VDDA PA�/TC1/INT VCC1 PA1/�UT1 HT45RM22 HT45RM23 10 MSOP-A Rev. 1.00 6 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Pin Description Pin Name Function OPT I/T O/T PA0 — ST NMOS General purpose I/O. Register enabled pull-high and wake-up. OUT0 CTRL0 — NMOS H-Bridge output pin 0 PA1 — ST NMOS General purpose I/O. Register enabled pull-high and wake-up. OUT1 CTRL0 — NMOS H-Bridge output pin 1 PA2 PAPU PAWK ST CMOS General purpose I/O. Register enabled pull-high and wake-up. AN0 ADCR AN — A/D channel 0 PA7 PAWK ST — General purpose input. Register enabled pull-high and wake-up. TC1 TMR1C ST — External Timer 1 clock input INT INTC0 CTRL1 ST — External interrupt input VCC1 VCC1 — PWR — H-Bridge positive power supply VSS1 VSS1 — PWR — H-Bridge negative power supply, ground VCC VCC — PWR — LDO input voltage VDD VDD — PWR — LDO output voltage, Power supply PA0/OUT0 PA1/OUT1 PA2/AN0 PA7/TC1/INT VSS Description VSS — PWR — Ground VDDA VDDA — PWR — Analog positive power supply VSSA VSSA — PWR — Analog negative power supply, ground NC — — — Not connected, can not be used. NC Note: I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; ST: Schmitt Trigger input CMOS: CMOS output; AN: Analog input pin NMOS: NMOS output Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-10˚C to 85˚C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.00 7 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver D.C. Characteristics Ta=25°C Symbol VDD Parameter Operating Voltage Test Conditions VDD — Conditions fSYS=4MHz Min. Typ. Max. Unit 2.2 — 5.5 V — 1 1.5 mA — 2 3 mA IDD Operating Current (HIRC) 3.0V No load, fSYS=4MHz 5.0V ADC disable ISTB Standby Current (WDT OSC on, LVR on) 3.0V No load, System HALT, 5.0V BRGON=0 — — 65 μA — — 80 μA VIL1 Input Low Voltage for PA, TC1 and INT 5.0V — 0 — 0.3VDD V VIH1 Input High Voltage for PA, TC1 and INT 5.0V — 0.7VDD — VDD V VIL2 Input Low Voltage for PA, TC1 and INT 2.3V — 0 — 0.2VDD V VIH2 Input High Voltage for PA, TC1 and INT 2.3V — 0.8VDD — VDD V VLVR Low Voltage Reset Voltage — 1.98 2.1 2.22 V IOH2 I/O Source Current (PA), LDO on 2.3V VOH=0.9VDD -1 -2 — mA IOL2 I/O Sink Current (PA), LDO on 2.3V VOL=0.1VDD 2 4 — mA LVR Enable, 2.1V option IOL3 PA7 Sink Current 2.3V VOL=0.1VDD 0.5 1 — mA IOL4 PA7 Sink Current 3.3V VOL=0.1VDD 1 1.5 — mA IOL5 PA7 Sink Current 5.0V VOL=0.1VDD RPH Pull-high Resistance of I/O Ports 2 3 — mA 3.0V — 20 60 100 kΩ 5.0V — 10 30 50 kΩ A.C. Characteristics Ta=25°C Symbol fSYS fHIRC Parameter System Clock System Clock (HIRC) tLVR Low Voltage Width to Reset fTIMER Timer Input Frequency (TC1) Test Conditions VDD — Conditions Min. Typ. Max. Unit 2.2V~5.5V 400 — 4000 kHz 3V/5V Ta=25°C -2% 4 +2% MHz 3V/5V Ta=0~70°C -5% 4 +5% MHz 2.2V~3.6V Ta=0~70°C -8% 4 +8% MHz 3.0V~5.5V Ta=0~70°C -8% 4 +8% MHz 2.2V~3.6V Ta=-40~85°C -12% 4 +12% MHz 3.0V~5.5V Ta=-40~85°C +12% MHz — — -12% 4 — 0.1 1 2 ms 0 — 4000 kHz — 45 90 180 μs — 32 65 130 μs — 1024 — tSYS 2.2V~5.5V 3V tWDTOSC Watchdog Oscillator Period tSST System Start-up Timer Period (wake-up From HALT) — — 2 — tSYS tINT Interrupt Pulse Width — — 1 — — μs tRSTD System Reset Delay Time — — — 100 — ms Rev. 1.00 5V For HIRC (By Configuration option) 8 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver LDO Electrical Characteristics Ta=-40~85°C, VIN=VOUT+1.0, IO=1mA, unless otherwise specified Symbol Parameter VOUT Output Voltage IOUT Output Current VIN Supply Voltage Min. Typ. Max. Unit VIN≥2.7V Test Conditions — 2.3±2% — V VIN <2.7V — VIN — V VDD≥2.7V — 7 8 mA 2.7 — 4.2 V — A/D Converter Electrical Characteristics Ta=25°C Symbol Parameter Test Conditions Conditions VDD AVDD Analog Operating Voltage — VAD AD Input Voltage — VREF=AVDD — 2.3V DNL1 Differential Non-linearity 2.7V 3.0V VREF=AVDD=VDD, tAD=0.5μs, Ta=25°C Min. Typ. Max. Unit 2.3 — 5.5 V 0 — AVDD/VREF V -6 — +6 LSB -3 — +3 LSB -10 — +10 LSB -4 — +4 LSB -15 — +15 LSB -4 — +4 LSB -20 — +20 LSB -8 — +8 LSB — 0.5 — mA — 0.6 — mA 5.0V 2.3V DNL2 Differential Non-linearity 2.7V 3.0V VREF=AVDD=VDD, tAD=0.5μs Ta=-40°C ~85°C 5.0V 2.3V INL1 Integral Non-linearity 2.7V 3.0V VREF=AVDD=VDD, tAD=0.5μs, Ta=25°C 5.0V 2.3V INL2 Integral Non-linearity 2.7V 3.0V VREF=AVDD=VDD, tAD=0.5μs Ta=-40°C ~85°C 5.0V 3.0V IADC Additional Power Consumption if A/D Converter is Used tAD A/D Clock Period 2.7V~5.5V 0.5 ─ 10 μs tADC AD Conversion Time 2.7V~5.5V 12-bit ADC ─ 16 — tAD tON2ST ADC On to ADC Start 2.7V~5.5V 2 ─ — μs Rev. 1.00 5.0V No load, tAD=0.5μs — — 9 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver H-Bridge Electrical Characteristics Ta=25°C Symbol VDDM Test Conditions Parameter Conditions VDD Operating Voltage — tCH_ON Charge Pump Turn On Time 5.0V tCH_OFF Charge Pump Turn Off Time 5.0V tBRG_ON H-Bridge Turn On Time 5.0V tBRG_OFF H-Bridge Turn Off Time 5.0V IOH I/O Source Current (OUT0, OUT1) 2.5V IOL I/O Sink Current (OUT0, OUT1) 2.5V Min. Typ. Max. — Unit 1.8 — 6 V VDD=VDDM=5V, IVDDM=0.5A — — 2 ms VDD=VDDM=2.3V, IVDDM=0.2A — — 2 ms VDD=VDDM=5V, IVDDM=0.5A — — 1 ms VDD=VDDM=2.3V, IVDDM=0.2A — — 1 ms VDD=VDDM=5V, IVDDM=0.5A — — 30 μs VDD=VDDM=2.3V, IVDDM=0.2A — — 90 μs VDD=VDDM=5V, IVDDM=0.5A — — 10 μs VDD=VDDM=2.3V, IVDDM=0.2A — — 10 μs VO=0.9VDD, HT45RM22 200 — — mA VO=0.9VDD, HT45RM23 400 — — mA VO=0.1VDD, HT45RM22 200 — — mA VO=0.1VDD, HT45RM23 400 — — mA Power on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms Rev. 1.00 10 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from the HIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clocking and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.00 11 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is ex ecuted except for instructions, such as “JMP” or “CALL” that demands a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC10~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly. However, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Rev. 1.00 12 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 4 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k B o tto m S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r S ta c k L e v e l 3 o f S ta c k C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 4 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 13 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Program Memory The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. Structure The Program Memory has a capacity of 2K×15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. • Location 000H This vector is reserved for use by the device reset for program initialization. After a device reset is initiated, the program will jump to this location and begin execution. • Location 004H This vector is used by the external interrupt. If the external interrupt pin receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. • Location 008H This internal vector is used by the Timer/Event Counter 0. If a Timer/Event Counter 0 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. Rev. 1.00 14 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver • Location 00CH This internal vector is used by the Timer/Event Counter 1. If a Timer/Event Counter 1 overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. • Location 010H This internal vector is used by the A/D Converter. If a completion of A/D conversion occurs, the program will jump to this location and begin execution if the A/D converter interrupt is enabled and the stack is not full. • Location 014H This location is used by the Time Base. If a Time Base overflow occurs, the program will jump to this location and begin execution if the Time Base interrupt is enabled and the stack is not full. • Location 018H This location is used by the PWM. When a PWM transition occurs from either low to high or high to low, dependent upon which one is selected, the program will jump to this location and begin execution if the PWM transition interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRDC [m]” or “TABRDL [m]” instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. Instruction Table Location Bits b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC[m] PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL[m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: PC10~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits Rev. 1.00 15 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “700H” which refers to the start address of the last page within the 2K Program Memory of the microcontroller. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “706H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the “TABRDC [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRDC [m]” instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer-note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address “706H”transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog. memory address “705H” transferred to tempreg2 and TBLH ; in this example the data “1AH”is transferred to ; tempreg1 and data “0FH”to register tempreg2 ; the value “00H” will be transferred to the high byte register TBLH : : org 700h; sets initial address of last page dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 16 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide and the capacity of each memory section is shown in the following Data Memory Structure diagram. The start address of the Data Memory for all devices is the address “00H”. Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the “SET [m].i” and “CLR [m].i” with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer registers. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the “SET [m].i” and “CLR [m].i” instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller are stored. Most of the registers are both read and write type but some are protected and are read only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value “00H”. Rev. 1.00 17 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver 00H IAR0 01H MP0 02H IAR1 03H MP1 04H Unused 05H ACC 06H PCL 07H TBLP 08H TBLH 09H WDTS 0AH STATUS 0BH INTC0 0CH TMR0 0DH TMR0C 0EH Unused 0FH Unused 10H PA 11H PAC 12H PAPU 13H PAWK 14H Unused 15H Unused 16H Unused 17H TMR1L 18H TMR1H 19H TMR1C 1AH CTRL0 1BH CTRL1 1CH Unused 1DH Unused 1EH INTC1 1FH Unused 20H ADRL 21H ADRH 22H ADCR 23H ACSR 24H Unused 25H BRGCR 26H BRGSW 27H Unused 28H PWMCR 29H PWML 2AH PWMH : : Unused 3FH : Unused, read as “00” Special Purpose Data Memory Rev. 1.00 18 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Special Function Register Description To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The locations of these registers within the Data Memory begin at the address “00H”. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of “00H”. Indirect Addressing Register – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 with MP0 and IAR1 with MP1 can access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, and MP1 together with IAR1 are used to access data from the Data Memory. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h ; setup size of block mov block, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 19 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. Rev. 1.00 20 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x “x” unknown Bit 7~6 Unimplemented, read as "0" Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 21 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver System Control Register These registers are used to provide control over various internal functions. Some of these include the H-Bridge output control, external Interrupt edge trigger type and Time Base function division ratio. CTRL0 Register Bit 7 6 5 4 3 2 1 0 Name — — OUTC — — — — PEG R/W — — R/W — — — — R/W POR — — 0 — — — — 0 2 1 0 Bit 7~6 Unimplemented, read as "0" Bit 5 OUTC: H-Bridge outputs OUT0/OUT1 or I/O control 0: H-Bridge outputs-OUT0/OUT1 1: I/O Bit 4~1 Unimplemented, read as "0" Bit 0 PEG: PWM transition selection for PWM interrupt 0: Falling edge 1: Raising edge CTRL1 Register Bit 7 6 5 4 3 Name INTES1 INTES0 TBSEL1 TBSEL0 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 0 0 0 1 0 1 0 Bit 7~6INTES1~INTES0: external interrupt edge selection 00: Disable 01: Rising edge trigger 10: Falling edge trigger 11: Dual edge trigger Bit 5~4TBSEL1~TBSEL0: Time base interrupt period selection 00: TB period = 1024 × (1/fTP), i.e 256 instruction cycles if fTP comes from fSYS 01: TB period = 2048 × (1/fTP), i.e 512 instruction cycles if fTP comes from fSYS 10: TB period = 4096 × (1/fTP), i.e 1024 instruction cycles if fTP comes from fSYS 11: TB period = 8192 × (1/fTP), i.e 2048 instruction cycles if fTP comes from fSYS Bit 3~0 D3~D0: undefined data bits These bits can be read or written by user software program. Input/Output Ports and Control Registers Within the area of Special Function Registers, the port data register PA and its associated control register PAC play a prominent role. These registers are mapped to specific addresses within the Data Memory. The data I/O register, is used to transfer the appropriate output or input data on the port. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialization, it is important to first setup the control register to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the “SET [m].i” and “CLR [m].i” instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control register during normal program operation is a useful feature of this device. Rev. 1.00 22 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Oscillator The device offers an HIRC oscillator as the system oscillator and a LIRC oscillator for the Watchdog Timer. Oscillator Overview The main system clock and its frequency division provide clock sources for the Time Base, Timers or PWM function. The fully integrated internal oscillator, requiring no external components, are provided to form the system oscillator. Type Internal High Speed RC Name Freq. HIRC 4MHz Oscillator Types System Clock Configurations There is only one method of generating the system clock, a high speed oscillator. The high speed oscillator is the internal 4MHz RC oscillator. An additional oscillator exists as a clock source for the Watchdog Timer and is known as the LIRC oscillator. More details are described in the accompanying sections. Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 4MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 4MHz will have a tolerance within 2%. Internal Low Speed Oscillator – LIRC The LIRC is a fully self-contained always enabled free funning on-chip RC oscillator with a typical period of 65μs at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop running, but as the WDT oscillator runs continuously, it will keep the watchdog active. Rev. 1.00 23 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Watchdog Timer The Watchdog Timer, also known as the WDT, is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when the Watchdog Timer counter overflows. Setting up the various Watchdog Timer options are controlled via the configuration options and the internal register WDTS. The Watchdog Timer is always enabled no matter whether the device operates in the normal mode or the power down mode. Also the Watchdog Timer clock is always derived from the LIRC oscillator which is always enabled. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2. If the WS0, WS1 and WS2 bits of the WDTS register are all set high, the prescaler division ratio will be 1:128, which will give a maximum time-out period. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power-down Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Two methods can be adopted to clear the contents of the Watchdog Timer. The first is using the Watchdog Timer software clear instructions and the second is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use single “CLR WDT” instruction while the second is to use the two commands “CLR WDT1” and “CLR WDT2”. For the first option, a simple execution of “CLR WDT” will clear the Watchdog Timer while for the second option, both “CLR WDT1” and “CLR WDT2” must both be executed to successfully clear the Watchdog Timer. Note that for the second option, if “CLR WDT1” is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a “CLR WDT2” instruction will clear the Watchdog Timer. Similarly after the “CLR WDT2” instruction has been executed, only a successive “CLR WDT1” instruction can clear the Watchdog Timer. WDTS Register Bit 7 6 5 4 3 2 1 0 Name — — — — — WS2 WS1 WS0 R/W — — — — — R/W R/W R/W POR — — — — — 1 1 1 Bit 7~3 Unimplemented, read as "0" Bit 2~0WS2~WS0: select WDT timeout period 000: 28 tWDTCK 001: 29 tWDTCK 010: 210 tWDTCK 011: 211 tWDTCK 100: 212 tWDTCK 101: 213 tWDTCK 110: 214 tWDTCK 111: 215 tWDTCK Rev. 1.00 24 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are four ways in which a reset can occur, through events occurring internally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. The I/O port and port control register will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Powe�-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay, typical time=100ms. Power-On Reset Timing Chart Rev. 1.00 25 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. The VLVR value is fixed at 2.1V. Note that the LVR function is always enabled regardless whether the device is in the normal mode or the powerdown mode. Note: tRSTD is power-on delay, typical time=100ms. Low Voltage Reset Timing Chart Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the Watchdog time-out flag TO will be set high. Note: tRSTD is power-on delay, typical time=100ms. WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during Power-down Mode The Watchdog time-out Reset during Power-down Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the A.C. Characteristics for tSST details. Note: The tSST value can be chosen to be either 1024 or 2 clock cycles via configuration option. WDT Time-out Reset during Power-down Mode Timing Chart Rev. 1.00 26 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power-down Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during Normal Mode operation 1 u WDT time-out reset during Normal Mode operation 1 1 WDT time-out reset during Power-down Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.00 Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 27 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register Program Counter Power-on Reset WDT Time-out (Normal Operation) WDT Time-out (HALT)* 0000 0000 0000 0000 0000 0000 MP0 xxxx xxxx xxxx xxxx uuuu uuuu MP1 xxxx xxxx xxxx xxxx uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu WDTS ---- -111 ---- -111 ---- -uuu STATUS --00 xxxx --1u uuuu --11 uuuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 -000 -000 -000 -000 -uuu –uuu TMR0 xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00-0 1000 00-0 1000 uu-u uuuu TMR1L xxxx xxxx xxxx xxxx uuuu uuuu TMR1H xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 00-0 1--- 00-0 1--- uu-u u--- PA 1-1- -111 1-1- -111 u-u- -uuu PAC 1-1- -111 1-1- -111 u-u- -uuu PAWK 0-0- -0-- 0-0- -0-- u-u- -u-- PAPU --0- -0-- --0- -0-- --u- -u-- CTRL0 --0- ---0 --0- ---0 --u- ---u CTRL1 1000 1010 1000 1010 uuuu uuuu BRGCR 0000 0000 0000 0000 uuuu uuuu BRGSW ---- 0000 ---- 0000 ---- uuuu PWMCR 0000 0000 0000 0000 uuuu uuuu uuuu uuuu PWML 0000 0000 0000 0000 PWMH ---- --00 ---- --00 ---- --uu ADRL xxxx ---- xxxx ---- uuuu ---- ADRH xxxx xxxx xxxx xxxx uuuu uuuu ADCR 01-- -0-- 01-- -0-- uu-- -u-- ACSR 11-- -000 11-- -000 uu-- -uuu Note: “u” stands for unchanged “x” stands for unknown “-” stands for unimplemented Rev. 1.00 28 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of most pin fully under user program control, pull-high selections and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides 4 bidirectional input/output lines labeled with port name PA. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, most pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using a register known as PAPU located in the Data Memory. The pull-high resistor is implemented using weak PMOS transistors. Note that only PA2 pin has a pullhigh resistor selection. PAPU Register Bit 7 6 5 4 3 2 1 0 Name — — D5 — — PAPU2 — — R/W — — R/W — — R/W — — POR — — 0 — — 0 — — “—”: Unimplemented, read as 0. D5: General data bit PAPUn: I/O Port Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the Power-down Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the PA2 and PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that pins PA2 and PA7 can be selected individually to have this wake-up feature using an internal register known as PAWK, located in the Data Memory. PAWK Register Bit 7 6 5 4 3 2 1 0 Name PAWK7 R/W R/W — D5 — — PAWK2 — — — R/W — — R/W — POR 0 — — 0 — — 0 — — “—”: Unimplemented, read as 0. D5: General data bit PAWKn: PA wake-up function enable 0: Disable 1: Enable Rev. 1.00 29 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver I/O Port Control Registers The only I/O port, named Port A, has its own control register known as PAC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pins PA2 will be setup as a CMOS output while the I/O pins PA0, PA1 and PA7 will be setup as an NMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 — D5 — — PAC2 PAC1 PAC0 R/W R/W — R/W — — R/W R/W R/W POR 1 — 1 — — 1 1 1 “—”: Unimplemented, read as "0" Bit 7PAC7: Reserved bit, must be equal to "1" and cannot be changed. Bit 6 Unimplemented, read as "0" Bit 5D5: General data bit Bit 4~3 Unimplemented, read as "0" Bit 2~0PACn: I/O Input/Output Control 0: Output 1: Input I/O Pin Structures The accompanying diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Generic CMOS Input/Output Ports Rev. 1.00 30 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver H-Bridge Outputs pin-shared with I/O pins Input/Output Port (PA7) Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The chosen function of the multi-function I/O pins is set by application program control. External Interrupt Input The external interrupt pin, INT, is pin-shared with PA7. To use the pin as an external interrupt input the correct bits in the INTC0 register must be programmed. The pin must also be setup as an input by setting the PAC7 bit in the Port Control Register. As the INT pin is pin-shared with PA7, there is no pull-high resistor internally connected to this pin. Note that even if the pin is setup as an external interrupt input the I/O function still remains. Rev. 1.00 31 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver External Timer/Event Counter Input The Timer/Event Counter pin, TC1 is pin-shared with PA7. For this shared pin to be used as the Timer/Event Counter input, the Timer/Event Counter must be configured to be in the Event Counter or Pulse Width Measurement Mode. This is achieved by setting the appropriate bits in the Timer/ Event Counter Register. The pin must also be setup as input by setting the appropriate bit in the Port Control Register. As the TC1 pin is pin-shared with PA7, there is no pull-high resistor internally connected to this pin. Note that even if the pin is setup as an external timer input the I/O function still remains. A/D Input The device has an input to the A/D converter. This analog input is pin-shared with PA2. If this pin is to be used as A/D input and not as I/O pin then the PCR bit in the A/D converter control register, ADCR, must be properly setup. There are no configuration options associated with the A/D converter. If chosen as an I/O pin, then pull-high resistor configuration remains, however if used as A/D input then the pull-high resistor configuration associated with this pin will be automatically disconnected. H-Bridge Outputs The H-Bridge function outputs, named OUT0 and OUT1, are pin-shared with I/O pins known as PA0 and PA1 respectively. The output function of the pins is chosen using the OUTC bit in the CTRL0 register. Note that when the OUTC bit is cleared to zero to configure the I/O pins to function as H-Bridge output pins, the corresponding port control bits will have no influence on the I/O pins direction control and thus these I/O pins shared with OUT0 and OUT1 will function as outputs pins. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, the I/ O data register and I/O port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register, PAC, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the port data register, PA, is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Read Modify Write Timing Pins on PA2 and PA7 each has a wake-up function, selected via the PAWK register. When the device is in the Power-down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of these pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 32 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Timer/Event Counters The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. This device contains one 8-bit and one 16-bit count-up timers. The 8-bit timer has only one operating mode, named as Timer Mode. While the 16-bit timer has three different operating modes, it can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. The provision of an internal prescaler to the clock circuitry on gives added range to the timers. There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the Timer/Event Counter and into which an initial value can be preloaded, and is known as TMR0 or TMR1L/TMR1H. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register, which defines the timer options and determines how the Timer/Event Counter is to be used, and has the name TMR0C or TMR1C. This device can have the timer clocks configured to come from the internal clock source. In addition, the timer clock source for the Timer/Event Counter 1 can also be configured to come from an external timer pin. Configuring the Timer/Event Counter Input Clock Source The Timer/Event Counter clock source can originate from various sources, an internal clock or an external pin. The internal clock source is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. For Timer/Event Counter 0, this internal clock source is first divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register bits T0PSC0~T0PSC2. For Timer/Event Counter 1, the internal clock source is derived from fSYS/4. An external clock source is used when the Timer/Event Counter 1 is in the event counting mode or pulse width measurement mode, the clock source being provided on the external timer pin, TC1. Depending upon the condition of the T1EG bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Timer Registers – TMR0, TMR1L/TMR1H The timer registers are special function registers located in the Special Purpose Data Memory and are the places where the actual timer values are stored. For the 8-bit Timer/Event Counters 0, the register is known as TMR0. For the 16-bit Timer/Event Counter 1, the timer registers are known as TMR1L/TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. Rev. 1.00 33 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note when using instructions to preload data into the low byte timer register, namely TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte timer register. The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. At the same time the data in the low byte buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. It must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Registers – TMR0C, TMR1C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. The timer control registers are known as TMRnC. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair TnM1/TnM0, must be set to the required logic levels. Note that the 8-bit timer can only operate in the timer mode. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the 16-bit timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of T1EG bit of the Timer Control Register TMR1C. Clock Structure for Timer0/PWM/Time Base Rev. 1.00 34 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver 8-bit Timer/Event Counter 0 16-bit Timer/Event Counter 1 TMR0C Register Bit 7 6 5 4 3 2 1 0 Name T0M1 T0M0 — T0ON D3 T0PSC2 T0PSC1 T0PSC0 R/W R/W R/W — R/W R/W R/W R/W R/W POR 0 0 — 0 1 0 0 0 Bit 7~6T0M1~T0M0: Timer 0 operation mode selection 00: no mode available 01: no mode available 10: Timer mode 11: no mode available Bit 5 Unimplemented, read as "0" Bit 4T0ON: Timer/Event Counter counting enable 0: Disable 1: Enable Bit 3 D3: undefined data bit This bit can be read or written by user software program. Bit 2~0T0PSC2~T0PSC0: Timer prescaler rate selection Timer internal clock= 000: fTP 001: fTP/2 010: fTP/4 011: fTP/8 100: fTP/16 101: fTP/32 110: fTP/64 111: fTP/128 Rev. 1.00 35 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver TMR1C Register Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 — T1ON T1EG — — — R/W R/W R/W — R/W R/W — — — POR 0 0 — 0 1 — — — Bit 7~6T1M1~T1M0: Timer 1 operation mode selection 00: no mode available 01: Event Counter mode 10: Timer mode 11: Pulse Width Measurement mode Bit 5 Unimplemented, read as "0" Bit 4T1ON: Timer/Event Counter counting enable 0: Disable 1: Enable Bit 3T1EG: Event Counter active edge selection 0: Count on rising edge 1: Count on falling edge Pulse Width Measurement active edge selection 0: Start counting on falling edge, stop on rising edge 1: Start counting on rising edge, stop on falling edge Bit 2~0 Unimplemented, read as "0" Timer Mode In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode Bit7 Bit6 1 0 In this mode the internal clock is used as the timer clock. The timer input clock source is fSYS for Timer/Event Counter 0 and fSYS/4 for Timer/Event Counter 1. However, for Timer/Event Counter 0 this timer clock source is further divided by a prescaler, the value of which is determined by the bits T0PSC2~T0PSC0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the interrupts can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register are reset to zero. Timer Mode Timing Chart (for Timer/Event Counter 0) Rev. 1.00 36 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Timer Mode Timing Chart (for Timer/Event Counter 1) Event Counter Mode In this mode, a number of externally changing logic events occurring on the external timer pin, TC1, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode Bit7 Bit6 0 1 In this mode, the external timer pin, TC1, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit T1EG, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/ Event Counter Interrupt Enable bit in the Interrupt Control Register is reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counter Mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Power-down Mode, the Timer/ Event Counter will continue to record externally changing logic events on the timer input pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. Event Counter Mode Timing Chart (T1EG=1) Rev. 1.00 37 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Pulse Width Measurement Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin, TC1. To operate in this mode, the Operating Mode Select bit pair, T1M1/T1M0, in the Timer Control Register must be set to the correct values shown. Control Register Operating Mode Select Bits for the Pulse Width Measurement Mode Bit7 Bit6 1 1 In this mode the internal clock, fSYS/4 is used as the internal clock for the 16-bit Timer/Event Counter. After the other bits in the Timer Control Register have been setup, the enable bit T1ON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. If the Active Edge Select bit T1EG, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, TC1, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/ Event Counter will stop counting. It is important to note that in the Pulse Width Measurement Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin, TC1. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. Not until the enable bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register is reset to zero. As the TC1 pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second is to ensure that the port control register configures the pin as an input. Pulse Width Capture Mode Timing Chart (T1EG=0) Rev. 1.00 38 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Prescaler Bits T0PSC0~T0PSC2 of the TMR0C register can be used to define a division ratio for the internal clock source of the Timer/Event Counter 0 enabling longer time-out periods to be setup. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, requires the use of an external timer pin for its operation. As this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a Timer/Event Counter input pin. This is achieved by ensuring that the mode select bits in the Timer/Event Counter control register select either the event counter or pulse width measurement mode. Additionally the corresponding Port Control Register bit must be set high to ensure that the pin is setup as an input. Any pull-high resistor connected to this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control register. When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the Timer/Event Counter interrupt is enabled, this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Powerdown condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the “HALT” instruction to enter the Power-down Mode. Rev. 1.00 39 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Timer Program Example This program example shows how the Timer/Event Counter registers are setup along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counters to be in the timer mode, which uses the internal system clock as their clock source. Timer Programming Example org 04h; External interrupt vector org 08h ; Timer Counter 0 interrupt vector jmp tmr0int ; jump here when Timer 0 overflows : : org 20h; main program : : ; internal Timer 0 interrupt routine tmr0int: : ; Timer 0 main program placed here : : begin: ; setup Timer 0 registers mov a,09bh ; setup Timer 0 preload value mov tmr0,a mov a,081h ; setup Timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmr0c.4 ; start Timer 0 : : Time Base The device includes a Time Base function which is used to generate a regular time interval signal. The Time Base time interval magnitude is determined using an internal 13 stage counter sets the division ratio of the clock source. This division ratio is controlled by both the TBSEL0 and TBSEL1 bits in the CTRL1 register. The clock source is derived from the system clock source fSYS. When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken when programming. Rev. 1.00 40 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Motor Controller The device contains a full motor driver function, which integrated PWM driver and H-Bridge driver functions. The motor controller is especially suitable for driving servo motors. Overview The motor controller function within the device includes an H-Bridge driver and 10-bit PWM function. Useful for the applications such as servo motor control, the PWM function generated signals with a variable duty cycle that is adjusted by setting particular values into corresponding PWM registers. It also provides complementary output controlled by setting the enable control bit, CPLEN, in the BRGCR register. The PWM signal or PWM complementary signal pair can be mapped into four driving signals which are used to drive the NMOS-type H-Bridge driver. To avoid the situation where both high and low drive transistors in the H-Bridge are simultaneously turned on, a dead time can be inserted when the driving signal is switched from a low to high level. The hardware protection circuits will force the corresponding driving signals to a low state when unpredictable conditions occur such as electrical noise or application program malfunction. The PWM signal transition will also generate interrupt request to inform the user to take any appropriate action with regard to adjusting the PWM duty cycle. 10-�it PWM PWM � PWMB PPSC[�:0] BRG�N H-B�idge D�iving Signal Cont�ol (fo� N-type only) Complementa�y Ci��uit Type Sele�tion DTDIS VDDM � DeadTime Inse�tion � � H-B�idge D�ive� �UT0 �UT1 fSYS DT[�:0] BRGM [1:0] BRGS M U X H/W P�ote�tion � PWM fSYS BRGS Softwa�e Cont�ol CPLEN DTPSC[1:0] CPPS[1:0] BRG�N To Inte��upt PEG Motor Controller Block Diagram Motor Controller Register Description Overall operation of the Motor Controller is controlled using five registers. A PWM duty register pair, named as PWMH and PWML, exists to store the desired 10-bit PWM duty value. The remaining three registers are control registers which are used for PWM setup, complementary output control, H-Bridge signal control, dead time insertion and H-Bridge driver functions such as the different operating and control modes as well as several timing related selections. When writing to the PWMH/PWML register pair, data must first be written to the PWML register before writing data to the PWMH register. Rev. 1.00 41 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver PWMH, PWML Registers Register PWMH PWML 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R/W — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W POR — — — — — — 0 0 0 0 0 0 0 0 0 0 “—”: Unimplemented, read as "0" D9~D0: PWM duty bits D9~D0 = 0→PWM duty = 0/1024 D9~D0 = 1→PWM duty = 2/1024 D9~D0 = 2→PWM duty = 3/1024 D9~D0 = 3→PWM duty = 4/1024 : : D9~D0 = 1022→PWM duty = 1023/1024 D9~D0 = 1023→PWM duty = 1024/1024 Writing data to these registers must be carried out in a specific way. First write the low byte data into the PWML register and then write the high byte data into the PWMH register. PWMCR Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name DT2 DT1 DT0 DTPSC1 DTPSC0 PPSC2 PPSC1 PPSC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~5 DT2~DT0: dead time selection 000: dead time is 1/fD 001: dead time is 2/fD 010: dead time is 3/fD 011: dead time is 4/fD 100: dead time is 5/fD 101: dead time is 6/fD 110: dead time is 7/fD 111: dead time is 8/fD Bit 4~3 DTPSC1~DTPSC0: dead time prescaler ratio 00: fD = fSYS/2 01: fD = fSYS/4 10: fD = fSYS/8 11: fD = fSYS/16 Bit 2~0 PPSC2~PPSC0: PWM prescaler ratio (the prescaler is shared with Timer 0) 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 42 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver BRGCR Register Bit 7 6 5 4 3 2 1 0 Name BRGON BRGS DTDIS CPLEN CPPS1 CPPS0 BRGM1 BRGM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit7BRGON: H-Bridge function enable control 0: Disable 1: Enable When BRGON is cleared to zero, all of the H-Bridge related functions will be turned off. At this time, the four NMOS drive transistor in the H-Bridge will also be switched off and the H-Bridge output OUT0/OUT1 will be in a floating stage. Bit6 BRGS: H-Bridge driving source selection. 0: from PWM signal 1: determined by software bits in the BRGSW register If BRGON=0 or BRGS=1, the PWM function will be disabled automatically. Bit 5DTDIS: Dead time insertion disable control 0: Enable 1: Disable Bit4 CPLEN: PWM complementary circuit enable control 0: Disable 1: Enable Bit 3~2CPPS1~CPPS0: Charge Pump circuit clock prescaler ratio 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 The charge pump clock prescaler ratio together with the system clock frequency should both be taken into consideration to select a suitable charge pump clock. Bit 1~0BRGM1~BRGM0: H-Bridge operating mode control 00: Brake → two outputs OUT0/OUT1 are connected to ground 01: Forward 10: Backward 11: Brake → two outputs OUT0/OUT1 are connected to VDDM If the H-Bridge operating mode is changed by modifying the BRGM1 and BRGM0 bits when the H-Bridge function is active, the operating mode will be changed immediately. BRGSW Register Bit 7 6 5 4 3 2 1 0 Name — — — — SDON SCON SBON SAON R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit3SDON: H-Bridge NMOS on/off controlled by SD 0: Off 1: On Bit2SCON: H-Bridge NMOS on/off controlled by SC 0: Off 1: On Bit1SBON: H-Bridge NMOS on/off controlled by SB 0: Off 1: On Rev. 1.00 43 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Bit0SAON: H-Bridge NMOS on/off controlled by SA 0: Off 1: On These software control bits are only effective if the BRGS bit is set high. Once the SAON/SBON/SCON/SDON is set, the SA/SB/SC/SD can turn on the related N-MOS and the control is independent with each other between SA/SB/SC/SD. Therefore, user has to take care not to turn on (SA, SB) or (SC, SD) simultaneously and inserting a proper dead time is necessary. PWM Operation The device contains a 10-bit PWM function used to provide the driving signals for the H-Bridge driver. A register pair, known as PWML/PWMH, is assigned to specify the PWM duty. It is here that the 10-bit value, which represents the overall duty of the fixed period of the signal waveform, should be placed. The PWM clock source is derived from the system clock fSYS. The system clock source can be divided by a prescaler and then drive the 10-bit counter to get a longer PWM period. The PWM duty cycle is determined by the duty register pair PWML/PWMH while the PWM period is determined by the 10-bit counter overflow period. Note that the PWM function will be turned off when the H-Bridge function is disabled or the H-Bridge driver is driven by the software control bits in the BRGSW register. P�es�ale� fSYS fPWM 10-�it Counte� �ve�flow BRG�N BRGS PPSC[�:0] 10-�it Compa�ato� Compa�e Mat�h S R To Inte��upt Duty/Pe�iod Management PWM Duty 10-�it shadow �egiste� 10-�it Duty �egiste� Pe�iod Dete�mined �y Counte� �ve�flow Update New Duty Value New Duty Value appea�s 10-bit PWM Block Diagram The 10-bit counter is a free running count-up counter and is driven by the clock source fPWM, which is obtained from fSYS divided by a certain ratio selected using the PWM prescaler rate selection bits, PPSC2~PPSC0, in the PWMCR register. The 10-bit Comparator will compare the 10-bit counter value with the PWM duty value stored in the PWML/PWMH registers. When the 10-bit counter value is less than the PWM duty value, the PWM signal will be in a high state. When the 10-bit counter value is equal to or greater than the PWM duty value, then the PWM signal will be in a low state. When the 10-bit counter overflows, the counter value will be zero and then the PWM signal will return to a high state. Thus the 10-bit counter overflow period determines the PWM signal period. When the PWM signal changes state from either low to high or high to low determined by the type selection bit PEG in the CTRL0 register, it will trigger an interrupt request and then the application program will jump to the corresponding interrupt vector if the corresponding interrupt control bit is enabled and the stack is not full. The PWM duty value is stored in the 10-bit duty register pair PWML/PWMH. Writing a value into the 10-bit PWM duty register must be carried out in a specific way. Writing data into the low byte PWM duty register, PWML, will only place the data in a low byte buffer and not directly into the low byte PWM duty register. The actual data transfer into the low byte PWM duty register, PWML, is only carried out when a write to its associated high byte PWM duty register, namely, PWMH, is executed. Using instructions to preload data into the high byte PWM duty register will result in the data being directly written to the high byte PWM duty register. At the same time the data in the low byte buffer will be transferred into its associated low byte PWM duty register. For this reason, the low byte PWM duty register should be written first. Rev. 1.00 44 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Note that if the PWM function is disabled and data is written to its duty registers, this data will be immediately written into the 10-bit PWM shadow registers. However, if the PWM function is enabled and the counter is counting, any new data written into the PWM duty registers during this period will remain in the PWM duty registers and will only be written into the PWM shadow registers the next time a PWM counter overflow occurs. Complementary PWM Signals For PWM signal generation, users can decide whether to have single end PWM signals or complementary PWM signal pairs to drive the H-Bridge driver. The complementary function is enabled by setting the CPLEN bit in the BRGCR register to 1. The PWM complementary signal is simply the reverse of the PWM signal and is shown in the accompanying diagram. PWM Complementa�y Fun�tion CPLEN PWM PWMB PWM PWMB Complementary Signal Diagram H-Bridge Driving Signal Control When a PWM single end signal or PWM complementary pair signal is generated, there are used to create the corresponding H-Bridge gate driving signals. The gate driving signals internally named SA1 and SC1 are used to drive the H-Bridge high drive transistors while the driving signals named SB1 and SD1 are used to drive the H-Bridge low drive transistors. BRGSW PWM PWMB H-B�idge D�iving Signal Cont�ol � � M U X SA1� SB1� SC1� SD1 BRGS BRGM [1:0] H-Bridge Driving Signal Control Block Diagram Rev. 1.00 45 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver When the H-Bridge driving signals are selected to be controlled by the PWM driver, which means the BRGS bit is cleared to zero, the related control circuit will automatically generate the corresponding driving signals according to the PWM signal and the H-bridge operating mode. In this mode the internal NMOS-type H-Bridge driver is used to drive external components. Note that if these gate driving signals are delivered to external pins when an external H-Bridge is to be used, the external H-Bridge must be implemented using NMOS transistors, otherwise, it will result in unpredictable operation. The relation between the PWM single end signals or the PWM complementary pair signals and the H-Bridge driving signals depends upon which mode the H-Bridge operates in. The accompanying table shows the relationship between the PWM signals and the gate driving signals. BRGON CPLEN SA SB SC 0 x BRGM[1:0] Operation xx xx 0 0 0 SD 0 1 0 00 Brake 0 1 0 1 1 0 01 Forward PWM 0 0 1 1 0 10 Backward 0 1 PWM 0 1 0 11 Brake 1 0 1 0 1 1 00 Brake 0 1 0 1 1 1 01 Forward PWM PWMB 0 1 1 1 10 Backward 0 1 PWM PWMB 1 1 11 Brake 1 0 1 0 PWM Controlled H-Bridge Gate Driving Signals – BRGS=0 In addition to PWM signal control, the H-Bridge driving signal control can also be derived from the application software by configuring the SAON, SBON, SCON and SDON bits in the BRGSW register when the BRGS bit is set high. Dead Time Insertion When the H-Bridge gate driving signals are used to drive the four NMOS power transistors, there may be a momentary condition when both high and low drive transistors will be simultaneously turned on. As this would result in a large DC current, to avoid this a dead time can be generated. The overall dead time insertion function is controlled by the enable bit named DTDIS in the BRGCR register. When the DTDIS bit is set high, the dead time insertion function will be turned off. The dead time insertion circuitry is driven by the dead time clock, fD, obtained from the internal dead time prescaler, which is divided ratio of the system clock fSYS. The dead time clock frequency ranges from fSYS/2 to fSYS/16 which is selected by the dead time prescaler selection bits DTPSC1~DTPSC0 in the PWMCR register. After the dead time clock source is determined, the inserted dead time duration can also be selected from 1 dead time clock period, 1/fD, to 8 dead time clock periods, 8/fD, by configuring the dead time selection bits, DT2~DT0, in the PWMCR register. fSYS SA1� SB1� SC1� SD1 SA� SB� Dead Time Inse�tion SC� DTDIS SA Ha�dwa�e P�ote�tion SD� DT [�:0] SB SC SD DTPSC [1:0] Dead Time Insertion Block Diagram Rev. 1.00 46 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver When the clock source and inserted dead time duration have been determined, the selected dead time will be inserted at the rising edge of the gate driving signals. This means that after the dead time is enabled, the gate driving signal rising edge will be delayed for the selected dead time period and before switching to a high state. The accompanying waveform diagram shows the gate driving signals with or without dead time insertion. Note that if the original high pulse width of the driving signal is less than the dead time duration, the signal high pulse will not be generated after the dead time has been inserted. SA1� SB1 SC1� SD1 Pulse is not gene�ated. (pulse width < dead time) SA�� SB� SC�� SD� Dead Time Dead Time Dead Time Gate Driving Signal Width/Without Dead Time Insertion When an unpredictable condition occurs, such as electrical noise or the application program malfunction, it may result in a condition where by the high and low drive transistors both are turned on simultaneously. The device provides hardware protection functions to avoid such situations. When the driving signals of the high and low drive transistors are both at a high level, the hardware protection circuits will automatically force the driving signals both to a low state no matter whether the dead time function is enabled or disabled. Both d�iving signal a�e fo��ed to low Both high and low d�iving signal a�e high SA� SA SB� SB Ha�dwa�e P�ote�tion SC� SC SD� SD Gate Driving Signal Hardware Protection The following diagram shows the timing relationship when the H-bridge, which is driven by the PWM signals, operates in different modes with the influence of complementary output control. Rev. 1.00 47 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Fo�wa�d pe�iod duty SA SB SC Dead time Dead time ina�tive a�tive SD Ba�kwa�d SA ina�tive a�tive SB SC SD Complementary Output – CPLEN=1&BRGS=0 Fo�wa�d pe�iod duty SA SB ina�tive SC ina�tive a�tive SD Ba�kwa�d SA ina�tive a�tive SB SC ina�tive SD Complementary Output – CPLEN=0&BRGS=0 Rev. 1.00 48 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver H-Bridge Driver The four gate driving signals are used to drive the NMOS transistors in the H-Bridge Driver. As larger gate drive currents are required, the H-Bridge NMOS transistors are driven by a charge pump. The charge pump clock is divided by an internal prescaler of which the divided ratio is selected by the charge pump prescaler ratio selection bits, CPPS1 and CPPS0, in the BRGCR register. The charge pump clock prescaler ratio together with the system clock frequency is used to select a suitable charge pump clock frequency. The charge pump circuit is controlled by the H-Bridge enable control bit, BRGON. When the BRGON bit is set high, the charge pump circuit will be enabled. If the BRGON bit is cleared to zero, the charge pump circuit will be switched off. It must be noted that no matter whether the charge pump circuit is enabled or disabled, a certain delay period, named tCH_ ON and tCH_OFF respectively, will be inserted after the control bit is updated before an operation starts or stops. H-B�idge D�ive� CPPS [1:0] Cha�ge Pump Ci��uit BRG�N SA The�mal Dete�to� �UT0 NM�S D�ive� VDDM SB SC SA SC SB SD �UT1 SD H-Bridge Driver Block Diagram The device also provides an internal thermal detector which prevents the device from operating under high device temperatures. When the internal device temperature is higher than about 150°C, the thermal detector will generate a shutdown signal to turn off the charge pump circuit and the H-Bridge Driver automatically. Once the thermal shutdown signal is generated, the charge pump circuit and the H-Bridge driver will not operate until the device returns to a temperature of below about 150°C. H-Bridge Output Control The H-Bridge outputs are pin-shared with the I/O pins PA0 and PA1. To operate as H-Bridge outputs and not as I/O pins, the OUTC bit in the CTRL0 register must be cleared to zero. Once the I/O pins PA0 and PA1 are used as the H-Bridge output pins, OUT0 and OUT1, the corresponding bits in the I/O port control register PAC.0 and PAC.1 have no effect on the output pins. Rev. 1.00 49 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Analog to Digital Converter – ADC The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a 1-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Structure A/D Converter Data Registers – ADRL, ADRH The device, which contains an internal 1-channel 12-bit A/D converter, requires two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. Only the high byte register, ADRH, utilizes its full 8-bit contents. The low byte register utilizes only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. In the following tables, D0~D11 are the A/D conversion data result bits. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ADRL D3 D2 D1 D0 — — — Bit 0 — ADRH D11 D10 D9 D8 D7 D6 D5 D4 A/D Data Registers Rev. 1.00 50 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver A/D Converter Control Register – ADCR, ACSR To control the function and operation of the A/D converter, two control registers known as ADCR and ACSR are provided. These 8-bit registers define functions such as whether the pin is used as analog input or not, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ADCR control register contains a PCR bit which determines whether the PA2 pin is used as analog input for the A/D converter input or not. Setting the bit high will select the A/D input function, clearing the bit to zero will select the I/O function. When the pin is selected to be an A/D input, its original I/O function will be removed. In addition, the internal pull-high resistor connected to this pin will be automatically removed if the pin is selected to be an A/D input. ADRH, ADRL Registers Bit ADRH 7 6 Name D11 D10 ADRL 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 — — — — R/W R R R R R R R R R R R R — — — — POR x x x x x x x x x x x x — — — — “x”: unknown “—”: unimplemented D11~D0: A/D converter conversion data ADCR Register Bit 7 6 5 4 3 2 1 0 Name START EOCB — — — PCR — — R/W R/W R — — — R/W — — POR 0 1 — — — 0 — — Bit 7START: Start the A/D conversion 0→1→0: Start 0→1: Reset the A/D converter and set EOCB to “1” This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running, the bit will be high. Rev. 1.00 Bit 5~3 Unimplemented, read as "0" Bit 2 PCR: A/D channel configuration 0: I/O 1: Analog input If the PCR bit is zero, the ADC circuit is power off to reduce power consumption. Bit 1~0: Unimplemented, read as "0" 51 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver ACSR Register Bit 7 6 5 4 3 2 1 0 Name TEST ADONB — — — ADCS2 ADCS1 ADCS0 R/W R/W R/W — — — R/W R/W R/W POR 1 1 — — — 0 0 0 Bit 7 TEST: for test mode use only Bit 6ADONB: ADC module on/off control bit. 0: ADC module is turn on 1: ADC module is turn off Bit 5~3 Unimplemented, read as "0" Bit 2~0ADCS2~ADCS0: Select A/D converter clock source 000: fSYS/2 001: fSYS/8 010: fSYS/32 011: Undefined, can not be used 100: fSYS 101: fSYS/4 110: fSYS/16 111: Undefined, can not be used A/D Operation The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically cleared to zero by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS The division ratio value is determined by the ADCS2~ADCS0 bits in the ACSR register. Controlling the power on/off function of the A/D converter circuitry is implemented using the ADONB bit. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2~ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD is 0.5µs, care must be taken for system clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the ADCS2~ADCS0 bits should not be set to “100”. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk* show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. Rev. 1.00 52 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver A/D Clock Period (tAD) fSYS ADCS2, ADCS1, ADCS0=000 (fSYS/2) ADCS2, ADCS1, ADCS0=001 (fSYS/8) ADCS2, ADCS1, ADCS0=010 (fSYS/32) ADCS2, ADCS1, ADCS0=011 ADCS2, ADCS1, ADCS0=100 (fSYS) ADCS2, ADCS1, ADCS0=101 (fSYS/4) ADCS2, ADCS1, ADCS0=110 (fSYS/16) ADCS2, ADCS1, ADCS0=111 1MHz 2μs 8μs 32μs Undefined 1μs 4μs 16μs Undefined 2MHz 1μs 4μs 16μs Undefined 500ns 2μs 8μs Undefined 4MHz 500ns 2μs 8μs Undefined 250ns* 1μs 4μs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADONB bit in the ACSR register. This bit must be zero to power on the A/D converter. When the ADONB bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if the pin is not selected for use as A/D input by clearing the PCR bit in the ADCR register, if the ADONB bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADONB is set high to reduce power consumption when the A/D converter function is not being used. A/D Input Pin The A/D analog input pin is pin-shared with an I/O pin on port A. The PCR bit in the ADCR register, determines whether the input pin is setup as an A/D converter analog input or I/O pin. If the PCR bit is set high then the pin will be setup to be an A/D converter input and the I/O function disabled. In this way, the pin can be changed under program control to change its function between A/D input and I/O function. The pull-high resistor, which is setup through register programming, will be automatically disconnected if the pin is setup as an A/D input. Note that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable the A/D input as when the PCR bit enables an A/D input, the status of the port control register will be overridden. Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCS2~ADCS0 in the ACSR register. • Step 2 Enable the A/D by clearing the ADONB bit in the ACSR register to zero. • Step 3 Select the pin to be used as A/D input and configure it by correctly programming the PCR bit in the ADCR register. • Step 4 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. • Step 5 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. Note that this bit should have been originally cleared to zero. Rev. 1.00 53 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver • Step 6 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs, the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. A/D Conversion Timing Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADONB high in the ACSR register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to the input line. If the A/D converter input line is used as a normal I/O, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. Rev. 1.00 54 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver A/D Transfer Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD, this gives a single bit analog input value of VDD/4096. 1 LSB = VDD ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × VDD ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Note that to reduce the quantization error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level. Ideal A/D Transfer Function Rev. 1.00 55 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example 1: using an EOCB polling method to detect the end of conversion clr ADE; disable ADC interrupt mov a, 01H movACSR, a; select fSYS/8 as A/D clock and ADONB=0 mov a,04H ; setup ADCR register to configure the pin as A/D input mov ADCR, a ; and connect the pin to the A/D Converter : : Start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a, ADRL ; read low byte conversion result value mov adrl_buffer, a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov adrh_buffer, a ; save result to user defined register : : jmp start_conversion ; start next A/D conversion Note: To power off the ADC module, it is necessary to set the ADONB bit high. Rev. 1.00 56 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Example 2: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt mov a, 01H movACSR, a; select fSYS/8 as A/D clock and ADONB=0 mov a,04H ; setup ADCR register to configure the pin as A/D input mov ADCR, a ; and connect the pin to the A/D Converter : : Start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE; enable ADC interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_: mov acc_stack, a ; save ACC to user defined memory mov a, STATUS mov status_stack, a ; save STATUS to user defined memory : : mov a, ADRL ; read low byte conversion result value mov adrl_buffer, a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov adrh_buffer, a ; save result to user defined register : : EXIT_ISR: mov a, status_stack mov STATUS, a ; restore STATUS from user defined memory mov a, acc_stack ; restore ACC from user defined memory clr ADF ; clear ADC interrupt flag reti Note: To power off the ADC module, it is necessary to set the ADONB bit high. Rev. 1.00 57 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains a single external interrupt and multiple internal interrupts. The external interrupt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the Timer/Event Counters overflow, Time Base, PWM transition and the A/D converter. Interrupt Registers Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using two registers, INTC0 and INTC1. By controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable control bit if cleared to zero will disable all interrupts. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/ disable bit or “F” for request flag. Function Enable Bit Request Flag Notes Global EMI — — INT Pin INTE INTF — n=0 or 1 Timer/Event Counter TnE TnF A/D Converter ADE ADF — Time Base TBE TBF — PWME PWMF — PWM edge interrupt Interrupt Register Bit Naming Conventions INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — T1F T0F INTF T1E T0E INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6T1F: Timer/Event Counter 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5T0F: Timer/Event Counter 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4INTF: External Interrupt Request Flag 0: No request 1: Interrupt request Bit 3T1E: Timer/Event Counter 1 Interrupt Control 0: Disable 1: Enable Bit 2T0E: Timer/Event Counter 0 Interrupt Control 0: Disable 1: Enable Rev. 1.00 58 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Bit 1INTE: External Interrupt Control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Name — PWMF TBF ADF — PWME TBE ADE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 PWMF: PWM transition Interrupt Request Flag 0: No request 1: Interrupt request Bit 5TBF: Time Base Interrupt Request Flag 0: No request 1: Interrupt request Bit 4ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 PWME: PWM transition Interrupt Control 0: Disable 1: Enable Bit 1TBE: Time Base Interrupt Control 0: Disable 1: Enable Bit 0ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Rev. 1.00 59 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Interrupt Operation A Timer/Event Counter overflow, a completion of A/D conversion, a Time Base event, a PWM transition or an active edge on the external interrupt pin will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI instruction, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Interrupt Structure Rev. 1.00 60 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Main P�og�am Inte��upt Request o� Inte��upt Flag Set �y Inst�u�tion N Ena�le �it set? Y Main P�og�am Automati�ally Disa�le Inte��upt Clea� EMI & Request Flag Wait fo� �~3 Inst�u�tion Cy�les ISR Ent�y ... ... RETI (it will set EMI automati�ally) Interrupt Flow When an interrupt request is generated, it takes 2 or 3 instruction cycle before the program jumps to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request, then it will take 3 cycles before the program jumps to the interrupt vector. Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Priority Vector External Interrupt 1 04H Timer/Event Counter 0 Overflow 2 08H Timer/Event Counter 1 Overflow 3 0CH 10H A/D Conversion Complete 4 Time Base Overflow 5 14H PWM Transition Interrupt 6 18H In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. Rev. 1.00 61 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, INTE, must first be set. An actual external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when an edge transition appears on the external INT pin. The type of transition that will trigger an external interrupt, whether high to low, low to high or both is determined by the INTES0 and INTES1 bits, which are bits 6 and 7 of the CTRL1 register respectively. These two bits can also disable the external interrupt function. INTES1 INTES0 0 0 External interrupt disable Edge Trigger Type 0 1 Rising edge Trigger 1 0 Falling edge Trigger 1 1 Both edge Trigger The external interrupt pin is pin-shared with the I/O pin PA7 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set and the edge trigger type has been selected using the CTRL1 register. The pin must also be setup as an input by setting the corresponding PAC.7 bit in the port control register. When the interrupt is enabled, the stack is not full and an active transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on this pin will remain valid even if the pin is used as an external interrupt input. Timer/Event Counter Interrupts For a Timer/Event Counter generated internal interrupt to occur, the global interrupt enable bit, EMI, and the corresponding internal interrupt enable bit, TnE, must be first set. An actual Timer/Event Counter interrupt will be generated when the Timer/Event Counter interrupt request flag, TnF, is set, a situation that will occur when the relevant Timer/Event Counter overflow occurs, a subroutine call to the relevant timer interrupt vector will take place. When the interrupt is serviced, the Timer/Event Counter interrupt request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Converter Interrupt For an A/D interrupt to occur, the global interrupt enable bit EMI and the corresponding interrupt enable bit ADE must be first set. An actual A/D interrupt will take place when the A/D converter request flag ADF is set, a situation that will occur when an A/D conversion process has completed. When the interrupt is enabled, the stack is not full and an A/D conversion process finishes execution, a subroutine call to the relevant A/D interrupt vector, will take place. When the interrupt is serviced, the A/D interrupt request flag ADF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Time Base Interrupt For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and a time base overflow occurs, a subroutine call to the time base vector will take place. When the interrupt is serviced, the time base interrupt flag, TBF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Rev. 1.00 62 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver CTRL1 Register Bit 7 6 5 4 3 2 1 0 Name INTES1 INTES0 TBSEL1 TBSEL0 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 0 0 0 1 0 1 0 Bit 7~6 Described elsewhere Bit 5~4TBSEL1~TBSEL0: Time base interrupt period selection 00: TB period = 1024 × (1/fTP), i.e 256 instruction cycles if fTP comes from fSYS 01: TB period = 2048 × (1/fTP), i.e 512 instruction cycles if fTP comes from fSYS 10: TB period = 4096 × (1/fTP), i.e 1024 instruction cycles if fTP comes from fSYS 11: TB period = 8192 × (1/fTP), i.e 2048 instruction cycles if fTP comes from fSYS Bit 3~0 D3~D0: undefined data bits PWM Transition Interrupt For a PWM transition interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit, PWME, must first be set. An actual PWM transition interrupt will take place when the internal PWM signal transition interrupt request flag PWMF is set, a situation that will occur when the internal PWM signal changes state from either high to low or low to high determined by the type selection bit, PEG, in the CTRL0 register. When the interrupt is enabled, the stack is not full and a PWM transition interrupt event occurs, a subroutine call to the PWM transition interrupt vector will take place. When the interrupt is serviced, the PWM interrupt flag, PWMF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processer when in the Power Down Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 63 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Power Down Mode and Wake-up Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the “HALT” instruction in the application program. When this instruction is executed, the following will occur: • The system oscillator will stop running and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present condition. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package type, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. The Watchdog Timer will continue to run when in the Power Down Mode and thus will consume some power since the Watchdog Timer is enabled and the clock source is derived from the LIRC oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on PA2 and PA7 • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wakeup that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Pins PA2 and PA7 can be setup via the PAWK register to permit a negative transition on the pin to wake-up the system. When a PA2 or PA7 pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. Rev. 1.00 64 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, then any interrupt requests will not generate a wake-up function of the related interrupt will be ignored. No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. Consult the table for the related time. LDO Function This device contains an LDO circuitry for the regulated power supply. The accompanying block diagram illustrates the basic functional operation. The internal LDO can provide fixed voltage for MCU and external power supply. The detailed specification of LDO is as following: • VIN: 2.7V~4.2V • VOUT = 2.3V±2% @ VIN≥2.7V & VOUT=Vin @ VIN <2.7V • Output Current : 7 mA (Typ); 8 mA (Max) VDD VCC VCC1 LD� VDD/VDDA �UT0 PA�/TC1/INT H-Bridge MCU �UT1 PA�/AN0 VSS/VSSA VSS Rev. 1.00 VSS1 65 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Configuration Option Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Watchdog Options 1 CLR WDT instructions: 1 or 2 instructions System Start-up Time Options 2 SST selection: 1024 or 2 clocks Application Circuit DC�.5~�.�V Li Bat VDD LD� VCC VCC1 LD� �ut0 TC1/INT �.�G RF SPI Host MCU H-Bridge PA�/AN0 NC MCU 66 M VDD VR VSS/AVSS VSS Rev. 1.00 �ut1 VDD/AVDD VSS1 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 67 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 68 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 69 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 70 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 71 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 72 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 73 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 74 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.00 75 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.00 76 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 77 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 78 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 79 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 80 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver 10-pin MSOP Outline Dimensions Symbol Min. Nom. Max. A — — 0.043 A1 0.000 — 0.006 A2 0.030 0.033 0.037 B 0.007 — 0.013 C 0.003 — 0.009 D — 0.118 BSC — E — 0.193 BSC — E1 — 0.118 BSC — e — 0.020 BSC — L 0.016 0.024 0.031 L1 — 0.037 BSC — y — 0.004 — θ 0° — 8° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A — — 1.10 A1 0.00 — 0.15 A2 0.75 0.85 0.95 B 0.17 — 0.33 C 0.08 — 0.23 D — 3.00 BSC — E — 4.90 BSC — E1 — 3.00 BSC — e — 0.50 BSC — L 0.40 0.60 0.80 L1 — 0.95 BSC — y — 0.1 — θ 0° — 8° 81 October 17, 2014 HT45RM22/HT45RM23 Small DC Motor 8-Bit Flash MCU with Driver Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 82 October 17, 2014