HT47C20L -- R-F Type Low Voltage 8-Bit Mask MCU

HT47C20L
R-F Type Low Voltage 8-Bit Mask MCU
Technical Document
· Tools Information
· FAQs
· Application Note
-
HA0029E
HA0030E
HA0034E
HA0036E
HA0045E
Using the Time Base Function in the HT47R20A-1
Using the RTC in the HT47R20A-1
Using the Buzzer Function in the HT47R20A-1
Using the PFD Function in the HT47R20A-1
Distinguishing between the Different Devices in the HT47 MCU Series
Features
· Operating voltage: 1.2V~2.2V
· One low voltage reset circuit
· Eight bidirectional I/O lines
· HALT function and wake-up feature reduce power
consumption
· Four input lines
· One interrupt input
· LCD bias C type
· One 16-bit programmable timer/event counter with
· One LCD driver with 20´2 or 20´3 or 19´4 segments
· Two channels RC type A/D converter
PFD (programmable frequency divider) function
· On-chip 32768Hz crystal oscillator
· Four-level subroutine nesting
· Watchdog Timer
· Bit manipulation instruction
· 2K´16 program memory ROM
· 16-bit table read instruction
· 64´8 data memory RAM
· Up to 122ms instruction cycle with 32768Hz system
clock
· One real time clock (RTC)
· One 8-bit prescaler for real time clock
· All instructions in one or two machine cycles
· One buzzer output
· 63 powerful instructions
· One low voltage detector
· 64-pin LQFP package
General Description
power applications among which are calculators, clock
timers, games, scales, toys, thermometers, hygrometers, body thermometers, capacitor scaler, other hand
held LCD products, and battery system in particular.
The HT47C20L is an 8-bit high performance RISC-like
microcontroller. Its single cycle instruction and
two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low
Rev. 2.50
1
June 23, 2008
HT47C20L
Block Diagram
P B 0 /IN T
P ro g ra m
R O M
S T
S T
S T
S T
P ro g ra m
C o u n te r
A C
A C
A C
A C
In te rru p t
C ir c u it
K 0
K 1
K 2
K 3
M
T im e r A
U
S y s te m C lo c k
T 1
R T C O u tp u t
P B 2 /T M R
X
IN T C
P B 3 /P F D
P F D
T im e r B
In s tr u c tio n
R e g is te r
M
M P
U
D A T A
M e m o ry
X
W D T
S h ifte r
S
D
S
P o rt B
A C C
C 1
L C D
M e m o ry
D o u b le
V o lta g e
Rev. 2.50
1
T 0
1
3 2 7 6 8 H z
( a lw a y s o n )
L C D D r iv e r
V 2
V 3
C O M 0 ~
C O M 2
C O M 3 /
S E G 1 9
P B 2 /T M R
P B 3
P o rt A
S E G 0 ~
S E G 1 8
2
P B 0 /IN T
P B 1
P B
P A
V 1
1
0
0
T im e B a s e
B P
C 2
0
R e a l T im e C lo c k
T im in g
G e n e ra to r
C 1
IN 0
C S
R S
C R
R T
IN 1
C S
R S
R T
R C
T y p e
A /D
C o n v e rte r
S T A T U S
A L U
O S
R E
V D
V S
C lo c k
M U X
In s tr u c tio n
D e c o d e r
O S C 2
A /D
P A
P A
P A
P A
P A
0 /B
1 /B
2
3 /P
4 ~ P
Z
Z
F D
A 7
June 23, 2008
HT47C20L
Pin Assignment
S E
S E
S E
V
O S
O S
R
G 2
G 1
G 0
V 3
V 2
V 1
C 2
C 1
N C
N C
D D
C 2
C 1
E S
N C
N C
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
P A
P A
P A
P B 0 /IN
P B
P B 2 /T M
P B
N
N
N
N
6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9
1
Z
2
Z
3
4
5
6
7
C
4 6
4
4 5
4 4
5
6
7
8
1
1 0
3
1 2
H T 4 7 C 2 0 L
6 4 L Q F P -A
9
T
R
4 7
2
D
C
C
C
4 8
1 1
1 3
1 4
1 5
1 6
1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
C O M
C O M
C O M
C O M
IN 0
C S 0
R S 0
C R T
R T 0
IN 1
C S 1
R S 1
R T 1
V S S
N C
N C
0
3 /S E G 1 9
2
1
0
Pin Description
I/O
Mask
Option
I
¾
I/O
Wake-up
Pull-high
or None
CMOS or
NMOS
Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without pull-high resistors
(mask option). NMOS output can be configured as Schmitt trigger input
with or without pull-high resistors. Each bit of NMOS output can be configured as wake up input by mask option. Of the eight bits, PA0~PA1 can be
set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O
pin or a PFD output by mask option.
I
¾
Four-bit Schmitt trigger input port. The PB is configured as with pull-high
resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT) by software application. While PB2 can be set as an
input pin or a timer/event counter input pin by software application.
VSS
¾
¾
Negative power supply, ground
V1~V3, C1~C2
¾
¾
Voltage pump
SEG19/COM3
COM2~COM0
O
SEG18~SEG0
O
¾
LCD driver outputs for LCD panel segments
Pin Name
RES
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
PB0/INT
PB1
PB2/TMR
PB3
Function
Schmitt trigger reset input. Active low.
1/2 or 1/3 or 1/4 SEG19/COM3 can be set as a segment or a common output driver for LCD
Duty
panel by mask option. COM2~COM0 are outputs for LCD panel plate.
VDD
¾
¾
Positive power supply
OSC2
OSC1
O
I
¾
OSC1 and OSC2 are connected to a 32768Hz crystal for the internal system clock and WDT source.
IN0
CS0
RS0
CRT0
RT0
I
O
O
O
O
¾
Oscillation input pin of channel 0
Reference capacitor connection pin of channel 0
Reference resistor connection pin of channel 0
Resistor/capacitor sensor connection pin for measurement of channel 0
Resistor sensor connection pin for measurement of channel 0
IN1
CS1
RS1
RT1
I
O
O
O
¾
Oscillation input pin of channel 1
Reference capacitor connection pin of channel 1
Reference resistor connection pin of channel 1
Resistor sensor connection pin for measurement of channel 1
Rev. 2.50
3
June 23, 2008
HT47C20L
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+2.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
¾
¾
1.2
1.5
2.2
V
VLVD
Low Voltage Detector Voltage
¾
¾
1.1
1.2
1.3
V
VLVR
Low Voltage Reset Voltage
¾
¾
1.0
1.1
1.2
V
IDD1
Operating Current
(LVR Disable, LVD Disable)
1.5V
No load, fSYS=32768Hz
A/D Off, LVD Off
¾
4
8
mA
IDD2
Operating Current
(LVR Disable, LVD Enable)
1.5V
No load, fSYS=32768Hz
A/D Off, LVD Off
¾
9
15
mA
IDD3
Operating Current
(LVR Enable, LVD Enable)
1.5V
No load, fSYS=32768Hz
A/D Off, LVD Off
¾
12
20
mA
ISTB1
Standby Current
(Mask Option Select LVR Disable,
LVD Disable, LCD Off)
1.5V
No load, system HALT
A/D Off, LVD Off
¾
1
2
mA
ISTB2
Standby Current
(Mask Option Select LVR Disable,
LVD Enable, LCD On or Off)
1.5V
No load, system HALT
A/D Off, LVD Off
¾
6
10
mA
ISTB3
Standby Current
(Mask Option Select LVR Enable,
LVD Enable, LCD On or Off)
1.5V
No load, system HALT
A/D Off, LVD Off
¾
9
15
mA
ISTB4
Standby Current
(Mask Option Select LVR Disable,
LVD Enable, LCD On or Off)
1.5V
No load, system HALT
A/D Off, LVD On
¾
8
15
mA
IAD
Additional Power Consumption if
A/D is Used
1.5
A/D On
*R=5.1kW, *C=500pF
¾
270
500
mA
VIL
Input Low Voltage for I/O Ports, INT, TMR
¾
¾
0
¾
0.3VDD
V
VIH
Input High Voltage for I/O Ports, INT, TMR
¾
¾
0.8VDD
¾
VDD
V
VIL1
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH1
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Sink Current
1.5V VOL=0.15V
0.3
0.6
¾
mA
IOH
I/O Port Source Current
1.5V VOH=1.35V
-0.2
-0.4
¾
mA
IOL1
Common 0~3 Output Sink Current
1.5V VOL=0.3V (1/2bias)
120
230
¾
mA
IOH1
Common 0~3 Output Source Current
1.5V VOH=2.7V (1/2bias)
-50
-100
¾
mA
IOL2
Segment 0~19 Output Sink Current
1.5V VOL=0.3V (1/2bias)
30
60
¾
mA
IOH2
Segment 0~19 Output Source Current
1.5V VOH=2.7V (1/2bias)
-20
-30
¾
mA
IOL3
Common 0~3 Output Sink Current
1.5V VOL=0.45V (1/3bias)
120
220
¾
mA
Rev. 2.50
4
June 23, 2008
HT47C20L
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
IOH3
Common 0~3 Output Source Current
1.5V VOH=4.05V (1/3bias)
-50
-100
¾
mA
IOL4
Segment 0~19 Output Sink Current
1.5V VOL=0.45V (1/3bias)
30
60
¾
mA
IOH4
Segment 0~19 Output Source Current
1.5V VOH=4.05V (1/3bias)
-20
-30
¾
mA
IOL5
RC oscillation Output Sink Current
1.5V VOL=0.15V
2
2.7
¾
mA
IOH5
RC oscillation Output Source Current
1.5V VOH=1.35V
-2
-3.1
¾
mA
RPH
Pull-high Resistance of I/O Ports and INT 1.5V
100
150
200
kW
Note:
*R means the resistance of RC type A/D converter
¾
*C means the capacitance of RC type A/D converter
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS1
System Clock
1.5V
¾
¾
32768
¾
Hz
fTIMER
Timer I/P Frequency (TMR)
1.5V
¾
0
¾
32768
Hz
tRES
External Reset Low Pulse Width
¾
¾
100
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
1.5V
¾
100
¾
¾
ms
tLVD
Low Voltage Detector Response Time
1.5V
¾
200
¾
¾
ms
fAD
A/D Converter Frequency
1.5V
¾
¾
¾
500
kHz
Note: tSYS=1/fSYS
Rev. 2.50
5
June 23, 2008
HT47C20L
Functional Description
Execution Flow
incremented by 1. The program counter then points to
the memory word containing the next instruction code.
The HT47C20L system clock is derived from a 32768Hz
crystal oscillator. The system clock is internally divided
into four non-overlapping clocks (T1, T2, T3 and T4).
One instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction
to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instruction. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 2048
addresses.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
In s tr u c tio n C lo c k
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
1
0
0
Time Base Interrupt
0
0
0
0
0
0
0
1
0
0
0
Real Time Clock Interrupt
0
0
0
0
0
0
0
1
1
0
0
Timer/event Counter Interrupt
0
0
0
0
0
0
1
0
0
0
0
@0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
S10~S0: Stack register bits
Rev. 2.50
@7~@0: PCL bits
6
June 23, 2008
HT47C20L
· Location 00CH
Program Memory - ROM
This area is reserved for the real time clock interrupt
service program. If a real time clock interrupt occurs,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´16 bits, addressed by the program counter and
table pointer.
· Location 010H
This area is reserved for the timer/event counter interrupt service program. If timer interrupt results from a
Timer/Event Counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 010H.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only. The table pointer (TBLP) is a read/write
register (07H), which indicates the table location. Before accessing the table, the location must be placed
in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (interrupt service routine) both employ the table read instruction,
the contents of the TBLH in the main routine are likely
to be changed by the table read instruction used in the
ISR. Errors can occur. In other words using the table
read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need two cycles to complete the
operation. These areas may function as normal program memory depending upon the requirements.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program
begins execution at location 004H.
· Location 008H
This area is reserved for the time base interrupt service program. If time base interrupt resulting from a
time base overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
E x te r n a l in te r r u p t s u b r o u tin e
0 0 8 H
0 0 C H
0 1 0 H
T im e B a s e In te r r u p t s u b r o u tin e
R e a l T im e C lo c k
In te r r u p t s u b r o u tin e
P ro g ra m
R O M
T im e r /e v e n t C o u n te r in te r r u p t s u b r o u tin e
n 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
7 F F H
Stack Register - STACK
1 6 b its
N o te : n ra n g e s fro m
0 to 7
This is a special part of the memory which is used to
save the contents of the Program Counter only. The stack
is organized into four levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
Program Memory
Instruction(s)
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Bits of table location
@7~@0: Bits of table pointer
P10~P8: Bits of current program counter
Rev. 2.50
7
June 23, 2008
HT47C20L
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent four return addresses are stored).
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
P A
S p e c ia l P u r p o s e
D a ta M e m o ry
1 3 H
Data Memory - RAM
1 4 H
The data memory is designed with 83´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(64´8). Most are read/write, but some are read only.
P B
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
The special function registers include the indirect addressing register 0 (00H), the memory pointer register 0 (MP0;
01H), the indirect addressing register 1 (02H), the memory
pointer register 1 (MP1;03H), the bank pointer (BP;04H),
the accumulator (ACC;05H), the program counter
lower-order byte register (PCL;06H), the table pointer
(TBLP;07H), the table higher-order byte register
(TBLH;08H), the real time clock control register
(RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers
(PA;12H, PB;14H), the interrupt control register 1
(INTC1;1EH), the Timer/Event counter A higher order byte
register (TMRAH; 20H), the Timer/Event Counter A lower
order byte register (TMRAL; 21H), the timer/event counter
control register (TMRC; 22H), the Timer/Event Counter B
higher order byte register (TMRBH; 23H), the Timer/Event
Counter B lower-order byte register (TMRBL; 24H), and
the RC oscillator type A/D converter control register
(ADCR; 25H). The remaining space before the 40H are
reserved for future expanded usage and reading these
location will return the result 00H. The general purpose
data memory, addressed from 40H to 7FH, is used for
data and control information under instruction command.
1 A H
1 B H
1 C H
1 D H
1 E H
IN T C 1
1 F H
2 0 H
T M R A H
2 1 H
T M R A L
2 2 H
T M R C
2 3 H
T M R B H
2 4 H
T M R B L
2 5 H
A D C R
2 6 H
: U n u s e d
3 F H
4 0 H
R e a d a s "0 0 "
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
7 F H
RAM Mapping (Bank 0)
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for
some dedicated bits, each bit in the data memory can be
set and reset by the ²SET [m].i² and ²CLR [m].i² instruction, respectively. They are also indirectly accessible
through memory pointer registers (MP0;01H,
MP1;03H).
Rev. 2.50
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HT47C20L
register will not change the TO or PDF flags. In addition it should be noted that operations related to the
status register may give different results from those
intended. The TO and PDF flags can only be
changed by the Watchdog Timer overflow, system
power-up, clearing the Watchdog Timer and executing the ²HALT² instruction.
The function of data movement between two indirect addressing registers are not supported. The memory
pointer registers, MP0 and MP1, are both 8-bit registers
which can be used to access the data memory by combining corresponding indirect addressing registers.
MP0 only can be applied to data memory, while MP1
can be applied to data memory and LCD display memory.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
is capable of carrying out immediate data operations.
The data movement between two data memory locations must pass through the accumulator.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
status are important and if the subroutine can corrupt
the status register, precautions must be taken to save it
properly.
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
The HT47C20L provides an external interrupt, an internal timer/event counter interrupt, an internal time base
interrupt, and an internal real time clock interrupt. The
interrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits to set the enable/disable and interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval, but
only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the
programmer may set the EMI bit and the corresponding
bit of INTC0 or INTC1 allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the SP is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
The ALU not only saves the results of a data operation
but can change the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF) and watchdog time-out flag (TO). It also
records the status information and controls the operation
sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction. PDF
is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
STATUS (0AH) Register
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HT47C20L
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC0), caused by a regular real time clock signal.
When the interrupt is enabled, and the stack is not full
and the RTF bit is set, a subroutine call to location 0CH
will occur. The related interrupt request flag (RTF) will be
reset and the EMI bit cleared to disable further interrupts.
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified locations in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program
which corrupts the desired control sequence, the contents must be saved first.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI² instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.
External interrupt is triggered by a high to low transition of
INT and the related interrupt request flag (EIF; bit 4 of
INTC0) will be set. When the interrupt is enabled, and the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag
(EIF) and EMI bits will be cleared to disable other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not
full and the TF bit is set, a subroutine call to location 10H
will occur. The related interrupt request flag (TF) will be
reset and the EMI bit cleared to disable further interrupts.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC0), caused
by a regular time base signal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a
subroutine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit
cleared to disable further interrupts.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Time Base Interrupt
2
08H
c
Real Time Clock Interrupt
3
0CH
d
Timer/event Counter Interrupt
4
10H
Bit No.
Label
Function
0
EMI
Control the master (global) interrupt (1=enabled; 0=disabled)
1
EEI
Control the external interrupt (1=enabled; 0=disabled)
2
ETBI
3
ERTI
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
TBF
Time base interrupt request flag (1=active; 0=inactive)
6
RTF
Real time clock interrupt request flag (1=active; 0=inactive)
7
¾
Control the time base interrupt (1=enabled; 0=disabled)
Control the real time clock interrupt (1=enabled; 0=disabled)
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
ETI
Control the timer/event counter interrupt (1=enabled; 0=disabled)
1~3, 5~7
¾
Unused bit, read as ²0²
4
TF
Internal timer/event counter interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
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HT47C20L
Watchdog Timer - WDT
The external interrupt request flag (EIF), real time clock
interrupt request flag (RTF), time base interrupt request
flag (TBF), enable external interrupt bit (EEI), enable
real time clock interrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI)
constitute an interrupt control register 0 (INTC0) which
is located at 0BH in the data memory. The timer/event
counter interrupt request flag (TF), enable timer/event
counter interrupt bit (ETI) on the other hand, constitute
an interrupt control register 1 (INTC1) which is located
at 1EH in the data memory. EMI, EEI, ETI, ETBI, and
ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being
serviced. Once the interrupt request flags (RTF, TBF,
TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by
a software instruction.
The clock source of the WDT (fS) is implemented by a
32768Hz crystal oscillator. The timer is designed to prevent a software malfunction or sequence jumping to an
unknown location with unpredictable results. The
Watchdog Timer can be disabled by mask option. If the
Watchdog Timer is disabled, all the executions related to
the WDT result in no operation.
The ²HALT² instruction is executed, WDT still counts and
can wake-up from halt mode due to the WDT time-out.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a ²warm reset² only the
Program Counter and SP are reset to 0. To clear the contents of WDT, three methods are adopted, external reset
(a low level to RES), software instruction, or a ²HALT² instruction. The software instructions are of two sets which
include ²CLR WDT² and the other set - ²CLR WDT1² and
²CLR WDT2². Of these two types of instruction, only one
can be active depending on the mask option - ²CLR WDT
times selection option². If the ²CLR WDT² is selected (i.e.,
CLR WDT times equal one), any execution of the ²CLR
WDT² instruction will clear the WDT. In case ²CLR WDT1²
and ²CLR WDT2² are chosen (i.e. ²CLR WDT² times equal
two), these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip because of
the time-out.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left, and enabling the interrupt is not well
controlled, the original control sequence will be damaged once the ²CALL subroutine² operates in the interrupt subroutine.
Oscillator Configuration
The HT47C20L provides one 32768Hz crystal oscillator
for real time clock and system clock. The 32768Hz crystal oscillator still work at halt mode. The halt mode stop
the system clock and T1 and ignores an external signal
to conserve power. The real time clock comes from
32768Hz crystal and still works at halt mode.
The WDT time-out period ranges from fS/215~fS/216. The
²CLR WDT² or ²CLR WDT1² and ²CLRWDT2² instruction only clear the last two-stage of the WDT.
Multi-function Timer
A 32768Hz crystal across OSC1 and OSC2 is needed
to provide the feedback and phase shift needed for the
oscillator, no other external components are needed.
O S C 1
3 2 7 6 8 H z
The HT47C20L provides a multi-function timer for the WDT,
time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source
coming from the 32768Hz. The multi-function timer also
provides a fixed frequency signal (fS/8) for the LCD driver
circuits, and a selectable frequency signal (ranges from
fS/22 to fS/29) for buzzer output by mask option.
fs
( s till w o r k s a t h a lt m o d e )
S y s te m c lo c k
( S to p s a t h a lt m o d e )
O S C 2
C r y s ta l O s c illa to r
T 1
( s to p s a t h a lt m o d e )
32768Hz Crystal
3 2 7 6 8 H z C ry s ta l O S C
fS
D iv id e r
fS /2
8
P r e s c a le r
C K
T
R
C K
T
R
T im e - o u t R e s e t
fS /2 1 5 ~ fS /2 1 6
W D T C le a r
Watchdog Timer
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Time Base
Power Down Operation - HALT
The time base offers a periodic time-out period to generate
a regular internal interrupt. Its time-out period ranges from
fS/212 to fS/215 selected by mask option. If time base
time-out occurs, the related interrupt request flag (TBF; bit
5 of INTC0) is set. But if the interrupt is enabled, and the
stack is not full, a subroutine call to location 08H occurs.
The halt mode is initialized by the ²HALT² instruction
and results in the following.
When the ²HALT² instruction is executed, the time base
still works and can wake up from halt mode. If the TBF is
set ²1² before entering the halt mode, the wake up function
will be disabled.
· The WDT will be cleared and recount again.
· The 32768Hz crystal oscillator will still work but the
system clock and T1 will turn off.
· The contents of the on-chip RAM and registers remain
unchanged.
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
· LCD driver is still running (by mask option).
· The time base and real time clock will still work.
Real Time Clock - RTC
The system can leave the halt mode by means of an external reset, an interrupt, an external falling edge signal
on port A or a WDT overflow. An external reset causes a
device initialization and the WDT overflow performs a
²warm reset². Examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is
cleared when system power-up or executing the ²CLR
WDT² instruction and is set when the ²HALT² instruction
is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program
Counter and SP, the others maintain their original status.
The real time clock is operated in the same manner as
the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to fS/215 by
software programming. Writing data to RT2, RT1 and
RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out
periods. If a real time clock time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC0) is set. But if
the interrupt is enabled, and the stack is not full, a subroutine call to location 0CH occurs. The real time clock
time-out signal can also be applied as a clock source of
Timer/Event Counter A, so as to get a longer time-out
period.
RT2
RT1
RT0
RTC Clock
Divided Factor
0
0
0
28
0
0
1
29
0
1
0
210
0
1
1
211
1
0
0
212
1
0
1
213
1
1
0
214
1
15
2
fS
D iv id e r
1
1
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences
may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt response takes place.
If an interrupt request flag is set to ²1² before entering
the halt mode the wake-up function of the related interrupt will be disabled.
fS /2
8
P r e s c a le r
M a s k O p tio n
L C D D r iv e r f S /8
B u z z e r
fS /2 2 ~ fS /2
9
T im e B a s e In te r r u p t
fS /2 1 2 ~ fS /2 1 5
Time Base
fS
fS /2
D iv id e r
R T 2
R T 1
R T 0
8
P r e s c a le r
8 to 1
M u x .
fS /2 8 ~ fS /2 1 5
R e a l T im e C lo c k In te r r u p t
Real Time Clock
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HT47C20L
If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be
delayed by more than one cycle. However, if the
wake-up results in the next instruction execution, the execution will be performed immediately.
To guarantee that the crystal oscillator has started and
stabilized, the SST (system start-up timer) provides an
extra delay of 8192 system clock pulses when the system powers up.
The functional unit chip reset status are shown below.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the halt mode.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, Real Time Clock,
Time Base
Clear. After master reset,
begin counting
Timer/event Counter
Off
· The LVR is enable and the VDD is lower then VLVR
Input/output Ports
Input mode
The WDT time-out during halt mode is different from
other chip reset conditions, since it can perform a warm
reset that just resets the Program Counter and SP leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
Stack Pointer
Points to the top of the stack
Reset
There are three ways in which a reset may occur.
· RES reset during normal operation
· RES reset during halt mode
· WDT time-out reset during normal operation
TO
PDF
0
0
System power-up
u
u
RES reset or LVR reset during normal
operation
0
1
RES reset or LVR reset wake-up from
HALT mode
1
u
WDT time-out during normal operation
1
1
WDT wake-up from HALT mode
V
D D
R E S
RESET Conditions
Reset Circuit
H A L T
W D T
T im e - o u t
R e s e t
R E S
Note: ²u² means ²unchanged²
O S C 1
W a rm
W D T
R e s e t
E x te rn a l
C o ld
R e s e t
S S T
1 3 - b it R ip p le
C o u n te r
V D D
P o w e r - o n D e te c tio n
R E S
tS
S T
Reset Configuration
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
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HT47C20L
The states of the registers are summarized in the following table:
Register
WDT time-out
RES reset
(normal Operation) (normal operation)
Reset
(power on)
RES reset
(HALT)
WDT time-out
(HALT)
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
0000 1---
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
Program
Counter
000H
000H
000H
000H
000H*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
RTCC
--xx 0111
--xx 0111
--xx 0111
--xx 0111
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Note:
²*² refers to ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
The timer/event counter clock source may come from
system clock or T1 (system clock/4) or real time clock
time-out signal or external source.
Timer/Event Counter
One 16-bit timer/event counter with PFD output or two
channels of RC type A/D converter is implemented in
Using external clock input allows the user to count external events, count external RC type A/D clock, measure
time intervals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
the HT47C20L. The ADC/TM bit (bit 1 of ADCR register)
decides whether timer A and timer B are composed of
one 16-bit timer/event counter or timer A and timer B are
composed of two channels RC type A/D converter.
The TMRAL, TMRAH, TMRBL, TMRBH composed of one
16-bit timer/event counter, when ADC/TM bit is ²0². The
TMRBL and TMRBH are timer/event counter preload
registers for lower-order byte and higher-order byte respectively.
C lo c k
T 1
A /D C lo c k
R e a l T im e C lo c k O u tp u t
There are six registers related to the timer/event counter
operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC
([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR
([25H]). Writing to TMRBL only writes the data into a low
S y s te m
D a ta B u s
M
U
1 6 - b it T im e r A
X
T M R 0
O v e r flo w
T
R
Q
P F D
T E
T M
T M
T M
T O
N
1
2
0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 - b it T im e r B
T M 2
T M 1
T M 0
R e lo a d
P A 3 D a ta C T R L
Timer/Event Counter
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HT47C20L
Bit No.
Label
0~2
¾
Unused bit, read as ²0²
3
TE
To define the TMR active edge of the timer/event counter
(0= active on low to high; 1= active on high to low)
4
TON
To enable/disable timer counting (0= disabled; 1= enabled)
TM0
TM1
TM2
To define the operating mode (TM2, TM1, TM0)
000= Timer mode (system clock)
001= Timer mode (system clock/4)
010= Timer mode (real time clock output)
011= A/D clock mode (RC oscillation decided by ADCR register)
100= Event counter mode (external clock)
101= Pulse width measurement mode (system clock/4)
110= Unused
111= Unused
5
6
7
Function
TMRC (22H) Register
In the event count, A/D clock or internal timer mode,
once the timer/event counter starts counting, it will count
from the current contents in the timer/event counter
(TMRAH and TMRAL) to FFFFH. Once overflow occurs,
the counter is reloaded from the timer/event counter
preload register (TMRBH and TMRBL) and generates
the corresponding interrupt request flag (TF; bit 4 of
INTC1) at the same time.
byte buffer, and writing to TMRBH will write the data and
the contents of the low byte buffer into the time/event
counter preload register (16-bit) simultaneously. The
timer/event counter preload register is changed by writing to TMRBH operations and writing to TMRBL will keep
the timer/event counter preload register unchanged.
Reading TMRAH will also latch the TMRAL into the low
byte buffer to avoid the false timing problem. Reading
TMRAL returns the contents of the low byte buffer. In
other words, the low byte of the timer/event counter can
not be read directly. It must read the TMRAH first to
make the low byte contents of timer/event counter be
latched into the buffer.
In the pulse width measurement mode with the TON
and TE bits equal to 1, once the TMR has received a
transient from low to high (or high to low if the TE bit is
0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that in this operation
mode, the timer/event counter starts counting not according to the logic level but according to the transient
edges. In the case of counter overflow, the counter is reloaded from the timer/event counter preload register
and issues interrupt request just like the other three
modes.
If the timer/event counter is on, the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written to. To
avoid conflicting between timer A and timer B, the
TMRAH, TMRAL, TMRBH and TMRBL registers
should be accessed with ²MOV² instruction under
timer off condition.
The TMRC is the timer/event counter control register,
which defines the timer/event counter options.
The timer/event counter control register define the operating mode, counting enable or disable and active edge.
To enable the counting operation, the timer On bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will automatically be
cleared after the measurement cycle is completed. But
in the other three modes, the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources and can also be applied as
a PFD (programmable frequency divider) output at PA3
by mask option. No matter what the operation mode is,
writing a 0 to ETI can disable the corresponding interrupt service. When the PFD function is selected, executing ²CLR PA.3² instruction to enable the PFD output and
executing ²SET PA.3² instruction to disable the PFD
output and PA.3 output low level.
Writing to timer B location puts the starting value in the
timer/event counter preload register, while reading timer
A yields the contents of the timer/event counter. Timer B
is timer/event counter preload register.
The TM0, TM1 and TM2 bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source comes from an external (TMR) pin. The A/D clock mode is used to count external A/D clock, the RC oscillation mode is decided by
ADCR register. The timer mode functions as a normal
timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level
duration of the external signal (TMR). The counting is
based on the T1 (system clock/4).
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HT47C20L
In the case of timer/event counter Off condition, writing
data to the timer/event counter preload register also reloads that data to the timer/ event counter. But if the
timer/event counter turns On, data written to the
timer/event counter preload register is kept only in the
timer/event counter preload register. The timer/event
counter will still operate until overflow occurs.
It is strongly recommended to load first the desired
value into TMRBL, TMRBH, TMRAL, and TMRAH registers then turn on the related timer/event counter for
proper operation. Because the initial value of TMRBL,
TMRBH, TMRAL and TMRAH are unknown.
If the timer/event counter is on, the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written to.
Only when the timer/event counter is off and when
the instruction ²MOV² is used could those four registers be read or written to.
When the timer/event counter (reading TMRAH) is read,
the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer.
Example for Timer/event counter mode (disable interrupt):
clr tmrc
clr adcr.1
; set timer mode
clr intc1.4
; clear timer/event counter interrupt request flag
mov a, low (65536-1000)
; give timer initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00110000b
; timer clock source=T1 and timer on
tmrc, a
p10:
clr wdt
snz intcl.4
; polling timer/event counter interrupt request flag
jmp p10
clr intcl.4
; clear timer/event counter interrupt request flag
; program continue
Rev. 2.50
16
June 23, 2008
HT47C20L
A/D Converter
Reading TMRAH/TMRBH will also latch the
TMRAL/TMRBL into the low byte buffer to avoid the
false timing problem. Reading TMRAL/TMRBL returns
the contents of the low byte buffer. In other word, the low
byte of timer A/timer B can not be read directly. It must
read the TMRAH/TMRBH first to make the low byte contents of timer A/timer B be latched into the buffer.
Two channels of RC type A/D converter are implemented in the HT47C20L. The A/D converter contains
two 16-bit programmable count-up counter and the
timer A clock source may come from the system clock,
T1 (system clock/4) or real time clock output. The timer
B clock source may come from the external RC oscillator. The TMRAL, TMRAH, TMRBL, TMRBH are composed
of the A/D converter when ADC/TM bit (bit 1 of ADCR register) is ²1².
If the A/D converter timer A and timer B are counting, the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. To avoid conflicting
between timer A and timer B, the TMRAH, TMRAL,
TMRBH and TMRBL registers should be accessed
with ²MOV² instruction under timer A and timer B off
condition.
The A/D converter timer B clock source may come from
channel 0 (IN0 external clock input mode, RS0~CS0 oscillation, RT0~CS0 oscillation, CRT0~CS0 oscillation
(CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is
a capacitor) or channel 1 (RS1~CS1 oscillation,
RT1~CS1 oscillation or IN1 external clock input). The
timer A clock source is from the system clock, T1 or real
time clock prescaler clock output decided by TMRC register.
The bit4~bit7 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to
TMRBH and TMRBL.
The TM0, TM1 and TM2 bits of TMRC define the clock
source of timer A. It is suggested that the clock source of
timer A use the system clock, instruction clock or real
time clock prescaler clock.
There are six registers related to A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of the ADCR register) decides
whether timer A overflows or timer B overflows, then the
TF bit is set and timer interrupt occurs. When the A/D
converter mode timer A or timer B overflows, the TON bit
is reset and stop counting. Writing TMRAH/TMRBH puts
the starting value in the timer A/timer B and reading
TMRAH/TMRBH gets the contents of the timer A/timer
B. Writing TMRAL/TMRBL only writes the data into a low
byte buffer, and writing TMRAH/TMRBH will write the
data and the contents of the low byte buffer into the
timer A/timer B (16-bit) simultaneously. The timer
A/timer B is change by writing TMRAH/TMRBH operations and writing TMRAL/TMRBL will keep the timer
A/timer B unchanged.
Rev. 2.50
The TON bit (bit 4 of TMRC) is set ²1², the timer A and
timer B will start counting until timer A or timer B overflows, the timer/event counter generates the interrupt request flag (TF ; bit 4 of INTC1) and the timer A and timer
B stop counting and reset the TON bit to ²0² at the same
time.
If the TON bit is ²1², the TMRAH, TMRAL, TMRBH
and TMRBL cannot be read or written to. Only when
the timer/event counter is off and when the instruction ²MOV² is used could those four registers be
read or written to.
17
June 23, 2008
HT47C20L
Bit No.
Label
Function
In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A overflow or timer B overflow.
OVB/OVA
(0= timer A overflow; 1= timer B overflow)
In the timer/event counter mode, this bit is void.
0
To define 16-bit timer/event counter or RC type A/D converter is enable.
(0= timer/event counter enable; 1= A/D converter is enable)
1
ADC/TM
2~3
¾
Unused bits, read as ²0²
M0
M1
M2
M3
To define the A/D converter operating mode (M3, M2, M1, M0)
0000= IN0 external clock input mode
0001= RS0~CS0 oscillation (reference resistor and reference capacitor)
0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)
0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)
0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)
0101= RS1~CS1 oscillation (reference resistor and reference capacitor)
0110= RT1~CS1 oscillation (resistor sensor and reference capacitor)
0111= IN1 external clock input mode
1XXX= Undefined mode
4
5
6
7
ADCR (25H) Register
S 1
S y s te m
C lo c k
O V B /O V A = 0
S 2
S y s te m
T im e r A
C lo c k /4
In te rru p t
S 3
R T C
O u tp u t
T O N
O V B /O V A = 1
T im e r B
R e s e t T O N
S 1 2
S 1 3
S 4
S 5
IN 0
C S 0
S 6
S 7
S 8
C R T 0
R S 0
S 9
R T 0
S 1 0
IN 1
S 1 1
C S 1
R S 1
R T 1
T N 2
T N 1
T N 0
S 1
S 2
S 3
M 3
M 2
M 1
M 0
S 4
S 5
S 6
S 7
S 8
S 9
S 1 0
S 1 1
S 1 2
S 1 3
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
O th e r
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
0
0
N o te : 0 = o ff, 1 = o n
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
N o te : 0 = o ff, 1 = o n
RC Type A/D Converter
Rev. 2.50
18
June 23, 2008
HT47C20L
Example for RC type AD converter mode (Timer A overflow):
clr tmrc
clr adcr.1
; set timer mode
clr intc1.4
; clear timer/event counter interrupt request flag
mov a, low (65536-1000)
; give timer A initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00010010b
; RS0~CS0; set RC type ADC mode; set Timer A overflow
mov adcr, a
mov a, 00h
; give timer B initial value
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
; timer A clock source=T1 and timer on
mov tmrc, a
p10:
clr wdt
snz intcl.4
; polling timer/event counter interrupt request flag
jmp p10
clr intcl.4
; clear timer/event counter interrupt request flag
; program continue
Rev. 2.50
19
June 23, 2008
HT47C20L
Example for RC type AD converter mode (Timer B overflow):
clr tmrc
clr adcr.1
; set timer mode
clr intc1.4
; clear timer/event counter interrupt request flag
a, 00h
; give timer A initial value
mov tmrbl, a
a, 00h
mov tmrbh, a
mov a, 00010011b
; RS0~CS0; set RC type ADC mode; set Timer B overflow
mov adcr,a
mov a, low (65536-1000)
; give timer B initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 00110000b
; timer A clock source=T1 and timer on
mov tmrc, a
p10:
clr wdt
snz intcl.4
; polling timer/event counter interrupt request flag
jmp p10
clr intcl.4
; clear timer/event counter interrupt request flag
; program continue
Input/Output Ports
When the structures of PA are open drain NMOS type, it
should be noted that, before reading data from the pads a
²1² should be written to the related bits to disable the
NMOS device. That is done first before executing the instruction ²MOV A, 0FFH² and ²MOV [12H], A² to disable
the related NMOS device, and then ²MOV A, [12H]² to get
a stable data.
There are 8-bit bidirectional input/output port and 4-bit
input port in the HT47C20L, labeled PA and PB which
are mapped to the data memory of [12H] and [14H] respectively. The high nibble of the PA is NMOS output
and input with pull-high resistors. The low nibble of the
PA can be used for input/output or output operation by
selecting NMOS or CMOS output by mask option. Each
bit on the PA can be configured as a wake-up input and
the low nibble of the PA with or without pull-high resistors by mask option. PB can only be used for input operation, and each bit on the port is with pull high resistor.
Both are for the input operation, these ports are
non-latched, that is, the inputs should be ready at the T2
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA output operation, all data are latched and
remain unchanged until the output latch is rewritten.
Rev. 2.50
After chip reset, these input lines remain at a high level
or are left floating (by mask option).
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into the
CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or to the
accumulator. Each bit of the PA output latches can not
use these instruction, which may change the input lines
to output lines (when the input lines are at low level).
20
June 23, 2008
HT47C20L
V
V
D D
V
D D
D D
W E A K
P u ll- u p
D a ta B u s
W R
D
C K
S
M a s k
O p tio n
B Z O p tio n
Q
M
U
D D
C K
W R
S
M a s k
O p tio n
B Z O p tio n
Q
P A 1 /B Z
Q
M
U
C h ip R e s e t
X
C h ip R e s e t
D
D a ta B u s
P A 0 /B Z
Q
V
W E A K
P u ll- u p
X
B Z S ig n a l
M
S y s te m
M
U
R e a d P a th
U
R e a d P a th
X
X
S y s te m
W a k e -u p
W a k e -u p
M a s k O p tio n
M a s k O p tio n
PA0/BZ, PA1/BZ Input/Output Lines
IR
C K
W R
S
Q
M
W E A K
P u ll- u p
M a s k O p tio n
M a s k
O p tio n
U
C h ip R e s e t
P F D
V D D
Q
D
D A T A B U S
V D D
O p tio n
X
P A 3 /P F D
S ig n a l
M
U
R e a d P a th
X
S y s te m
W a k e -u p
M a s k O p tio n
PA3/PFD Input/Output Line
V
D D
W E A K
P u ll- u p
D a ta B u s
W r ite
D
Q
C K
S
P A 4 ~ P A 7
Q
C h ip R e s e t
R e a d I/O
S y s te m
W a k e -u p
M a s k O p tio n
PA4~PA7 Input/Output Line
Rev. 2.50
21
June 23, 2008
HT47C20L
V
V
V
W E A K
P u ll- u p
C K
W r ite
S
D D
W E A K
P u ll- u p
M a s k
O p tio n
Q
D
D a ta B u s
D D
D D
M a s k O p tio n
P A 2
Q
C h ip R e s e t
R e a d D a ta
R e a d I/O
D a ta B u s
P B 0 ~ P B 3
S y s te m
W a k e -u p
M a s k O p tio n
PB Input Lines
PA2 Input/Output Lines
LCD Display Memory
LCD Driver Output
The HT47C20L provides an area of embedded data
memory for LCD display. The LCD display memory is
designed into 20´4 bits. If the LCD selected 19´4 segments output, the 53H of the LCD display memory can
not be accessed. This area is located from 40H to 53H
of the RAM at Bank 1. Bank pointer (BP; located at 04H
of the data memory) is the switch between the general
data memory and the LCD display memory. When the
BP is set ²1² any data written into 40H~53H will effect
the LCD display (indirect addressing mode using MP1).
When the BP is cleared ²0², any data written into
40H~53H has to access the general purpose data memory. The LCD display memory can be read and written
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automatically read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
On or Off, a ²1² or a ²0² is written to the corresponding
bit of the display memory, respectively.
The output number of the HT47C20L LCD driver can be
20´2 or 20´3 or 19´4 by mask option (i.e.1/2 duty, 1/3
duty or 1/4 duty).
The bias type LCD driver is ²C² type. If the 1/2 duty or
1/3 duty type is selected, the 1/2 bias type is selected. If
the 1/4 duty type is selected, the 1/3 bias type is selected. A capacitor has to be connected between C1 and
C2. The two kinds of the configurations of V1, V2 and V3
pins are as follows:
C 1
C 2
V 1
V 2
V 3
The figure illustrates the mapping between the display
memory and LCD pattern for the HT47C20L.
4 0 H
C O M
4 1 H
4 2 H
V
V1, V2, V3 Application Diagram
4 3 H
5 1 H
5 2 H
5 3 H
B it
0
S E G M E N T
D D
0
1
1
2
2
3
3
0
1
2
3
1 7
1 8
1 9
Display Memory (Bank 1)
Rev. 2.50
22
June 23, 2008
HT47C20L
D u r in g a R e s e t P u ls e :
2 V
V D
V S
2 V
V D
V S
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e :
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
2 V
V D
V S
C O M 0
C O M 1
C O M 2
L C D s e g m e n ts o n C O M
0 ,1 ,2 s id e s b e in g u n lit
O n ly L C D s e g m e n ts o n
C O M 0 s id e b e in g lit
O n ly L C D s e g m e n ts o n
C O M 1 s id e b e in g lit
O n ly L C D s e g m e n ts o n
C O M 2 s id e b e in g lit
L C D s e g m e n ts o n
C O M 0 ,1 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 0 ,2 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 1 ,2 s id e s b e in g lit
L C D s e g m e n ts o n
C O M 0 ,1 ,2 s id e s b e in g lit
H a lt M o d e :
2 V
V D
V S
2 V
V D
V S
C O M 0 ,C O M 1 ,C O M 2
A ll L C D d r iv e r o u tp u ts
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D D
D
S
D
S
D
S
D
S
D
S
S
S
D
D
D D
D D
D D
D D
D D
D D
LCD Driver Output (1/3 Duty, 1/2 Bias)
Rev. 2.50
23
June 23, 2008
HT47C20L
3 V D D
2 V D D
V D D
C O M 0
V S S
3 V D D
2 V D D
V D D
C O M 1
V S S
3 V D D
2 V D D
V D D
C O M 2
V S S
3 V D D
2 V D D
C O M 3
V D D
V S S
3 V D D
2 V D D
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V D D
V S S
LCD Driver Output (1/4 Duty, 1/3 Bias)
Rev. 2.50
24
June 23, 2008
HT47C20L
Voltage Low Detector
Programmable Frequency Divider - PFD
The HT47C20L provides a voltage low detector for battery system application. If the battery voltage is lower
than the specified value, the battery low flag (BLF; bit 5
of RTCC) is set. The specified value is 1.2V±0.1V. The
voltage low detector circuit can be turn On or Off by writing a ²1² or a ²0² to BON (bit 3 of RTCC register). A delay time of 1ms is required to monitor the BLF after
setting the BON bit. The BLF is invalid when the BON is
cleared as ²0². The voltage low detector can be disabled
by mask option.
The PFD output shares pin with PA3 as determined by
mask option.
When the PFD option is selected, setting PA3 ²0² will
enable the PFD output and setting PA3 ²1² will disable
the PFD output and PA3 output at low level.
PA3
HT47C20L provides a pair of buzzer output BZ and BZ,
which share pins with PA0 and PA1 respectively, determined by mask option. Its output frequency can also be
selected by mask option.
0
(CLR PA.1)
0
(CLR PA.0)
PA0= BZ
PA1= BZ
1
(SET PA.1)
0
(CLR PA.0)
PA0= BZ
PA1= 0
1 (SET PA.3)
PA3= 0
The low voltage reset circuit is used to monitor the power
supply of the device. If the power supply voltage of the device is lower than 1.1V±0.1V, the device will automatically
reset internally. It is enabled or disabled by mask option.
The LVR includes the following specification:
· The low voltage (lower than 1.1V±0.1V) must be main-
Function
1
(SET PA.0)
X
PA3= PFD Output
Low Voltage Reset - LVR
When the buzzer function is selected, setting PA.0 and
PA.1 ²0² simultaneously will enable the buzzer output
and setting PA.0 ²1² will disable the buzzer output and
setting PA.0 ²0² and PA.1 ²1² will only enable the BZ
output and disable the BZ output.
PA0
0 (CLR PA.3)
PFD output frequency=
1
1
´
2 timer overflow period
Buzzer
PA1
Function
tained for over 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and does not perform
the reset function.
· The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
· During HALT mode, the LVR will disable.
PA0= 0
PA1= 0
Buzzer Enable
Bit No.
Label
Read/Write
Function
0
1
2
RT0
RT1
RT2
R/W
8 to 1 multiplexer control inputs to select the real time clock prescaler output
3
BON
R/W
Voltage low detector enable/disable control bit
²0² indicates voltage detector is disabled
²1² indicates voltage detector is enabled
4, 6~7
¾
¾
Unused bit, read as ²unknown²
5
BLF
R
Battery low flag
²0² indicates that the voltage is not low
²1² indicates that the voltage is low
RTCC (09H) Register
Note: ²X² means ²invalid²
Rev. 2.50
25
June 23, 2008
HT47C20L
Mask Option
The following shows many kinds of mask options in the HT47C20L. All these options should be defined in order to ensure proper system functioning.
No.
Mask Option
1
WDT enable or disable selection. WDT can be enabled or disabled by mask option.
2
CLR WDT times selection. This option defines how to clear the WDT by instruction. One time means that
the ²CLR WDT² can clear the WDT. ²Two times² means that only if both of the ²CLR WDT1² and ²CLR
WDT2² have been executed, then WDT can be cleared.
3
Time base time-out period selection. The time base time-out period ranges from fS/212 to fS/215. ²fS² stands
for the 32768Hz frequency.
4
Buzzer output frequency selection. There are eight types of frequency signals for the buzzer output:
fS/22~fS/29. ²fS² stands for the 32768Hz.
5
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA NMOS output
only) all have the capability to wake-up the chip from a halt mode by a following edge.
6
Pull high selection. This option is to decide whether the pull high resistance is viable or not on the low nibble
of the PA.
7
PA CMOS or NMOS selection.
The structure of the low nibble of the PA can be selected as CMOS or NMOS. When CMOS is selected, the
related pins can only be used for output operations. When NMOS is selected, the related pins can be used
for input or output operations.
8
I/O pins share with other function selection.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
9
LCD common selection. There are three types of selection: 2 common (1/2 duty, 1/2 bias) 3 common (1/3
duty, 1/2 bias) or 4 common (1/4 duty, 1/3 bias). If the 4 common is selected, the segment output pin
²SEG19/COM3² will be set as a common output ²COM3².
10
The low voltage reset and the low voltage detector enable or disable selection.
There are three types of selection. The low voltage reset and the voltage detector are both enabled or both
disabled or the low voltage reset is disabled but the voltage low detector is enabled.
11
LCD on or LCD off at the halt mode selection.
The LCD can be enable or disable at the halt mode by mask option.
Rev. 2.50
26
June 23, 2008
HT47C20L
Application Circuits
S E G 0 ~ 1 8
C O M 0 ~ 3
O S C 1
3 2 7 6 8 H z
C 1
O S C 2
L C D
P a n e l
0 .1 m F
C 2
V
V 1
D D
V 2
1 0 0 k W
R E S
0 .1 m F
0 .1 m F
0 .1 m F
V 3
V
D D
IN 0
C S 0
C R T 0
R
o r C
R T 0
R S 0
IN T
IN 1
T M R
C S 1
R S 1
R T 1
P A 0 ~ P A 7
P B 0 ~ P B 3
H T 4 7 C 2 0 L
Rev. 2.50
27
June 23, 2008
HT47C20L
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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HT47C20L
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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HT47C20L
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
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HT47C20L
Package Information
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
4 8
G
3 3
H
I
3 2
4 9
F
A
B
E
6 4
1 7
K
a
J
1 6
1
Symbol
A
Rev. 2.50
Dimensions in mm
Min.
Nom.
Max.
8.9
¾
9.1
B
6.9
¾
7.1
C
8.9
¾
9.1
D
6.9
¾
7.1
E
¾
0.4
¾
F
0.13
¾
0.23
G
1.35
¾
1.45
H
¾
¾
1.6
I
0.05
¾
0.15
J
0.45
¾
0.75
K
0.09
¾
0.20
a
0°
¾
7°
41
June 23, 2008
HT47C20L
Holtek Semiconductor Inc. (Headquarters)
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Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
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Tel: 886-2-2655-7070
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Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.50
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