HT45R22E Remote Type 8-bit OTP MCU with EEPROM

HT45R22E
Remote Type 8-bit OTP MCU with EEPROM
Features
CPU Features
· Table read instructions
· Operating voltage:
· 63 powerful instructions
· 4-level subroutine nesting
fSYS= 4MHz: 2.2V~3.6V
· Program Memory: 4K´15
· Bit manipulation instruction
· Data Memory: 128´8
· Low voltage reset function
· Embedded 1024´8 EEPROM
· 20/24-pin SOP package types
· Up to 1ms instruction cycle with 4MHz system clock
Peripheral Features
at VDD= 3V
· Up to 22 bidirectional I/O lines
· Idle/Sleep mode and wake-up functions to reduce
· External interrupt input shared with an I/O line
power consumption
· Two 8-bit programmable Timer/Event Counter with
· Oscillator types:
overflow interrupt and prescaler
External high freuency Crystal -- HXT
External RC -- ERC
Internal high frequency RC -- HIRC
External low frequency crystal -- LXT
Internal low frequency RC -- LIRC
· Time-Base function
· Programmable Frequency Divider - PFD shared
with I/O line
· Two integrated operational amplifiers with interrupt
· Four operational modes: Normal, Slow, Idle, Sleep
function - one with programmable gain control
· Fully integrated internal 4095kHz oscillator requires
· Single comparator with interrupt and low power
no external components
consumption
· Watchdog Timer function
· LIRC oscillator function for watchdog timer
· All instructions executed in one or two instruction
cycles
General Description
The device is an 8-bit high performance, RISC architecture microcontrollers specifically designed for operational amplifier applications. The usual Holtek
microcontroller features of low power consumption, I/O
flexibility, timer functions, oscillator options, internal
comparator, internal operational amplifiers, power down
and wake-up functions, watchdog timer and low voltage
reset, combine to provide the device with a wide range
Rev. 1.20
of functional options while still maintaining a high level
of cost effectiveness. The fully integrated system oscillator HIRC, which requires no external components and
which has three frequency selections, opens up a huge
range of new application possibilities for this device,
some of which may include remote control appliances,
car reversing systems, level meters, consumer products, household appliances subsystem controllers, etc.
1
February 25, 2011
HT45R22E
Block Diagram
The following block diagram illustrates the main functional blocks.
T im in g
G e r n e r a tio n
P F D
D r iv e r
I/O
P o rts
8 - b it
R IS C
M C U
C o re
E E P R O M
1 0 2 4 x 8
O P A x 2 ,
C o m p a ra to rx 1
R O M , R A M
M e m o ry
T im e
B a s e
T im e r
Pin Assignment
P A 4 /T C 1 /A 0 P
1
2 0
V S S
P A 3 /IN T /A 0 N
2
1 9
V D D
P A 2 /T C 0 /A 0 X
3
1 8
P A 5 /O S C 2
P A 1 /P F D /A 1 X
4
1 7
P A 6 /O S C 1
P A 0 /P F D /A 1 N
5
1 6
P A 7 /R E S
P C 6 /A 1 P
6
1 5
P C 5
P C 7 /C P
7
1 4
P C 4
P C 0 /C N
8
1 3
P B 3
P C 1 /C X
9
1 2
P B 2 /S D A
P B 0 /W P
1 0
1 1
P B 1 /S C L
H T 4 5 R 2 2 E
2 0 S O P -A
P A 4 /T C 1 /A 0 P
1
2 4
V S S
P A 3 /IN T /A 0 N
2
2 3
V D D
P A 2 /T C 0 /A 0 X
3
2 2
P A 5 /O S C 2
P A 1 /P F D /A 1 X
4
2 1
P A 6 /O S C 1
P A 0 /P F D /A 1 N
5
2 0
P A 7 /R E S
P C 6 /A 1 P
6
1 9
P C 5
P C 7 /C P
7
1 8
P C 4
P C 0 /C N
8
1 7
P C 3
P C 1 /C X
9
1 6
P C 2
P B 0 /W P
1 0
1 5
P B 5
P B 1 /S C L
1 1
1 4
P B 4
P B 2 /S D A
1 2
1 3
P B 3
H T 4 5 R 2 2 E
2 4 S O P -A
Note: Bracketed pin names indicate non-default pinout remapping locations.
Rev. 1.20
2
February 25, 2011
HT45R22E
Pin Description
Pin Name
PA0/PFD/A1N
Function
OPT
I/T
PA0
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS PFD output
A1N
PA1/PFD/A1X
PA2/TC0/A0X
PA3/INT/A0N
¾
Description
OPA1 inverting input pin
PA1
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PFD
CTRL0
¾
CMOS Complementary PFD output
A1X
COPA3C
¾
OPAO
PA2
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
TC0
¾
ST
¾
A0X
COPA3C
¾
OPAO
PA3
PAPU
PAWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
INT
¾
ST
A0N
PA4
PA4/TC1/A0P
COPA3C OPAI
O/T
TC1
A0P
COPA3C OPAI
PAPU
PAWK
ST
¾
ST
COPA3C OPAI
PAPU
PAWK
ST
OSC2
CO
¾
PA6
PAPU
PAWK
ST
OSC1
CO
OSC
PA5
PA5/OSC2
PA6/OSC1
PA7
PAWK
ST
RES
CO
ST
PB0
PBPU
ST
WP
¾
ST
PB1
PBPU
ST
SCL
¾
ST
PB2
PBPU
ST
PA7/RES
PB0/WP
PB1/SCL
PB2/SDA
OPA1 output pin
External Timer 0 clock input
OPA0 output pin
¾
External interrupt input
¾
OPA0 inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
External Timer 1 clock input
¾
OPA0 non-inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
Reset input
CMOS General purpose I/O. Register enabled pull-up.
¾
EEPROM write protect pin
CMOS General purpose I/O. Register enabled pull-up.
¾
EEPROM serial clock input pin
CMOS General purpose I/O. Register enabled pull-up.
SDA
¾
ST
PB3
PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PB4, PB5
PBn
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up.
PC0
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC0/CN
CN
¾
EEPROM serial data pin
Comparator inverting input pin
PC1
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CX
COPA2C
¾
CMPO Comparator output pin
PC1/CX
Rev. 1.20
COPA3C CMPI
¾
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February 25, 2011
HT45R22E
Pin Name
PC2~PC5
Function
OPT
I/T
PCn
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC6
PCPU
PCWK
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up.
PC6/A1P
A1P
PC7
PC7/CP
CP
COPA3C OPAI
PCPU
PCWK
ST
COPA3C CMPI
O/T
¾
Description
OPA1 non-inverting input pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Comparator non-inverting input pin
VDD
VDD
¾
PWR
¾
Power supply
VSS
VSS
¾
PWR
¾
Ground
Note:
I/T: Input type
O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power
CO: Configuration option
ST: Schmitt Trigger input
CMOS: CMOS output
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
OPAI: Operational Amplifier input
OPAO: Operational Amplifier output
CMPI: Comparator input
CMPO: Comparator output
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+3.6V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................100mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
4
February 25, 2011
HT45R22E
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
Conditions
VDD
Operating Voltage
¾
fSYS=4MHz
2.2
¾
3.6
V
IDD1
Operating Current
(HXT, ERC)
3V
No load, fSYS=4MHz
¾
0.8
1.2
mA
IDD2
Operating Current
(HIRC)
3V
No load, fSYS=4095kHz
¾
0.8
2.1
mA
IDD3
Operating Current
(HIRC + LXT, Slow Mode)
3V
No load, fSYS=32768Hz
(LVR disabled, LXTLP=1)
¾
5
10
mA
ISTB1
Standby Current
(LIRC On, LXT Off)
3V
No load, system HALT
¾
¾
5
mA
ISTB2
Standby Current
(LIRC Off, LXT Off)
3V
No load, system HALT
¾
¾
1
mA
ISTB3
Standby Current
(LIRC Off, LXT On, LXTLP=1)
3V
No load, system HALT
¾
¾
5
mA
VIL1
Input Low Voltage for I/O,
TCn and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O,
TCn and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
VLVR=2.10V
1.98
2.10
2.22
V
IOH
I/O Port Source Current
3V
VOH=0.9VDD
-2
-4
¾
mA
IOL1
I/O Port Sink Current
(PA, PB, PC)
3V
VOL=0.1VDD
4
8
¾
mA
IOL2
PA7 Sink Current
3V
VOL=0.1VDD
2
3
¾
mA
RPH
Pull-high Resistance (I/O)
3V
20
60
100
kW
0.665
0.700
0.735
VDD
VOPBIAS
OPA/Comparator bias voltage
deviation (Bias=0.7/0.5/0.1VDD
3V
selected by A1PS[2:0], A0PS[2:0],
CPS[2:0] bits)
No load
0.475
0.500
0.525
VDD
0.995
0.100
0.105
VDD
GOP
OPA1 Gain deviation (Software
gain controlled by A1G[2:0])
No load
+5
%
3V
¾
-5
Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD.
Rev. 1.20
5
February 25, 2011
HT45R22E
EEPROM - D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
0°C to +70°C
2.2
¾
3.6
V
-40°C to +85°C
2.4
¾
3.6
V
VCC
VCC
Operating Voltage
¾
Conditions
ICC1
Operating Current
3V
Read at 100kHz
¾
¾
2
mA
ICC2
Operating Current
3V
Write at 100kHz
¾
¾
5
mA
VIL
Input Low Voltage
¾
¾
-1
¾
0.3VCC
V
VIH
Input High Voltage
¾
¾
0.7VCC
¾
VCC+0.5
V
VOL
Output Low Voltage
2.4V
IOL=2.1mA
¾
¾
0.4
V
ILI
Input Leakage Current
3V
VIN=0 or VCC
¾
¾
1
mA
3V
VOUT=0 or VCC
¾
¾
1
mA
ILO
Output Leakage Current
ISTB1
Standby Current
3V
VIN=0 or VCC
¾
¾
5
mA
ISTB2
Standby Current
2.4V
VIN=0 or VCC
¾
¾
4
mA
CIN
Input Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
6
pF
COUT
Output Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
8
pF
Note: These parameters are periodically sampled but not 100% tested
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
fSYS
fHIRC
fERC
System Clock
System Clock
(HIRC)
System Clock (ERC)
Min.
Typ.
Max.
Unit
32
¾
4095
kHz
Conditions
¾
2.2V~3.6V
3V
Ta=25°C
-2%
4095
+2%
kHz
3V
Ta=0~70°C
-5%
4095
+5%
kHz
2.2V~
Ta=0~70°C
3.6V
-8%
4095
+8%
kHz
2.2V~
Ta= -40°C~85°C
3.6V
-12%
4095
+12%
kHz
3V
Ta=25°C, R=120kW *
-2%
4
+2%
MHz
3V
Ta=0~70°C, R=120kW *
-5%
4
+5%
MHz
3V
Ta= -40°C~85°C,
R=120kW *
-7%
4
+7%
MHz
2.2V~ Ta= -40°C~85°C,
3.6V R=120kW *
-11%
4
+11%
MHz
¾
32768
¾
Hz
0
¾
4095
kHz
fLXT
System Clock (LXT)
¾
fTIMER
Timer Input Frequency
(TCn)
¾
fLIRC
LIRC Oscillator
3V
¾
5.0
10.0
15.0
kHz
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
Rev. 1.20
¾
2.2V~3.6V
6
February 25, 2011
HT45R22E
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
For HXT/LXT
¾
1024
¾
tSYS
For ERC/IRC
(By configuration option)
¾
2
¾
tSYS
VDD
tSST
System Start-up time Period
¾
Conditions
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
RESTD
Reset Delay Time
¾
¾
¾
100
¾
ms
Note:
1. tSYS=1/fSYS
2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
EEPROM - A.C. Characteristics
Standard Mode*
Symbol
Parameter
Remark
VCC=3V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the first
clock pulse is generated
4000
¾
600
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
ns
tBUF
Bus Free Time
Time in which the bus
must be free before a new
transmission can start
4700
¾
1200
¾
ns
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
¾
100
¾
50
ns
tWR
Write Cycle Time
¾
5
¾
5
ms
¾
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 3.6V
For relative timing, refer to timing diagrams
Rev. 1.20
7
February 25, 2011
HT45R22E
Power-on Reset Characteristics
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RRVDD
VDD raising rate to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
tPOR
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
¾
¾
1
¾
¾
ms
V
D D
tP
O R
R R
V D D
V
P O R
T im e
Comparator Amplifier Characteristics
Test Conditions
Symbol
Parameter
VDD
ICOMP
SCOM Operating Current
3V
Min.
Typ.
Max.
Unit
CPCS[1:0]=00B
¾
200
300
mA
CPCS[1:0]=01B
¾
5
10
mA
CPCS[1:0]=10B
¾
1
2
mA
Conditions
VOS
Comparator Input Offset Voltage
3V
¾
-10
¾
10
mV
VCM
Comparator Common Mode
Voltage Range
¾
¾
0
¾
VDD-1.4V
V
tPD
Comparator Response Time
(With 10mV overdrive)
3V
CPCS[1:0]=00B
¾
¾
2
ms
3V
CPCS[1:0]=01B
¾
¾
60
ms
¾
CPCS[1:0]=10B
¾
¾
400
ms
Min.
Typ.
Max.
Unit
Operational Amplifier Characteristics
Test Conditions
Symbol
Parameter
VDD
Conditions
Power Down Current
3V
¾
¾
¾
0.1
mA
VOPOS1
Input Offset Voltage
3V
Without calibration,
OPOF[3:0]=1000B
-15
¾
15
mV
VOPOS2
By Calibration
-4
¾
4
mV
¾
VSS
¾
VDD-1.4V
V
3V
¾
60
80
¾
dB
Common Mode Rejection Ratio
3V
VCM=0~VDD-1.4V
60
80
¾
dB
Slew Rate +, Slew Rate -
3V
No load
1.8
2.5
¾
V/ms
3V
RL=1M, CL=100p
500
¾
¾
kHz
Input Offset Voltage
3V
VCM
Common Mode Voltage Range
¾
PSRR
Power Supply Rejection Ratio
CMRR
SR
GBW
Rev. 1.20
Gain Band Width
8
February 25, 2011
HT45R22E
Characteristics Curves
IR C F r e q u e n c y C u r v e
4 4 0 0
4 0 9 5 k H z + 5 %
4 3 0 0
5 0 °C
F re q u e n c y (k H z )
4 2 0 0
2 5 °C
4 0 °C
4 1 0 0
-2 0 °C
4 0 0 0
4 0 9 5 k H z - 5 %
3 9 0 0
3 8 0 0
3 .6 V
3 .4 V
3 .2 V
2 .8 V
3 .0 V
2 .6 V
2 .4 V
2 .2 V
V o lta g e (V D D )
Note: VDD=2.2V~3.6V, -20°C£Ta£50°C, IRC has accuracy of ±5%
Rev. 1.20
9
February 25, 2011
HT45R22E
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O control system with
maximum reliability and flexibility.
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/
Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.20
10
February 25, 2011
HT45R22E
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. However, it
must be noted that only the lower 8 bits, known as the
Program Counter Low Register, are directly addressable by user.
P ro g ra m
T o p o f S ta c k
B o tto m
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
PCL Register
Low Byte
PC11~PC8
PCL7~PCL0
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 4
Device
Stack Levels
HT45R22E
4
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
Program Counter
Program Counter
High Byte
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
C o u n te r
Arithmetic and Logic Unit - ALU
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register. By transferring data directly into this register, a short
program jump can be executed directly. However, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory that is
256 locations. When such program jumps are executed,
it should also be noted that a dummy cycle will be inserted.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
Stack
RLC
· Increment and Decrement INCA, INC, DECA, DEC
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 4 levels and is neither part of the
Data or Program Memory space, and is neither readable
nor writeable. The activated level is indexed by the
Stack Pointer, SP, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the Program Counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the
stack. After a device reset, the Stack Pointer will point to
the top of the stack.
Rev. 1.20
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
11
February 25, 2011
HT45R22E
Program Memory
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applications which may be useful during debug or for products
requiring frequent upgrades or program changes.
· Timer/Event 0/1 counter interrupt vector
This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs, the
program will jump to its respective location and begin
execution if the associated Timer/Event Counter interrupt is enabled and the stack is not full.
· Time base interrupt vector
This internal vector is used by the internal Time Base.
If a Time Base overflow occurs, the program will jump
to this location and begin execution if the Time Base
counter interrupt is enabled and the stack is not full.
Structure
The Program Memory has a capacity of 4K´15. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
Device
Capacity
HT45R22E
4K´15
· Multi-function interrupt vector
This vector is used by the OPA0,OPA1 and Comparator. When either an OPA or Comparator, dependent
upon which one is selected, requires interrupt servicing, the program will jump to this location and begin
execution if the output interrupt is enabled and the
stack is not full.
Look-up Table
Special Vectors
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Reset Vector
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated,
the program will jump to this location and begin execution.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
· External interrupt vector
This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge
transition, the program will jump to this location and
begin execution if the external interrupt is enabled and
the stack is not full. The external interrupt active edge
transition type, whether high to low, low to high or both
is specified in the CTRL1 register.
0 0 0 H
R e s e t
0 0 4 H
E x te rn a l
In te rru p t
0 0 8 H
T im e r 0
In te rru p t
0 0 C H
T im e r 1
In te rru p t
0 1 0 H
0 1 4 H
T im e B a s e
In te rru p t
0 1 8 H
M u lti- fu n c tio n
In te rru p t
F F F H
1 5 b its
Program Memory Structure
Rev. 1.20
12
February 25, 2011
HT45R22E
at the Program Memory address ²0F06H² or 6 locations
after the start of the last page. Note that the value for the
table pointer is referenced to the first address of the
present page if the ²TABRDC [m]² instruction is being
used. The high byte of the table data which in this case
is equal to zero will be transferred to the TBLH register
automatically when the ²TABRDL [m]² instruction is executed.
The following diagram illustrates the addressing/data
flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
T a b le C o n te n ts L o w
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
B y te
Table Read
Table Program Example
The accompanying example shows how the table
pointer and table data is defined and retrieved from the
device. This example uses raw table data located in the
last page which is stored there using the ORG statement. The value at this ORG statement is ²0F00H²
which refers to the start address of the last page within
the 4K Program Memory of the device. The table pointer
is setup here to have an initial value of ²06H². This will
ensure that the first data read from the data table will be
Instruction
Table Location Bits
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: Table Pointer TBLP bits
Rev. 1.20
13
February 25, 2011
HT45R22E
· Table Read Program Example
tempreg1 db
?
; temporary register #1
tempreg2 db
?
; temporary register #2
:
:
mov a,06h
; initialise table pointer - note that this address
; is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl
;
;
;
;
tempreg1
dec tblp
tabrdl
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²0F06H² transferred to
tempreg1 and TBLH
; reduce value of table pointer by one
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²0F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org 0F00h
dc
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
RAM Data Memory
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored.
Structure
Divided into two sections, the first of these is an area of
RAM where special function registers are located. These
registers have fixed locations and are necessary for correct operation of the device. Many of these registers can
be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for
general purpose use. All locations within this area are
read and write accessible under program control.
IA R 0
0 1 H
M P 0
S p e c ia l
P u rp o s e
R e g is te r s
1 2 8 b y te s
G e n e ra l
P u rp o s e
R e g is te r s
3 F H
4 0 H
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8
bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address
²00H².
B F H
Data Memory Structure
Note:
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
Rev. 1.20
0 0 H
14
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer registers.
February 25, 2011
HT45R22E
Special Purpose Data Memory
the same way as normal registers providing a convenient way with which to indirectly address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to is the address specified
by the related Memory Pointer. The following example
shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4.
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
locations of these registers within the Data Memory begin at the address ²00H². Any unused Data Memory locations between these special function registers and the
point where the General Purpose Memory begins is reserved and attempting to read data from these locations
will return a value of ²00H².
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 with MP0 and IAR1 with MP1, can together
access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 7 H
3 8 H
3 9 H
3 A H
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
3 E H
3 F H
IA
M
IA
M
R 0
P 0
R 1
P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P A P U
P A W K
P B
P B C
P B P U
P C
P C C
P C P U
C T R L 0
C T R L 1
S C O M C
IN T C 1
M F IC
C
C
C
C
C
C
C M P
C M P
O P A
O P A
O P A
O P A
O P 0
O P 1
0 C
1 C
0
1
2
3
O
O
C
C
C
C
C
C
P C W K
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory
Rev. 1.20
15
February 25, 2011
HT45R22E
· Indirect Addressing Program Example
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 code
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory
addresses.
Accumulator - ACC
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location. However, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it. Note that bits 0~3 of the
STATUS register are both readable and writeable bits.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
Rev. 1.20
16
February 25, 2011
HT45R22E
· STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
TO
PDF
OV
Z
AC
C
R/W
¾
¾
R
R
R/W
R/W
R/W
R/W
POR
¾
¾
0
0
x
x
x
x
²x² unknown
Bit 7, 6
Unimplemented, read as ²0²
Bit 5
TO: Watchdog Time-Out flag
0: After power up or executing the ²CLR WDT² or ²HALT² instruction
1: A watchdog time-out occurred.
Bit 4
PDF: Power down flag
0: After power up or executing the ²CLR WDT² instruction
1: By executing the ²HALT² instruction
Bit 3
OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1
AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
Interrupt Control Registers - INTC0, INTC1, MFIC
Input/Output Ports and Control Registers
These 8-bit registers, known as INTC0, INTC1 and
MFIC, control the operation of external, internal timers,
time base and multi-function interrupts. The MFIC register is used to control a comparator and two operational
amplifier interrupts. By setting various bits within these
registers using standard bit manipulation instructions,
the enable/disable function of each interrupt can be independently controlled. A master interrupt bit within this
register, the EMI bit, acts like a global enable/disable
and is used to set all of the interrupt enable bits on or off.
This bit is cleared when an interrupt routine is entered to
disable further interrupt and is set by executing the
²RETI² instruction.
Within the area of Special Function Registers, the port
PA, PB, PC etc., data I/O registers and their associated
control register PAC, PBC, PCC etc., play a prominent
role. These registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table. The data I/O registers, are used to transfer the appropriate output or input data on the port. The control
registers specifies which pins of the port are set as inputs and which are set as outputs. To setup a pin as an
input, the corresponding bit of the control register must
be set high, for an output it must be set low. During program initialisation, it is important to first setup the control
registers to specify which pins are outputs and which
are inputs before reading data from or writing data to the
I/O ports. One flexible feature of these registers is the
ability to directly program single bits using the ²SET
[m].i² and ²CLR [m].i² instructions. The ability to change
I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these
devices.
Timer/Event Counter Registers
This device contains two 8-bits wide Timer/Event Counters. One is known as Timer/Event Counter 0, while the
other is known as Timer/Event Counter 1. Timer/Event
Counter 0 has an associated timer register known as
TMR0, and Timer/Event Counter 1 has an associated
timer register known as TMR1. These are the register
locations where the timer values are located. Two associated control registers, known as TMR0C and TMR1C,
contain the setup information for the two individual
Timer/Event Counters.
Rev. 1.20
17
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HT45R22E
System Control Registers - CTRL0, CTRL1
These registers are used to provide control over various internal functions. Some of these include the PFD control, I/O
remapping function, certain system clock options, the LXT Oscillator low power control, external Interrupt edge trigger
type, Watchdog Timer enable function, Time Base function division ratio, and the LXT oscillator enable control.
· CTRL0 Register
Bit
7
6
5
4
3
2
1
0
Name
PCFG
PFDCS
¾
¾
PFDEN1
PFDEN0
LXTLP
CLKMOD
R/W
R/W
R/W
¾
¾
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
PCFG: I/O configuration
0: INTB/TC0/PFD pin-shared with PA3/PA2/PA0
1: INTB/TC0/PFD pin-shared with PC5/PC4/PC3
PFDCS: PFD clock source
0: Timer 0
1: Timer 1
Bit 6
Bit 5~4
Bit 3~2:
Bit 1
Bit 0
unimplemented, read as ²0²
PFDEN[1:0]: PFD/PFDB enable/ disable
00: Both disable
01: unimplemented, read as ²0²
10: PFD enable
11: PFD and PFDB enable
LXTLP: LXT oscillator low power control function
0: LXT oscillator quick start-up mode
1: LXT oscillator Low Power Mode
CLKMOD: System clock mode selection
0: High speed - HIRC used as system clock
1: Low speed - LXT used as system clock, HIRC oscillator stopped
This clock mode selection is only valid if the oscillator configuration option has selected the
HIRC+LXT.
· CTRL1 Register
Bit
7
6
5
4
3
2
1
0
Name
INTEG1
INTEG0
TBSEL1
TBSEL0
WDTEN3
WDTEN2
WDTEN1
WDTEN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
1
0
1
0
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210 ´ (1/fTP)
01: 211 ´ (1/fTP)
10: 212 ´ (1/fTP)
11: 213 ´ (1/fTP)
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is ²0101²
If the ²watchdog timer enable² is configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0¹1010.
Bit 3~0
Note:
Rev. 1.20
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HT45R22E
Wake-up Function Register - PAWK, PCWK
The SCL line is an input line and is the clock signal for
both the reading and writing of data. These two
EEPROM pins are shared with I/O pins as shown in the
table. Any pull-high resistors configuration options for
these pin shared pins also remain valid for the
EEPROM. Care must be taken if these pins are used as
normal I/O pins, as any signals on the pins may be seen
by the EEPROM as a valid read or write operation command. If this happens the EEPROM may inadvertently
generate signals on its SDA line which could create unexpected programming errors. The Internal EEPROM
can be directly controlled using the pin-shared I/O pins
or it can be directly connected to external I/Os and controlled by some other external master device. In this latter case care should be taken to ensure that the
pin-shared I/Os for the SDA and SCL lines are both
setup as inputs. In addition, the EEPROM provides a
write protection function and that is controlled by PB0
pin.
When the microcontroller enters the Idle/Sleep Mode,
various methods exist to wake the device up and continue with normal operation. One method is to allow a
falling edge on the I/O pins to have a wake-up function.
This register is used to select which Port A or Port C I/O
pins are used to have this wake-up function.
Pull-high Registers - PAPU, PBPU, PCPU
The I/O pins, if configured as inputs, can have internal
pull-high resistors connected, which eliminates the need
for external pull-high resistors. These registers select
which I/O pins are connected to internal pull-high resistors.
Software COM Register - SCOMC
The pins PB0~PB3 on Port B can be used as SCOM
lines to drive an external LCD panel. To implement this
function, the SCOMC register is used to setup the correct bias voltages on these pins.
Type
Comparator & Operational Amplifier Control
Registers - CMP0C, CMP1C, COPA0C, COPA1C,
COPA2C, COPA3C, OPA0OC, OPA1OC
HT45R22E
EEPROM Pin
SDA
SCL
WP
I/O Pin
PB2
PB1
PB0
Capacity
These registers are used to control the internal comparator and two operational amplifiers in the device. The
internal bits within registers are used to enable and disable the comparator and operational amplifiers, monitor
the output, select the operating current and control the
interrupt edge of the comparator, select the internal software gain and reference voltage bias and control the offset cancellation function of the operational amplifiers.
1024´8 bits
EEPROM I/O Shared Pins
EEPROM Functional Description
· Serial clock - SCL
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
· Serial data - SDA
The SDA pin is bidirectional for serial data transfer.
The pin is open drain driven and may be wired-OR
with any number of other open drain or open collector
devices.
EEPROM Data Memory
The HT45R22E device contains an internal 8K capacity
EEPROM memory with a 1024´8 bits structure. An
EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a
non-volatile form of memory, with data retention even
when its power supply is removed. By incorporating this
kind of data memory, a whole new host of application
possibilities are made available to the designer. The
availability of EEPROM storage allows information such
as product identification numbers, calibration values,
specific user data, system setup data or other product
information to be stored directly within the product
microcontroller.
· Write protect - WP
The EEPROM has a write protect pin that provides
hardware data protection. The write protect pin allows
normal read/write operations when the connection is
grounded. When the write protect pin is connected to
VDD, the write protection feature is enabled and operates as shown in the following table.
WP Pin Status
Protect Array
At VDD
Full Array (8K)
At VSS
Normal Read/Write Operations
Accessing the EEPROM Data Memory
Memory Organization
The internal EEPROM Data Memory has a 2-wire serial
interface structure for data transfer. These two lines are
the Serial Data line on pin SDA, and the Serial Clock line
on pin SCL. The SDA line is bi-directional and is the line
where the data is written to and read from the EEPROM.
Internally organized with 1024 8-bit words, the 8K requires a 10-bit data word address for random word addressing.
Rev. 1.20
19
February 25, 2011
HT45R22E
Device Operations
The 8th bit device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
· Start condition
1
0
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
0
0
0
0
R /W
D e v ic e A d d r e s s
Write Operations
· Stop condition
· Byte write
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
nonvolatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until write is
complete (refer to Byte write timing).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
Device Addressing
The 8K EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
· Page write
The 8K EEPROM is capable of a 16-byte page write.
A page write is initiated in the same way as a byte
write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first
data word, the microcontroller can transmit up to 15
more data words. The EEPROM will respond with a
ze r o a f t e r e a c h d a t a w o r d r e c e i v e d . T h e
microcontroller must terminate the page write sequence
with a stop condition (refer to Page write timing).
The data word address lower four bits are internally incremented following the receipt of each data word.
The higher data word address bits are not incremented, retaining the memory page row location.
D a ta a llo w e d
to c h a n g e
S D A
S C L
S ta rt
c o n d itio n
1
N o A C K
s ta te
A d d re s s o r
a c k n o w le d g e
v a lid
S to p
c o n d itio n
These page addressing bits on the 8K device should be
considered the most significant bits of the data word address which follows.
D e v ic e a d d r e s s
S D A
S
W o rd a d d re s s
D A T A
A 2 A 1 A 0
P
R /W
S ta rt
A C K
A C K
A C K
S to p
Byte Write Timing
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A n
D A T A n + 1
D A T A n + x
S
S ta rt
P
A C K
A C K
A C K
A C K
Page Write Timing
Rev. 1.20
20
February 25, 2011
HT45R22E
· Acknowledge polling
· Current address read
To maximize bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller should respond
with a ²no ACK² signal (high) followed by a stop condition (refer to Current read timing).
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
· Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition
(refer to Random read timing).
S e n d C o n tro l B y te
w ith R /W = 0
(A C K = 0 )?
N o
Y e s
N e x t O p e r a tio n
Acknowledge Polling Flow
· Sequential read
Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with
an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address
limit is reached, the data word address will roll over
and the sequential read continues. The sequential
read operation is terminated when the microcontroller
responds with a ²no ACK² signal (high) followed by a
stop condition.
· Write protect
The EEPROM has a write-protect function and programming will then be inhibited when the WP pin is
connected to VDD. Under this mode, the EEPROM is
used as a serial ROM.
· Read operations
The EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
D e v ic e a d d r e s s
S D A
D A T A
S to p
S
P
S ta rt
A C K
N o A C K
Current Read Timing
D e v ic e a d d r e s s
W o rd a d d re s s
D e v ic e a d d r e s s
S
S D A
D A T A
S to p
P
S
S ta rt
A C K
A C K
S ta rt
A C K
N o A C K
Random Read Timing
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
S
S ta rt
D A T A n + x
S to p
P
A C K
A C K
N o A C K
Sequential Read Timing
Rev. 1.20
21
February 25, 2011
HT45R22E
Timing Diagram
tF
S C L
tS
U :S T A
S D A
tS
tH
tR
tL
O W
tH
D :S T A
IG H
tH
tS
D :D A T
U :D A T
P
tA
S D A
A
V a lid
O U T
tS
U :S T O
tB
U F
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
R
S to p
S to p
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. The flexible features of the oscillator functions
ensure that the best optimisation can be achieved in
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of
configuration options and registers.
System Clock Configurations
There are five system oscillators. Three high speed oscillators and two low speed oscillators. The high speed
oscillators are the external crystal/ceramic oscillator HXT, the external - ERC, and the internal RC oscillator HIRC. The two low speed oscillator are the external
32768Hz oscillator - LXT and the internal 10kHz
(VDD=3V) oscillator - LIRC.
System Oscillator Overview
External Crystal/Resonator Oscillator - HXT
In addition to being the source of the main system clock
the oscillators also provide clock sources for the Watchdog Timer and Time Base functions. External oscillators
requiring some external components as well as two fully
integrated internal oscillators, requiring no external
components, are provided to form a wide range of both
fast and slow system oscillators.
Type
Name
Freq.
Pins
External Crystal
HXT
400kHz~
4MHz
OSC1/
OSC2
External RC
ERC
400kHz~
4MHz
OSC1
Internal High
Speed RC
HIRC
4095kHz
¾
C 1
O S C 1
R p
OSC1/
OSC2
External Low
Speed Crystal
LXT
Internal Low
Speed RC
LIRC
Rev. 1.20
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation. However, for some crystals and
most resonator types, to ensure oscillation and accurate
frequency generation, it is necessary to add two small
value external capacitors, C1 and C2. The exact values
of C1 and C2 should be selected in consultation with the
crystal or resonator manufacturer¢s specification.
C 2
R f
O S C 2
In te r n a l
O s c illa to r
C ir c u it
T o in te r n a l
c ir c u its
32768Hz
XT1/
XT2*
10kHz
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
¾
Crystal/Resonator Oscillator - HXT
22
February 25, 2011
HT45R22E
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
4MHz
8pF
10pF
1MHz
100pF
100pF
Note:
P A 5 /O S C 2
C2
P A 6 /O S C 1
N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s
Internal RC Oscillator - HIRC
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values
External 32768Hz Crystal Oscillator - LXT
External RC Oscillator - ERC
When the microcontroller enters the Idle/Sleep Mode,
the system clock is switched off to stop microcontroller
activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power-down Mode. To do this,
another clock, independent of the system clock, must be
provided. To do this a configuration option exists to allow
a high speed oscillator to be used in conjunction with a
low speed oscillator, known as the LXT oscillator. The
LXT oscillator is implemented using a 32768Hz crystal
connected to pins OSC1/OSC2. However, for some
crystals, to ensure oscillation and accurate frequency
generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and
C2 should be selected in consultation with the crystal or
resonator manufacturer¢s specification. The external
parallel feedback resistor, Rp, is required. The LXT oscillator must be used together with the HIRC oscillator.
Using the ERC oscillator only requires that a resistor,
with a value between 24kW and 120kW, is connected between OSC1 and VDD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator
configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor
has no influence over the frequency and is connected
for stability purposes only. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that
the influence of the power supply voltage, temperature
and process variations on the oscillation frequency are
minimised. As a resistance/frequency reference point, it
can be noted that with an external 120K resistor connected and with a 3V voltage power supply and temperature of 25 degrees, the oscillator will have a frequency
of 4MHz within a tolerance of 2%. Here only the OSC1
pin is used, which is shared with I/O pin PA6, leaving pin
PA5 free for use as a normal I/O pin.
V
R
In te rn a l R C
O s c illa to r
In te r n a l
O s c illa to r
C ir c u it
C 1
D D
3 2 7 6 8 H z
O S C
R p
In te rn a l R C
O s c illa to r
P A 6 /O S C 1
4 7 0 p F
T o in te r n a l
c ir c u its
C 2
P A 5 /O S C 2
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d .
2 . A lth o u g h n o t s h o w n p in s h a v e a
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External RC Oscillator - ERC
External LXT Oscillator
Internal RC Oscillator - HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4095kHz. Device trimming during the manufacturing
process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of
the power supply voltage, temperature and process
variations on the oscillation frequency are minimised.
As a result, at a power supply of either 3V and at a temperature of 25 degrees, the fixed oscillation frequency of
4095kHz will have a tolerance within 2%. Note that if this
internal system clock option is selected, as it requires no
external pins for its operation, I/O pins PA5 and PA6 are
free for use as normal I/O pins.
Rev. 1.20
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32768Hz
8pF
10pF
Note:
1. C1 and C2 values are for guidance only.
2. RP=5M~10MW is recommended.
32768 Hz Crystal Recommended Capacitor Values
LXT Oscillator Low Power Function
The LXT oscillator can function in one of two modes, the
Quick Start Mode and the Low Power Mode. The mode
selection is executed using the LXTLP bit in the CTRL0
register.
23
February 25, 2011
HT45R22E
LXTLP Bit
LXT Mode
Mode Types and Selection
0
Quick Start
1
Low-power
The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher
power requirements, while the opposite is of course true
for the lower frequency oscillators. With the capability of
dynamically switching between fast and slow oscillators,
the device has the flexibility to optimise the performance/power ratio, a feature especially important in
power sensitive portable applications.
After power-on, the LXTLP bit will be automatically
cleared to zero ensuring that the LXT oscillator is in the
Quick Start operating mode. In the Quick Start Mode the
LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can
be placed into the Low-power mode by setting the
LXTLP bit high. The oscillator will continue to run but
with reduced current consumption, as the higher current
consumption is only required during the LXT oscillator
start-up. In power sensitive applications, such as battery
applications, where power consumption must be kept to
a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds
after power-on.
If the LXT oscillator is used, then the internal RC oscillator, HIRC, must be used as the high frequency oscillator.
If the HXT or the ERC oscillator is chosen as the high
frequency system clock, then the LXT oscillator cannot
be used for sharing the same pins. The CLKMOD bit in
the CTRL0 register can be used to switch the system
clock from the high speed HIRC oscillator to the low
speed LXT oscillator. When the HALT instruction is executed and the device enters the Idle/Sleep Mode, the
LXT oscillator will always continue to run. For this device
the LXT crystal is connected to the OSC1/OSC2 pins
and LXT will always run (the LXT oscillator enable control bit is not used). Note that CLKMOD is only valid in
HIRC+LXT oscillator configuration.
It should be noted that, no matter what condition the
LXTLP bit is set to, the LXT oscillator will always function normally. The only difference is that it will take more
time to start up if in the Low-power mode.
Internal Low Speed Oscillator - LIRC
OSC1/OSC2 Configuration
The LIRC is a fully self-contained free running on-chip
RC oscillator with a typical frequency of 10kHz at 3V requiring no external components. When the device enters the Idle/Sleep Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the LIRC can be disabled
via a configuration option.
Operating
Mode
Normal
HIRC + LXT
HXT
ERC
HIRC
HIRC
LXT
Run
Run
Run
Run
Run
Slow
¾
¾
¾
Stop
Run
Sleep
Stop
Stop
Stop
Stop
Run
²¾² unimplemented
Operating Mode Control
Operating Modes
By using the LXT low frequency oscillator in combination with a high frequency oscillator, the system can be
selected to operate in a number of different modes.
These Modes are Normal, Slow, Idle and Sleep.
f
H X T
C L K M O D
( D e te r m in e N o r m a l/
S lo w M o d e )
H X T
C o n fig u r a tio n o p tio n
f
E R C
f
H IR C
E R C
M U X
H IR C
( N o r m a l)
M U X
(S L O W
f
f
S Y S
)
L X T
L X T
C o n fig u r a tio n o p tio n
L IR C
f
L IR C
f
M U X
S Y S
T o w a tc h d o g tim e r
/4
System Clock Configurations
Rev. 1.20
24
February 25, 2011
HT45R22E
Mode Switching
to run when the device enters the Idle/Sleep Mode. To
keep the LXT power consumption to a minimum level
the LXTLP bit in the CTRL0 register, which controls the
low power function, should be set high.
The devices are switched between one mode and another using a combination of the CLKMOD bit in the
CTRL0 register and the HALT instruction. The CLKMOD
bit chooses whether the system runs in either the Normal or Slow Mode by selecting the system clock to be
sourced from either a high or low frequency oscillator.
The HALT instruction forces the system into either the
Idle or Sleep Mode, depending upon whether the LXT
oscillator is running or not. The HALT instruction operates independently of the CLKMOD bit condition.
Wake-up
After the system enters the Idle/Sleep Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on PA0 to PA7 or PC0 to PC7
· A system interrupt
When a HALT instruction is executed and the LXT oscillator is not running, the system enters the Sleep mode
the following conditions exist:
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in their
original status.
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or LXT oscillator. The WDT will stop if its clock source
originates from the system clock.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Pins PA0~PA7 and PC0~PC7 can be setup via the
PAWK and PCWK registers to permit a negative transition on the pin to wake-up the system. When a PA0~PA7
or PC0~PC7 pin wake-up occurs, the program will resume execution at the instruction following the ²HALT²
instruction.
Standby Current Considerations
As the main reason for entering the Idle/Sleep Mode is
to keep the current consumption of the MCU to as low a
value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is not
full, in which case the regular interrupt response takes
place. If an interrupt request flag is set to ²1² before entering the Idle/Sleep Mode, then any interrupt requests will
not generate a wake-up function of the related interrupt
will be ignored. No matter what the source of the wake-up
event is, once a wake-up event occurs, there will be a
time delay before normal program execution resumes.
Consult the table for the related time.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
If the configuration options have enabled the Watchdog
Timer internal oscillator LIRC then this will continue to
run when in the Idle/Sleep Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. The LXT, if configured for use, will
also consume a limited amount of power, as it continues
Rev. 1.20
25
February 25, 2011
HT45R22E
powered up. Although any other data written to
WDTEN3~WDTEN0 will ensure that the Watchdog
Timer is enabled, for maximum protection it is recommended that the value 0101B is written to these bits.
No matter what the source of the wake-up event is, once
a wake-up event occurs, there will be a time delay before normal program execution resumes. Consult the table for the related time.
The Watchdog Timer clock can emanate from three different sources, selected by configuration option. These
are LXT, fSYS/4, or LIRC. It is important to note that when
the system enters the Idle/Sleep Mode the instruction
clock is stopped, therefore if the configuration options
have selected fSYS/4 as the Watchdog Timer clock
source, the Watchdog Timer will cease to function. For
systems that operate in noisy environments, using the
LIRC or the LXT as the clock source is therefore the recommended choice. The division ratio of the prescaler is
determined by bits 0, 1 and 2 of the WDTS register,
known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and with the WS0, WS1
and WS2 bits of the WDTS register all set high, the
prescaler division ratio will be 1:128, which will give a
maximum time-out period.
Oscillator Type
Wake-up
Source
External RES
ERC, IRC
Crystal
tRSDT + tSST1
tRSDT + tSST2
tSST1
tSST2
PA, PC Port
Interrupt
WDT Overflow
Note:
1. tSYS (system clock)
2. tRSTD is power-on delay, typical time=100ms
3. tSST1= 2 or 1024 tSYS
4. tSST2= 1024 tSYS
Wake-up Delay Time
Watchdog Timer
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Idle/Sleep Mode,
when a Watchdog Timer time-out occurs, the device will
be woken up, the TO bit in the status register will be set
and only the Program Counter and Stack Pointer will be
reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT instruction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have
no effect, only the execution of a ²CLR WDT2² instruction will clear the Watchdog Timer. Similarly after the
²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain
uncontrollable external events such as electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the Watchdog
Timer function is not enabled, then any instructions related to the Watchdog Timer will result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two internal registers WDTS and CTRL1. Enabling the Watchdog Timer
can be controlled by both a configuration option and the
WDTEN bits in the CTRL1 internal register in the Data
Memory.
Configuration
Option
CTRL1
Register
WDT
Function
Disable
Disable
OFF
Disable
Enable
ON
Enable
x
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~
WDTEN0 in the CTRL1 register are written with the binary value 1010B and WDT configuration option is disable. This will be the condition when the device is
Rev. 1.20
26
February 25, 2011
HT45R22E
· WDTS Register
Bit
7
6
5
4
3
2
1
0
Name
¾
¾
¾
¾
¾
WS2
WS1
WS0
R/W
¾
¾
¾
¾
¾
R/W
R/W
R/W
POR
¾
¾
¾
¾
¾
1
1
1
Bit 7~3
unimplemented, read as ²0²
Bit 2~0
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
C L R
W D T 1 F la g
C L R
W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
/4
L X T
L IR C
Y S
C L R
C o n fig .
O p tio n
S e le c t
fW
D T C K
W D T C lo c k S o u r c e S e le c tio n
1 5 s ta g e c o u n te r
W D T T im e - o u t
W S 2 ~ W S 0
Watchdog Timer
Rev. 1.20
27
February 25, 2011
HT45R22E
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
In te rn a l R e s e t
V D D
0 .9 V
R E S
t RR
SS TT DD ++
t SS
SS TT
Note: tRSTD is power-on delay, typical time=100ms
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
V
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
D D
0 .0 1 m F * *
1 N 4 1 4 8 *
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
V D D
1 0 k W ~
1 0 0 k W
Reset Functions
R E S /P A 7
3 0 0 W *
0 .1 ~ 1 m F
V S S
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
Rev. 1.20
D D
Note:
²*² It is recommended that this component is
added for added ESD protection
²**² It is recommended that this component is
added in environments where power line noise
is significant
External RES Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
28
February 25, 2011
HT45R22E
· RES Pin Reset
W D T T im e - o u t
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
tS
In te rn a l R e s e t
WDT Time-out Reset during Idle/Sleep
Timing Chart
Note:
D D
D D
tR
S T D
+
tS
S T
In te rn a l R e s e t
RES Reset Timing Chart
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Idle/Sleep function or Watchdog Timer. The reset flags
are shown in the table:
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
L V R
S T D
+
tS
Low Voltage Reset Timing Chart
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tS
RESET Conditions
0
0
Power-on reset
u
u
RES or LVR reset during Normal or Slow
Mode operation
1
u
WDT time-out reset during Normal or
Slow Mode operation
1
1
WDT time-out reset during Idle or Sleep
Mode operation
Item
· Watchdog Time-out Reset during Normal Operation
+
PDF
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
Note: tRSTD is power-on delay, typical time=100ms
S T D
TO
Note: ²u² stands for unchanged
S T
In te rn a l R e s e t
tR
The tSST can be chosen to be either 1024 or 2
clock cycles via configuration option if the system clock source is provided by ERC or HIRC.
The SST is 1024 for HXT or LXT.
Reset Initial Conditions
Note: tRSTD is power-on delay, typical time=100ms
tR
S T
S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms
WDT Time-out Reset during Normal Operation
Timing Chart
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer
· Watchdog Time-out Reset during Idle/Sleep mode
Stack Pointer will point to the top
of the stack
The Watchdog time-out Reset during Idle/Sleep mode
is a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
Rev. 1.20
29
February 25, 2011
HT45R22E
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
Register
Power-on
Reset
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(Idle/Sleep)
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
-00- -00-
-00- -00-
-00- -00-
-uu- -uu-
MFIC
-000 -000
-000 -000
-000 -000
-uuu -uuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
uuuu uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
0000 1---
0000 1---
0000 1---
uuuu u---
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAWK
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAPU
-000 0000
-000 0000
-000 0000
-uuu uuuu
PB
--11 1111
--11 1111
--11 1111
--uu uuuu
PBC
--11 1111
--11 1111
--11 1111
--uu uuuu
PBPU
--00 0000
-000 0000
-000 0000
--uu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCWK
0000 0000
0000 0000
0000 0000
uuuu uuuu
PCPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTRL0
-0-- 0000
-0-- 0000
-0-- 0000
-u-- uuuu
CTRL1
1000 1010
1000 1010
1000 1010
uuuu uuuu
CMP0C
-000 0000
-000 0000
-000 0000
-uuu uuuu
CMP1C
000- 0-00
000- 0-00
000- 0-00
uuu- u-uu
COPA0C
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA1C
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA2C
0000 0000
0000 0000
0000 0000
uuuu uuuu
COPA3C
0000 0000
0000 0000
0000 0000
uuuu uuuu
OPA0OC
0x00 1000
0x00 1000
0x00 1000
uuuu uuuu
OPA1OC
0x00 1000
0x00 1000
0x00 1000
uuuu uuuu
Note:
²-² not implemented; ²u² means ²unchanged²; ²x² means ²unknown²
Rev. 1.20
30
February 25, 2011
HT45R22E
Port A, Port C Wake-up
Input/Output Ports
If the HALT instruction is executed, the device will enter
the Idle/Sleep Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the PA0~PA7 or PC0~PC7 pins from high to low. After a
HALT instruction forces the microcontroller into entering
the Idle/Sleep Mode, the processor will remain idle or in
a low-power state until the logic condition of the selected
wake-up pin on Port A or Port C changes from high to
low. This function is especially suitable for applications
that can be woken up via external switches. Note that
pins PA0 to PA7 and PC0~PC7 can be selected individually to have this wake-up feature using an internal register known as PAWK and PCWK, located in the Data
Memory.
Holtek microcontrollers offer considerable flexibility on
their I/O ports. Most pins can have either an input or output designation under user program control. Additionally, as there are pull-high resistors and wake-up
software configurations, the user is provided with an I/O
structure to meet the needs of a wide range of application possibilities.
For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, when configured as an input have the capability
of being connected to an internal pull-high resistor.
These pull-high resistors are selectable via a register
known as PAPU, PBPU and PCPU located in the Data
Memory. The pull-high resistors are implemented using
weak PMOS transistors. Note that pin PA7 does not
have a pull-high resistor selection.
· PAWK, PAC, PAPU, PBC, PBPU, PCWK, PCC, PCPU Registers
Bit
Register
Name
POR
7
6
5
4
3
2
1
0
PAWK
00H
PAWK7
PAWK6
PAWK5
PAWK4
PAWK3
PAWK2
PAWK1
PAWK0
PAC
FFH
PAC7
PAC6
PAC5
PAC4
PAC3
PAC2
PAC1
PAC0
PAPU
00H
¾
PAPU6
PAPU5
PAPU4
PAPU3
PAPU2
PAPU1
PAPU0
PBC
3FH
¾
¾
PBC5
PBC4
PBC3
PBC2
PBC1
PBC0
PBPU
00H
¾
¾
PBPU5
PBPU4
PBPU3
PBPU2
PBPU1
PBPU0
PCWK
00H
PCWK7
PCWK6
PCWK5
PCWK4
PCWK3
PCWK2
PCWK1
PCWK0
PCC
FFH
PCC7
PCC6
PCC5
PCC4
PCC3
PCC2
PCC1
PCC0
PCPU
00H
PCPU7
PCPU6
PCPU5
PCPU4
PCPU3
PCPU2
PCPU1
PCPU0
²¾² Unimplemented, read as ²0²
PAWKn, PCWKn: PA, PC wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn: Pull-high function enable
0: disable
1: enable
Rev. 1.20
31
February 25, 2011
HT45R22E
I/O Port Control Registers
· PFD Output
Each Port has its own control register, known as PAC,
PBC and PCC which controls the input/output configuration. With this control register, each I/O pin with or
without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function
as an input, the corresponding bit of the control register
must be written as a ²1². This will then allow the logic
state of the input pin to be directly read by instructions.
When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it
should be noted that the program will in fact only read
the status of the output data latch and not the actual
logic status of the output pin.
The device contains a PFD function which single or
dual outputs which are pin-shared with I/O pins. The
output function of these pins are chosen using the
CTRL0 register. Note that the corresponding bit of the
port control register, must setup the pin as an output to
enable the PFD and PFD outputs. If the port control
register has setup these pins as inputs, then these
pins will function as normal logic inputs with the usual
pull-high selection, even if the PFD function has been
selected.
· Comparator Input/Outputs
The device has two comparator inputs and a single
comparator output, pin-shared with PC0, PC1 and
PC7. Software options determine if these pins have
I/O or comparator functions via bits in the COPA2C
and COPA3C registers. The comparator function together with the comparator interrupt transition type is
selected via bits in the CMP0C and CMP1C registers.
If used as I/O pins then full pull-high resistor selections remain, however if used as comparator inputs
then any pull-high resistor selections will be automatically disconnected.
Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
· OPA0 and OPA1 input/outputs
There are two OPAs in this device. These pins PA4,
PA3 and PA2 are pin-shared with the non-inverting input pin A0P, the inverting input pin A0N and the output
pin A0X of the 1st OPA, respectively. Pins PC6, PA0
and PA1 are pin-shared with the non-inverting input
pin A1P, the inverting input pin A1N and the output pin
A1X of the 2nd OPA, respectively. Software options
determine these pins have I/O or analog OPA functions via bits in the COPA3C resister. Once selected
as analog functions, the I/O functions and pull-high resistors are disabled automatically.
· External Interrupt Input
The external interrupt pin, INT, is pin-shared with an
I/O pin. To use the pin as an external interrupt input
the correct bits in the INTC0 register must be programmed. The pin must also be setup as an input by
setting the PAC3 bit in the Port Control Register. A
pull-high resistor can also be selected via the appropriate port pull-high resistor register. Note that even if
the pin is setup as an external interrupt input the I/O
function still remains.
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
· External Timer/Event Counter Input
The Timer/Event Counter pins, TC0 and TC1 are
pin-shared with I/O pins. For these shared pins to be
used as Timer/Event Counter inputs, the Timer/Event
Counter must be configured to be in the Event Counter or Pulse Width Capture Mode. This is achieved by
setting the appropriate bits in the Timer/Event Counter
Control Register. The pins must also be setup as inputs by setting the appropriate bit in the Port Control
Register. Pull-high resistor options can also be selected using the port pull-high resistor registers. Note
that even if the pin is setup as an external timer input
the I/O function still remains.
Rev. 1.20
32
February 25, 2011
HT45R22E
Programming Considerations
port, modify it to the required new bit values and then rewrite this data back to the output ports.
Within the user program, one of the first things to consider is port initialisation. After a reset, the I/O data register and I/O port control register will be set high. This
means that all I/O pins will default to an input state, the
level of which depends on the other connected circuitry
and whether pull-high options have been selected. If the
port control registers, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated port data
register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide
by loading the correct value into the port control register
or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
T 1
S y s te m
T 2
T 3
R e a d fro m
W r ite C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P o rt
W r ite to P o r t
P u ll- H ig h
S e le c t
S y s te m
D D
W e a k
P u ll- u p
Q
C K
S
I/O
p in
D a ta B it
Q
D
C K
Q
S
R e a d D a ta R e g is te r
T 4
Pins PA0 to PA7 and PC0 to PC7 each has a wake-up
function, selected via the PAWK and the PCWK registers respectively. When the device is in the Idle/Sleep
Mode, various methods are available to wake the device
up. One of these is a high to low transition of any of
these pins. Single or multiple pins on Port A or Port C
can be setup to have this function.
Q
C h ip R e s e t
R e a d C o n tr o l R e g is te r
T 3
Read Modify Write Timing
V
D
T 2
P o rt D a ta
C o n tr o l B it
D a ta B u s
T 1
T 4
C lo c k
M
U
X
W a k e -u p
P A a n d P C o n ly
W a k e - u p S e le c t
Generic Input/Output Ports
Rev. 1.20
33
February 25, 2011
HT45R22E
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
Q
S
C h ip R e s e t
P A 7 /R E S
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
W a k e -u p (P A 7 )
P A W K 7
R E S fo r P A 7 o n ly
PA7 NMOS Input/Output Port
V
P u ll- H ig h
S e le c t
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
D D
W e a k
P u ll- u p
Q
C K
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P B 0 /S C O M 0 ~
P B 3 /S C O M 3
P B 4 ,P B 5
D a ta B it
Q
D
Q
C K
S
M
R e a d D a ta R e g is te r
U
X
V
D D
/2
C O M n E N
S C O M E N
PB Input/Output Port
Rev. 1.20
34
February 25, 2011
HT45R22E
Timer/Event Counters
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains two
count-up timers of 8-bit capacity. As the timers have
three different operating modes, they can be configured
to operate as a general timer, an external event counter
or as a pulse width capture device. The provision of an
internal prescaler to the clock circuitry on gives added
range to the timers.
value loaded by the preload register to the full count of
FFH at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting. Note that to achieve a maximum full
range count of FFH, the preload register must first be
cleared to all zeros. It should be noted that after
power-on, the preload registers will be in an unknown
condition.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control
Register which defines the timer options and determines how the timer is to be used. The device can have
the timer clock configured to come from the internal
clock source. In addition, the timer clock source can also
be configured to come from an external timer pin.
Note that if the Timer/Event Counter is in an OFF condition and data is written to its preload register, this data
will be immediately written into the actual counter. However, if the counter is enabled and counting, any new
data written into the preload data register during this period will remain in the preload register and will only be
written into the actual counter the next time an overflow
occurs.
Timer Control Registers - TMR0C, TMR1C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
Configuring the Timer/Event Counter Input Clock
Source
The Timer/Event Counter clock source can originate
from various sources, an internal clock or an external
pin. The internal clock source is used when the timer is
in the timer mode or in the pulse width capture mode.
For Timer/Event Counter 0, this internal clock source is
first divided by a prescaler, the division ratio of which is
conditioned by the Timer Control Register bits
T0PSC0~T0PSC2. For Timer/Event Counter 0, the internal clock source can be either fSYS or the LXT Oscillator, the choice of which is determined by the T0S bit in
the TMR0C register.
The Timer Control Register is known as TMRnC. It is the
Timer Control Register together with its corresponding
Timer Register that controls the full operation of the
Timer/Event Counter. Before the timer can be used, it is
essential that the Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during
program initialisation.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width capture mode, bits 7 and 6 of the
Timer Control Register, which are known as the bit pair
TnM1/TnM0, must be set to the required logic levels.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the basic on/off control of the respective timer. Setting the bit high allows the
counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division
ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If
the timer is in the event count or pulse width capture
mode, the active transition edge level type is selected by
the logic level of bit 3 of the Timer Control Register
which is known as TnEG. The TnS bit selects the internal clock source if used.
An external clock source is used when the Timer/Event
Counter n is in the event counting mode, the clock
source being provided on an external timer pin TCn. Depending upon the condition of the TnE bit, each high to
low, or low to high transition on the external timer pin will
increment the counter by one.
Timer Registers - TMR0, TMR1
The timer registers are special function registers located
in the Special Purpose Data Memory and is the place
where the actual timer value is stored. These registers
are known as TMR0 and TMR1. The value in the timer
registers increases by one each time an internal clock
pulse is received or an external transition occurs on the
external timer pin. The timer will count from the initial
Rev. 1.20
35
February 25, 2011
HT45R22E
P W M
P W M C 0
P W M C 1
C o n tro l
P W M 0 , P W M 1
T im e - B a s e e v e n t in te r r u p t P e r io d
1
(2 10 ~ 2 13 ) *
fT P
T im e - B a s e C o n tr o l
T 0 S
fS
Y S
fL
X T
0
M U X
1
fT
T 0 P S C
[2 :0 ]
P
7 S ta g e C o u n te r
7
T o T im e r 0 in te r n a l c lo c k
(fT 0 C K = fT P ~ fT P /1 2 8 )
8 -1 M U X
7
T 2 P S C
T o T im e r 2 in te r n a l c lo c k
(fT 2 C K = fT P ~ fT P /1 2 8 )
8 -1 M U X
[2 :0 ]
T im e r P r e s c a le r
Clock Structure for Timer/Time Base
D a ta B u s
T 0 M 1 , T 0 M 0
T im e r 0 In te r n a l C lo c k
(fT P )
T C 0
C X
P r e lo a d R e g is te r
M o d e C o n tro l
T 0 O V
O v e r flo w
to In te rru p t
U p C o u n te r
M U X
T 0 O N
T 0 E G
T M R 0 S
¸
2
P F D 0
8-bit Timer/Event Counter 0 Structure
D a ta B u s
T 1 M 1 , T 1 M 0
fS Y S /4
L X T O s c illa to r
M
U
X
P r e lo a d R e g is te r
M o d e C o n tro l
T 1 O V
T 1 S
O v e r flo w
to In te rru p t
U p C o u n te r
T C 1
T 1 O N
T 1 E G
¸
2
P F D 1
8-bit Timer/Event Counter 1 Structure
P F D C S
P F D 0
0
P F D 1
1
M U X
Rev. 1.20
36
P F D
o u tp u t
February 25, 2011
HT45R22E
· TMR0C Register
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0S
T0ON
T0EG
T0PSC2
T0PSC1
T0PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
1
0
0
0
Bit 7,6
T0M1, T0M0: Timer 0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0, the Time-Base
Bit 4
T0ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
Rev. 1.20
37
February 25, 2011
HT45R22E
· TMR1C Register
Bit
7
6
5
4
3
2
1
0
Name
T1M1
T1M0
T1S
T1ON
T1EG
¾
¾
¾
R/W
R/W
R/W
R/W
R/W
R/W
¾
¾
¾
POR
0
0
0
0
1
¾
¾
¾
Bit 7,6
T1M1, T1M0: Timer 1 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
Bit 4
T1ON: Timer/event counter counting enable
0: disable
1: enable
Bit 3
T1EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse width capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
unimplemented, read as ²0²
Timer Mode
ever, the internal interrupts can be disabled by ensuring
that the ETnI bits of the INTCn register are reset to zero.
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer TCn pin, can be
recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
Bit7 Bit6
1
0
In this mode the internal clock is used as the timer clock.
The timer input clock source is either fSYS, fSYS/4 or the
LXT oscillator. However, this timer clock source is further divided by a prescaler, the value of which is determined by the bits TnPSC2~TnPSC0 in the Timer
Control Register. The timer-on bit, TnON must be set
high to enable the timer to run. Each time an internal
clock high to low transition occurs, the timer increments
by one; when the timer is full and overflows, an interrupt
signal is generated and the timer will reload the value already loaded into the preload register and continue
counting. A timer overflow condition and corresponding
internal interrupt is one of the wake-up sources, how-
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7 Bit6
0
1
In this mode, the external timer TCn pin is used as the
Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnEG, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the TnEG is high, the counter
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
Rev. 1.20
38
February 25, 2011
HT45R22E
TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control
Register have been setup, the enable bit TnON, which is
bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the
external timer pin.
will increment each time the external timer pin receives
a high to low transition. When it is full and overflows, an
interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload
register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control
Register is reset to zero.
If the Active Edge Select bit TnEG, which is bit 3 of the
Timer Control Register, is low, once a high to low transition has been received on the external timer pin, the
Timer/Event Counter will start counting until the external
timer pin returns to its original high level. At this point the
enable bit will be automatically reset to zero and the
Timer/Event Counter will stop counting. If the Active
Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when
the external timer pin returns to its original low level. As
before, the enable bit will be automatically reset to zero
and the Timer/Event Counter will stop counting. It is important to note that in the pulse width capture Mode, the
enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its
original level, whereas in the other two modes the enable bit can only be reset to zero under program control.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Idle/Sleep Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input TCn pin. As a
result when the timer overflows it will generate a timer
interrupt and corresponding wake-up source.
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, TnM1/TnM0, in the Timer Control
Register must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the TCn pin. As the
enable bit has now been reset, any further transitions on
the external timer pin will be ignored. The timer cannot
begin further pulse width capture until the enable bit is
set high again by the program. In this way, single shot
pulse measurements can be easily made.
Bit7 Bit6
1
1
In this mode the internal clock, fSYS , fSYS/4 or the LXT, is
used as the internal clock for the 8-bit Timer/Event
Counter. However, the clock source, fSYS, for the 8-bit
timer is further divided by a prescaler, the value of which
is determined by the Prescaler Rate Select bits
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart (TnEG=1)
E x te rn a l T C n
P in In p u t
T n O N - w ith T n E = 0
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+ 1
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart (TnEG=0)
Rev. 1.20
39
February 25, 2011
HT45R22E
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the corresponding Interrupt Control Register is reset to zero.
nected interfaces such as buzzers. The PFDEN[1:0] in
CTRL0 register can select a single PFD pin or the complimentary pair PFD and PFD for those devices with
dual outputs.
The Timer/Event Counter overflow signal is the clock
source for the PFD function, which is controlled by
PFDCS bit in CTRL0. For applicable devices the clock
source can come from either Timer/Event Counter 0 or
Timer/Event Counter 1. The output frequency is controlled by loading the required values into the timer
prescaler and timer registers to give the required division ratio. The counter will begin to count-up from this
preload register value until full, at which point an overflow signal is generated, causing both the PFD and PFD
outputs to change state. The counter will then be automatically reloaded with the preload register value and
continue counting-up.
As the TCn pin is shared with an I/O pin, to ensure that
the pin is configured to operate as a pulse width capture
pin, two things have to happen. The first is to ensure that
the Operating Mode Select bits in the Timer Control
Register place the Timer/Event Counter in the pulse
width capture Mode, the second is to ensure that the
port control register configures the pin as an input.
Prescaler
Bits T0PSC0~T0PSC2 of the TMR0C register can be
used to define a division ratio for the internal clock
source of the Timer/Event Counter enabling longer time
out periods to be setup.
If the CTRL0 register has selected the PFD function,
then for both PFD outputs to operate, it is essential for
the Port A control register PAC, to setup the PFD pins as
outputs. If only one pin is setup as an output, the other
pin can still be used as a normal data input pin. However, if both pins are setup as inputs then the PFD will
not function. For devices with dual outputs the PFD outputs will only be activated if bit PA0 is set high. For devices with a single PFD output, bit PA1 must be set high
to activate the PFD. These output data bits can be used
as the on/off control bit for the PFD outputs. Note that
the PFD outputs will all be low if the output data bit is
cleared to zero.
PFD Function
The Programmable Frequency Divider provides a
means of producing a variable frequency output suitable
for applications, such as piezo-buzzer driving or other
interfaces requiring a precise frequency generator.
Depending upon which device is used, there is either a
single output, PFD, or a complimentary output pair, PFD
and PFD. As the pins are shared with I/O pins, the function is selected using the CTRL0 register. Note that the
PFD pin is the inverse of the PFD pin generating a complementary output and supplying more power to con-
T im e r O v e r flo w
P F D
C lo c k
P A 0 o r P A 1 D a ta
P F D
O u tp u t a t P A 0
P F D
O u tp u t a t P A 1
PFD Function - Complementary Outputs
T im e r O v e r flo w
P F D
C lo c k
P A 0 D a ta
P F D
O u tp u t a t P A 0
PFD Function - Single Output
Rev. 1.20
40
February 25, 2011
HT45R22E
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also
important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer registers are unknown. After the timer has been initialised
the timer can be turned on and off by controlling the enable bit in the timer control register.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very precise values of frequency can be generated.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width capture mode, requires the
use of an external timer pin for its operation. As this pin
is a shared pin it must be configured correctly to ensure
that it is setup for use as a Timer/Event Counter input
pin. This is achieved by ensuring that the mode select
bits in the Timer/Event Counter control register, select
either the event counter or pulse width capture mode.
Additionally the corresponding Port Control Register bit
must be set high to ensure that the pin is setup as an input. Any pull-high resistor connected to this pin will remain valid even if the pin is used as a Timer/Event
Counter input.
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the Timer/Event Counter interrupt
is enabled this will in turn generate an interrupt signal.
However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also
generate a wake-up signal if the device is in a
Power-down condition. This situation may occur if the
Timer/Event Counter is in the Event Counting Mode and
if the external signal continues to change state. In such
a case, the Timer/Event Counter will continue to count
these external events and if an overflow occurs the device will be woken up from its Power-down condition. To
prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing
the ²HALT² instruction to enter the Idle/Sleep Mode.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal
interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width capture
mode, the internal system clock is also used as the timer
clock source but the timer will only run when the correct
logic condition appears on the external timer input pin. As
this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a
result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is
configured to be in the event counting mode, which again
is an external event and not synchronised with the internal system or timer clock.
Timer Program Example
The program shows how the Timer/Event Counter registers are setup along with how the interrupts are enabled
and managed. Note how the Timer/Event Counter is
turned on, by setting bit 4 of the Timer Control Register.
The Timer/Event Counter can be turned off in a similar
way by clearing the same bit. This example program
sets the Timer/Event Counters to be in the timer mode,
which uses the internal system clock as their clock
source.
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
Rev. 1.20
41
February 25, 2011
HT45R22E
· Timer Programming Example
org
04h
; external interrupt vector
org 08h
; Timer Counter 0 interrupt vector
jmp tmr0int
; jump here when Timer 0 overflows
:
:
org 20h
; main program
:
:
;internal Timer 0 interrupt routine
tmr0int:
:
; Timer 0 main program placed here
:
:
begin:
;setup Timer 0 registers
mov a,09bh
; setup Timer 0 preload value
mov tmr0,a
mov a,081h
; setup Timer 0 control register
mov tmr0c,a
; timer mode and prescaler set to /2
;setup interrupt register
mov a,00dh
; enable master interrupt and both timer interrupts
mov intc0,a
:
:
set tmr0c.4
; start Timer 0
:
:
Time Base
Operational Amplifiers
The device includes a Time Base function which is used
to generate a regular time interval signal.
There are two fully integrated Operational Amplifiers in
the device, OPA0 and OPA1. These OPAs can be used
for user specified analog signal processing. The OPAs
can be disabled or enabled entirely under software control using internal registers. With specific control registers, some OPA related applications can be easily
implemented, such as Unity Gain Buffer, Non-Inverting
Amplifier, Inverting Amplifier and various kinds of filters,
etc.
The Time Base time interval magnitude is determined
using an internal 13 stage counter sets the division ratio
of the clock source. This division ratio is controlled by
both the TBSEL0 and TBSEL1 bits in the CTRL1 register. The clock source is selected using the T0S bit in the
TMR0C register.
When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time
Base clock source is the same as the Timer/Event
Counter clock source, care should be taken when programming.
Rev. 1.20
Comparator & Operational Amplifier Registers
The internal Operational Amplifiers are fully under the
control of internal registers, COPA0C, COPA1C,
COPA2C, COPA3C, OPA0OC and OPA1OC. These
control the enable/disable function, input path selection,
gain control, polarity and calibration function.
42
February 25, 2011
HT45R22E
Operational Amplifier Operation
Note that the EA0I, EA1I interrupt control bits should be
set to ²0² before entering halt mode for power saving.
The advantages of multiple switches and input path options, various reference voltage selection, up to 8 kinds of
internal software gain control, output with interrupt function, offset reference voltage calibration function and
power down control for low power consumption enhance
the flexibility of these two OPAs to suit a wide range of application possibilities.
The following block diagram illustrates the main functional blocks of the OPAs and Comparator in this device.
S12
EA0I
S11
A0N
A0X
A0
To OPA0 interrupt
A0P
0.7VDD
0.5VDD
0.1VDD
MUX
S13
A0PS[2:0]
MA0P
A0X
A1NS[1:0]
S21
MUX
A1N
MA1N
R1
10K
S22
R2
S23
500K
EA1I
A1
A1P
0.7VDD
0.5VDD
0.1VDD
A1X
To OPA1 interrupt
MA1P
MUX
CINTS[1:0]
A1PS[2:0]
S24
=00: rasing edge
=01: falling edge
=10: both edge
Edge
control
CNS[1:0]
to interrupt
A1X
MUX
MCN
POL
TC0 pin
CN
mux
C
CP
0.7VDD
0.5VDD
0.1VDD
debounce
CX
(COUT)
MCP
To timer 0 external
clock input
TMR0S
MUX
CPS[2:0]
CX
Rev. 1.20
43
February 25, 2011
HT45R22E
· COPA0C Register
Bit
7
6
5
4
3
2
1
0
Name
A0PS2
A0PS1
A0PS0
CPS2
CPS1
CPS0
CNS1
CNS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
A0PS2~A0PS0: OPA0 Non-inverting input signal selection bits
000: A0P pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
Bit 4~2
CPS2~CPS0: Comparator Non-inverting input signal selection bits
000: CP pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
Bit 1~0
CNS1~CNS0: Comparator Inverting input signal selection bits
00: CN pin
01: A1X
10: VSS
11: Unimplemented
· COPA1C Register
Bit
7
6
5
4
3
2
1
0
Name
A1G2
A1G1
A1G0
A1PS2
A1PS1
A1PS0
A1NS1
A1NS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~5
A1G2~A1G0: OPA1 Gain control bits
000: 6.25
001: 12.5
010: 18.75
011: 25
100: 31.25
101: 37.5
110: 43.75
111: 50
Bit 4~2
A1PS2~A1PS0: OPA1 Non-inverting input signal selection bits
000: A1P pin
001: 0.7VDD
010: 0.5VDD
011: 0.1VDD
100: VSS
101: A0X, the OPA0 internal output pin
Bit 1~0
A1NS1~A1NS0: OPA1 Inverting input signal selection bits
00: A1N pin
01: A0X, the OPA0 internal output pin
10: VSS
11: Unimplemented
Rev. 1.20
44
February 25, 2011
HT45R22E
· COPA2C Register
Bit
7
6
5
4
3
2
1
0
Name
S24
S23
S22
S21
S13
S12
S11
CXC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
S24: Switch S24 on/off control bit
0: Off
1: On
S23: Switch S23 on/off control bit
0: Off
1: On
S22: Switch S22 on/off control bit
0: Off
1: On
S21: Switch S21 on/off control bit
0: Off
1: On
S13: Switch S13 on/off control bit
0: Off
1: On
S12: Switch S12 on/off control bit
0: Off
1: On
S11: Switch S11 on/off control bit
0: Off
1: On
CXC: PC1/CX pin is as CX pin or GPIO (PC1) control bit
0: PC1 pin
1: CX pin (I/O pull-high disable)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
· COPA3C Register
Bit
7
6
5
4
3
2
1
0
Name
A1XC
A1PC
A1NC
A0XC
A0PC
A0NC
CPC
CNC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.20
A1XC: PA1/PFD/A1X pin is as A1X pin or the other pin functions control bit
0: the other pin functions
1: A1X pin (I/O pull-high disable)
A1PC: PC6/A1P pin is as A1P pin or GPIO (PC6) control bit
0: PC6 pin
1: A1P pin (I/O pull-high disable)
A1NC: PA0/PFD/A1N pin is as A1N pin or the other pin functions control bit
0: the other pin functions
1: A1N pin (I/O pull-high disable)
A0XC: PA2/TC0/A0X pin is as A0X pin or the other pin functions control bit
0: the other pin functions
1: A0X pin (I/O pull-high disable)
A0PC: PA4/TC1/A0P pin is as A0P pin or the other pin functions control bit
0: the other pin functions
1: A0P pin (I/O pull-high disable)
A0NC: PA3/INT/A0N pin is as A0N pin or the other pin functions control bit
0: the other pin functions
1: A0N pin (I/O pull-high disable)
CPC: PC7/CP pin is as CP pin or GPIO (PC7) control bit
0: PC7 pin
1: CP pin (I/O pull-high disable)
CNC: PC0/CN pin is as CP pin or GPIO (PC0) control bit
0: PC0 pin
1: CN pin (I/O pull-high disable)
45
February 25, 2011
HT45R22E
· OPA0OC Register
Bit
7
6
5
4
3
2
1
0
Name
A0EN
A0OP
A0OFM
A0RS
A0OF3
A0OF2
A0OF1
A0OF0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
A0EN: Operational amplifier OPA0 enable/disable
0: disable
1: enable
Bit 6
A0OP: Operational amplifier output; positive logic. This bit is read only.
Bit 5
A0OFM: Operational amplifier mode or input offset voltage cancellation mode
0: operational amplifier mode
1: input offset voltage cancellation mode
Bit 4
A0RS: Operational amplifier input offset voltage cancellation reference selection bit
0: select OPN as the reference input
1: select OPP as the reference input
Bit 3~0
A0OF3~A0OF0: Operational amplifier input offset voltage cancellation control bits
· OPA1OC Register
Bit
7
6
5
4
3
2
1
0
Name
A1EN
A1OP
A1OFM
A1RS
A1OF3
A1OF2
A1OF1
A1OF0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
A1EN: Operational amplifier OPA1 enable/disable
0: disable
1: enable
Bit 6
A1OP: Operational amplifier output; positive logic. This bit is read only.
Bit 5
A1OFM: Operational amplifier mode or input offset voltage cancellation mode
0: operational amplifier mode
1: input offset voltage cancellation mode
Bit 4
A1RS: Operational amplifier input offset voltage cancellation reference selection bit
0: select OPN as the reference input
1: select OPP as the reference input
Bit 3~0
A1OF3~A1OF0: Operational amplifier input offset voltage cancellation control bits
Rev. 1.20
46
February 25, 2011
HT45R22E
Operational Amplifier Offset Cancellation function
Comparator
Each of the internal OPAs allows for a commode mode
adjustment method of its input offset voltage.
A0RS
A0OFM
S1A
S2A
S3A
0
0
ON
ON
OFF
0
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
S 1 A
A 0 P
S 2 A
A 0 N
The device contains a fully integrated Comparator
whose operation is controlled by the Comparator control
registers, known as the CMP0C, CMP1C, COPA0C,
COPA2C and COPA3C registers. The CEN bit within
CMP0C register is used as the enable or disable bit for
the comparator function. The advantages of multiple input resources, multiple reference voltage options, output polarity control, output to Timer counter, multiple
output interrupt triggers, comparator output wakeup
MCU function, comparator output with de-bounce options, comparator operating current selection and power
down control for low power consumption enhance the
flexibility of this comparator to suit a wide range of application possibilities.
A 0 O P
S 3 A
A 0 O F 0 ~ A 0 O F 3
A 0 E N
A 0 X
Functions
A1RS
A1OFM
S1B
S2B
S3B
0
0
ON
ON
OFF
0
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
S 1 B
A 1 P
A 1 N
S 2 B
1 .5 k W
The Comparator can work with OPAs or standalone as
shown in the main functional blocks of the OPAs and
Comparator in this device. This comparator provides
three operating current options, which are 200mA, 5mA
and 1mA. The purpose of this design is to provide the suitable comparator power consumption for different operating modes of the device. The higher the operating
current, the shorter the comparator response time, therefore, the designer can select the higher operating current
for the device working at normal mode and a lower one
for the device entering power down mode. By this way,
this comparator can operate under very low power consumption and perform as a wakeup resource when the
device enters power down mode. In addition, this device
provides different comparator output de-bounce time options for different input signal. If the input signal is noise
sensitive, then the better choice will be the longer
de-bounce time. The designer could select the suitable
de-bounce time according to the input signal.
A 1 O P
S 3 B
A 1 O F 0 ~ A 1 O F 3
A 1 E N
A 1 X
The calibration steps are as following:
1. Set A0OFM=1 to setup the offset cancellation mode,
here S3A is closed.
2. Set A0RS to select which input pin is to be used as
the reference voltage - S1 or S2 is closed
3. Adjust A0OF0~A0OF3 until the output status
changes
4. Set A0OFM = 0 to restore the normal OPA mode
5. Repeat the same procedure from steps 1 to 4
for OPA1.
Rev. 1.20
47
February 25, 2011
HT45R22E
· CMP0C Register
Bit
7
6
5
4
3
2
1
0
Name
¾
CEN
CPOL
COUT
DBC1
DBC0
CPCS1
CPCS0
R/W
¾
R/W
R/W
R
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
CEN: comparator on/off bit
0: off
1: on
Note that the designer should enable the comparator first before enabling the comparator
interrupt, in order to prevent an unexpected interrupt.
Bit 5
CPOL: comparator output polarity control bit
0: not inverted
1: inverted
Bit 4
COUT: comparator output bit.
CPOL=0: If the CP pin input voltage is less than CN pin, then the COUT is ²0².
If the CP pin input voltage is greater than CN pin, then the COUT is ²1².
CPOL=1: If the CP pin input voltage is less than CN pin, then the COUT is ²1².
If the CP pin input voltage is greater than CN pin, then the COUT is ²0².
Bit 3~2
DBC1, DBC0: De-bounce time selection, up to application signal
00: no de-bounce
01: de-bounce time= 1 system clock
10: de-bounce time= 4 system clock
11: de-bounce time= 16 system clock
Bit 1~0
CPCS1, CPCS0]: Comparator operating current selection for low power consumption
00: 200mA
01: 5mA
10: 1mA
11: not implemented
· CMP1C Register
Bit
7
6
5
4
3
2
1
0
Name
A0VRC
A1VRC
CPVRC
¾
R/W
R/W
R/W
R/W
¾
TMR0S
¾
CINTS1
CINTS0
R/W
¾
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7
A0VRC: OPA0 non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (A0P) pin
Bit6
A1VRC: OPA1 non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (A1P) pin
Bit5
CPVRC: Comparator non-inverting input connection control bit
0: connected to internal reference voltage only
1: connected to both internal reference voltage and external I/O (CP) pin
Note that the above setting of these three bits, which are A0VRC, A1VRC and CPVRC, is valid
when the non inverting input pins are selected to be connected to the internal reference voltage
by A0PS[2:0],A1PS[2:0] and CPS[2:0] control bits respectively.
Bit 4, 2
unimplemented, read as ²0²
Bit 3
TMR0S: signal input path selection for Timer 0 Event counter
0: from TC0 pin
1: from comparator output
Bit 1~0
CINTS1, CINTS0: comparator interrupt trigger type selection
00: falling edge
01: rising edge
10: both edge
11: reserved
Rev. 1.20
48
February 25, 2011
HT45R22E
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter or Time Base requires
microcontroller attention, their corresponding interrupt
will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to
their respective needs.
The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
The device contains a single external interrupt and multiple internal interrupts. The external interrupt is controlled by the action of the external interrupt pin, while
the internal interrupts are generated by the various functions such as Timer/Event Counters, OPAs, Comparator
and Time Base.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by using two registers, INTC0 and INTC1. By controlling the appropriate
enable bits in this registers each individual interrupt can
be enabled or disabled. Also when an interrupt occurs,
the corresponding request flag will be set by the
microcontroller. The global enable control bit if cleared
to zero will disable all interrupts.
When an interrupt request is generated, it takes 2 or 3
instruction cycle before the program jumps to the interrupt vector. If the device is in the Sleep or Idle Mode and
is woken up by an interrupt request, then it will take 3 cycles before the program jumps to the interrupt vector.
Main
Program
Interrupt Operation
Interrupt Request or
Interrupt Flag Set by Instruction
A Timer/Event Counter overflow, an active edge on the
external interrupt pin, a comparator output transition, an
OPA output falling edge or a Time Base event will all
generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI instruction,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Rev. 1.20
N
Enable Bit Set ?
Y
Main
Program
Automatically Disable Interrupt
Clear EMI & Request Flag
Wait for 2 ~ 3 Instruction Cycles
ISR Entry
RETI
(it will set EMI automatically)
Interrupt Flow
49
February 25, 2011
HT45R22E
A u to m a tic a lly D is a b le d w h e n in te r r u p t
e v e n t is s e r v ic e d E n a b le d m a n u a lly o r
a u to m a tic a lly w ith R E T I in s tr u c tio n
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
E M I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
E M I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
E M I
T im e B a s e
In te r r u p t R e q u e s t F la g T B F
E T B I
E M I
M u lti- fu n c tio n
In te r r u p t R e q u e s t F la g M F F
E M F I
E M I
C o m p a ra to r In te rru p t
R e q u e s t F la g C F
E C I
O P A 0 In te rru p t
R e q u e s t F la g A 0 F
E A 0 I
O P A 1 In te rru p t
R e q u e s t F la g A 1 F
E A 1 I
P r io r ity
H ig h
In te rru p t
P o llin g
L o w
Interrupt Scheme
Interrupt Priority
appears on the external INT line. The type of transition
that will trigger an external interrupt, whether high to
low, low to high or both is determined by the INTEG0
and INTEG1 bits, which are bits 6 and 7 respectively, in
the CTRL1 control register. These two bits can also disable the external interrupt function.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
Time Base Overflow
4
14H
Multi-function Interrupt
(Comparator, OPA0, OPA1)
5
18H
INTEG0
0
0
External interrupt disable
Edge Trigger Type
0
1
Rising edge Trigger
1
0
Falling edge Trigger
1
1
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin
PA3 and can only be configured as an external interrupt
pin if the corresponding external interrupt enable bit in
the INTC0 register has been set and the edge trigger
type has been selected using the CTRL1 register. The
pin must also be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and an active
transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location
04H, will take place. When the interrupt is serviced, the
external interrupt request flag, EIF, will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor
connections on this pin will remain valid even if the pin is
used as an external interrupt input.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF, is
set, a situation that will occur when an edge transition
Rev. 1.20
INTEG1
50
February 25, 2011
HT45R22E
· INTC0 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
T1F
T0F
EIF
ET1I
ET0I
EEI
EMI
R/W
¾
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
¾
0
0
0
0
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
T1F: Timer/Event Counter 1 interrupt request flag
0: inactive
1: active
Bit 5
T0F: Timer/Event Counter 0 interrupt request flag
0: inactive
1: active
Bit 4
EIF: External interrupt request flag
0: inactive
1: active
Bit 3
ET1I: Timer/Event Counter 1 interrupt enable
0: disable
1: enable
Bit 2
ET0I: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
Bit 1
EEI: External interrupt enable
0: disable
1: enable
Bit 0
EMI: Master interrupt global enable
0: disable
1: enable
· INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
¾
R/W
MFF
TBF
¾
¾
EMFI
ETBI
¾
¾
R/W
R/W
¾
¾
R/W
R/W
POR
¾
¾
0
0
¾
¾
0
0
¾
Bit 7
unimplemented, read as ²0²
Bit 6
MFF: Multi-function interrupt request flag
0: inactive
1: active
Bit 5
TBF: Time Base event interrupt request flag
0: inactive
1: active
Bit 4~3
unimplemented, read as ²0²
Bit 2
EMFI: Multi-function interrupt enable
0: disable
1: enable
Bit 1
ETBI: Time Base event interrupt enable
0: disable
1: enable
Bit 0
unimplemented, read as ²0²
Rev. 1.20
51
February 25, 2011
HT45R22E
· MFIC Register
Bit
7
6
5
4
3
2
1
0
Name
¾
A1F
A0F
CF
¾
EA1I
EA0I
ECI
R/W
¾
R/W
R/W
R/W
¾
R/W
R/W
R/W
POR
¾
0
0
0
¾
0
0
0
Bit 7
unimplemented, read as ²0²
Bit 6
A1F: OPA1 interrupt request flag
0: inactive
1: active
Bit 5
A0F: OPA0 interrupt request flag
0: inactive
1: active
Bit 4
CF: Comparator interrupt request flag
0: inactive
1: active
Bit 3
unimplemented, read as ²0²
Bit 2
EA1I: OPA1 interrupt enable
0: disable
1: enable
Bit 1
EA0I: OPA0 interrupt enable
0: disable
1: enable
Bit 0
ECI: Comparator interrupt enable
0: disable
1: enable
Timer/Event Counter Interrupt
Multi-function Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETnI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, TnF, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a
subroutine call to the relevant timer interrupt vector, will
take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, EMFI, must first be
set. An actual Multi-function interrupt will take place
when the Multi-function interrupt request flag, MFF, is
set, a situation that will occur when OPA0 or OPA1 output has a falling edge, or a Comparator output transition
occurs. When the interrupt is enabled, the stack is not
full and a Multi-function interrupt request occurs, a subroutine call to the Multi-function interrupt vector at location 18H, will take place. When the interrupt is serviced,
the Multi-function interrupt request flag, MFF, will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts. After the
Multi-function took place, the programmer can check
what the interrupt source was by interrogating the request flags, A0F, A1F or CF within the MFIC register.
Time Base Interrupt
For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit
ETBI, must first be set. An actual Time Base interrupt
will take place when the time base request flag TBF is
set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full
and a time base overflow occurs a subroutine call to
time base vector will take place. When the interrupt is
serviced, the time base interrupt flag, TBF will be automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Rev. 1.20
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
52
February 25, 2011
HT45R22E
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Idle/Sleep Mode.
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory device during the programming process. During the development process, these options are selected using the HT-IDE
software development tools. As these options are programmed into the device using the hardware programming tools,
once they are selected they can not be changed later by the application software. All options must be defined for proper
system function, the details of which are shown in the table.
No.
Options
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: LXT, LIRC or fSYS/4
Note: LXT oscillator must be selected by OSC configuration option if WDT clock source is from LXT.
3
CLRWDT instructions: 1 or 2 instructions
4
System oscillator configuration: HXT, HIRC, ERC, HIRC + LXT
5
LVR function: enable or disable
6
LVR voltage: 2.10V
7
RES or PA7 pin function
8
SST: 1024 or 2 clocks (determine tSST for HIRC/ERC)
9
Internal RC: 4095kHz
Rev. 1.20
53
February 25, 2011
HT45R22E
Application Circuits
V
D D
0 .0 1 m F * *
V D D
P A 0 /P F D /A 1 N
0 .1 m F
R e s e t
C ir c u it
1 0 k W ~
1 0 0 k W
1 N 4 1 4 8 *
0 .1 ~ 1 m F
3 0 0 W *
R E S
P A 2 /T C 0 /A 0 X
P A 3 /IN T /A 0 N
P A 4 /T C 1 /A 0 P
P B 0 ~ P B 7
V S S
O S C 1
O S C
C ir c u it
P A 1 /P F D /A 1 X
P C 0 /C
P C 1 /C
P C 2 ~ P C
P C 6 /A 1
P C 7 /C
N
X
5
P
P
O S C 2
S e e O s c illa to r
S e c tio n
Note:
²*² It is recommended that this component is added for added ESD protection.
²**² It is recommended that this component is added in environments where power line noise is significant.
Rev. 1.20
54
February 25, 2011
HT45R22E
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 4MHz system
oscillator, most instructions would be implemented
within 1ms and branch or call instructions would be implemented within 2ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter Idle/Sleep Mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.20
66
February 25, 2011
HT45R22E
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.20
67
February 25, 2011
HT45R22E
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
a
F
· MS-013
Symbol
A
Min.
Nom.
Max.
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.496
¾
0.512
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.20
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
12.60
¾
13.00
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
68
February 25, 2011
HT45R22E
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1
1 2
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Nom.
Max.
A
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.598
¾
0.613
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
A
Rev. 1.20
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
15.19
¾
15.57
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
69
February 25, 2011
HT45R22E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W, SOP 24W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.20
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
70
February 25, 2011
HT45R22E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
B 0
C
D 1
P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 20W
Symbol
Description
Dimensions in mm
24.0
+0.3/-0.1
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
1.50
+0.1/-0.0
+0.25/-0.00
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
21.3±0.1
SOP 24W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55
+0.10/-0.00
D1
Cavity Hole Diameter
1.50
+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
11.5±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
Rev. 1.20
71
February 25, 2011
HT45R22E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may presenFebruary 26, 2010t a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date
information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
72
February 25, 2011