Data Sheet

HT48R0AA-1
Cost-Effective I/O Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0013E HT48 & HT46 LCM Interface Design
HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
HA0049E Read and Write Control of the HT1380
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Buzzer driving pair and PFD supported
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· HALT function and wake-up feature reduce power
consumption
· 23 bidirectional I/O lines
· Up to 0.5ms instruction cycle with 8MHz system clock
· An interrupt input shared with an I/O line
at VDD=5V
· 8-bit programmable timer/event counter with
· All instructions in one or two machine cycles
overflow interrupt and 8-stage prescaler
· 15-bit table read instruction
· 8-bit programmable timer/event counter and
· 4-level subroutine nesting
overflow interrupt
· Bit manipulation instruction
· External crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· Low voltage reset function
· 4096´15 Program memory ROM
· 24/28-pin SKDIP/SOP package
· 128´8 Data memory RAM
General Description
HALT and wake-up functions, Watchdog Timer, buzzer
driver, as well as low cost, enhance the versatility of
these devices to suit a wide range of application
possibilities such as industrial control, consumer products, subsystem controllers, etc.
The HT48R0AA-1 is an 8-bit high performance, RISC
architecture microcontroller devices specifically designed for cost-effective multiple I/O control product applications.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator configuration options,
Rev. 1.11
1
December 30, 2008
HT48R0AA-1
Block Diagram
T M R 1 C
P D 0 /IN T
M
T M R 1
U
fS
X
In te rru p t
C ir c u it
S T A C K
P ro g ra m
M e m o ry
IN T C
/4
T M R 1
M
T M R 0
P ro g ra m
C o u n te r
Y S
U
P r e s c a le r
fS
Y S
T M R 0
X
T M R 0 C
E N /D IS
In s tr u c tio n
R e g is te r
M
M P
U
W D T S
X
D a ta
M e m o ry
W D T P r e s c a le r
P A C
M U X
In s tr u c tio n
D e c o d e r
P B C
O S C 2
O S
R
V
V
P D C
X
P B 0 /B Z
P B 1 /B Z
P B 2 ~ P B 7
P O R T C
P C 0 /T M R 0
P C 1 ~ P C 4
P C 5 /T M R 1
P C
A C C
C 1
E S
D D
S S
fS
Y S
/4
W D T O S C
P O R T B
P B
P C C
U
P A 0 ~ P A 7
B Z /B Z
S T A T U S
S h ifte r
T im in g
G e n e ra to r
P O R T A
P A
A L U
M
W D T
P O R T D
P D 0 /IN T
P D
Pin Assignment
1
2 8
P B 6
2
2 7
P B 7
P B 5
1
2 4
P B 6
P A 3
3
2 6
P A 4
P B 4
2
2 3
P B 7
P A 2
4
2 5
P A 5
P A 3
3
2 2
P A 4
P A 1
5
2 4
P A 6
P A 2
4
2 1
P A 5
P A 0
6
2 3
P A 7
P A 1
5
2 0
P A 6
P B 3
7
2 2
O S C 2
P A 0
6
1 9
P A 7
P B 2
8
2 1
O S C 1
P B 3
7
1 8
O S C 2
P B 1 /B Z
9
2 0
V D D
P B 2
8
1 7
O S C 1
P B 0 /B Z
1 0
1 9
R E S
P B 1 /B Z
9
1 6
V D D
V S S
1 1
1 8
P C 5 /T M R 1
P B 0 /B Z
1 0
1 5
R E S
P D 0 /IN T
1 2
1 7
P C 4
V S S
1 1
1 4
P C 5 /T M R 1
P C 0 /T M R 0
1 3
1 6
P C 3
P D 0 /IN T
1 2
1 3
P C 0 /T M R 0
P C 1
1 4
1 5
P C 2
H T 4 8 R 0 A A -1
2 4 S K D IP -A /S O P -A
Rev. 1.11
P B 5
P B 4
H T 4 8 R 0 A A -1
2 8 S K D IP -A /S O P -A
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December 30, 2008
HT48R0AA-1
Pin Description
Pin Name
PA0~PA7
PB0/BZ
PB1/BZ
PB2~PB7
PC0/TMR0
PC1~PC4
PC5/TMR1
I/O
Configuration
Options
Description
I/O
Pull-high
Wake-up
Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by
configuration option. Software instructions determined the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by a pull-high configuration option).
Pull-high
I/O or BZ/BZ
Bidirectional 8-bit I/O port. Software instructions determined the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by a pull-high configuration option). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with an 8 bits timer/event
counter).
Pull-high
Bidirectional 6-bit I/O lines. Software instructions determine the CMOS output
or Schmitt trigger input with a pull-high resistor (determined by a pull-high configuration option). The Timer/Event Counter 0 and the Timer/Event Counter 1
counter input (Schmitt trigger input without pull-high resistor) are pin-shared
with the PC0 and PC5, respectively.
Bi-directional I/O line. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by a pull-high configuration option). the external interrupt input INT, is pin-shared with PD0 and is activated on a high to low transition.
I/O
I/O
PD0/INT
I/O
Pull-high
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
RES
I
¾
Schmitt trigger reset input. Active low.
OSC1
OSC2
I
O
Crystal
or RC
Note:
OSC1, OSC2 are connected to an RC network or Crystal (determined by configuration options) for the internal system clock. In the case of RC operation,
OSC2 is the output terminal for 1/4 system clock.
The pull-high resistors of each I/O port (PA, PB, PC, PD) are controlled by configuration options.
Each pin on PA can be programmed through a configuration option to have a wake-up function.
Pins PC1~PC4 exist but are not bonded out on the 24-pin package.
Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.11
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December 30, 2008
HT48R0AA-1
D.C. Characteristics
Symbol
VDD
IDD1
IDD2
Parameter
Operating Voltage
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
0.6
1.5
mA
¾
2
4
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
Operating Current
(Crystal OSC)
3V
Operating Current
(RC OSC)
3V
No load, fSYS=4MHz
5V
No load, fSYS=4MHz
5V
IDD3
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Standby Current
(WDT Enabled)
3V
Standby Current
(WDT Disabled)
3V
VIL1
Input Low Voltage for I/O Ports,
TMR0, TMR1 and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR0, TMR1 and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
ISTB2
5V
No load, fSYS=8MHz
No load, system HALT
5V
No load, system HALT
5V
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
VLVR
Rev. 1.11
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
¾
LVR enabled
2.7
3.0
3.3
V
Pull-high Resistance
Low Voltage Reset Voltage
4
December 30, 2008
HT48R0AA-1
A.C. Characteristics
Symbol
fSYS1
fSYS2
fTIMER
Parameter
System Clock (Crystal OSC)
System Clock (RC OSC)
Timer I/P Frequency
(TMR0/TMR1)
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
11
23
46
ms
8
17
33
ms
¾
1024
¾
tSYS*
1
¾
¾
ms
¾
1024
¾
tSYS*
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V
tWDT2
Watchdog Time-out Period
(System Clock)
¾
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Reset Time
¾
¾
0.25
1
2
ms
Without WDT prescaler
5V
Without WDT prescaler
¾
Wake-up from HALT
Note: *tSYS=1/fSYS1, 1/fSYS2
Rev. 1.11
5
December 30, 2008
HT48R0AA-1
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupts, the PC manipulates
the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme ensures that each instruction is effectively executed in a cycle. If an instruction changes the contents of the program counter, such
as subroutine calls or jumps, in which case, two cycles
are required to complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
*11
*10
*9
*8
@7
@3
@2
@1
@0
Skip
Program Counter+2
Loading PCL
@6
@5
@4
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.11
@[email protected]: PCL bits
6
December 30, 2008
HT48R0AA-1
· Location 00CH
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
· Table location
Certain locations in the program memory are reserved
for special usage:
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, one page=256 words) and ²TABRDL
[m]² (the last page) transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is
well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining
1-bit words are read as ²0². The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
· Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
· Location 008H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a
Timer/Event Counter 0 overflow, and if the interrupt is
enabled and the stack is not full, the program begins execution at location 008H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r 1
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@[email protected]: Table pointer bits
Rev. 1.11
7
December 30, 2008
HT48R0AA-1
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the Stack Pointer will point to
the top of the stack.
0 0 H
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
0 2 H
0 3 H
0 4 H
0 5 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 4 return addresses are stored).
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
S p e c ia l P u r p o s e
D a ta M e m o ry
0 F H
Data Memory - RAM
The data memory has a capacity of 149´8 bits and is
divided into two functional groups: special function registers and general purpose data memory (128´8). Most
are read/write, but some are read only. The unused
space before the 20H is reserved for future expanded
usage and reading these locations will return the result
²00H². The general purpose data memory, addressed
from 20H to 9FH, is used for data and control information under instruction commands.
1 0 H
T M R 1
1 1 H
T M R 1 C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
1 A H
P D C
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 2 8 B y te s )
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP).
: U n u s e d
R e a d a s "0 0 "
9 F H
RAM Mapping
Arithmetic and Logic Unit - ALU
Indirect Addressing Register
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation to
[00H] access the data memory pointed to by MP. Reading location 00H itself indirectly will return the result
00H. Writing indirectly results in no operation.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
The memory pointer register (MP) is an 8-bit register
used to access the RAM by combining corresponding
indirect addressing register.
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
Accumulator
Status Register - STATUS
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Rev. 1.11
The ALU not only saves the results of a data operation but
also changes the status register.
8
December 30, 2008
HT48R0AA-1
Bit No.
Labels
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition, operations related to the status register may
give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the ²CLR WDT² or
²HALT² instruction. The PDF flag can be affected
only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.
External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF;
bit 4 of the INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
The internal Timer/Event Counter 0 interrupt is initialized
by setting the Timer/Event Counter 0 interrupt request
flag (T0F; bit 5 of the INTC), caused by a timer 0 overflow.
When the interrupt is enabled, the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to enable or disable the interrupt request flags.
The internal timer/event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (;bit 6 of the INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from
becoming full.
Rev. 1.11
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
9
December 30, 2008
HT48R0AA-1
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EEI
Controls the external interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0= disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC (0BH) Register
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip
itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate
oscillator frequency is desired.
Priority Vector
External Interrupt
1
04H
Timer/Event Counter 0 Overflow
2
08H
Timer/Event Counter 1 Overflow
3
0CH
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors in
OSC1 and OSC2 are required.
Once the interrupt request flags (T0F, T1F, EIF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction. It is
recommended that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack
is left and enabling the interrupt is not well controlled, the
original control sequence will be damaged once the
²CALL² operates in the interrupt subroutine.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by configuration options to conserve power.
Watchdog Timer - WDT
Oscillator Configuration
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), determines the configuration
options. This timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by configuration options. If the
Watchdog Timer is disabled, all the executions related
to the WDT result in no operation.
There are 2 oscillator circuits in the microcontroller.
V
O S C 1
D D
O S C 1
4 7 0 p F
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C
O s c illa to r
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 17ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s at 5V
System Oscillator
All of them are designed for system clocks, namely the
external RC oscillator and the external Crystal oscillator,
which are determined by configuration options. No matter
what oscillator type is selected, the signal provides the
system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
Rev. 1.11
10
December 30, 2008
HT48R0AA-1
S y s te m
C lo c k /4
W D T P r e s c a le r
O p tio n
S e le c t
8 - b it C o u n te r
7 - b it C o u n te r
W D T
O S C
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and operates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user's defined flags, which can be used to
indicate some specified status.
· The system oscillator will be turned off but the WDT
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
· All of the I/O ports maintain their original status.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer; the others
remain in their original status.
WDTS (09H) Register
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by configuration options. Awakening from an I/O
port stimulus, the program will resume execution of the
next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
The WDT overflow under normal operation will initialize a
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the program counter and stack pointer are reset to zero.
To clear the WDT contents (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the configuration option - ²CLR WDT times
selection configuration option². If the ²CLR WDT² is selected (i.e. CLRWDT times is equal to one), any execution of the ²CLR WDT² instruction will clear the WDT. In
the case that ²CLR WDT1² and ²CLR WDT2² are chosen
(i.e. CLRWDT times is equal to two), these two instructions must be executed to clear the WDT; otherwise, the
WDT may reset the chip as a result of time-out.
Power Down Operation - HALT
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
Rev. 1.11
11
December 30, 2008
HT48R0AA-1
Reset
The functional unit chip reset status are shown below.
There are three ways in which a reset can occur:
Program Counter
000H
Interrupt
Disable
· WDT time-out reset during normal operation
Prescaler
Clear
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
Stack Pointer
Points to the top of the stack
· RES reset during normal operation
· RES reset during HALT
TO
PDF
V
V
D D
D D
0 .0 1 m F
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up from HALT mode
1
u
WDT time-out during normal operation
1
1
WDT wake-up from HALT mode
1 0 0 k W
1 0 0 k W
R E S
R E S
0 .1 m F
1 0 k W
B a s ic
R e s e t
C ir c u it
H i-n o is e
R e s e t
C ir c u it
0 .1 m F
Reset Circuit
Note: ²u² stands for ²unchanged²
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
V D D
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
R E S
tS
S T
S S T T im e - o u t
An extra configuration option load time delay is added
during system reset (power-up, WDT time-out at normal
mode or RES reset).
C h ip
R e s e t
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
R E S
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
R e s e t
Reset Configuration
Rev. 1.11
12
December 30, 2008
HT48R0AA-1
The states of the registers is summarized in the table.
Register
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
TBLP
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PCC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PD
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Timer/Event Counter
TMR0/TMR1 location; writing to TMR0/TMR1 makes
the starting value be placed in the Timer/Event Counter
0/1 preload register and reading TMR0/TMR1 retrieves
the contents of the Timer/Event Counter 0/1. The
TMR0C/TMR1C is a timer/event counter control register, which defines some configuration options.
Two timer/event counters (TMR0, TMR1) are implemented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may come from an external source or from the
system clock. The Timer/Event Counter 1 also contains
an 8-bit programmable count-up counter and the clock
may come from an external source or from the system
clock divided by 4.
The TMR0C is the Timer/Event Counter 0 control register, which defines the operating mode, counting enable
or disable and active edge.
Using an external clock input allows the user to count external events, measure time internals or pulse widths, or
generate an accurate time base. While using the internal
clock allows the user to generate an accurate time base.
The T0M0, T0M1, T1M0, T1M1 bits define the operating
mode. The event count mode is used to count external
events, which means the clock source comes from an
external (TMR0/TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
fINT clock/instruction clock (Timer0/Timer1). The pulse width
measurement mode can be used to count the high or low
level duration of the external signal (TMR0/TMR1). The
counting is based on the fINT clock/instruction clock
(Timer0/Timer1).
The Timer/Event Counter 0 can generate PFD signal by
using external or internal clock and the PFD frequency
is determine by the equation fINT/[2´(256-N)].
There are 2 registers related to the Timer/Event Counter
0/1; TMR0/TMR1 ([0DH]/[10H]), TMR0C/TMR1C
([0EH]/[11H]). Two physical registers are mapped to
Rev. 1.11
13
December 30, 2008
HT48R0AA-1
TMR0/TMR1 has received a transient from low to high
(or high to low if the T0E/T1E bits is ²0²) it will start
counting until the TMR0/TMR1 returns to the original
level and resets the T0ON/T1ON. The measured result
will remain in the Timer/Event Counter 0/1 even if the
activated transient occurs again. In other words, only
one cycle measurement can be done. Until setting the
T0ON/T1ON, the cycle measurement will function again
as long as it receives further transient pulse. Note that,
in this operating mode, the Timer/Event Counter 0/1
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contents in the Timer/Event Counter 0/1 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0/1 preload register and generates
the interrupt request flag (T0F/T1F; bit 5/6 of the INTC) at
the same time.
In the pulse width measurement mode with the
T0ON/T1ON and T0E/T1E bits equal to one, once the
Bit No.
0~2
Label
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: fINT=fSYS/2
001: fINT=fSYS/4
010: fINT=fSYS/8
T0PSC0~
011: fINT=fSYS/16
T0PSC2
100: fINT=fSYS/32
101: fINT=fSYS/64
110: fINT=fSYS/128
111: fINT=fSYS/256
3
T0E
4
T0ON
5
¾
6
7
Function
T0M0
T0M1
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable or disable timer 0 counting (0=disable; 1=enable)
Unused bit, read as ²0²
Defines the operating mode (T0M1, T0M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH) Register
Bit No.
Label
0~2
¾
Function
Unused bit, read as ²0²
3
T1E
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
T1ON
Enable or disable timer 1 counting (0=disabled; 1=enabled)
5
¾
6
7
T1M0
T1M1
Unused bit, read as²0²
Defines the operating mode (T1M1, T1M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C (11H) Register
Rev. 1.11
14
December 30, 2008
HT48R0AA-1
Input/Output Ports
starts counting not according to the logic level but according to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter 0/1 preload register and issues the
interrupt request just like the other two modes. To enable the counting operation, the timer ON bit
(T0ON/T1ON; bit 4 of TMR0C/TMR1C) should be set to
1. In the pulse width measurement mode, the
T0ON/T1ON will be cleared automatically after the measurement cycle is completed. But in the other two
modes the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
There are 23 bidirectional input/output lines in the
microcontroller, labeled from PA to PD, which are mapped
to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H or
18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically under software control. To
function as an input, the corresponding latch of the control register must write a ²1². The input source also depends on the control register. If the control register bit is
²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the
internal bus. The latter is possible in the
²read-modify-write² instruction.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload
register will also reload that data to the Timer/Event
Counter 0/1. But if the Timer/Event Counter 0/1 is turned
on, data written to it will only be kept in the Timer/Event
Counter 0/1 preload register. The Timer/Event Counter
0/1 will still operate until overflow occurs (a Timer/Event
Counter 0/1 reloading will occur at the same time). When
the Timer/Event Counter 0/1 (reading TMR0/TMR1) is
read, the clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this must be taken
into consideration by the programmer.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high configuration options). Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² (m=12H, 14H, 16H or 18H) instructions.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of the
Timer/Event Counter 0. The definitions are as shown.
The overflow signal of the Timer/Event Counter 0 can be
used to generate PFD signals for buzzer driving.
fS
Y S
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
T 0 P S C 2 ~ T 0 P S C 0
D a ta B u s
T
T 0 M 1
T 0 M 0
T M R 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T 0 E
T 0 M 1
T 0 M 0
T 0 O N
T im e r /E v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
1 /2
B Z
B Z
Timer/Event Counter 0
D a ta B u s
f S Y S /4
T 1 M 1
T 1 M 0
T M R 1
T im e r /E v e n t C o u n te r 1
P r e lo a d R e g is te r
R e lo a d
T 1 E
T 1 M 1
T 1 M 0
T 1 O N
T im e r /E v e n t
C o u n te r 1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 1
Rev. 1.11
15
December 30, 2008
HT48R0AA-1
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
The I/O functions of PB0/PB1 are shown below.
Each line of port A has a capability of waking-up the device. The highest 2 bits of port C and the highest 7-bit of
port D are not physically implemented; on reading them a
²0² is returned whereas writing then results in
no-operation.
PB0 I/O
I
I
PB1 I/O
I
O O O
PB0/PB1 Mode
x
C B B C B B C B B
PB0 Data
x
x
0
1
D
0
1 D0 0
1
PB1 Data
x
D
x
x
x
x
x D1 x
x
PB0 Pad Status I
I
I
I
D
0
B D0 0
B
PB1 Pad Status I
D
0
B
I
I
I D1 0
B
C o n tr o l B it
Q
D
( P B 0 , P B 1 O n ly )
S
O O O
D D
P A
P B
P C
P D
D a ta B it
Q
D
S
0 ~ P A 7
0 ~ P B 7
0 ~ P C 5
0
Q
M
P B 0
B Z /B Z
M
R e a d D a ta R e g is te r
I
Q
C K
C K
I
P u ll- h ig h
O p tio n
C h ip R e s e t
W r ite D a ta R e g is te r
I
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
R e a d C o n tr o l R e g is te r
O O O O O O
²I² input, ²O² output, ²D, D0, D1² data,
²B² buzzer configuration option, BZ or BZ, ²x²
don¢t care
²C² CMOS output
The external input pins TMR0 and TMR1 are pin-shared
with pin PC0 and PC5 respectively, and the external interrupt pin INT is pin-shared with the I/O pin PD0.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ configuration option is selected, the output signal in output mode of PB0/PB1 will
be the PFD signal generated by the Timer/Event Counter 0 overflow signal. The input mode always remain in
its original functions. Once the BZ/BZ configuration option is selected, the buzzer output signals are controlled
by the PB0 data register only.
W r ite C o n tr o l R e g is te r
I
Note:
There is a pull-high configuration option available for all
I/O lines (bit configuration option). Once the pull-high
configuration option of an I/O line is selected, the I/O line
have pull-high resistor. Otherwise, the pull-high resistor
is absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
D a ta B u s
I
U
U
X
B Z E N
( P B 0 , P B 1 o n ly )
X
S y s te m W a k e -u p
( P A o n ly )
O P 0 ~ O P 7
T M R 0 fo r P C 0 o n ly
T M R 1 fo r P C 5 o n ly
IN T fo r P D 0 o n ly
Input/Output Ports
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Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device drops to within a range of
0.9V~VLVR, such as when changing a battery, the LVR
will automatically reset the device internally.
V D D
5 .5 V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .0 V
· The low voltage (0.9V~VLVR) has to remain in its origi-
2 .2 V
nal state for longer than 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and will
not perform a reset function.
0 .9 V
· The LVR uses an ²OR² function with the external RES
Note:
signal to perform a chip reset.
V
V
VOPR is the voltage range for proper chip operation at 4MHz system clock.
D D
5 .5 V
V
L V R D e te c t V o lta g e
L V R
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before starting the normal operation.
*2: Since low voltage state has to be maintained its original state for longer than 1ms, therefore after 1ms delay,
the device enters the reset mode.
Configuration Options
The following table shows all kinds of configuration options in the microcontroller. All of the configuration options must
be defined to ensure proper system functioning.
Items
Configuration Options
1
WDT clock source: WDT oscillator or fSYS/4
2
WDT function: enable or disable
3
CLRWDT instructions: 1 or 2 instructions
4
PA bit wake-up enable or disable
5
PA, PB, PC, PD pull-high enable or disable (By port)
6
BZ/BZ enable or disable
7
LVR enable or disable
8
System oscillator: RC or crystal
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Application Circuits
V
D D
P A 0 ~ P A 7
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S
V
P B 2 ~ P B 7
P C 1 ~ P C 4
P C 5 /T M R 1
V S S
O S C
4 7 0 p F
P D 0 /IN T
C 1
O S C 1
fS
Y S
/4
O S C 1
O S C 2
C 2
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
R 1
H T 4 8 R 0 A A -1
Note:
D D
R
P C 0 /T M R 0
0 .1 m F
O S C
C ir c u it
P B 0 /B Z
P B 1 /B Z
O S C 2
O S C
C r y s ta l/R e s o n a to r
S y s te m O s c illa to r
F o r R 1 , C 1 , C 2 s e e n o te
C ir c u it
1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.11
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.11
27
December 30, 2008
HT48R0AA-1
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.11
28
December 30, 2008
HT48R0AA-1
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.11
29
December 30, 2008
HT48R0AA-1
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.11
30
December 30, 2008
HT48R0AA-1
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.11
31
December 30, 2008
HT48R0AA-1
Package Information
24-pin SKDIP (300mil) Outline Dimensions
A
A
1 3
2 4
B
1 3
2 4
B
1 2
1
1 2
1
H
H
C
C
D
D
E
F
I
G
E
F
I
G
Fig2. 1/2 Lead Packages
Fig1. Full Lead Packages
· MS-001d (see fig1)
Symbol
A
Dimensions in mil
Min.
Nom.
Max.
1230
¾
1280
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
· MS-001d (see fig2)
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
1160
¾
1195
B
240
¾
280
C
115
¾
195
D
115
¾
150
E
14
¾
22
F
45
¾
70
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
32
August 8, 2008
HT48R0AA-1
· MO-095a (see fig2)
Symbol
A
Rev. 1.11
Dimensions in mil
Min.
Nom.
Max.
1145
¾
1185
B
275
¾
295
C
120
¾
150
D
110
¾
150
E
14
¾
22
F
45
¾
60
G
¾
100
¾
H
300
¾
325
I
¾
¾
430
33
December 30, 2008
HT48R0AA-1
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.11
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
598
¾
613
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
34
December 30, 2008
HT48R0AA-1
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
A
Rev. 1.11
F
I
G
Dimensions in mil
Min.
Nom.
Max.
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
¾
¾
375
35
December 30, 2008
HT48R0AA-1
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.11
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
697
¾
713
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
36
December 30, 2008
HT48R0AA-1
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 24W, SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.11
2.0±0.5
24.8+0.3/-0.2
30.2±0.2
37
December 30, 2008
HT48R0AA-1
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 24W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55+0.10/-0.00
D1
Cavity Hole Diameter
1.50+0.25/-0.00
24.0±0.3
11.5±0.1
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
21.3±0.1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
Rev. 1.11
2.0±0.1
38
December 30, 2008
HT48R0AA-1
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.11
39
December 30, 2008