HT45F4MA HT45FH4MA HT45FH4MA-1

Power Bank 8-Bit Flash MCU
HT45F4MA
HT45FH4MA
HT45FH4MA-1
Revision: V1.10
Date: ���������������
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Table of Contents
Features............................................................................................................. 6
CPU Features.......................................................................................................................... 6
Peripheral Features.................................................................................................................. 6
General Description ......................................................................................... 7
Selection Table.................................................................................................. 8
Block Diagram................................................................................................... 8
Pin Assignment................................................................................................. 9
Pin Description............................................................................................... 10
HT45F4MA............................................................................................................................. 10
HT45FH4MA/HT45FH4MA-1..................................................................................................11
Internal Connection Description............................................................................................. 12
Level Shift Input/Output Relationship and Reset Condition................................................... 12
Absolute Maximum Ratings........................................................................... 12
D.C. Characteristics........................................................................................ 13
A.C. Characteristics........................................................................................ 14
LVD & LVR Electrical Characteristics........................................................... 15
A/D Converter Electrical Characteristics...................................................... 15
Over Current Circuit Electrical Characteristics........................................... 16
Over Voltage Circuit Electrical Characteristics........................................... 16
LDO Regulator Electrical Characteristics.................................................... 17
Level Converter Electrical Characteristics................................................... 17
Power on Reset Electrical Characteristics................................................... 18
System Architecture....................................................................................... 18
Clocking and Pipelining.......................................................................................................... 18
Program Counter.................................................................................................................... 19
Stack...................................................................................................................................... 20
Arithmetic and Logic Unit – ALU............................................................................................ 20
Flash Program Memory.................................................................................. 21
Structure................................................................................................................................. 21
Special Vectors...................................................................................................................... 21
Look-up Table......................................................................................................................... 22
Table Program Example......................................................................................................... 23
In Circuit Programming.......................................................................................................... 24
On-Chip Debug Support – OCDS.......................................................................................... 25
RAM Data Memory.......................................................................................... 25
Structure................................................................................................................................. 25
Rev. 1.10
2
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Special Function Register Description......................................................... 27
Indirect Addressing Registers – IAR0, IAR1.......................................................................... 27
Memory Pointers – MP0, MP1............................................................................................... 27
Bank Pointer – BP.................................................................................................................. 28
Accumulator – ACC................................................................................................................ 28
Program Counter Low Register – PCL................................................................................... 28
Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 28
Status Register – STATUS..................................................................................................... 29
EEPROM Data Memory................................................................................... 31
EEPROM Data Memory Structure......................................................................................... 31
EEPROM Registers............................................................................................................... 31
Reading Data from the EEPROM ......................................................................................... 33
Writing Data to the EEPROM................................................................................................. 33
Write Protection...................................................................................................................... 33
EEPROM Interrupt................................................................................................................. 33
Programming Considerations................................................................................................. 34
Oscillator......................................................................................................... 35
Oscillator Overview................................................................................................................ 35
System Clock Configurations................................................................................................. 35
Internal RC Oscillator – HIRC................................................................................................ 36
Internal 32kHz Oscillator – LIRC............................................................................................ 36
Operating Modes and System Clocks.......................................................... 36
System Clocks....................................................................................................................... 36
System Operation Modes....................................................................................................... 37
Control Register..................................................................................................................... 39
Operating Mode Switching..................................................................................................... 41
Standby Current Considerations............................................................................................ 45
Wake-up................................................................................................................................. 45
Watchdog Timer.............................................................................................. 46
Watchdog Timer Clock Source............................................................................................... 46
Watchdog Timer Control Register.......................................................................................... 46
Watchdog Timer Operation.................................................................................................... 47
Reset and Initialisation................................................................................... 48
Reset Functions..................................................................................................................... 48
Reset Initial Conditions.......................................................................................................... 51
Input/Output Ports.......................................................................................... 54
Pull-high Resistors................................................................................................................. 54
Port A Wake-up...................................................................................................................... 55
I/O Port Control Registers...................................................................................................... 55
I/O Pin Structures................................................................................................................... 56
Programming Considerations................................................................................................. 57
Rev. 1.10
3
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Timer Modules – TM....................................................................................... 57
Introduction............................................................................................................................ 57
TM Operation......................................................................................................................... 58
TM Clock Source.................................................................................................................... 58
TM Interrupts.......................................................................................................................... 58
TM External Pins.................................................................................................................... 59
TM Input/Output Pin Control Register.................................................................................... 60
Programming Considerations................................................................................................. 62
Standard Type TM – STM............................................................................... 63
Standard TM Operation.......................................................................................................... 63
Standard Type TM Register Description................................................................................ 63
Standard Type TM Operating Modes..................................................................................... 68
Periodic Type TM – PTM................................................................................. 78
Periodic TM Operation........................................................................................................... 78
Periodic Type TM Register Description.................................................................................. 79
Periodic Type TM Operation Modes....................................................................................... 84
Analog to Digital Converter........................................................................... 93
A/D Overview......................................................................................................................... 93
A/D Converter Register Description....................................................................................... 93
A/D Converter Data Registers – ADRL, ADRH...................................................................... 94
A/D Converter Control Registers – ADCR0, ADCR1, ACERL................................................ 94
A/D Operation........................................................................................................................ 98
A/D Input Pins........................................................................................................................ 99
Summary of A/D Conversion Steps...................................................................................... 100
Programming Considerations............................................................................................... 101
A/D Transfer Function.......................................................................................................... 101
A/D Programming Example.................................................................................................. 102
Complementary PWM Output...................................................................... 104
Over Current and Voltage Protection ......................................................... 105
OCP/OVP Register.............................................................................................................. 106
OCP Operational Amplifier Offset Cancellation Function......................................................111
OCP Comparator Offset Cancellation Function....................................................................112
OVP Comparator Offset Cancellation Function....................................................................112
Rev. 1.10
4
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Interrupts........................................................................................................113
Interrupt Registers.................................................................................................................113
Interrupt Register Contents...................................................................................................113
Interrupt Operation................................................................................................................118
External Interrupt.................................................................................................................. 120
OVP Interrupt....................................................................................................................... 120
OCP Interrupt....................................................................................................................... 120
Multi-function Interrupt......................................................................................................... 121
A/D Converter Interrupt........................................................................................................ 121
Time Base Interrupts............................................................................................................ 121
EEPROM Interrupt............................................................................................................... 123
LVD Interrupt........................................................................................................................ 123
TM Interrupts........................................................................................................................ 123
Interrupt Wake-up Function................................................................................................. 124
Programming Considerations............................................................................................... 124
Low Voltage Detector – LVD........................................................................ 125
LVD Register........................................................................................................................ 125
LVD Operation...................................................................................................................... 126
Application Circuits...................................................................................... 127
Instruction Set............................................................................................... 129
Introduction.......................................................................................................................... 129
Instruction Timing................................................................................................................. 129
Moving and Transferring Data.............................................................................................. 129
Arithmetic Operations........................................................................................................... 129
Logical and Rotate Operations............................................................................................. 130
Branches and Control Transfer............................................................................................ 130
Bit Operations...................................................................................................................... 130
Table Read Operations........................................................................................................ 130
Other Operations.................................................................................................................. 130
Instruction Set Summary............................................................................. 131
Table Conventions................................................................................................................ 131
Instruction Definition.................................................................................... 133
Package Information.................................................................................... 142
16-pin NSOP (150mil) Outline Dimensions.......................................................................... 143
20-pin SSOP (150mil) Outline Dimensions.......................................................................... 144
Rev. 1.10
5
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Features
CPU Features
• Operating Voltage
♦♦
fSYS = 7.5MHz: 2.55V~5.5V
♦♦
fSYS = 15MHz: 4.5V~5.5V
• Up to 0.27μs instruction cycle with 15MHz system clock at VDD= 5V
• Power down and wake-up functions to reduce power consumption
• Oscillators
♦♦
Internal RC -- HIRC
♦♦
Internal 32kHz -- LIRC
• Fully intergrated internal 30MHz oscillator requires no external components
• Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
• All instructions executed in one or two instruction cycles
• Table read instructions
• 63 powerful instructions
• 4-level subroutine nesting
• Bit manipulation instruction
Peripheral Features
• Flash Program Memory: 2K×16
• RAM Data Memory: 128×8
• EEPROM Memory: 64×8
• Watchdog Timer function
• Up to 16 bidirectional I/O lines
• Two pin-shared external interrupts
• Multiple Timer Module for time measure, input capture, compare match output, PWM output
function or single pulse output function
• Over current protection (OCP) with interrupt
• Over voltage protection (OVP) with interrupt
• Dual Time-Base functions for generation of fixed time interrupt signals
• 8-channel 12-bit resolution A/D converter
• Low voltage reset function ([email protected])
• Low voltage detect function
• One integrated LDO: 5V output for HT45FH4MA/HT45FH4MA-1 only
• 2 level shift output pins for HT45FH4MA/HT45FH4MA-1 only
• 16-pin NSOP, 20-pin SSOP package
Rev. 1.10
6
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Features
Device
HT45FH4MA
AX/BX pin at Reset
—
HT45FH4MA-1
Output high
AX/BX pin at Reset
Output low
CX/DX pin at Reset
Output low
Output low
—
Internally Connected
PB5/OUTL → A, PB4/OUTH → C
PB3/TP1_0 → ENBF
PB5/OUTL → A, PB4/OUTH → C
PB3/TP1_0 → Floating
Level Shift
AX/BX is inversion output of input A
CX/DX is inversion output of input C
AX/BX is non-inversion output of input A.
CX/DX is inversion output of input C.
Level Shift Enable Control – ENBF Controlled by PB3/TP1_0
Always enabled
Peripheral Features Comparison Table
General Description
The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller.
Offering users the convenience of Flash Memory multi-programming features, this device also
includes a wide range of functions and features. Other memory includes an area of RAM Data
Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial
numbers, calibration data etc.
Analog features include a multi-channel 12-bit A/D converter, an over voltage protection function,
an over current protection function and a LDO regulator. Multiple and extremely flexible Timer
Modules provide timing, pulse generation and PWM generation functions. Protective features such
as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent
noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical
environments.
A full choice of HIRC and LIRC oscillator functions are provided including a fully integrated
system oscillator which requires no external components for its implementation. The ability to
operate and switch dynamically between a range of operating modes using different clock sources
gives users the ability to optimise microcontroller operation and minimize power consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the device will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
Rev. 1.10
7
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Selection Table
Most features are common to all devices and the main features distinguishing them are the I/O pin
count and Level Shift output pins. The following table summarises the main features of each device.
Part No.
VDD
Program
Memory
Data
Memory
Data
EEPROM
I/O
Ext.
Interrupt
A/D
Timer
Module
LDO
Level Shift
Output Pins
Stacks
Package
—
—
4
16NSOP
20SSOP
4
20SSOP
4
20SSOP
HT45F4MA
2.55V~
5.5V
2K×16
128×8
64×8
16
2
12-bit×8
16-bit STM×1
10-bit PTM×1
HT45FH4MA
2.55V~
5.5V
2K×16
128×8
64×8
13
2
12-bit×8
16-bit STM×1
10-bit PTM×1
√
HT45FH4MA-1
2.55V~
5.5V
2K×16
128×8
64×8
13
2
12-bit×8
16-bit STM×1
10-bit PTM×1
√
AX/BX
CX/DX
AX/BX
CX/DX
Block Diagram
Low Voltage
Detect
Flash/EEPROM
Programming
Circuitry
Watchdog
Timer
Stack
EEPROM
Data
Memory
Flash
Program
Memory
RAM Data
Memory
8-bit
RISC
MCU
Core
Time Base
Low Voltage
Reset
Internal
Reset Circuit
Interrupt
Controller
Internal RC
Oscillator
OCP
OVP
LDO
Level
Shift
Timer
Modules
I/O
12-Bit A/D
Converter
(HT45FH4MA/
HT45FH4MA-1 only)
Rev. 1.10
8
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Pin Assignment
 
 
 
 
 
 
 
 
Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the “/”
sign can be used for higher priority.
2. Both real MCU and OCDS EV devices have the same package type. The OCDSCK and OCDSDA pins
are only available for the OCDS EV device. More details are described in the OCDS section.
3. For HT45FH4MA device the I/O lines, PB3~PB5, are internally connected to the level shift inputs, ENBF,
C and A respectively.
4. For HT45FH4MA-1 device the I/O lines, PB4~PB5, are internally connected to the level shift inputs, C
and A, respectively.
Rev. 1.10
9
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Pin Description
With the exception of the power pins and some relevant transformer control pins, all pins on these
devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O
function of the pins. However these Port pins are also shared with other function such as the Analog
to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table,
however the details behind how each pin is configured is contained in other sections of the datasheet.
HT45F4MA
Pin Name
Function
PA0~PA7
General purpose I/O port A
OPT
I/T
O/T
Pin-Shared Mapping
PAPU
PAWU
ST
CMOS
—
PB0~PB7
General purpose I/O port B
PBPU
ST
CMOS
OVP
Over voltage protection input
OCVPR1
AN
—
PA0
—
OCP
Over current protection input
OCVPR1
AN
—
PA3
DAPWR
D/A Converter power input
OCVPR0
PWR
AN
—
PA0~PA7
PA1
AN0~AN7
A/D Converter input 0~7
ADCR0
ACERL
VREF
A/D Converter reference voltage input
ADCR1
AN
—
PA1
INT0, INT1
External interrupt 0, 1
INTEG
INTC0
INTC2
ST
—
PA5, PA6
TCK0, TCK1
TM0, TM1 input
—
ST
—
PA5, PA6
TP0_0, TP0_1
TM0 I/O
TMPC
ST
CMOS PA7, PB0
TP1_0, TP1_1
TM1 I/O
TMPC
ST
CMOS PB3, PB1
ICPCK
In-circuit programming clock pin
—
ST
ICPDA
In-circuit programming data/address pin
—
ST
OCDSCK
On-chip debug support clock pin
—
ST
OCDSDA
On-chip debug support data/address pin
—
ST
OUTL, OUTH
Complementary PWM output
—
PWR
—
VDD
Positive power supply
—
PWR
—
—
VSS
Negative power supply, ground
—
PWR
—
—
—
PA7
CMOS PA6
—
PA7
CMOS PA6
PB5, PB4
Note: I/T: Input type; O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power;
AN: analog signal;
CMOS: CMOS output;
ST: Schmitt Trigger input
Rev. 1.10
10
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
HT45FH4MA/HT45FH4MA-1
Pin Name
Function
PA0~PA7
General purpose I/O port A
OPT
I/T
O/T
Pin-Shared
Mapping
PAPU
PAWU
ST
CMOS
—
PB0~PB2, PB6~PB7
General purpose I/O port B
PBPU
ST
CMOS
OVP
Over voltage protection input
OCVPR1
AN
—
PA0
—
OCP
Over current protection input
OCVPR1
AN
—
PA3
DAPWR
D/A Converter power input
OCVPR0 PWR
PA1
AN0~AN7
A/D Converter input 0~7
ADCR0
ACERL
VREF
A/D Converter reference voltage input
ADCR1
AN
—
PA1
INT0, INT1
External interrupt 0, 1
INTEG
INTC0
INTC2
ST
—
PA5, PA6
TCK0, TCK1
TM0, TM1 input
—
ST
—
PA5, PA6
TP0_0, TP0_1
TM0 I/O
TMPC
ST
CMOS PA7, PB0
CMOS PB1
AN
—
PA0~PA7
TP1_1
TM1 I/O
TMPC
ST
ICPCK
In-circuit programming clock pin
—
ST
ICPDA
In-circuit programming data/address pin
—
ST
OCDSCK
On-chip debug support clock pin
—
ST
OCDSDA
On-chip debug support data/address pin
—
ST
V5
5V LDO output
—
—
PWR
—
VCC
LDO power supply and Level shift output
driving supply
—
PWR
—
—
VDD
Positive power supply
—
PWR
—
—
VSS
Negative power supply, ground
—
PWR
—
—
AX, BX (HT45FH4MA)
—
PA7
CMOS PA6
—
PA7
CMOS PA6
Level shift outputs of input A
—
—
—
—
AX, BX (HT45FH4MA-1) Level shift outputs of input A
—
—
—
—
CX, DX
—
—
—
Rev. 1.10
Level shift outputs of input C
11
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Internal Connection Description
Signal Name
Function
OPT
I/T
O/T
Pin-Shared
Mapping
PB4~PB5
General purpose input/output. Register enabled pull-up.
PBPU
Internally connected to the level shift inputs respectively.
ST
CMOS
—
OUTL, OUTH
PWM output
Internally connected to the level shift inputs A and C
TMPC
—
CMOS
PB5, PB4
A, C
Level shift inputs
Internally connected to PB5/OUTL and PB4/OUTH
respectively
—
—
—
—
ENBF
Level shift enable
For HT45FH4MA →Internally connected to PB3/TP1_0
For HT45FH4MA-1 →Floating input
—
—
—
—
Note: I/T: Input type; O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power;
AN: analog signal;
CMOS: CMOS output;
ST: Schmitt Trigger input
Level Shift Input/Output Relationship and Reset Condition
Level Shift Output
Level Shift Input
A input = Low
A input = High
Reset State
AX, BX (HT45FH4MA)
High
Low
Low
AX, BX (HT45FH4MA-1)
Low
High
High
Level Shift Output
CX, DX
Level Shift Input
C input = Low
C input = High
High
Low
Reset State
Low
Absolute Maximum Ratings
Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V
Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V
Storage Temperature.....................................................................................................-50˚C to 150˚C
Operating Temperature...................................................................................................-40˚C to 85˚C
IOL Total.................................................................................................................................... 120mA
IOH Total...................................................................................................................................-120mA
Total Power Dissipation.......................................................................................................... 500mW
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum
Ratings" may cause substantial damage to these devices. Functional operation of these devices at
other conditions beyond those listed in the specification is not implied and prolonged exposure to
extreme conditions may affect devices reliability.
Rev. 1.10
12
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
D.C. Characteristics
Ta=25˚C
Symbol Parameter
VDD
IOH
IOL
ILEAK
2.55
—
5.5
fSYS=fHIRC/2=15MHz
4.5
—
5.5
2.55
—
5.5
fSYS=fLIRC=32kHz
3V
fSYS=7.5MHz, No load,
All peripherals off
—
2.4
3.6
—
5.4
8.1
4.5V fSYS=15MHz, No load,
5V All peripherals off
—
5.0
7.5
—
6.0
9.0
Standby Current (IDLE1 Mode)
Standby Current (SLEEP Mode)
VOL
fSYS=fHIRC/4=7.5MHz
—
Standby Current (IDLE0 Mode)
VOH
Max.
Operating Voltage (LIRC)
Operating Current (LIRC)
VIL
Typ.
—
IDD
VIH
Min.
Conditions
Operating Voltage (HIRC)
Operating Current (HIRC)
ISTB
Test Conditions
VDD
Input High Voltage (I/O Ports)
Input Low Voltage (I/O Ports)
5V
3V
5V
3V
5V
fSYS=32kHz, No load,
All peripherals off
No load, All peripherals off
4.5V fHIRC=30MHz, No load,
5V All peripherals off
3V
5V
No load, All peripherals off
—
40
60
—
60
90
—
1.3
3.0
—
2.2
5.0
—
4.0
6.0
—
4.6
6.9
—
1.3
3.0
—
2.2
5.0
Unit
V
mA
mA
μA
μA
mA
μA
5V
—
3.5
—
VDD
—
—
0.8VDD
—
VDD
V
5V
—
0
—
1.5
V
V
0
—
0.2VDD
Output High Voltage
(PA, PB0~PB3, PB6, PB7)
3V
IOH=-2.4mA
2.7
—
—
5V
IOH=-6mA
4.5
—
—
Output High Voltage
(PB4, PB5)
3V
IOH=-16mA
2.7
—
—
5V
IOH=-40mA
4.5
—
—
Output Low Voltage
(PA, PB0~PB3, PB6, PB7)
3V
IOL=6.4mA
—
—
0.3
5V
IOL=16mA
—
—
0.5
Output Low Voltage
(PB4, PB5)
3V
IOL=16mA
—
—
0.3
5V
IOL=40mA
—
—
0.5
I/O Port Source Current
(PA, PB0~PB3, PB6, PB7)
3V
-2.4
-4.8
—
-6
-12
—
I/O Port Source Current
(PB4, PB5)
3V
-16
-32
—
-40
-80
—
I/O Port Sink Current
(PA, PB0~PB3, PB6, PB7)
3V
6.4
12.8
—
16
32
—
I/O Port Sink Current
(PB4, PB5)
3V
16
32
—
40
80
—
Input Leakage current
5V
—
5V
5V
5V
5V
—
VOH=0.9VDD
VOH=0.9VDD
VOL=0.1VDD
VOL=0.1VDD
VIN=VDD or VIN=VSS
3V
—
V
V
V
V
V
mA
mA
mA
mA
—
—
±1
μA
20
60
100
KΩ
KΩ
RPH
Pull-high Resistance of I/O Ports
5V
—
10
30
50
VDR
RAM Data Retention Voltage
—
—
1.0
—
—
V
IDDP
Supply Current During Programming
—
—
—
—
10
mA
Rev. 1.10
13
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
A.C. Characteristics
Ta=25˚C
Symbol
fSYS
Parameter
System Clock
Test Conditions
Min.
Typ.
Max.
2.55V~5.5V fSYS=fHIRC/4
—
—
7.5
4.5V~5.5V fSYS=fHIRC/2
—
—
15
Condition
VDD
2.55V~5.5V fSYS=fLIRC
fHIRC
fLIRC
High Speed Internal RC Oscillator
(HIRC)
Low Speed Internal RC Oscillator
(LIRC)
5V
Ta=25°C
—
—
32
Typ.-2%
30
Typ.+2%
4.0V~5.5V Ta=-10°C to 85°C
Typ.-5%
30
Typ.+5%
3.6V~5.5V Ta=-40°C to 85°C
Typ.-10%
30
Typ.+10%
5V
Ta=25°C
Typ.-10%
32
Typ.+10%
5V
Ta=-40°C to 85°C
Typ.-30%
32
Typ.+30%
2.55V~5.5V Ta=-40°C to 85°C
Typ.-50%
32
Typ.+60%
Unit
MHz
kHz
MHz
kHz
Minimum Software Reset Width to
Reset
—
—
45
90
120
μs
System Reset Delay Time (POR
Reset, LVR Hardware Reset, LVR
Software Reset, WDT Software Reset)
—
—
25
50
100
ms
System Reset Delay Time
(WDT Time-out Hardware Cold Reset)
—
—
8.3
16.7
33.3
ms
—
Wake-up from SLEEP
mode or IDLE0 mode
16
—
—
1/fSYS
—
Wake-up from IDLE1
mode
2
—
—
1/fSYS
System Start-up Timer Period
(fSYS = fLIRC)
—
Wake-up from IDLE
mode or SLEEP mode
2
—
—
1/fSYS
tINT
External Interrupt Minimum Pulse
Width
—
—
10
—
—
μs
tTCK
TM TCK Input Pin Minimum Pulse
Width
—
—
0.3
—
—
μs
tEERD
EEPROM Read Time
—
—
—
—
4
tSYS
tEEWR
EEPROM Write Time
—
—
—
2
4
ms
tSRESET
tRSTD
tSST
System Start-up Timer Period
(fSYS = fHIRC/4)
Rev. 1.10
14
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
LVD & LVR Electrical Characteristics
Ta=25˚C
Symbol
VLVR
VLVD
Test Conditions
Parameter
Conditions
VDD
Low Voltage Reset Voltage
Low Voltage Detection Voltage
Min.
Typ.-5%
Typ.
—
LVR enable
—
LVD enable,
selected voltage=2.7V
2.7
—
LVD enable,
selected voltage=3.0V
3.0
—
LVD enable,
selected voltage=3.3V
—
LVD enable,
selected voltage=3.6V
3.6
—
LVD enable,
selected voltage=4.0V
4.0
Typ.-5%
Max.
Unit
2.55 Typ.+5%
3.3
V
Typ.+5%
V
1.25 Typ.+3%
V
μA
VBG
Bandgap Reference Voltage
—
—
Typ.-3%
IBG
Additional current for Bandgap
Reference
—
—
—
200
ILVD
Additional Current for LVD Enable
—
30
45
—
60
90
tBGS
VBG Turn on Stable Time
—
—
—
200
μs
tLVR
Minimum Low Voltage Width to Reset
—
—
120
240
480
μs
tLVD
Minimum Low Voltage Width to Interrupt
—
—
60
120
240
μs
LVDO Stable Time
Bandgap is ready,
5V
LVD off → on
—
—
15
μs
tLVDS
3V
—
5V
No load
300
μA
A/D Converter Electrical Characteristics
Ta=25˚C
Symbol
Parameter
Test Conditions
VDD
Condition
Min.
Typ.
Max.
Unit
VDD
A/D Converter Operating Voltage
—
—
2.7
—
5.5
V
VADI
A/D Converter Input Voltage
—
—
0
—
VREF
V
VREF
A/D Converter Reference Voltage
—
—
2
—
VDD
V
IADC
Additional Current for A/D
Converter Enable
3V
—
0.90
1.35
5V
—
1.20
1.80
No load
mA
DNL
Differential Non-linearity
5V
VREF=VDD, tADCK=0.5μs
—
±1
±3
LSB
INL
Integral Non-linearity
5V
VREF=VDD, tADCK=0.5μs
—
±2
±4
LSB
tADCK
A/D Converter Clock Period
—
—
0.5
—
10
μs
tADC
A/D Converter Conversion Time
(A/D Sample and Hold Time)
—
—
—
16
—
tADCK
tADS
A/D Converter Sampling Time
—
—
—
4
—
tADCK
tON2ST
A/D Converter On-to-Start Time
—
—
4
—
—
μs
Rev. 1.10
15
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Over Current Circuit Electrical Characteristics
Ta=25˚C
Symbol
Test Conditions
Parameter
VDD
3V
Condition
OCPEN=1
Min.
Typ.
Max.
Unit
—
300
500
—
450
600
-15
—
15
mV
μA
IOCP
Operating Current
VOS_CMP
Comparator Input Offset Voltage
Without calibration,
5V CBOF[5:0]=100000B
With calibration
-4
—
4
mV
VHYS
Hysteresis
5V
—
20
40
60
mV
VCM_CMP Comparator Common Mode Voltage Range 5V
—
VSS
—
VDD-1.4
V
-15
—
15
mV
-4
—
4
mV
VOS_OPA
5V
Without calibration,
5V AOF[5:0]=100000B
With calibration
OPA Input Offset Voltage
OPA Common Mode Voltage Range
5V
VSS
—
VDD-1.4
V
DNL
Differential Nonlinearity
D/A Converter reference
5V
voltage=VDD
—
—
±1
LSB
INL
Integral Nonlinearity
5V
D/A Converter reference
voltage=VDD
—
—
±2
LSB
VCM_OPA
—
Over Voltage Circuit Electrical Characteristics
Ta=25˚C
Symbol
Parameter
Test Conditions
VDD
3V
Condition
OVPEN=1
Min.
Typ.
Max.
Unit
—
300
500
—
450
600
-15
—
15
mV
—
4
mV
40
60
mV
μA
IOVP
Operating Current
VOS
Input Offset Voltage
Without calibration,
5V CAOF[5:0]=100000B
With calibration
-4
VHYS
Hysteresis
5V
—
20
VCM
Common Mode Voltage Range 5V
—
VSS
—
VDD-1.4
V
—
—
±1
LSB
—
—
±2
LSB
5V
DNL
Differential Nonlinearity
5V D/A Converter reference voltage=VDD
INL
Integral Nonlinearity
5V D/A Converter reference voltage=VDD
Rev. 1.10
16
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
LDO Regulator Electrical Characteristics
CLOAD=1μF, Ta=25˚C
Symbol
VIN
VOUT
Parameter
Input Voltage
Test Conditions
VDD
Condition
—
Typ.
Max.
Unit
6
—
28
V
—
Ta=25˚C,
ILOAD=1mA, VIN=VOUT + 1V
Typ.-2%
5
Typ.+2%
V
—
-40˚C ≤ Ta < 85˚C,
ILOAD=1mA, VIN=VOUT + 1V
Typ.-5%
5
Typ.+5%
V
Output Voltage
—
Min.
ΔVLOAD
Load Regulation (Note 1)
—
1mA ≤ ILOAD ≤ 30mA
VIN=VOUT+1V
—
0.09
0.18
%/mA
VDROP
Dropout Voltage (Note 2)
—
ΔVOUT=2%, ILOAD=1mA
VIN=VOUT+2V
—
—
100
mV
IQ
Quiescent Current
—
No load, VIN=12V
—
2
4
μA
ΔVLINE
Line Regulation
—
6V ≤ VIN ≤ 28V, ILOAD=1mA
—
—
0.2
%/V
TC
Temperature Coefficient
—
-40˚C ≤ Ta < 85˚C,
VIN=VOUT + 1V, ILOAD=10mA
—
±0.9
±2
mV/˚C
Note: 1. Load regulation is measured at a constant junction temperature, using pulse testing with a low ON time
and is guaranteed up to the maximum power dissipation. Power dissipation is determined by the input/
output differential voltage and the output current. Guaranteed maximum power dissipation will not be
available over the full input/output range. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - Ta) / θJA.
2. Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the
output voltage from the value at VIN = VOUT + 2V.
Level Converter Electrical Characteristics
Ta=25˚C
Symbol
Parameter
Test Conditions
VDD
Condition
Min.
Typ.
Max.
Unit
ISOURCE
Output Source Current of AX, BX, AX, BX,
CX, DX
—
VCC=12V, VOH=10.4V
-60
-90
—
mA
ISINK
Output Sink Current of AX, BX, AX, BX,
CX, DX
—
VCC=12V, VOL=1.6V
60
90
—
mA
Rev. 1.10
17
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Power on Reset Electrical Characteristics
Symbol
Ta= 25°C
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VPOR
VDD Start Voltage to Ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Rising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to
Ensure Power-on Reset
—
—
1
—
—
ms
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The device takes advantage of the usual features found within
RISC microcontrollers providing increased speed of operation and enhanced performance. The
pipelining scheme is implemented in such a way that instruction fetching and instruction execution
are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch
or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which
carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions,
etc. The internal data path is simplified by moving data through the Accumulator and the ALU.
Certain internal registers are implemented in the Data Memory and can be directly or indirectly
addressed. The simple addressing methods of these registers along with additional architectural
features ensure that a minimum of external components is required to provide a functional I/O and
A/D control system with maximum reliability and flexibility. This makes the device suitable for lowcost, high-volume production for controller applications.
Clocking and Pipelining
The main system clock, derived from either an HIRC or LIRC oscillator is subdivided into four
internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the
beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4
clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms
one instruction cycle. Although the fetching and execution of instructions takes place in consecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle. The exception to this are instructions where the
contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the
instruction will take one more instruction cycle to execute.
Rev. 1.10
18
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU


   
   
System Clock and Pipelining
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
  
    
 Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has
been met, the next instruction, which has already been fetched during the present instruction execution,
is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Program Counter
Rev. 1.10
Program Counter High byte
PCL Register
PC10~PC8
PCL7~PCL0
19
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is
available for program control and is a readable and writeable register. By transferring data directly
into this register, a short program jump can be executed directly, however, as only this low byte
is available for manipulation, the jumps are limited to the present page of memory, that is 256
locations. When such program jumps are executed it should also be noted that a dummy cycle
will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is
needed to pre-fetch.
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is neither part of the data nor part of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction,
RET or RETI, the Program Counter is restored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can
still be executed which will result in a stack overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program branching. If the stack is overflow, the first Program
Counter save in the stack will be lost.
P ro g ra m
T o p o f S ta c k
B o tto m
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
S ta c k L e v e l 3
o f S ta c k
C o u n te r
P ro g ra m
M e m o ry
S ta c k L e v e l 4
Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU
receives related instruction codes and performs the required arithmetic or logical operations after
which the result will be placed in the specified register. As these ALU calculation or operations may
result in carry, borrow or other status changes, the status register will be correspondingly updated to
reflect these changes. The ALU supports the following functions:
• Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA
• Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA
• Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC
• Increment and Decrement INCA, INC, DECA, DEC
• Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI
Rev. 1.10
20
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device the
Program Memory is Flash type, which means it can be programmed and re-programmed a large
number of times, allowing the user the convenience of code modification on the same device.
By using the appropriate programming tools, this Flash device offers users the flexibility to
conveniently debug and develop their applications while also offering a means of field programming
and updating.
Structure
The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the
Program Counter and also contains data, table information and interrupt entries. Table data, which
can be setup in any location within the Program Memory, is addressed by a separate table pointer
register.
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The location
000H is reserved for use by the device reset for program initialisation. After a device reset is
initiated, the program will jump to this location and begin execution.
        
­ € ­ €  ­ Program Memory Structure
Rev. 1.10
21
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Look-up Table
Any location within the Program Memory can be defined as a look-up table where programmers can
store fixed data. To use the look-up table, the table pointer must first be setup by placing the address
of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers
define the total address of the look-up table.
After setting up the table pointer, the table data can be retrieved from the Program Memory using
the “TABRD [m]” or “TABRDL[m]” instructions, respectively. When the instruction is executed,
the lower order table byte from the Program Memory will be transferred to the user defined
Data Memory register [m] as specified in the instruction. The higher order table data byte from
the Program Memory will be transferred to the TBLH special register. Any unused bits in this
transferred higher order byte will be read as “0”.
The accompanying diagram illustrates the addressing data flow of the look-up table.
A d d re s s
L a s t p a g e o r
T B H P R e g is te r
T B L P R e g is te r
Instruction
D a ta
1 6 b its
R e g is te r T B L H
U s e r S e le c te d
R e g is te r
H ig h B y te
L o w B y te
Table Location Bits
b10
b9
b8
b7
TABRD [m]
@10
@9
@8
@7
TABRDL [m]
1
1
1
@7
b6
b5
b4
b3
b2
b1
b0
@6
@5
@4
@3
@2
@1
@0
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: b10~b0: Table location bits
@[email protected]: Table pointer (TBLP) bits
@[email protected]: Table pointer (TBHP) bits
Rev. 1.10
22
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Table Program Example
The following example shows how the table pointer and table data is defined and retrieved from the
microcontroller. This example uses raw table data located in the Program Memory which is stored
there using the ORG statement. The value at this ORG statement is “700H” which refers to the start
address of the last page within the 2K words Program Memory of the device. The table pointer is
setup here to have an initial value of “06H”. This will ensure that the first data read from the data
table will be at the Program Memory address “706H” or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page if the
“TABRD [m]” instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the “TABRD [m]” instruction is
executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Table Read Program Example
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise low table pointer - note that this address is referenced
mov tblp,a
mov a,07h ; initialise high table pointer
mov tbhp,a
:
:
tabrd tempreg1 ; transfers value in table referenced by table pointer data at program
; memory address “706H” transferred to tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address “705H” transferred to tempreg2 and TBLH
; in this example the data “1AH” is transferred to tempreg1 and data “0FH”
; to register tempreg2
:
:
org 700h; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.10
23
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
In Circuit Programming
The provision of Flash type Program Memory provides the user with a means of convenient and easy
upgrades and modifications to their programs on the same device. As an additional convenience,
Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with
a programmed or un-programmed microcontroller, and then programming or upgrading the program
at a later stage. This enables product manufacturers to easily keep their manufactured products
supplied with the latest program releases without removal and re-insertion of the device.
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pins
MCU Programming Pins
ICPDA
PA6
Programming Serial Data/Address
Pin Description
ICPCK
PA7
Programming Clock
VDD
VDD
Power Supply
VSS
VSS
Ground
During the programming process, the user must take care to ensure that no other outputs are
connected to these two pins.
The Program Memory and EEPROM data memory can both be programmed serially in-circuit using
this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional
line for the clock. Two additional lines are required for the power supply. The technical details
regarding the in-circuit programming of the device are beyond the scope of this document and will
be supplied in supplementary literature.
W r ite r C o n n e c to r
S ig n a ls
M C U
P r o g r a m m in g
P in s
V D D
W r ite r _ V D D
P A 6
IC P D A
IC P C K
P A 7
W r ite r _ V S S
V S S
*
*
T o o th e r C ir c u it
Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance
of * must be less than 1nF.
Rev. 1.10
24
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
On-Chip Debug Support – OCDS
An EV chip exists for the purposes of device emulation. This EV chip device also provides an
“On-Chip Debug” function to debug the device during the development process. The EV chip
and the actual MCU devices are almost functionally compatible except for the “On-Chip Debug”
function. Users can use the EV chip device to emulate the real chip device behavior by connecting
the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is
the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin.
When users use the EV chip for debugging, other functions which are shared with the OCDSDA
and OCDSCK pins in the actual MCU device will have no effect in the EV chip. However, the two
OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory
programming pins for ICP. For a more detailed OCDS description, refer to the corresponding
document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”.
MCU Device
Holtek e-Link Pins
EV Chip Device
HT45F4MA
HT45V4MA
HT45FH4MA
HT45VH4MA
HT45FH4MA-1
HT45VH4MA-1
EV Chip Pins
Pin Description
OCDSDA
OCDSDA
On-Chip Debug Support Data/Address input/output
OCDSCK
OCDSCK
On-Chip Debug Support Clock input
VDD
VDD
Power Supply
GND
VSS
Ground
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored.
Structure
Divided into two sections, the first of these is an area of RAM, known as the Special Function Data
Memory. Here are located registers which are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some
remain protected from user manipulation. The second area of Data Memory is known as the General
Purpose Data Memory, which is reserved for general purpose use. All locations within this area are
read and write accessible under program control.
The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are
accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible
in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer
to the correct value. The start address of the Data Memory for the device is the address 00H.
Rev. 1.10
25
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
00H
01H
0�H
03H
0�H
05H
06H
07H
0�H
09H
0�H
0BH
0CH
0DH
0EH
0FH
10H
11H
1�H
13H
1�H
15H
16H
17H
1�H
19H
1�H
1BH
1CH
1DH
1EH
1FH
�0H
�1H
��H
�3H
��H
�5H
�6H
�7H
Bank 0� 1
I�R0
MP0
I�R1
MP1
BP
�CC
PCL
TBLP
TBLH
TBHP
ST�TUS
SMOD
LVDC
INTEG
INTC0
INTC1
INTC�
MFI0
MFI1
MFI�
P�
P�C
P�PU
P�WU
Un�sed
TMPC
WDTC
TBC
Un�sed
EE�
EED
�DRL
�DRH
�DCR0
�DCR1
�CERL
Un�sed
CTRL
LVRC
��H
�9H
��H
�BH
�CH
�DH
�EH
�FH
30H
31H
3�H
33H
3�H
35H
36H
37H
:
:
3CH
3DH
3EH
3FH
�0H
�1H
��H
�3H
��H
�5H
�6H
�7H
��H
�9H
��H
:
:
:
7FH
Bank 0 Bank 1
TM0C0
TM0C1
TM0DL
TM0DH
TM0�L
TM0�H
TM0RP
TM1C0
TM1C1
TM1DL
TM1DH
TM1�L
TM1�H
TM1RPL
TM1RPH
Un�sed
PB
PBC
PBPU
EEC
OCPREF
OVPREF
OCVPR0
OCVPR1
OCVPR�
OCVPR3
OCVPR�
OCVPR5
CPR
Un�sed
: Un�sed� read as 00H
Special Purpose Data Memory Structure
00H
Special Purpose
Data Memory
7FH
80H
General Purpose
Data Memory
FFH
Data Memory Structure
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section,
however several registers require a separate description in this section.
Indirect Addressing Registers – IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM
register space, do not actually physically exist as normal registers. The method of indirect addressing
for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in
contrast to direct memory addressing, where the actual memory address is specified. Actions on the
IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather
to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can
access data from any bank. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the
registers indirectly will result in no operation.
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be manipulated in the same way as normal
registers providing a convenient way with which to address and track data. When any operation to
the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller
is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to
access data from all banks according to BP register. Direct Addressing can only be used with Bank 0,
all other Banks must be addressed indirectly using MP1 and IAR1.
The following example shows how to clear a section of four Data Memory locations already defined
as locations adres1 to adres4.
Indirect Addressing Program Example
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ´code´
org00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp0,a ; setup memory pointer with first RAM address
loop:
clr IAR0 ; clear the data at address defined by mp0
inc mp0; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific
Data Memory addresses.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Bank Pointer – BP
For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the
required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to
select Data Memory Banks 0~1.
The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power
Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the
Special Function Data Memory is not affected by the bank selection, which means that the Special
Function Registers can be accessed from within any bank. Directly addressing the Data Memory
will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing
data from Bank1 must be implemented using Indirect Addressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7 ~ 1
Unimplemented, read as "0"
Bit 0
DMBP0: Select Data Memory Banks
0: Bank 0
1: Bank 1
Accumulator – ACC
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Program Counter Low Register – PCL
To provide additional program control functions, the low byte of the Program Counter is made
accessible to programmers by locating it within the Special Purpose area of the Data Memory. By
manipulating this register, direct jumps to other program locations are easily implemented. Loading
a value directly into this PCL register will cause a jump to the specified Program Memory location,
however, as the register is only 8-bit wide, only jumps within the current Program Memory page are
permitted. When such operations are used, note that a dummy cycle will be inserted.
Look-up Table Registers – TBLP, TBHP, TBLH
These three special function registers are used to control operation of the look-up table which is
stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location
where the table data is located. Their value must be setup before any table read commands are
executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing
for easy table data pointing and reading. TBLH is the location where the high order byte of the table
data is stored after a table read data instruction has been executed. Note that the lower order table
data byte is transferred to a user defined location.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Status Register – STATUS
This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation
and system management flags are used to record the status and operation of the microcontroller.
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions
like most other registers. Any data written into the status register will not change the TO or PDF flag.
In addition, operations related to the status register may give different results due to the different
instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or
by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing
the “HALT” or “CLR WDT” instruction or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of the latest operations.
• C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by
executing the “HALT” instruction.
• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is
set by a WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will
not be pushed onto the stack automatically. If the contents of the status registers are important and if
the subroutine can corrupt the status register, precautions must be taken to correctly save it.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
×
×
×
×
"×" unknown
Rev. 1.10
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5
TO: Watchdog Time-Out flag
0: After power up or executing the "CLR WDT" or "HALT" instruction
1: A watchdog time-out occurred.
Bit 4
PDF: Power down flag
0: After power up or executing the "CLR WDT" instruction
1: By executing the "HALT" instruction
Bit 3
OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2
Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1
AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble in subtraction
Bit 0
C: Carry flag
0: No carry-out
1: An operation results in a carry during an addition operation or if a borrow does
not take place during a subtraction operation
C is also affected by a rotate through carry instruction.
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
EEPROM Data Memory
One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which
stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile
form of memory, with data retention even when its power supply is removed. By incorporating
this kind of data memory, a whole new host of application possibilities are made available to the
designer. The availability of EEPROM storage allows information such as product identification
numbers, calibration values, specific user data, system setup data or other product information to
be stored directly within the product microcontroller. The process of reading and writing data to the
EEPROM memory has been reduced to a very trivial affair.
EEPROM Data Memory Structure
The EEPROM Data Memory capacity is up to 64×8 bits. Unlike the Program Memory and RAM
Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly
accessible in the same way as the other types of memory. Read and Write operations to the
EEPROM are carried out in single byte operations using an address and data register in Bank 0 and
a single control register in Bank 1.
EEPROM Registers
Three registers control the overall operation of the internal EEPROM Data Memory. These are the
address register, EEA, the data register, EED and a single control register, EEC. As both the EEA
and EED registers are located in Bank 0, they can be directly accessed in the same way as any other
Special Function Register. The EEC register however, being located in Bank1, cannot be directly
addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer
and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H
in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register,
BP, set to the value, 01H, before any operations on the EEC register are executed.
EEPROM Control Registers List
Name
Bit
7
6
5
4
3
2
1
0
EEA
—
—
D5
D4
D3
D2
D1
D0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
Bit
7
6
5
4
3
2
1
0
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
EEA Register
Rev. 1.10
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5 ~ 0
Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
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Power Bank 8-Bit Flash MCU
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7 ~ 0
Data EEPROM data
Data EEPROM data bit 7 ~ bit 0
EEC Register
Bit
7
6
5
4
3
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7 ~ 4
Unimplemented, read as "0"
Bit 3
WREN: Data EEPROM Write Enable
0: Disable
1: Enable
This is the Data EEPROM Write Enable Bit which must be set high before Data
EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM write operations.
Bit 2
WR: EEPROM Write Control
0: Write cycle has finished
1: Activate a write cycle
This is the Data EEPROM Write Control Bit and when set high by the application
program will activate a write cycle. This bit will be automatically reset to zero by the
hardware after the write cycle has finished. Setting this bit high will have no effect if
the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM Read Enable
0: Disable
1: Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data
EEPROM read operations.
Bit 0
RD: EEPROM Read Control
0: Read cycle has finished
1: Activate a read cycle
This is the Data EEPROM Read Control Bit and when set high by the application
program will activate a read cycle. This bit will be automatically reset to zero by the
hardware after the read cycle has finished. Setting this bit high will have no effect if
the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction.
The WR and RD can not be set to “1” at the same time.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Reading Data from the EEPROM
To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set
high to enable the read function. The EEPROM address of the data to be read must then be placed
in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated.
Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When
the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can
be read from the EED register. The data will remain in the EED register until another read or write
operation is executed. The application program can poll the RD bit to determine when the data is
valid for reading.
Writing Data to the EEPROM
The EEPROM address of the data to be written must first be placed in the EEA register and the data
placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC
register must first be set high to enable the write function. After this, the WR bit in the EEC register
must be immediately set high to initiate a write cycle. These two instructions must be executed
consecutively. The global interrupt bit EMI should also first be cleared before implementing any
write operations, and then set again after the write cycle has started. Note that setting the WR bit
high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is
controlled using an internal timer whose operation is asynchronous to microcontroller system clock,
a certain time will elapse before the data will have been written into the EEPROM. Detecting when
the write cycle has finished can be implemented either by polling the WR bit in the EEC register or
by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically
cleared to zero by the microcontroller, informing the user that the data has been written to the
EEPROM. The application program can therefore poll the WR bit to determine when the write cycle
has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data
Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a
further measure of protection against spurious write operations. During normal program operation,
ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect
write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as
the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt
enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its
associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function
Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag
will be automatically reset, the EEPROM interrupt flag must be manually reset by the application
program. More details can be obtained in the Interrupt section.
Rev. 1.10
33
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where
the EEPROM control register exist. Although certainly not necessary, consideration might be given
in the application program to the checking of the validity of new write data by a simple read back
process. When writing data the WR bit must be set high immediately after the WREN bit has been
set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be
cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that
the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is
totally complete. Otherwise, the EEPROM read or write operation will fail.
Programming Examples
Reading data from the EEPROM - polling method
MOV A, EEPROM_ADRES ;
MOV EEA, A
MOV A, 040H ;
MOV MP1, A ;
MOV A, 01H ;
MOV BP, A
SET IAR1.1 ;
SET IAR1.0 ;
BACK:
SZ IAR1.0 ;
JMP BACK
CLR IAR1 ;
CLR BP
MOV A, EED ;
MOV READ_DATA, A
user defined address
setup memory pointer MP1
MP1 points to EEC register
setup Bank Pointer
set RDEN bit, enable read operations
start Read Cycle - set RD bit
check for read cycle end
disable EEPROM read/write
move read data to register
Writing Data to the EEPROM - polling method
CLR EMI
MOV A, EEPROM_ADRES MOV EEA, A
MOV A, EEPROM_DATA MOV EED, A
MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR BP
Rev. 1.10
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM read/write
34
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation
are selected through a combination of configuration options and registers.
Oscillator Overview
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no
external components, are provided to form a wide range of both fast and slow system oscillators.
The higher frequency oscillators provide higher performance but carry with it the disadvantage of
higher power requirements, while the opposite is of course true for the lower frequency oscillators.
With the capability of dynamically switching between fast and slow system clock, the device has the
flexibility to optimize the performance/power ratio, a feature especially important in power sensitive
portable applications.
Type
Name
Freq.
Internal High Speed RC
HIRC
30MHz
Internal Low Speed RC
LIRC
32kHz
Oscillator Types
System Clock Configurations
There are two methods of generating the system clock, a high speed oscillator and a low speed
oscillator. The high speed oscillator is the internal 30MHz RC oscillator. The low speed oscillator
is the internal 32kHz (LIRC) oscillator. Selecting whether the low or high speed oscillator is used
as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD
register and as the system clock can be dynamically selected.
The actual source clock used for the high speed and the low speed oscillators is chosen via a combination
of configuration options and registers. The frequency of the slow speed or high speed system clock is
also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two
oscillator selections must be made namely one high speed and one low speed system oscillators. It is not
possible to choose a no-oscillator selection for either the high or low speed oscillator.
High Speed
Oscillator
HIRC
fH
6-stage Prescaler
fH/2
fH/4
fH/8
fH/16
fSYS
fH/32
Low Speed
Oscillator
LIRC
fH/64
fSUB
HLCLK,
CKS2~CKS0 bits
System Clock Configurations
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Internal RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has several frequencies of either 30MHz by option. Device trimming
during the manufacturing process and the inclusion of internal frequency compensation circuits are
used to ensure that the influence of the power supply voltage, temperature and process variations on
the oscillation frequency are minimised. Note that if this internal system clock option is selected, as
it requires no external pins for its operation.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its
implementation. Device trimming during the manufacturing process and the inclusion of internal
frequency compensation circuits are used to ensure that the influence of the power supply voltage,
temperature and process variations on the oscillation frequency are minimised.
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
true in battery powered portable applications. The fast clocks required for high performance will
by their nature increase current consumption and of course vice-versa, lower speed clocks reduce
current consumption. As Holtek has provided this device with both high and low speed clock
sources and the means to switch between them dynamically, the user can optimise the operation of
their microcontroller to achieve the best performance/power ratio.
System Clocks
The device has many different clock sources for both the CPU and peripheral function operation.
By providing the user with a wide range of clock options using configuration options and register
programming, a clock system can be configured to obtain maximum application performance.
The main system clock, can come from either a high frequency, fH, or low frequency, fSUB, source,
and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed
system clock can be sourced from the HIRC oscillator. The low speed system clock source can be
sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed
system oscillator has a range of fH/2~fH/64.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
   


 ­ 
€
 ‚ ƒ „ … †   ­ System Clock Configurations
Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to
conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.
System Operation Modes
There are five different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There are two modes allowing normal operation of the
microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP,
IDLE0 and IDLE1 Mode, are used when the microcontroller CPU is switched off to conserve power.
Operating Mode
Rev. 1.10
Description
CPU
fSYS
fSUB
fTBC
NORMAL mode
On
fH~fH/64
On
On
SLOW mode
On
fSUB
On
On
ILDE0 mode
Off
Off
On
On
IDLE1 mode
Off
On
On
On
SLEEP mode
Off
Off
On
Off
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of
its functions operational and where the system clock is provided by the high speed oscillator. This
mode operates allowing the microcontroller to operate normally with a clock source will come from
the high speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio
ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the
SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided
clock ratio reduces the operating current.
SLOW Mode
This is also a mode where the microcontroller operates normally although now with a slower speed
clock source. The clock source used will be from fSUB. Running the microcontroller in this mode
allows it to run with much lower operating currents. In the SLOW Mode, the fH is off.
SLEEP Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the
SMOD register is low. In the SLEEP mode the CPU will be stopped. However the fSUB clock will
continue to operate.
IDLE0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the
system oscillator will be inhibited from driving the CPU, the system oscillator will be stopped, the
low frequency fSUB will be on.
IDLE1 Mode
The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the
SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the
system oscillator will be inhibited from driving the CPU, the system oscillator will continue to run,
and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the
low frequency fSUB will be on.
Note: If LVDEN=1 and the SLEEP or IDLE mode is entered, the LVD and bandgap functions will
not be disabled, and the fSUB clock will be forced to be enabled.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Control Register
The SMOD register is used to control the internal clocks within the device.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
—
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
—
R
R
R/W
R/W
POR
1
1
0
—
0
0
1
0
Bit 7 ~ 5
Rev. 1.10
CKS2 ~ CKS0: The system clock selection when HLCLK is “0”
000: fSUB 001: fSUB 010: fH/64
011: fH/32
100: fH/16
101: fH/8
110: fH/4
111: fH/2
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be LIRC, a divided version of the high
speed system oscillator can also be chosen as the system clock source.
Bit 4
Unimplemented, read as "0"
Bit 3
LTO: LIRC System OSC SST ready flag 0: Not ready
1: Ready
This is the low speed system oscillator SST ready flag which indicates when the low
speed system oscillator is stable after power on reset or a wake-up has occurred. The
flag will change to a high level after 1~2 cycles.
Bit 2
HTO: HIRC System OSC SST ready flag 0: Not ready
1: Ready
This is the high speed system oscillator SST ready flag which indicates when the high
speed system oscillator is stable after a wake-up has occurred. This flag is cleared to
“0” by hardware when the device is powered on and then changes to a high level after
the high speed system oscillator is stable. Therefore this flag will always be read as “1”
by the application program after device power-on. The flag will be low when in the
SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag
will change to a high level after 15~16 clock cycles if the HIRC oscillator is used.
Bit 1
IDLEN: IDLE Mode Control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0
HLCLK: System Clock Selection
0: fH/2 ~ fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fSUB clock is used as the
system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~
fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to
the fSUB clock and the fH clock will be automatically switched off to conserve power.
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
×
0
0
Bit 7 FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Bit 6~3
Unimplemented, read as "0"
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register
values. This in effect acts like a software reset function. This bit can only be cleared to
0 by the application program.
Bit 0
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Rev. 1.10
40
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
  
   
  
   
  
Operating Mode Switching
The device can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the
HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/
SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT
instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by
the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the
high speed clock source will stop running to conserve power. When this happens it must be noted
that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation
of other internal functions such as the TMs. The accompanying flowchart shows what happens when
the device moves between the various operating modes.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to 0 and setting the CKS2~CKS0 bits to 000B or 001B in the SMOD register.This will
then use the low speed system oscillator which will consume less power. Users may decide to do this
for certain operations which do not require high performance and can subsequently reduce power
consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be
stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
                       Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or
HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a
certain amount of time will be required for the high frequency clock to stabilise, the status of the
HTO bit is checked. The amount of time required for high speed system oscillator stabilization
depends upon which high speed system oscillator type is used.
                                Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0”. When this
instruction is executed under the conditions described above, the following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT” instruc­tion,
but the Time Base clock fTBC and the low frequency fSUB will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock together with the Time Base clock fTBC and the low frequency fSUB will be on
and the application program will stop at the “HALT” instruc­tion.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Standby Current Considerations
As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the
device to as low a value as possible, perhaps only in the order of several micro-amps except in the
IDLE1 Mode, there are other considerations which must also be taken into account by the circuit
designer if the power consumption is to be minimised. Special attention must be made to the I/O pins
on the device. All high-impedance input pins must be connected to either a fixed high or low level as
any floating input pins could create internal oscillations and result in increased current consumption.
This also applies to devices which have different package types, as there may be unbonbed pins.
These must either be setup as outputs or if setup as inputs must have pull-high resistors connected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs. These should be placed in a condition in which minimum current is drawn or connected
only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode
the system oscillator is on, if the system oscillator is from the high speed system oscillator, the
additional standby current will also be perhaps in the order of several hundred micro-amps.
Wake-up
After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources
listed as follows:
• An external falling edge on Port A
• A system interrupt
• A WDT overflow
If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The actual
source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is
cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when
executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wakeup that only resets the Program Counter and Stack Pointer, the other flags remain in their original
status.
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal fSUB clock which is in turn supplied
by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to
218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC
register. The LIRC internal oscillator has an approximate period of 32 kHz at a supply voltage of 5V.
However, it should be noted that this specified internal clock period can vary with VDD, temperature
and process variations.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. The WDTC register is initiated to 01010011B at any reset but keeps unchanged at the
WDT time-out occurrence in a power down state.
WDTC Register
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit 7~3
Bit 2~0
Rev. 1.10
WE4~WE0: WDT function software control
10101 or 01010: Enabled
Other: Reset MCU
When these bits are changed by the environmental noise to reset the microcontroller,
the reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in
the CTRL register will be set to 1.
WS2~WS0: WDT Time-out period selection
000: 28/fSUB
001: 210/fSUB
010: 212/fSUB
011: 214/fSUB
100: 215/fSUB
101: 216/fSUB
110: 217/fSUB
111: 218/fSUB
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
FSYSON: fSYS Control in IDLE Mode
Describe elsewhere.
Bit 6~3
Unimplemented, read as "0"
Bit 2
LVRF: LVR function reset flag
Describe elsewhere.
Bit 1
LRF: LVR Control register software reset flag
Describe elsewhere.
Bit 0
WRF: WDT Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the application
program. Note that this bit can only be cleared to 0 by the application program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, the clear WDT instruction will not be executed in
the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are
five bits, WE4~WE0, in the WDTC register to enable the WDT function. When the WE4~WE0 bits
value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits
are changed to any other values except 01010B and 10101B, which is caused by the environmental
noise, it will reset the microcontroller after 2~3 LIRC clock cycles.
WE4 ~ WE0 Bits
WDT Function
01010B or 10101B
Enable
Any other value
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value is written into the WE4~WE0 bit filed except
01010B and 10101B, the second is using the Watchdog Timer software clear instructions and the
third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT.
The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32
kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
WDTC Register
WE4~WE0 bits
Reset MCU
CLR
“CLR WDT”Instruction
LIRC
fSUB
8-stage Divider
fSUB/28
WDT Prescaler
WS2~WS0
(fSUB/28 ~ fSUB/218)
8-to-1 MUX
WDT Time-out
(28/fSUB ~ 218/fSUB)
Watchdog Timer
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set
to some predetermined condition irrespective of outside parameters. The most important reset
condition is after power is first applied to the microcontroller. In this case, internal circuitry will
ensure that the microcontroller, after a short delay, will be in a well defined state and ready to
execute the first program instruction. After this power-on reset, certain important internal registers
will be set to defined states before the program commences. One of these registers is the Program
Counter, which will be reset to zero forcing the microcontroller to begin program execution from the
lowest Program Memory address.
Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All
types of reset operations result in different register conditions being setup. Another reset exists in the
form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power
supply voltage falls below a certain threshold.
Reset Functions
There are four ways in which a microcontroller reset can occur, through events occurring internally:
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. All the I/O port and port control registers will power up in a high condition ensuring that
all pins will be first set to inputs.
VDD
Power-on
Reset
tRSTD
SST Time-o�t
Note: tRSTD is power-on delay, typical time=50ms
Power-On Reset Timing Chart
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the
device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage
of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery,
the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will
also be set to 1. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the
low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage
and will not perform a reset function. The actual VLVR is fixed at a voltage value of 2.55V by the
LVS bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the
environmental noise, the LVR will reset the device after 2~3 LIRC clock cycles. When this happens,
the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of
01010101B. Note that the LVR function will be automatically disabled when the device enters the
power down mode.
Note:tRSTD is power-on delay, typical time=50ms
Low Voltage Reset Timing Chart
• LVRC Register
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7 ~ 0
Rev. 1.10
LVS7 ~ LVS0: LVR voltage select
01010101: 2.55V
00110011: 2.55V
10011001: 2.55V
10101010: 2.55V
Any other value: Generates MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by the above defined LVR
voltage value, an MCU reset will be generated. The reset operation will be activated
after 2~3 LIRC clock cycles. In this situation this register contents will remain the
same after such a reset occurs.
Any register value, other than the four defined values above, will also result in the
generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock
cycles. However in this situation this register contents will be reset to the POR value.
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
• CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
FSYSON: fSYS Control in IDLE Mode
Describe elsewhere.
Bit 6~3
Unimplemented, read as "0"
Bit 2
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Bit 1
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register
values. This in effect acts like a software reset function. This bit can only be cleared to
0 by the application program.
Bit 0
WRF: WDT Control register software reset flag
Describe elsewhere.
Watchdog Time-out Reset During Normal Operation
The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the
Watchdog time-out flag TO will be set to “1”.
Note: tRSTD is power-on delay, typical time=16.7ms
WDT Time-out Reset During Normal Operation Timing Chart
Watchdog Time-out Reset During SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details.
Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC. The tSST is 1~2 clock for the LIRC.
WDT Time-out Reset During SLEEP or IDLE Timing Chart
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO
PDF
0
0
Power-on reset
RESET Conditions
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
“u” stands for unchanged
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer Modules
Timer Modules will be turned off
Input/Output Ports
I/O ports will be setup as inputs and AN0~AN7 as A/D input pins
Stack Pointer
Stack Pointer will point to the top of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Reset
(Power On)
WDT Time-out
(Normal
Operation)
LVR Reset
WDT Time-out
(SLEEP/IDLE)
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
---- ---0
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP
---- -xxx
- - - - - uuu
- - - - - uuu
- - - - - uuu
STATUS
--00 xxxx
- - 1 u uuuu
- - u u uuuu
- - 1 1 uuuu
SMOD
11 0 - 0 0 1 0
11 0 - 0 0 1 0
11 0 - 0 0 1 0
u uu - uuuu
LVDC
--00 -000
--00 -000
--00 -000
- - uu - uuu
INTEG
---- 0000
---- 0000
---- 0000
- - - - uuuu
INTC0
-000 0000
-000 0000
-000 0000
- uuu uuuu
INTC1
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC2
-000 -000
-000 -000
-000 -000
- uuu - uuu
MFI0
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI1
--00 --00
--00 --00
--00 --00
- - uu - - uu
MFI2
--00 --00
--00 --00
--00 --00
- - uu - - uu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PAWU
0000 0000
0000 0000
0000 0000
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBPU
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMPC
11 0 0 0 0 0 0
11 0 0 0 0 0 0
11 0 0 0 0 0 0
uuuu uuuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
Register
Rev. 1.10
TBC
0 0 11 - 111
0 0 11 - 111
0 0 11 - 111
uuuu - uuu
EEA
--00 0000
--00 0000
--00 0000
- - uu uuuu
EED
0000 0000
0000 0000
0000 0000
uuuu uuuu
EEC
---- 0000
---- 0000
---- 0000
- - - - uuuu
ADRL (ADRFS=0)
xxxx ----
xxxx ----
xxxx ----
uuuu - - - -
ADRL (ADRFS=1)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=0)
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRH (ADRFS=1)
---- xxxx
---- xxxx
---- xxxx
- - - - uuuu
ADCR0
0 11 0 0 0 0 0
0 11 0 0 0 0 0
0 11 0 0 0 0 0
uuuu uuuu
ADCR1
00-0 -000
00-0 -000
00-0 -000
uu - u - uuu
ACERL
1111 1111
1111 1111
1111 1111
uuuu uuuu
CTRL
0--- -x00
0--- -000
0--- -000
u - - - - uuu
LVRC
0101 0101
0101 0101
0101 0101
uuuu uuuu
TM0C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
52
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Reset
(Power On)
WDT Time-out
(Normal
Operation)
LVR Reset
WDT Time-out
(SLEEP/IDLE)
TM0C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0DH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0AH
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM0RP
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1C0
0000 0---
0000 0---
0000 0---
uuuu u - - -
TM1C1
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1DH
---- --00
---- --00
---- --00
- - - - - - uu
TM1AL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1AH
---- --00
---- --00
---- --00
- - - - - - uu
TM1RPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
TM1RPH
---- --00
---- --00
---- --00
- - - - - - uu
CPR
---0 0000
---0 0000
---0 0000
- - - u uuuu
OCPREF
0000 0000
0000 0000
0000 0000
uuuu uuuu
OVPREF
--00 0000
--00 0000
--00 0000
- - uu uuuu
OCVPR0
0000 0000
0000 0000
0000 0000
uuuu uuuu
OCVPR1
000- 0000
000- 0000
000- 0000
uuu - uuuu
OCVPR2
0010 0000
0010 0000
0010 0000
uuuu uuuu
OCVPR3
0010 0000
0010 0000
0010 0000
uuuu uuuu
OCVPR4
0010 0000
0010 0000
0010 0000
uuuu uuuu
OCVPR5
---- -xxx
---- -xxx
---- -xxx
- - - - - uuu
Register
Note: “-” not implement
“u” stands for “unchanged”
“x” stands for “unknown”
Rev. 1.10
53
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output
designation of every pin fully under user program control, pull-high selections for all ports and
wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a
wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA and PB. These I/O
ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used for input and output operations. For input
operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge
of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is
latched and remains unchanged until the output latch is rewritten.
Bit
Register
Name
7
6
5
4
3
2
1
0
PA
D7
D6
D5
D4
D3
D2
D1
D0
PAC
D7
D6
D5
D4
D3
D2
D1
D0
PAPU
D7
D6
D5
D4
D3
D2
D1
D0
PAWU
D7
D6
D5
D4
D3
D2
D1
D0
PB
D7
D6
D5
D4
D3
D2
D1
D0
PBC
D7
D6
D5
D4
D3
D2
D1
D0
PBPU
D7
D6
D5
D4
D3
D2
D1
D0
Note: The I/O lines, PB3~PB5, are not connected to the external pins for both HT45FH4MA and
HT45FH4MA-1 devices.
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the
use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when
configured as an input have the capability of being connected to an internal pull-high resistor. These
pull-high resistors are selected using registers PAPU~PBPU, and are implemented using weak
PMOS transistors.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
I/O Port A bit7~ bit 0 Pull-High Control
0: Disable
1: Enable
PBPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
Rev. 1.10
I/O Port B bit 7~ bit 0 Pull-High Control
0: Disable
1: Enable
54
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves
power, a feature that is important for battery and other low-power applications. Various methods
exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port
A pins from high to low. This function is especially suitable for applications that can be woken up
via external switches. Each pin on Port A can be selected individually to have this wake-up feature
using the PAWU register.
PAWU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
I/O Port A bit 7 ~ bit 0 Wake Up Control
0: Disable
1: Enable
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PBC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to function as an input, the corresponding bit of the
control register must be written as a “1”. This will then allow the logic state of the input pin to be
directly read by instructions. When the corresponding bit of the control register is written as a “0”,
the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it should be noted that the program will in fact
only read the status of the output data latch and not the actual logic status of the output pin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7 ~ 0
I/O Port A bit 7 ~ bit 0 Input/Output Control
0: Output
1: Input
PBC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7 ~ 0
Rev. 1.10
I/O Port B bit 7~bit 0 Input/Output Control
0: Output
1: Input
55
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared
structures does not permit all types to be shown.
 
     Generic Input/Output Structure
 €  
 ­
­
   
A/D Input/Output Structure
Rev. 1.10
56
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Programming Considerations
Within the user program, one of the first things to consider is port initialisation. After a reset, all of
the I/O data and port control registers will be set high. This means that all I/O pins will default to
an input state, the level of which depends on the other connected circuitry and whether pull-high
selections have been chosen. If the port control registers, PAC~PBC, are then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated
port data registers, PA~PB, are first programmed. Selecting which pins are inputs and which are
outputs can be achieved byte-wide by loading the correct values into the appropriate port control
register or by programming individual bits in the port control register using the “SET [m].i” and
“CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write
operation takes place. The microcontroller must first read in the data on the entire port, modify it to
the required new bit values and then rewrite this data back to the output ports.
Read/Wite Timing
Port A has the additional capability of providing wake-up functions. When the device is in the
SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high
to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this
function.
Timer Modules – TM
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions the device includes several Timer Modules,
abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide
operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output
as well as being the functional unit for the generation of PWM signals. Each of the TMs has two
individual interrupts. The addition of input and output pins for each TM ensures that users are
provided with timing units with a wide and flexible range of features.
The common features of the different TM types are described here with more detailed information
provided in the individual Standard and periodic TM section.
Introduction
The device contains a 16-bit Standard TM and a 10-bit Periodic TM, each TM having a reference
name of TM0 and TM1. Although similar in nature, the different TM types vary in their feature
complexity. The common features to the Standard and Periodic TMs will be described in this section
and the detailed operation will be described in corresponding sections. The main features of the
Standard TM are summarised in the accompanying table.
Rev. 1.10
57
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
STM
PTM
Timer/Counter
Function
√
√
I/P Capture
√
√
Compare Match Output
√
√
PWM Channels
1
1
Single Pulse Output
PWM Alignment
PWM Adjustment Period & Duty
1
1
Edge
Edge
Duty or Period
Duty or Period
TM Function Summary
TM0
TM1
16-bit STM
10-bit PTM
TM Name/Type Reference
TM Operation
The two different types of TMs offer a diverse range of functions, from simple timing operations
to PWM signal generation. The key to understanding how the TM operates is to see it in terms of
a free running counter whose value is then compared with the value of pre-programmed internal
comparators. When the free running counter has the same value as the pre-programmed comparator,
known as a compare match situation, a TM interrupt signal will be generated which can clear the
counter and perhaps also change the condition of the TM output pin. The internal TM counter is
driven by a user selectable clock source, which can be an internal clock or an external pin.
TM Clock Source
The clock source which drives the main counter in each TM can originate from various sources.
The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM
control registers. The clock source can be a ratio of the system clock fSYS or the internal high clock
fH, the fTBC clock source or the external TCKn pin. The TCKn pin clock source is used to allow an
external signal to drive the TM as an external clock source or for event counting.
TM Interrupts
The two different types of TMs have two internal interrupts, the internal comparator A or comparator
P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is
generated, it can be used to clear the counter and also to change the state of the TM output pin.
Rev. 1.10
58
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TM External Pins
Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM
input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in
the TMnC0 register. This external TM input pin allows an external clock source to drive the internal
TM. This external TM input pin is shared with other functions but will be connected to the internal
TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a
rising or falling active edge.
The TMs each have one or two output pins. When the TM is in the Compare Match Output Mode,
these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare
match situation occurs. The external TPn output pin is also the pin where the TM generates the
PWM output waveform. As the TM output pins are pin-shared with other function, the TM output
function must first be setup using registers. A single bit in one of the registers determines if its
associated pin is to be used as an external TM output pin or if it is to have another function. The
number of output pins for each TM type is different, the details are provided in the accompanying
table.
STM and PTM output pin names have an “_n” suffix. Pin names that include a “_0” or “_1” suffix
indicate that they are from a TM with multiple output pins. This allows the TM to generate a
complimentary output pair, selected using the I/O register data bits.
TM0
TM1
HT45F4MA
Device
TP0_0, TP0_1
TP1_0, TP1_1
HT45FH4MA/HT45FH4MA-1
TP0_0, TP0_1
TP1_1
TM Output Pins
Note: The TP1_0 signal, which is pin-shared with the PB3 pin, is only used to be internally
connected to the level shift enable control input for the HT45FH4MA device and is not
bonded to the external TM output pin for both the HT45FH4MA and HT45FH4MA-1 devices.
Rev. 1.10
59
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TM Input/Output Pin Control Register
Selecting to have a TM input/output or whether to retain its other shared function is implemented
using one register, with a single bit in each register corresponding to a TM input/output pin. Setting
the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain
its original other function.
TM0 Function Pin Control Block Diagram
              TM1 Function Pin Control Block Diagram
Rev. 1.10
60
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TMPC Register
Rev. 1.10
Bit
Register
Name
7
6
Name
OUTHN
OUTLN
R/W
R/W
R/W
R/W
R/W
POR
1
1
0
0
5
4
OUTCP1 OUTCP0
3
2
1
0
T1CP1
T1CP0
T0CP1
T0CP0
R/W
R/W
R/W
R/W
0
0
0
0
Bit 7
OUTHN: OUTH signal inverting control
0: Non-inverted
1: Inverted
This bit is used to control whether the OUTH signal is inverted or not before output.
Bit 6
OUTLN: OUTL signal inverting control
0: Non-inverted
1: Inverted
This bit is used to control whether the OUTL signal is inverted or not before output.
Bit 5~4
OUTCP [1:0]: OUTH and OUTL pin control
00: Normal I/O function, i.e., PB5 and PB4
01: PB5 and OUTH
10: OUTL and PB4
11: OUTL and OUTH
If these bits are set to “11”, the dead time circuitry will be automatically enabled.
If these bits are set to a value except “11”, then the dead time circuitry will be
automatically disabled.
Note that the PB5/OUTL and PB4/OUTH lines are not bonded to the external pins and
internally connected to the level shift inputs for the HT45FH4MA and HT45FH4MA-1
devices.
Bit 3
T1CP1: TP1_1 pin control
0: TP1_1 pin is disabled
1: TP1_1 pin is enabled
Bit 2
T1CP0: TP1_0 pin control
0: TP1_0 pin is disabled
1: TP1_0 pin is enabled
Note that the TP1_0 line which is pin-shared with I/O line PB3 is internally connected
to the level shift enable control input for the HT45FH4MA device. This signal is
not bonded to the external pin and can not be used as the TM output pin for both the
HT45FH4MA and HT45FH4MA-1 devices.
Bit 1
T0CP1: TP0_1 pin control
0: TP0_1 pin is disabled
1: TP0_1 pin is enabled
Bit 0
T0CP0: TP0_0 pin control
0: TP0_0 pin is disabled
1: TP0_0 pin is enabled
61
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Programming Considerations
The TM Counter Registers, the Capture/Compare CCRA registers and the TM1 CCRP registers,
being either 16-bit or 10-bit, all have a low and high byte structure. The high bytes can be directly
accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing
to these register pairs must be carried out in a specific way. The important point to note is that
data transfer to and from the 8-bit buffer and its related low byte only takes place when a write
or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers
are implemented in the way shown in the following diagram and accessing these register pairs is
carried out in a specific way described above, it is recommended to use the “MOV” instruction to
access the CCRA or CCRP low byte registers, named TMxAL or TMxRPL, using the following
access procedures. Accessing the CCRA or CCRP low byte register without following these access
procedures will result in unpredictable values.
     The following steps show the read and write procedures:
• Writing Data to CCRA or CCRP
♦♦
Step 1. Write data to Low Byte TMxAL or TMxRPL
– note that here data is only written to the 8-bit buffer.
♦♦
Step 2. Write data to High Byte TMxAH or TMxRPH
– here data is written directly to the high byte registers and simultaneously data is latched from
the 8-bit buffer to the Low Byte registers.
• Reading Data from the Counter Registers and CCRA or CCRP
Rev. 1.10
♦♦
Step 1. Read data from the High Byte TMxDH, TMxAH or TMxRPH
– here data is read directly from the High Byte registers and simultaneously data is latched
from the Low Byte register into the 8-bit buffer.
♦♦
Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxRPL
– this step reads data from the 8-bit buffer.
62
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Standard Type TM – STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM
can also be controlled with an external input pin and can drive two external output pins. These two
external output pins can be the same signal or the inverse signal.
Name
TM No.
TM Input Pin
TM Output Pin
16-bit STM
0
TCK0
TP0_0, TP0_1
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‚   Standard Type TM Block Diagram (n=0)
Standard TM Operation
At its core is a 16-bit count-up counter which is driven by a user selectable internal or external clock
source. There are also two internal comparators with the names, Comparator A and Comparator
P. These comparators will compare the value in the counter with CCRP and CCRA registers. The
CCRP is 8-bits wide whose value is compared with the highest 8 bits in the counter while the CCRA
is the 16 bits and therefore compares with all counter bits.
The only way of changing the value of the 16-bit counter using the application program, is to
clear the counter by changing the T0ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Standard
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.
Standard Type TM Register Description
Overall operation of the Standard TM is controlled using seven registers. A read only register pair
exists to store the internal counter 16-bit value, while a read/write register pair exists to store the
internal 16-bit CCRA value. The remaining two registers are control registers which setup the
different operating and control modes.
Rev. 1.10
63
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM0C0
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
—
—
—
TM0C1
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
TM0DL
D7
D6
D5
D4
D3
D2
D1
D0
TM0DH
D15
D14
D13
D12
D11
D10
D9
D8
TM0AL
D7
D6
D5
D4
D3
D2
D1
D0
TM0AH
D15
D14
D13
D12
D11
D10
D9
D8
TM0RP
D7
D6
D5
D4
D3
D2
D1
D0
16-bit Standard TM Register List
TM0C0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
T0PAU
T0CK2
T0CK1
T0CK0
T0ON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
T0PAU: TM0 Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6 ~ 4
T0CK2 ~ T0CK0: Select TM0 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fTBC
110: TCK0 rising edge clock
111: TCK0 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
T0ON: TM0 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from
low to high.
Bit 2 ~ 0
Unimplemented, read as "0"
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TM0C1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
T0M1
T0M0
T0IO1
T0IO0
T0OC
T0POL
T0DPX
T0CCLR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 6
T0M1~T0M0: Select TM0 Operating Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the bits. In the Timer/
Counter Mode, the TM output pin control must be disabled.
Bit 5 ~ 4
T0IO1~T0IO0: Select TM0 output function Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: Force inactive state
01: Force active state
10: PWM output
11: Single pulse output
Capture Input Mode
00: Input capture at rising edge of TM capture input pin
01: Input capture at falling edge of TM capture input pin
10: Input capture at falling/rising edge of TM capture input pin
11: Input capture disabled
Timer/counter Mode
Unused
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the T0IO1~T0IO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The
TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the T0IO1~T0IO0 bits
are both zero, then no change will take place on the output. The initial value of the TM
output pin should be setup using the T0OC bit. Note that the output level requested by
the T0IO1~T0IO0 bits must be different from the initial value setup using the T0OC
bit otherwise no change will occur on the TM output pin when a compare match
occurs. After the TM output pin changes state it can be reset to its initial level by
changing the level of the T0ON bit from low to high.
In the PWM Mode, the T0IO1 and T0IO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the T0IO1 and T0IO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the T0IO1 and T0IO0 bits are changed when the TM is
running.
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August 08, 2014
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Power Bank 8-Bit Flash MCU
Bit 3
T0OC: TM0 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2
T0POL: TM0 Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TM output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
Bit 1
T0DPX: TM0 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
Bit 0
T0CCLR: Select TM0 Counter clear condition
0: TM Comparatror P match 1: TM Comparatror A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not
used in the PWM, Single Pulse or Input Capture Mode.
TM0DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
TM0DL: TM0 Counter Low Byte Register bit 7 ~ bit 0
TM 16-bit Counter bit 7 ~ bit 0
TM0DH Register
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
Rev. 1.10
TM0DH: TM0 Counter High Byte Register bit 7 ~ bit 0
TM 16-bit Counter bit 15 ~ bit 8
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TM0AL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7 ~ 0
TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0
TM 16-bit CCRA bit 7 ~ bit 0
TM0AH Register
Bit
7
6
5
4
3
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
TM0AH: TM0 CCRA High Byte Register bit 7 ~ bit 0
TM 16-bit CCRA bit 15 ~ bit 8
TM0RP Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
Rev. 1.10
TM0RP: TM0 CCRP High Byte Register bit 7 ~ bit 0
TM0 CCRP 8-bit register, compared with the TM0 Counter bit 15 ~ bit 8. Comparator P Match Period
0: 65536 TM0 clocks
1~255: 256 × (1~255) TM0 clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the T0CCLR bit is set to
zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Standard Type TM Operating Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the T0M1 and T0M0 bits in the TM0C1 register.
Compare Output Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the T0CCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both T0AF and T0PF interrupt request flags for Comparator Aand
Comparator P respectively, will both be generated.
If the T0CCLR bit in the TM0C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the T0AF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
T0CCLR is high no T0PF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a T0AF interrupt request flag
is generated after a compare match occurs from Comparator A. The T0PF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
T0IO1 and T0IO0 bits in the TM0C1 register. The TM output pin can be selected using the T0IO1
and T0IO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
T0ON bit changes from low to high, is setup using the T0OC bit. Note that if the T0IO1 and T0IO0
bits are zero then no pin change will take place.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Co�nter Val�e
CCRP = 0
TnCCLR = 0; TnM[1:0] = 00
Co�nter
overflow
0xFFFF
CCRP > 0
Co�nter cleared by CCRP val�e
CCRP > 0
CCRP
Pa�se Res�me
CCR�
Stop
Co�nter
Reset
Time
TnON
TnP�U
TnPOL
CCRP Int.
Fla� TnPF
CCR� Int.
Fla� Tn�F
TM O/P Pin
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t To��le
with Tn�F fla�
Now TnIO1� TnIO0 = 10
�ctive Hi�h O�tp�t
Select
O�tp�t not affected by
Tn�F fla�. Remains Hi�h
�ntil reset by TnON bit
Here TnIO1� TnIO0 = 11
To��le O�tp�t Select
O�tp�t inverts
when TnPOL is hi�h
O�tp�t Pin
Reset to initial val�e
O�tp�t controlled
by other pin-shared f�nction
Compare Match Output Mode -- TnCCLR = 0
Note: 1. With TnCCLR = 0 a Comparator P match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON bit rising edge
4. n = 0
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TnCCLR = 1; TnM[1:0] = 00
Co�nter Val�e
CCR� = 0
Co�nter overflows
CCR� > 0 Co�nter cleared by CCR� val�e
0xFFFF
CCR� = 0
CCR�
Pa�se Res�me
Co�nter
Reset
Stop
CCRP
Time
TnON
TnP�U
TnPOL
No Tn�F fla�
�enerated on
CCR� overflow
CCR� Int.
Fla� Tn�F
CCRP Int.
Fla� TnPF
TM O/P Pin
O�tp�t does
not chan�e
TnPF not
�enerated
O�tp�t Pin set
to Initial Level
Low if TnOC = 0
O�tp�t not affected by
Tn�F fla� remains Hi�h
�ntil reset by TnON bit
O�tp�t To��le
with Tn�F fla�
Now TnIO1� TnIO0 = 10
�ctive Hi�h O�tp�t
Select
O�tp�t controlled by
other pin-shared f�nction
O�tp�t inverts
when TnPOL is hi�h
O�tp�t Pin
Reset to initial val�e
Here TnIO1� TnIO0 = 11
To��le O�tp�t Select
Compare Match Output Mode -- TnCCLR = 1
Note: 1. With TnCCLR = 1 a Comparator A match will clear the counter
2. The TM output pin controlled only by the TnAF flag
3. The output pin reset to initial state by a TnON rising edge
4. The TnPF flags is not generated when TnCCLR = 1
5. n = 0
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Timer/Counter Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 10 respectively and
also the T0IO1 and T0IO0 bits should be set to 10 respectively. The PWM function within the TM is
useful for applications which require functions such as motor control, heating control, illumination
control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a
square wave AC waveform can be generated with varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the T0CCLR bit has no effect as the PWM
period. Both of the CCRAand CCRP registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. Which register is used to control either frequency or duty cycle
is determined using the T0DPX bit in the TM0C1 register.
The PWM waveform frequency and duty cycle can therefore be controlled by the values in the
CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be
generated when a compare match occurs from either Comparator A or Comparator P. The T0OC bit
In the TM0C1 register is used to select the required polarity of the PWM waveform while the two
T0IO1 and T0IO0 bits are used to enable the PWM output or to force the TM output pin to a fixed
high or low level. The T0POL bit is used to reverse the polarity of the PWM output waveform.
• 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=0
CCRP
1~255
Period
CCRP×256
Duty
0
65536
CCRA
If fSYS = 7.5MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128,
The STM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 3.66kHz, duty = 128/512= 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
• 16-bit STM, PWM Mode, Edge-aligned Mode, T0DPX=1
CCRP
1~255
CCRA
Period
Duty
0
CCRP×256
65536
The PWM output period is determined by the CCRA register value together with the TM clock
while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0.
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Co�nter Val�e
Co�nter Cleared
by CCRP
TnDPX = 0; TnM [1:0] = 10
CCRP
Pa�se Res�me
Co�nter reset
Co�nter Stop when TnON
if TnON bit low ret�rns hi�h
CCR�
Time
TnON
TnP�U
TnPOL
CCR� Int.
Fla� Tn�F
CCRP Int.
Fla� TnPF
TM O/P Pin
TnOC = 1
TM O/P Pin
TnOC = 0
PWM D�ty Cycle
set by CCR�
PWM Period
set by CCRP
PWM res�mes
operation
O�tp�t controlled by
O�tp�t Inverts
other pin-shared f�nction
When TnPOL = 1
PWM Mode -- TnDPX = 0
Note: 1. Here TnDPX = 0 - Counter cleared by CCRP
2. A counter clear sets PWM Period
3. The internal PWM function continues running even when TnIO[1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
5. n = 0
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Co�nter Val�e
Co�nter Cleared
by CCR�
TnDPX = 1; TnM [1:0] = 10
CCR�
Co�nter reset
Co�nter Stop when TnON
if TnON bit low ret�rns hi�h
Pa�se Res�me
CCRP
Time
TnON
TnP�U
TnPOL
CCR� Int.
Fla� Tn�F
CCRP Int.
Fla� TnPF
TM O/P Pin
TnOC = 1
TM O/P Pin
TnOC = 0
PWM res�mes
operation
PWM D�ty Cycle
set by CCRP
PWM Period
set by CCR�
O�tp�t controlled by
other pin-shared f�nction
O�tp�t Inverts
When TnPOL = 1
PWM Mode -- TnDPX = 1
Note: 1. Here TnDPX = 1 - Counter cleared by CCRA
2. A counter clear sets PWM Period
3. The internal PWM function continues even when TnIO[1:0] = 00 or 01
4. The TnCCLR bit has no influence on PWM operation
5. n = 0
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Single Pulse Mode
To select this mode, bits T0M1 and T0M0 in the TM0C1 register should be set to 10 respectively
and also the T0IO1 and T0IO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the T0ON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the T0ON bit
can also be made to automatically change from low to high using the external TCK0 pin, which will
in turn initiate the Single Pulse output. When the T0ON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The T0ON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
T0ON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
            Single Pulse Generation (n= 0)
Rev. 1.10
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Power Bank 8-Bit Flash MCU
TnM [1:0] = 10; TnIO [1:0] = 11
Co�nter Stopped
by CCR�
Co�nter Val�e
CCR�
Pa�se
Co�nter reset
Co�nter Stops when TnON
by software
ret�rns hi�h
Res�me
CCRP
Time
TnON
TCn pin
Software
Tri��er
Cleared by
CCR� match
��to. set
by TCKn pin
Software
Tri��er
Software
Tri��er
Software
Clear
Software
Tri��er
TCKn pin
Tri��er
TnP�U
TnPOL
CCRP Int.
Fla� TnPF
No CCRP
Interr�pt
�enerated
CCR� Int.
Fla� Tn�F
TnIO1� TnIO0 = 00
O�tp�t Inactive
TnIO1� TnIO0 = 11 Sin�le P�lse O�tp�t
TnIO1� TnIO0 = 11
TM O/P Pin
TnOC = 1
TM O/P Pin
TnOC = 0
O�tp�t Inverts
When TnPOL = 1
P�lse Width
set by CCR�
Single Pulse Mode
Note: 1. Counter stopped by CCRA match
2. CCRP is not used
3. The pulse is triggered by the TCKn pin or setting the TnON bit high
4. A TCKn pin active edge will automatically set the TnON bit high
5. In the Single Pulse Mode, TnIO [1:0] must be set to “11” and can not be changed.
6. n = 0
Rev. 1.10
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Power Bank 8-Bit Flash MCU
However a compare match from Comparator A will also automatically clear the T0ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter
can only be reset back to zero when the T0ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The T0CCLR and T0DPX bits are not used in
this Mode.
Capture Input Mode
To select this mode bits T0M1 and T0M0 in the TM0C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the TP0_0 or TP0_1 pin, whose active edge can be either a rising edge, a falling edge or
both rising and falling edges; the active edge transition type is selected using the T0IO1 and T0IO0
bits in the TM0C1 register. The counter is started when the T0ON bit changes from low to high
which is initiated using the application program.
When the required edge transition appears on the TP0_0 or TP0_1 pin the present value in the
counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what
events occur on the TP0_0 or TP0_1 pin the counter will continue to free run until the TnON bit
changes from high to low. When a CCRP compare match occurs the counter will reset back to zero;
in this way the CCRP value can be used to control the maximum counter value. When a CCRP
compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the
number of overflow interrupt signals from the CCRP can be a useful method in measuring long
pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TP0_0 or TP0_1
pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set
high, then no capture operation will take place irrespective of what happens on the TP0_0 or TP0_1
pin, however it must be noted that the counter will continue to run.
As the TP0_0 or TP0_1 pin is pin shared with other functions, care must be taken if the TM is in the
Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The T0CCLR and T0DPX bits are not used in
this Mode.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TnM [1:0] = 01
Co�nter
Val�e
Co�nter
overflow
CCRP
Stop
Co�nter
Reset
YY
XX
Pa�se Res�me
Time
TnON
ed�e
TnP�U
TM Capt�re
Pin TPn_x
�ctive
ed�e
�ctive
ed�e
�ctive
CCR� Int.
Fla� Tn�F
CCRP Int.
Fla� TnPF
CCR�
Val�e
TnIO [1:0]
Val�e
XX
00 - Risin� ed�e
YY
01 - Fallin� ed�e
XX
YY
10 - Both ed�es
11 - Disable Capt�re
Capture Input Mode
Note: 1. TnM[1:0] = 01 and active edge set by the TnIO[1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. The TnCCLR bit is not used
4. No output function - TnOC and TnPOL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero
6. n = 0
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Periodic Type TM – PTM
The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/
Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can
also be controlled with an external input pin and can drive one or two external output pins.
Name
TM No.
TM Input Pin
TM Output Pin
HT45F4MA
Device
10-bit PTM
1
TCK1
TP1_0, TP1_1
HT45FH4MA/HT45FH4MA-1
10-bit PTM
1
TCK1
TP1_1
Periodic TM Operation
At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock
source. There are two internal comparators with the names, Comparator A and Comparator P. These
comparators will compare the value in the counter with the CCRA and CCRP registers.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the T1ON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control the output pin. All operating setup conditions are
selected using relevant internal registers.
„…
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Periodic Type TM Block Diagram (n=1) – HT45F4MA
Rev. 1.10
78
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
„…
‡
† …
„…
† …
„ˆ  ‰
„ˆ ‰ ‡
„ Š „ˆ
   ‚

€ 
€ 

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‹ ƒ Œ ‚ ‚ Œ   Œ  Ž  ‘
Periodic Type TM Block Diagram (n=1) – HT45FH4MA/HT45FH4MA-1
Periodic Type TM Register Description
Overall operation of the Periodic TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which
setup the different operating and control modes.
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TM1C0
T1PAU
T1CK2
T1CK1
T1CK0
T1ON
—
—
—
TM1C1
T1M1
T1M0
T1IO1
T1IO0
T1OC
T1POL
TM1DL
D7
D6
D5
D4
D3
D2
D1
D0
TM1DH
—
—
—
—
—
—
D9
D8
T1CAPTS T1CCLR
TM1AL
D7
D6
D5
D4
D3
D2
D1
D0
TM1AH
—
—
—
—
—
—
D9
D8
TM1RPL
D7
D6
D5
D4
D3
D2
D1
D0
TM1RPH
—
—
—
—
—
—
D9
D8
10-bit Periodic TM Register List
Rev. 1.10
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Power Bank 8-Bit Flash MCU
TM1C0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
T1PAU
T1CK2
T1CK1
T1CK0
T1ON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
T1PAU: TM1 Counter Pause Control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TM will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6 ~ 4
T1CK2 ~ T1CK0: Select TM1 Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: fH
110: TCK1 rising edge clock
111: TCK1 falling edge clock
These three bits are used to select the clock source for the TM. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source fSYS is
the system clock, while fH and fTBC are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
T1ON: TM1 Counter On/Off Control
0: Off
1: On
This bit controls the overall on/off function of the TM. Setting the bit high enables the
counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the
counter from counting and turn off the TM which will reduce its power consumption.
When the bit changes state from low to high the internal counter value will be reset to
zero, however when the bit changes from high to low, the internal counter will retain
its residual value until the bit returns high again.
If the TM is in the Compare Match Output Mode then the TM output pin will be reset
to its initial condition, as specified by the TM Output control bit, when the bit changes
from low to high.
Bit 2~0
Unimplemented, read as "0"
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TM1C1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
Name
T1M1
T1M0
T1IO1
T1IO0
T1OC
T1POL
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
T1CAPTS T1CCLR
Bit 7~6
T1M1~T1M0: Select TM1 Operation Mode
00: Compare Match Output Mode
01: Capture Input Mode
10: PWM Mode or Single Pulse Output Mode
11: Timer/Counter Mode
These bits setup the required operating mode for the TM. To ensure reliable operation
the TM should be switched off before any changes are made to the T1M1 and T1M0
bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T1IO1~T1IO0: Select TP1_0, TP1_1 output function
Compare Match Output Mode
00: No change
01: Output low
10: Output high
11: Toggle output
PWM Mode/Single Pulse Output Mode
00: PWM Output inactive state
01: PWM Output active state
10: PWM output
11: Single pulse output
Capture input Mode
00: Input capture at rising edge of TP1_0, TP1_1
01: Input capture at falling edge of TP1_0, TP1_1
01: Input capture at falling/rising edge of TP1_0, TP1_1
11: Input capture disabled
Timer/Counter Mode
Unused.
These two bits are used to determine how the TM output pin changes state when a
certain condition is reached. The function that these bits select depends upon in which
mode the TM is running.
In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the
TM output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present
state when a compare match occurs from the Comparator A. When the bits are both
zero, then no change will take place on the output. The initial value of the TM output
pin should be setup using the T1OC bit in the TM1C1 register. Note that the output
level requested by the T1IO1 and T1IO0 bits must be different from the initial value
setup using the T1OC bit otherwise no change will occur on the TM output pin when
a compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the T1ON bit from low to high.
In the PWM Mode, the T1IO1 and T1IO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the T1IO1 and T1IO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the T1IO1 and T1IO0 bits are changed when the TM is
running.
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Power Bank 8-Bit Flash MCU
Bit 3
T1OC: TP1_0, TP1_1 output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
Bit 2
T1POL: TP1_0, TP1_1 output Polarity control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1_0 and TP1_1 output pins. When the bit is set
high the TM output pin will be inverted and not inverted when the bit is zero. It has no
effect if the TM is in the Timer/Counter Mode.
Bit 1
T1CAPTS: TM1 capture trigger source select
0: From TP1 pin
1: From TCK1 pin
Bit 0
T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparator P match
1: TM1 Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T1CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not
used in the PWM Mode, Single Pulse or Input Capture Mode.
TM1DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM1DL: TM1 Counter Low Byte Register bit 7 ~ bit 0
TM1 10-bit Counter bit 7 ~ bit 0
TM1DH Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
TM1DH: TM1 Counter Low Byte Register bit 1 ~ bit 0
TM1 10-bit Counter bit 9 ~ bit 8
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August 08, 2014
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Power Bank 8-Bit Flash MCU
TM1AL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TM1AL: TM1 CCRA Low Byte Register bit 7 ~ bit 0
TM1 10-bit CCRA bit 7 ~ bit 0
TM1AH Register
Bit
7
6
5
4
3
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
TM1AH: TM1 CCRA Low Byte Register bit 1 ~ bit 0
TM1 10-bit CCRA bit 9 ~ bit 8
TM1RPL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TM1RPL: TM1 CCRP Low Byte Register bit 7 ~ bit 0
TM1 10-bit CCRP bit 7 ~ bit 0
TM1RPH Register
Bit
Rev. 1.10
7
6
5
4
3
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
TM1RPH: TM1 CCRP Low Byte Register bit 1 ~ bit 0
TM1 10-bit CCRP bit 9 ~ bit 8
83
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Periodic Type TM Operation Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the T1M1 and T1M0 bits in the TM1C1 register.
Compare Match Output Mode
To select this mode, bits T1M1 and T1M0 in the TM1C1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the T1CCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both T1AF and T1PF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the T1CCLR bit in the TM1C1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the T1AF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
T1CCLR is high no T1PF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a T1AF interrupt request flag
is generated after a compare match occurs from Comparator A. The T1PF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
T1IO1 and T1IO0 bits in the TM1C1 register. The TM output pin can be selected using the T1IO1
and T1IO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
T1ON bit changes from low to high, is setup using the T1OC bit. Note that if the T1IO1 and T1IO0
bits are zero then no pin change will take place.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Counter Value
Counter overflow
CCRP=0
0x3FF
T1CCLR = 0; T1M [1:0] = 00
CCRP > 0
Counter cleared by CCRP value
CCRP > 0
Counter
Restart
Resume
CCRP
Pause
CCRA
Stop
Time
T1ON
T1PAU
T1POL
CCRP Int.
Flag T1PF
CCRA Int.
Flag T1AF
TM O/P Pin
Output pin set to
initial Level Low
if T1OC=0
Output not affected by T1AF
flag. Remains High until reset
by T1ON bit
Output Toggle with
T1AF flag
Here T1IO [1:0] = 11
Toggle Output select
Note T1IO [1:0] = 10
Active High Output select
Output Inverts
when T1POL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – T1CCLR=0
Note: 1. With T1CCLR=0 – A Comparator P match will clear the counter
2. The TM output pin is controlled only by the T1AF flag
3. The output pin is reset to its initial state by a T1ON bit rising edge
Rev. 1.10
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August 08, 2014
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Power Bank 8-Bit Flash MCU
Counter Value
T1CCLR = 1; T1M [1:0] = 00
CCRA = 0
Counter overflow
CCRA > 0 Counter cleared by CCRA value
0x3FF
CCRA=0
Resume
CCRA
Pause
Stop
Counter Restart
CCRP
Time
T1ON
T1PAU
T1POL
No T1AF flag
generated on
CCRA overflow
CCRA Int.
Flag T1AF
CCRP Int.
Flag T1PF
T1PF not
generated
Output does
not change
TM O/P Pin
Output pin set to
initial Level Low
if T1OC=0
Output not affected by
T1AF flag. Remains High
until reset by T1ON bit
Output Toggle with
T1AF flag
Here T1IO [1:0] = 11
Toggle Output select
Note T1IO [1:0] = 10
Active High Output select
Output Inverts
when T1POL is high
Output Pin
Reset to Initial value
Output controlled by
other pin-shared function
Compare Match Output Mode – T1CCLR=1
Note: 1. With T1CCLR=1 – A Comparator A match will clear the counter
2. The TM output pin is controlled only by the T1AF flag
3. The output pin is reset to its initial state by a T1ON bit rising edge
4. A T1PF flag is not generated when T1CCLR=1
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Timer/Counter Mode
To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 11 respectively.
The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode
generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output
pin is not used. Therefore the above description and Timing Diagrams for the Compare Match
Output Mode can be used to understand its function. As the TM output pin is not used in this mode,
the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 10 respectively
and also the T1IO1 and T1IO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the T1CCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The T1OC bit in the TM1C1 register is used to
select the required polarity of the PWM waveform while the two T1IO1 and T1IO0 bits are used to
enable the PWM output or to force the TM output pin to a fixed high or low level. The T1POL bit is
used to reverse the polarity of the PWM output waveform.
• 10-bit PTM, PWM Mode
Period
Duty
CCRP
CCRA
If fSYS=7.5MHz, TM clock source select fH, CCRP = 100 and CCRA=40,
The PTM PWM output frequency = fH/100=300kHz, duty=40/100=40%,
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Counter Value
T1M [1:0] = 10
Counter cleared
by CCRP
Counter Reset when
T1ON returns high
CCRP
Pause Resume
CCRA
Counter Stop if
T1ON bit low
Time
T1ON
T1PAU
T1POL
CCRA Int.
Flag T1AF
CCRP Int.
Flag T1PF
TM O/P Pin
(T1OC=1)
TM O/P Pin
(T1OC=0)
PWM Duty Cycle
set by CCRA
PWM Period
set by CCRP
PWM resumes
operation
Output controlled by
Output Inverts
other pin-shared function
when T1POL = 1
PWM Mode
Note: 1. Here Counter cleared by CCRP
2. A counter clear sets the PWM Period
3. The internal PWM function continues running even when T1IO [1:0] = 00 or 01
4. The T1CCLR bit has no influence on PWM operation
Rev. 1.10
88
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Single Pulse Output Mode
To select this mode, bits T1M1 and T1M0 in the TM1C1 register should be set to 10 respectively
and also the T1IO1 and T1IO0 bits should be set to 11 respectively. The Single Pulse Output Mode,
as the name suggests, will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to high transition of the T1ON bit, which can
be implemented using the application program. However in the Single Pulse Mode, the T1ON bit
can also be made to automatically change from low to high using the external TCK1 pin, which will
in turn initiate the Single Pulse output. When the T1ON bit transitions to a high level, the counter
will start running and the pulse leading edge will be generated. The T1ON bit should remain high
when the pulse is in its active state. The generated pulse trailing edge will be generated when the
T1ON bit is cleared to zero, which can be implemented using the application program or when a
compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the T1ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter
can only be reset back to zero when the T1ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The T1CCLR is not used in this Mode.
            Single Pulse Generation
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Counter Value
T1M [1:0] = 10 ; T1IO [1:0] = 11
Counter stopped
by CCRA
Counter Reset when
T1ON returns high
CCRA
Pause
Counter Stops
by software
Resume
CCRP
Time
T1ON
Software
Trigger
Auto. set by
TCK1 pin
Cleared by
CCRA match
TCK1 pin
Software
Trigger
Software
Trigger
Software
Software Trigger
Clear
TCK1 pin
Trigger
T1PAU
T1POL
CCRP Int.
Flag T1PF
No CCRP Interrupts
generated
CCRA Int.
Flag T1AF
TM O/P Pin
(T1OC=1)
TM O/P Pin
(T1OC=0)
Output Inverts
when T1POL = 1
Pulse Width
set by CCRA
Single Pulse Mode
Note: 1. Counter stopped by CCRA
2. CCRP is not used
3. The pulse is triggered by the TCK1 pin or by setting the T1ON bit high
4. A TCK1 pin active edge will automatically set the T1ON bit high
5. In the Single Pulse Mode, T1IO [1:0] must be set to “11” and can not be changed.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Capture Input Mode
To select this mode bits T1M1 and T1M0 in the TM1C1 register should be set to 01 respectively.
This mode enables external signals to capture and store the present value of the internal counter
and can therefore be used for applications such as pulse width measurements. The external signal is
supplied on the TP1 or TCK1 pin, selected by the T1CAPTS bit in the TM1C0 register. The input
pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active
edge transition type is selected using the T1IO1 and T1IO0 bits in the TM1C1 register. The counter
is started when the T1ON bit changes from low to high which is initiated using the application
program.
When the required edge transition appears on the TP1 or TCK1 pin the present value in the counter
will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events
occur on the TP1 or TCK1 pin the counter will continue to free run until the T1ON bit changes from
high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way
the CCRP value can be used to control the maximum counter value. When a CCRP compare match
occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow
interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The T1IO1
and T1IO0 bits can select the active trigger edge on the TP1 or TCK1 pin to be a rising edge, falling
edge or both edge types. If the T1IO1 and T1IO0 bits are both set high, then no capture operation
will take place irrespective of what happens on the TP1 or TCK1 pin, however it must be noted that
the counter will continue to run.
As the TP1 or TCK1 pin is pin shared with other functions, care must be taken if the TM1 is in the
Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin
may cause an input capture operation to be executed. The T1CCLR, T1OC and T1POL bits are not
used in this Mode.
Rev. 1.10
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Counter Value
T1M [1:0] = 01
Counter cleared
by CCRP
Counter Counter
Stop
Reset
CCRP
YY
Pause
Resume
XX
Time
T1ON
T1PAU
TM capture
pin TP1 or
TCK1
Active
edge
Active
edge
Active edge
CCRA Int.
Flag T1AF
CCRP Int.
Flag T1PF
CCRA
Value
T1IO [1:0]
Value
XX
00 – Rising edge
YY
01 – Falling edge
XX
10 – Both edges
YY
11 – Disable Capture
Capture Input Mode
Note: 1. T1M [1:0] = 01 and active edge set by the T1IO [1:0] bits
2. A TM Capture input pin active edge transfers the counter value to CCRA
3. T1CCLR bit not used
4. No output function – T1OC and T1POL bits are not used
5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero
Rev. 1.10
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Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic
systems. However, to properly process these signals by a microcontroller, they must first be
converted into digital signals by A/D converters. By integrating the A/D conversion electronic
circuitry into the microcontroller, the need for external components is reduced significantly with the
corresponding follow-on benefits of lower costs and reduced component space requirements.
A/D Overview
The device contains a multi-channel analog to digital converter which can directly interface to
external analog signals, such as that from sensors or other control signals and convert these signals
directly into a 12-bit digital value.
Input Channels
A/D Channel Select Bits
Input Pins
8
ACS4, ACS3~ACS0
AN0~AN7
The accompanying block diagram shows the overall internal structure of the A/D converter, together
with its associated registers.
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A/D Converter Structure
A/D Converter Register Description
Overall operation of the A/D converter is controlled using five registers. A read only register pair
exists to store the ADC data 12-bit value. The remaining three registers are control registers which
setup the operating and control function of the A/D converter.
Name
ADRL(ADRFS=0)
Bit
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
ADRL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
ADRH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
ADCR0
START
EOCB
ADOFF
ADRFS
ACS3
ACS2
ACS1
ACS0
ADCR1
ACS4
VBGEN
—
VREFS
—
ADCK2
ADCK1
ADCK0
ACERL
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
A/D Converter Register List
Rev. 1.10
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A/D Converter Data Registers – ADRL, ADRH
As the devices contain an internal 12-bit A/D converter, they require two data registers to store the
converted value. These are a high byte register, known as ADRH, and a low byte register, known
as ADRL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero.
ADRFS
0
1
ADRH
7
6
5
D11 D10 D9
0
0
0
4
D8
0
ADRL
3
2
1
0
7
D7
D6
D5
D4
D3
D11 D10 D9
D8
D7
6
5
4
3
2
1
0
D2
D1
D0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
A/D Data Registers
A/D Converter Control Registers – ADCR0, ADCR1, ACERL
To control the function and operation of the A/D converter, three control registers known as ADCR0,
ADCR1 and ACERL are provided. These 8-bit registers define functions such as the selection of
which analog channel is connected to the internal A/D converter, the digitised data format, the A/
D clock source as well as controlling the start function and monitoring the A/D converter end of
conversion status. The ACS3~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register
define the ADC input channel number. As the device contains only one actual analog to digital
converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It
is the function of the ACS4~ACS0 bits to determine which analog channel input signals or internal
1.25V is actually connected to the internal A/D converter.
The ACERL control register contains the ACE7~ACE0 bits which determine which pins on Port A
are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D
converter input. Setting the corresponding bit high will select the A/D input function, clearing the
bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an
A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In
addition, any internal pull-high resistors connected to these pins will be automatically removed if the
pin is selected to be an A/D input.
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ADCR0 Register
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
ADOFF
ADRFS
ACS3
ACS2
ACS1
ACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
0
0
0
0
0
Bit 7
START: Start the A/D conversion
0 → 1 → 0: start
0 → 1: reset the A/D converter and set EOCB to “1”
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
When the bit is set high the A/D converter will be reset.
Bit 6
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed.
When the conversion process is running the bit will be high.
Bit 5
ADOFF : ADC module power on/off control bit
0: ADC module power on
1: ADC module power off
This bit controls the power to the A/D internal function. This bit should be cleared
to zero to enable the A/D converter. If the bit is set high then the A/D converter will
be switched off reducing the device power consumption. As the A/D converter will
consume a limited amount of power, even when not executing a conversion, this may
be an important consideration in power sensitive battery powered applications.
Note: 1. It is recommended to set ADOFF= 1 before entering IDLE/SLEEP Mode for
saving power.
2. ADOFF= 1 will power down the ADC module.
Rev. 1.10
Bit 4
ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D data register section.
Bit 3 ~ 0
ACS3 ~ ACS0: Select A/D channel (when ACS4 is “0”)
0000: AN0
0001: AN1
0010: AN2
0011: AN3
0100: AN4
0101: AN5
0110: AN6
0111: AN7
1xxx: AN8 ( from OPA output for OCP )
These are the A/D channel select control bits. As there is only one internal hardware A/
D converter each of the eight A/D inputs must be routed to the internal converter using
these bits. If bit ACS4 in the ADCR1 register is set high then the internal 1.25V will be
routed to the A/D Converter.
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ADCR1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
ACS4
VBGEN
—
VREFS
—
ADCK2
ADCK1
ADCK0
R/W
R/W
R/W
—
R/W
—
R/W
R/W
R/W
POR
0
0
—
0
—
0
0
0
Bit 7
ACS4: Selecte Internal 1.25V as ADC input Control
0: Disable
1: Enable
This bit enables 1.25V to be connected to the A/D converter. The VBGEN bit must
first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D
converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to
the A/D converter and the other A/D input channels disconnected.
Bit 6
VBGEN: Internal 1.25V Control
0: Disable
1: Enable
This bit controls the internal Bandgap circuit on/off function to the A/D converter.
When the bit is set high the bandgap 1.25V voltage can be used by the A/D converter.
If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then
the bandgap reference circuit will be automatically switched off to conserve power.
When 1.25V is switched on for use by the A/D converter, a time tBG should be allowed
for the bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5
Unimplemented, read as "0"
Bit 4
VREFS: Selecte ADC reference voltage
0: Internal ADC power
1: VREF pin
This bit is used to select the reference voltage for the A/D converter. If the bit is high
then the A/D converter reference voltage is supplied on the external VREF pin. If the
pin is low then the internal reference is used which is taken from the power supply pin
VDD.
Bit 3
Unimplemented, read as "0"
Bit 2 ~ 0
ADCK2 ~ ADCK0: Select ADC clock source
000: fSYS
001: fSYS/2
010: fSYS/4
011: fSYS/8
100: fSYS/16
101: fSYS/32
110: fSYS/64
111: Undefined
These three bits are used to select the clock source for the A/D converter.
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ACERL Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7
ACE7: Define PA7 is A/D input or not
0: Not A/D input
1: A/D input, AN7
Bit 6
ACE6: Define PA6 is A/D input or not
0: Not A/D input
1: A/D input, AN6
Bit 5
ACE5: Define PA5 is A/D input or not
0: Not A/D input
1: A/D input, AN5
Bit 4
ACE4: Define PA4is A/D input or not
0: Not A/D input
1: A/D input, AN4
Bit 3
ACE3: Define PA3 is A/D input or not
0: Not A/D input
1: A/D input, AN3
Bit 2
ACE2: Define PA2 is A/D input or not
0: Not A/D input
1: A/D input, AN2
Bit 1
ACE1: Define PA1 is A/D input or not
0: Not A/D input
1: A/D input, AN1
Bit 0
ACE0: Define PA0 is A/D input or not
0: Not A/D input
1: A/D input, AN0
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A/D Operation
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to “0” by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen
to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the
ADCK2~ADCK0 bits in the ADCR1 register.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0,
there are some limitations on the A/D clock source speed range that can be selected. As the
recommended range of permissible A/D clock period, tADCK, is from 0.5µs to 10µs, care must be
taken for selected system clock frequencies. For example, if the system clock operates at a frequency
of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D
clock periods that are less than the minimum A/D clock period or greater than the maximum A/D
clock period which may result in inaccurate A/D conversion values.
Refer to the following table for examples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken, as the values may be out of the recommended
A/D clock period range.
A/D Clock Period (tADCK)
fSYS
1MHz
ADCK2,
ADCK1,
ADCK0
=000
(fSYS)
ADCK2,
ADCK1,
ADCK0
=001
(fSYS/2)
ADCK2,
ADCK1,
ADCK0
=010
(fSYS/4)
ADCK2,
ADCK1,
ADCK0
=011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
=100
(fSYS/16)
ADCK2,
ADCK1,
ADCK0
=101
(fSYS/32)
ADCK2,
ADCK1,
ADCK0
=110
(fSYS/64)
ADCK2,
ADCK1,
ADCK0
=111
1μs
2μs
4μs
8μs
16μs*
32μs*
64μs*
Undefined
2MHz
500ns
1μs
2μs
4μs
8μs
16μs*
32μs*
Undefined
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs*
Undefined
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
Undefined
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
Undefined
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
Undefined
20MHz
50ns*
100ns*
200ns*
400ns*
800ns
1.6μs
3.2μs
Undefined
A/D Clock Period Examples
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the
ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ACERL registers, if
the ADOFF bit is zero then some power will still be consumed. In power conscious applications it
is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power supply
pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made
using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set
high, the VREF pin function will be selected and the other pin functions will be disabled automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other
functions. The ACE7~ACE0 bits in the ACERL registers, determine whether the input pins are setup
as A/D converter analog inputs or whether they have other functions. If the ACE7~ACE0 bits for its
corresponding pin is set high then the pin will be setup to be an A/D converter input and the original
pin functions disabled. In this way, pins can be changed under program control to change their
function between A/D inputs and other functions. All pull-high resistors, which are setup through
register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note
that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable
the A/D input as when the ACE7~ACE0 bits enable an A/D input, the status of the port control
register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can
also be supplied from the power supply pin, a choice which is made through the VREFS bit in the
ADCR1 register. The analog input values must not be allowed to exceed the value of VREF.
€
­         A/D Input Structure
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an A/D
conversion process.
• Step 1
Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the
ADCR1 register.
• Step 2
Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero.
• Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming
the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 register.
• Step 4
Select which pins are to be used as A/D inputs and configure them by correctly programming the
ACE7~ACE0 bits in the ACERL register.
• Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to
ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and
the A/D converter interrupt bit, ADE, must both be set high to do this.
• Step 6
The analog to digital conversion process can now be initialised by setting the START bit in
the ADCR0 register from low to high and then low again. Note that this bit should have been
originally cleared to zero.
• Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0
register can be polled. The conversion process is complete when this bit goes low. When this
occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method, if the interrupts are enabled and the stack is not full, the program can wait for
an A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit
in the ADCR0 register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period.
Rev. 1.10
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Power Bank 8-Bit Flash MCU
€ €
‚  
­
­                       
 A/D Conversion Timing
Programming Considerations
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the
ADCR0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are
used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then
this may lead to some increase in power consumption.
A/D Transfer Function
As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to
FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single
bit analog input value of VDD or VREF divided by 4096.
1 LSB= (VDD or VREF)/4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage= A/D output digital value × (VDD or VREF)/4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level.
    
 
      Ideal A/D Transfer Function
Rev. 1.10
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A/D Programming Example
The following two programming examples illustrate how to setup and implement an A/D conversion.
In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect
when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to
determine when the conversion is complete.
Example: using an EOCB polling method to detect the end of conversion
clr ADE;
mov a,03H
mov ADCR1,a;
clr ADOFF
mova,0Fh ;
mov ACERL,a
mova,01h
mov ADCR0,a ;
:
start_conversion:
clr START ;
set START ;
clr START ;
polling_EOC:
sz EOCB ;
jmp polling_EOC ;
mov a,ADRL ;
mov ADRL_buffer,a ;
mov a,ADRH ;
mov ADRH_buffer,a ;
:
:
jmp start_conversion ;
Rev. 1.10
disable ADC interrupt
select fSYS/8 as A/D clock and switch off 1.25V
setup ACERL to configure pins AN0~AN3
enable and connect AN0 channel to A/D converter
high pulse on start bit to initiate conversion
reset A/D
start A/D
poll the ADCR0 register EOCB bit to detect end of A/D conversion
continue polling
read low byte conversion result value
save result to user defined register
read high byte conversion result value
save result to user defined register
start next a/d conversion
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Example: using the interrupt method to detect the end of conversion
clr ADE ;
mova,03H
mov ADCR1,a ;
Clr ADOFF
mova,0Fh ;
mov ACERL,a
mova,01h
mov ADCR0,a ;
Start_conversion:
clr START ;
set START ;
clr START ;
clrADF ;
setADE ;
set EMI ;
:
:
;
ADC_ISR:
mov acc_stack,a ;
mov a,STATUS
mov status_stack,a ;
:
:
mov a,ADRL ;
mov adrl_buffer,a ;
mov a,ADRH ;
mov adrh_buffer,a ;
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ;
mov a,acc_stack ;
reti
Rev. 1.10
disable ADC interrupt
select fSYS/8 as A/D clock and switch off 1.25V
setup ACERL to configure pins AN0~AN3
enable and connect AN0 channel to A/D converter
high pulse on START bit to initiate conversion
reset A/D
start A/D
clear ADC interrupt request flag
enable ADC interrupt
enable global interrupt
ADC interrupt service routine
save ACC to user defined memory
save STATUS to user defined memory
read
save
read
save
low byte conversion result value
result to user defined register
high byte conversion result value
result to user defined register
restore STATUS from user defined memory
restore ACC from user defined memory
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Complementary PWM Output
The device provides a complementary output pair of signals which can be used as a PWM driver
signal. The signal is sourced from the TM1 output signal, TP1. For PMOS type upper side driving,
the PWM output is an active low signal while for NMOS type lower side driving the PWM output
is an active high signal. When these complementary PWM outputs are both used to drive the
upper and low sides, the dead time generator will automatically be enabled and a dead time, which
is programmable using the DTPSC and DT bits in the CPR register, will be inserted to prevent
excessive DC currents. The dead time will be inserted whenever the rising edge of the dead time
generator input signal occurs. With a dead time insertion, the output signals are eventually sent
out to the external power transistors. The dead time generator will only be enabled if both of the
complementary outputs are used, as determined by the OUTCP bits in the TMPC register.
A
TP1
B
fH
Prescaler
DTPSC [1:0]
C
Dead Time
Generator
E
fD
D
PWMH
(driving upper side PMOS, active low)
PWML
(driving lower side NMOS, active high)
DT [2:0] OUTCP [1:0]
Complementary PWM Output Block Diagram
TP1
A
B
C
D
E
Dead Time
Dead Time
Dead Time
Dead Time
Dead Time
Dead Time
Complementary PWM Output Waveform
Rev. 1.10
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CPR Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
DTPSC1
DTPSC0
DT2
DT1
DT0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7 ~ 5
Unimplemented, read as "0"
Bit 4 ~ 3
DTPSC1~DTPSC0: dead time prescaler division ratio select
00: fD=fH/1
01: fD=fH/2
10: fD=fH/4
11: fD=fH/8
Bit 2 ~ 0
DT2~DT0: dead time select
000: Dead time is [(1/fD)-(1/fH)] ~ (1/fD)
001: Dead time is [(2/fD)-(1/fH)] ~ (2/fD)
010: Dead time is [(3/fD)-(1/fH)] ~ (3/fD)
011: Dead time is [(4/fD)-(1/fH)] ~ (4/fD)
100: Dead time is [(5/fD)-(1/fH)] ~ (5/fD)
101: Dead time is [(6/fD)-(1/fH)] ~ (6/fD)
110: Dead time is [(7/fD)-(1/fH)] ~ (7/fD)
111: Dead time is [(8/fD)-(1/fH)] ~ (8/fD)
Over Current and Voltage Protection
The device includes an over voltage and over current protection function which provides a
protection mechanism for the battery charge and discharge applications.
• OVP protection
To prevent the output voltage from exceeding 5.4V, the OVP input voltage is compared with a
reference voltage generated by a 6-bit D/A converter. The 6-bit D/A converter power is supplied
by the external power pin named DAPWR. Once the OVP input voltage is greater than the
reference voltage, it will force the OUTH and OUTL signals inactive, i.e., the OUTH signal will
be forced into a high state and the OUTL signal will be forced into a low state before the polarity
control, to turn the external MOS off for over voltage protection.
• OCP protection
To prevent the possibility of large battery currents, the OCP input voltage from the battery sense
resistor is compared with a reference voltage generated by an 8-bit D/A converter. The 8-bit D/
A converter power is supplied by the external power pin named DAPWR. Once the OCP input
voltage is greater than the reference voltage, it will force the OUTH and OUTL signals inactive,
i.e., the OUTH signal will be forced into a high state and the OUTL signal will be forced into a
low state before the polarity control, to turn the external MOS off for over current protection.
The OUTH and OUTL signals can be forced to an inactive state when either an over voltage or an
over current event occurs. If an over voltage or an over current event occurs, the corresponding
interrupt will be generated. Once the over voltage or over current condition has disappeared, the
OUTH and OUTL signals will recover to drive the PWM output.
The operational amplifier in the over current protection circuitry can be configured in an inverting or
non-inverting OPA configuration to sense the battery current when the battery is undergoing a charge
or discharge operation. It is recommended that the OPA should be in a non-inverting mode during a
charge operation and in an inverting mode during a discharge operation.
More information for the OUTH and OUTL signal polarity and output control is described in the
TMPC register.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
OUTL
OVP (Interrupt & Flag)
6 bit
D/A
DAPWR
CA
OVP
OUTHN
OUTH
OVP1EN
M
U
X
OVP0EN
To ADC
OCPR[7:0]
OCP1EN
8 bit
DAC
OCP0EN
M
U
X
0
1
0
1
AX/BX (HT45FH4MA)
AX/BX (HT45FH4MA-1)
Level
Shift
CX/DX
For HT45FH4MA/
HT45FH4MA-1 only
TP1
PWMH
TP1
PWML
OUTCP1
OUTCP0
Inverter or
Non-Inverter OPA
OPAMC
Level
Shift
OUTLN
OVPR[5:0]
OCP (Interrupt & Flag)
CB
A
OCP
R
To ADC Input (AN8)
15R
Over Voltage and Over Current Protection Block Diagram
OCP/OVP Register
Overall operation of the over current and over voltage protection is controlled using several
registers. Two registers are used to provide the reference voltages for the over current and over
voltage protection respectively. There are three registers which are used to cancel out the operational
amplifier and comparator input offset. A register exists to store the operational amplifier output
status as a logical condition. The remaining registers are control registers which control the OCP/
OVP function, pin function, output status together with the hysteresis function. For a more detailed
description regarding the input offset voltage cancellation procedures, refer to the corresponding
application notes on the Holtek website.
Bit
Register
Name
7
6
5
4
3
2
1
0
OCPREF
OCPR7
OCPR6
OCPR5
OCPR4
OCPR3
OCPR2
OCPR1
OCPR0
OVPREF
—
—
OVPR5
OVPR4
OVPR3
OVPR2
OVPR1
OVPR0
OCVPR0
OCPEN
OVPEN
OCP1EN
OCP0EN
OVP1EN
OVP0EN
CHYBEN
CHYAEN
OCVPR1
OPAMC
OVPC
OCPC
—
DBB1
DBB0
DBA1
DBA0
OCVPR2
AOFM
ARS
AOF5
AOF4
AOF3
AOF2
AOF1
AOF0
OCVPR3
CAOFM
CARS
CAOF5
CAOF4
CAOF3
CAOF2
CAOF1
CAOF0
OCVPR4
CBOFM
CBRS
CBOF5
CBOF4
CBOF3
CBOF2
CBOF1
CBOF0
OCVPR5
—
—
—
—
—
AX
CBX
CAX
OCP/OVP Register Lists
Rev. 1.10
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Power Bank 8-Bit Flash MCU
OCPREF Register
Bit
7
6
5
4
3
2
1
0
Name
OCPR7
OCPR6
OCPR5
OCPR4
OCPR3
OCPR2
OCPR1
OCPR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7 ~ 0
OCPR7~OCPR0: Over Current Protection reference voltage select
OCP Reference voltage= (DAPWR/256)×OCPR, where OCPR is the OCPREF register
content in decimal notation.
OVPREF Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
OVPR5
OVPR4
OVPR3
OVPR2
OVPR1
OVPR0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5 ~ 0
OVPR5~OVPR0: Over voltage Protection reference voltage select
OVP Reference voltage= (DAPWR/64)×OVPR, where OVPR is the OVPREF register
content in decimal notation.
OCVPR0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
OCPEN
OVPEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
OCP1EN OCP0EN OVP1EN OVP0EN CHYBEN CHYAEN
Bit 7
OCPEN: Over Current Protection function Enable control
0: Disable
1: Enable
If the OCPEN bit is cleared to 0, the over current protection function is disabled and
no power will be consumed. This results in the operational amplifier, comparator and
D/A converter all being switched off.
Bit 6
OVPEN: Over Voltage Protection function Enable control
0: Disable
1: Enable
If the OVPEN bit is cleared to 0, the over voltage protection function is disabled and
no power will be consumed. This results in the comparator and D/A converter all being
switched off.
Bit 5
OCP1EN: OUTL Over Current Protection Enable control
0: Disable
1: Enable
This bit is used to control whether the OUTL signal is forced into an inactive state
when an over current condition occurs. If the OCPEN and OCP1EN bits both are set
to 1, the OUTL signal will be forced inactive when an over current condition occurs. If
the OUTL signal protection function is disabled by clearing the OCP1EN bit to 0, the
OUTL signal will not be affected when an over current condition occurs.
107
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Rev. 1.10
Bit 4
OCP0EN: OUTH Over Current Protection Enable control
0: Disable
1: Enable
This bit is used to control whether the OUTH signal is forced into an inactive state
when an over current condition occurs. If the OCPEN and OCP0EN bits both are set
to 1, the OUTH signal will be forced inactive when an over current condition occurs.
If the OUTH signal protection function is disabled by clearing the OCP0EN bit to 0,
the OUTH signal will not be affected when an over current condition occurs.
Bit 3
OVP1EN: OUTL Over Voltage Protection Enable control
0: Disable
1: Enable
This bit is used to control whether the OUTL signal is forced into an inactive state
when an over voltage condition occurs. If the OVPEN and OVP1EN bits both are set
to 1, the OUTL signal will be forced inactive when an over voltage condition occurs.
If the OUTL signal protection function is disabled by clearing the OVP1EN bit to 0,
the OUTL signal will not be affected when an over voltage condition occurs.
Bit 2
OVP0EN: OUTH Over Voltage Protection Enable control
0: Disable
1: Enable
This bit is used to control whether the OUTH signal is forced into an inactive state
when an over voltage condition occurs. If the OVPEN and OVP0EN bits both are set
to 1, the OUTH signal will be forced inactive when an over voltage condition occurs.
If the OUTH signal protection function is disabled by clearing the OVP0EN bit to 0,
the OUTH signal will not be affected when an over voltage condition occurs.
Bit 1
CHYBEN: Over Current Protection Comparator Hysteresis Enable control
0: Disable
1: Enable
Bit 0
CHYAEN: Over Voltage Protection Comparator Hysteresis Enable control
0: Disable
1: Enable
108
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
OCVPR1 Register
Bit
7
6
5
4
3
2
1
0
Name
OPAMC
OVPC
OCPC
—
DBB1
DBB0
DBA1
DBA0
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
POR
0
0
0
—
0
0
0
0
Bit 7
OPAMC: Over Current Protection Operational Amplifier Mode Control
0: Inverting mode
1: Non- Inverting mode
Bit 6
OVPC: Over Voltage Protection Pin Control
0: OVP pin is disabled
1: OVP pin is enabled
Bit 5
OCPC: Over Current Protection Pin Control
0: OCP pin is disabled
1: OCP pin is enabled
Bit 4
Unimplemented, read as "0"
Bit 3~2
DBB1~DBB0: Over Current Protection Comparator Debounce Time Select
00: No debounce
01: debounce time = (15~16) × 1/fH
10: debounce time = (31~32) × 1/fH
11: debounce time = (63~64) × 1/fH
DBA1~DBA0: Over Voltage Protection Comparator Debounce Time Select
00: No debounce
01: debounce time = (15~16) × 1/fH
10: debounce time = (31~32) × 1/fH
11: debounce time = (63~64) × 1/fH
Bit 1~0
OCVPR2 Register
Bit
7
6
5
4
3
2
1
0
Name
AOFM
ARS
AOF5
AOF4
AOF3
AOF2
AOF1
AOF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
0
0
0
0
0
Bit 7
Bit 6
Bit 5~0
Rev. 1.10
AOFM: Over Current Protection Operational Amplifier Input Offset Voltage Cancellation
Mode Select
0: Operational Amplifier mode
1: Input Offset Voltage Cancellation mode
ARS: Over Current Protection Operational Amplifier Offset Voltage Cancellation Reference
Input Select
0: Operational Amplifier negative input selected
1: Operational Amplifier positive input selected
AOF5~AOF0: Operational Amplifier Input Voltage Offset Cancellation Setting
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
OCVPR3 Register
Bit
7
6
5
4
3
2
1
0
Name
CAOFM
CARS
CAOF5
CAOF4
CAOF3
CAOF2
CAOF1
CAOF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
0
0
0
0
0
Bit 7
Bit 6
Bit 5~0
CAOFM: Over Voltage Protection Comparator Input Offset Voltage Cancellation
Mode Select
0: Comparator mode
1: Input Offset Voltage Cancellation mode
CARS: Over Voltage Protection Comparator Offset Voltage Cancellation Reference
Input Select
0: Comparator negative input selected
1: Comparator positive input selected
CAOF5~CAOF0: Over Voltage Protection Comparator Input Voltage Offset Cancellation
Setting
OCVPR4 Register
Bit
7
6
5
4
3
2
1
0
Name
CBOFM
CBRS
CBOF5
CBOF4
CBOF3
CBOF2
CBOF1
CBOF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
1
0
0
0
0
0
Bit 7
Bit 6
Bit 5~0
Rev. 1.10
CBOFM: Over Current Protection Comparator Input Offset Voltage Cancellation
Mode Select
0: Comparator mode
1: Input Offset Voltage Cancellation mode
CBRS: Over Current Protection Comparator Offset Voltage Cancellation Reference
Input Select
0: Comparator negative input selected
1: Comparator positive input selected
CBOF5~CBOF0: Over Current Protection Comparator Input Voltage Offset Cancellation
Setting
110
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
OCVPR5 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
AX
CBX
CAX
R/W
—
—
—
—
—
R
R
R
POR
—
—
—
—
—
x
x
x
“x”: unknown
Bit 7~3
Unimplemented, read as "0"
Bit 2
AX: Over Current Protection Operational Amplifier Digital Output
0: positive input voltage < negative input voltage
1: positive input voltage > negative input voltage
Bit 1
CBX: Over Current Protection Comparator Digital Output
0: positive input voltage < negative input voltage
1: positive input voltage > negative input voltage
Bit 0
CAX: Over Voltage Protection Comparator Digital Output
0: positive input voltage < negative input voltage
1: positive input voltage > negative input voltagel
OCP Operational Amplifier Offset Cancellation Function
OPA allows for a commode mode adjustment method of its input offset voltage.
ARS
AOFM
S1
S2
S3
0
0
0
ON
ON
OFF
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
The calibration steps are as following:
• Set AOFM= 1 to setup the offset cancellation mode, here S3 is closed
• Set ARS to select which input pin is to be used as the reference voltage – S1 or S2 is closed
• Adjust AOF0~AOF5 until the output status changes
• Set AOFM= 0 to restore the normal OPA mode
Rev. 1.10
111
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
OCP Comparator Offset Cancellation Function
CMP allows for a commode mode adjustment method of its input offset voltage.
CARS
CAOFM
S1
S2
S3
0
0
ON
ON
OFF
0
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
C o m p a r a to r A + in p u t
C o m p a r a to r A - in p u t
S 1
S 3
S 2
C A
C o m p a ra to r A o u tp u t
C A O F 0 ~ C A O F 5 , O C P E N
The calibration steps are as following:
• Set CAOFM= 1 to setup the offset cancellation mode, here S3 is closed
• Set CARS to select which input pin is to be used as the reference voltage – S1 or S2 is closed
• Adjust CAOF0~CAOF5 until the output status changes
• Set CAOFM= 0 to restore the normal Comparator A mode
OVP Comparator Offset Cancellation Function
CMP allows for a commode mode adjustment method of its input offset voltage.
CBRS
CBOFM
S1
S2
S3
0
0
0
ON
ON
OFF
1
OFF
ON
ON
1
0
ON
ON
OFF
1
1
ON
OFF
ON
C o m p a r a to r B + in p u t
C o m p a r a to r B - in p u t
S 1
S 3
S 2
C B
C o m p a ra to r B o u tp u t
C B O F 0 ~ C B O F 5 , O V P E N
The calibration steps are as following:
• Set CBOFM= 1 to setup the offset cancellation mode, here S3 is closed
• Set CBRS to select which input pin is to be used as the reference voltage – S1 or S2 is closed
• Adjust CBOF0~CBOF5 until the output status changes
• Set CBOFM= 0 to restore the normal Comparator B mode
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer Module or an A/D converter requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs. The device contains several external
interrupt and internal interrupts functions. The external interrupt is generated by the action of
the external INT0 and INT1 pins, while the internal interrupts are generated by various internal
functions such as the TMs, Comparator, Time Base, LVD, EEPROM and the A/D converter.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in
the accompanying table. The registers fall into three categories. The first is the INTC0~INTC2
registers which setup the primary interrupts, the second is the MFI0~MFI2 registers which setup the
Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger
edge type.
Each register contains a number of enable bits to enable or disable individual registers as well as
interrupt flags to indicate the presence of an interrupt request. The naming convention of these
follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of
that interrupt followed by either an “E” for enable/disable bit or “F” for request flag.
Function
Enable Bit
Global
INTn Pin
Request Flag
EMI
—
INTnE
INTnF
Notes
—
n= 0 or 1
OVP
OVPE
OVPF
—
OCP
OCPE
OCPF
—
A/D Converter
ADE
ADF
Multi-function
MFnE
MFnF
n= 0~2
Time Base
TBnE
TBnF
n= 0 or 1
LVE
LVF
—
—
LVD
EEPROM
TM
DEE
DEF
TnPE
TnPF
TnAE
TnAF
—
n= 0 or 1
Interrupt Register Bit Naming Conventions
Interrupt Register Contents
Rev. 1.10
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INTEG
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
INTC0
—
INT0F
OCPF
OVPF
INT0E
OCPE
OVPE
EMI
INTC1
ADF
MF2F
MF1F
MF0F
ADE
MF2E
MF1E
MF0E
INTC2
—
INT1F
TB1F
TB0F
—
INT1E
TB1E
TB0E
MFI0
—
—
T0AF
T0PF
—
—
T0AE
T0PE
MFI1
—
—
T1AF
T1PF
—
—
T1AE
T1PE
MFI2
—
—
DEF
LVF
—
—
DEE
LVE
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Power Bank 8-Bit Flash MCU
INTEG Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
INT1S1
INT1S0
INT0S1
INT0S0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
0
Bit 7 ~ 4 Unimplemented, read as "0"
Bit 3 ~ 2
INT1S1, INT1S0: Defines INT1 interrupt active edge
00: Disabled Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt
Bit 1 ~ 0
INT0S1, INT0S0: Defines INT0 interrupt active edge
00: Disabled Interrupt
01: Rising Edge Interrupt
10: Falling Edge Interrupt
11: Dual Edge Interrupt
INTC0 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
Name
—
INT0F
OCPF
OVPF
INT0E
OCPE
OVPE
EMI
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Unimplemented, read as "0"
Bit 6
INT0F: INT0 Interrupt Request Flag
0: No request
1: Interrupt request
Bit 5
OCPF: over current protection interrupt request flag
0: No request
1: Interrupt request
Bit 4
OVPF: over voltage protection interrupt request flag
0: No request
1: Interrupt request
Bit 3 INT0E: INT0 Interrupt Control
0: Disable
1: Enable
Bit 2
OCPE: Over current protection Interrupt Control
0: Disable
1: Enable
Bit 1
OVPE: Over voltage protection Interrupt Control
0: Disable
1: Enable
Bit 0
EMI: Global Interrupt Control
0: Disable
1: Enable
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Power Bank 8-Bit Flash MCU
INTC1 Register
Bit
7
6
5
4
3
2
1
0
Name
ADF
MF2F
MF1F
MF0F
ADE
MF2E
MF1E
MF0E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Rev. 1.10
ADF: A/D Converter Interrupt Request Flag
0: No request
1: Interrupt request
MF2F: Multi-function Interrupt 2 Request Flag
0: No request
1: Interrupt request
MF1F: Multi-function Interrupt 1 Request Flag
0: No request
1: Interrupt request
MF0F: Multi-function Interrupt 0 Request Flag
0: No request
1: Interrupt request
ADE: A/D Converter Interrupt Control
0: Disable
1: Enable
MF2E: Multi-function Interrupt 2 Control
0: Disable
1: Enable
MF1E: Multi-function Interrupt 1 Control
0: Disable
1: Enable
MF0E: Multi-function Interrupt 0 Control
0: Disable
1: Enable
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August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
INTC2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
INT1F
TB1F
TB0F
—
INT1E
TB1E
TB0E
R/W
—
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
—
0
0
0
—
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Rev. 1.10
Unimplemented, read as "0"
INT1F: INT1 Interrupt Request Flag
0: No request
1: Interrupt request
TB1F: Time Base 1 Interrupt Request Flag
0: No request
1: Interrupt request
TB0F: Time Base 0 Interrupt Request Flag
0: No request
1: Interrupt request
Unimplemented, read as "0"
INT1E: INT1 Interrupt Control
0: Disable
1: Enable
TB1E: Time Base 1 Interrupt Control
0: Disable
1: Enable
TB0E: Time Base 0 Interrupt Control
0: Disable
1: Enable
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Power Bank 8-Bit Flash MCU
MFI0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
T0AF
T0PF
—
—
T0AE
T0PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5
T0AF: TM0 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4
T0PF: TM0 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3 ~ 2
Unimplemented, read as "0"
Bit 1
T0AE: TM0 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0
T0PE: TM0 Comparator P match interrupt control
0: Disable
1: Enable
MFI1 Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
T1AF
T1PF
—
—
T1AE
T1PE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7~6
Unimplemented, read as "0"
Bit 5
T1AF: TM1 Comparator A match interrupt request flag
0: No request
1: Interrupt request
Bit 4
T1PF: TM1 Comparator P match interrupt request flag
0: No request
1: Interrupt request
Bit 3~2
Unimplemented, read as "0"
Bit 1
T1AE: TM1 Comparator A match interrupt control
0: Disable
1: Enable
Bit 0
T1PE: TM1 Comparator P match interrupt control
0: Disable
1: Enable
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MFI2 Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
DEF
LVF
—
—
DEE
LVE
R/W
—
—
R/W
R/W
—
—
R/W
R/W
POR
—
—
0
0
—
—
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5
DEF: Data EEPROM interrupt request flag
0: No request
1: Interrupt request
Bit 4
LVF: LVD interrupt request flag
0: No request
1: Interrupt request
Bit 3 ~ 2
Unimplemented, read as "0"
Bit 1
DEE: Data EEPROM Interrupt Control
0: Disable
1: Enable
Bit 0
LVE: LVD Interrupt Control
0: Disable
1: Enable
Interrupt Operation
When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A
match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether
the request flag actually generates a program jump to the relevant interrupt vector is determined by
the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to
its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual
interrupt will not be generated and the program will not jump to the relevant interrupt vector. The
global interrupt enable bit, if cleared to zero, will disable all interrupts.
When an interrupt is generated, the Program Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will
then fetch its next instruction from this interrupt vector. The instruction at this vector will usually
be a “JMP” which will jump to another section of program which is known as the interrupt service
routine. Here is located the code to control the appropriate interrupt. The interrupt service routine
must be terminated with a “RETI”, which retrieves the original Program Counter address from
the stack and allows the microcontroller to continue with normal execution at the point where the
interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
accompanying diagrams with their order of priority. Some interrupt sources have their own
individual vector while others share the same multi-function interrupt vector. Once an interrupt
subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit,
EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring.
However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded.
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Power Bank 8-Bit Flash MCU
If an interrupt requires immediate servicing while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until
the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from
becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that
is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or
IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set
before the device is in SLEEP or IDLE Mode.
EMI auto disabled in ISR
Legend
xxF
Request Flag – no auto reset in ISR
xxF Request Flag – auto reset in ISR
xxE Enable Bit
Interrupt
Name
Request
Flags
Enable
Bits
TM0 P
T0PF
T0PE
TM0 A
T0AF
T0AE
TM1 P
T1PF
T1PE
TM1 A
T1AF
T1AE
Interrupt
Name
Request
Flags
EEPROM
LVF
LVE
DEF
DEE
Master
Enable
Vector
Over Voltage
Protection
OVPF
OVPE
EMI
04H
Over Current
Protection
OCPF
OCPE
EMI
08H
INT0 Pin
INT0F
INT0E
EMI
0CH
M.Funct. 0
MF0F
MF0E
EMI
10H
M.Funct. 1
MF1F
MF1E
EMI
14H
M.Funct. 2
MF2F
MF2E
EMI
18H
ADE
EMI
1CH
A/D
LVD
Enable
Bits
ADF
Time Base 0
TB0F
TB0E
EMI
20H
Time Base 1
TB1F
TB1E
EMI
24H
INT1E
EMI
28H
INT1 Pin
INT1F
Priority
High
Low
Interrupts contained within
Multi-Function Interrupts
Interrupt Structure
Rev. 1.10
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Power Bank 8-Bit Flash MCU
External Interrupt
The external interrupts are controlled by signal transitions on the pins INT0, INT1. An external
interrupt request will take place when the external interrupt request flags, INT0F, INT1F, are set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address, the
global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E, INT1E, must
first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to
enable the external interrupt function and to choose the trigger edge type. As the external interrupt
pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their
external interrupt enable bit in the corresponding interrupt register has been set. The pin must also
be setup as an input by setting the corresponding bit in the port control register. When the interrupt
is enabled, the stack is not full and the correct transition type appears on the external interrupt pin,
a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the
external interrupt request flags, INT0F, INT1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input. The
INTEG register is used to select the type of active edge that will trigger the external interrupt. A
choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
OVP Interrupt
An OVP Interrupt request will take place when the Over Voltage Protection Interrupt request flag,
OVPF, is set, which occurs when the Over Voltage Protection function detects an over voltage
condition. To allow the program to branch to its respective interrupt vector address, the global
interrupt enable bit, EMI, and Over Voltage Protection Interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and an over voltage condition occurs, a subroutine call
to the OVP Interrupt vector, will take place. When the Over Voltage Protection Interrupt is serviced,
the EMI bit will be automatically cleared to disable other interrupts and the interrupt request flag
will be also automatically cleared.
OCP Interrupt
An OCP Interrupt request will take place when the Over Current Protection Interrupt request flag,
OCPF, is set, which occurs when the Over Current Protection function detects an over current
condition. To allow the program to branch to its respective interrupt vector address, the global
interrupt enable bit, EMI, and Over Current Protection Interrupt enable bit, must first be set. When
the interrupt is enabled, the stack is not full and an over current condition occurs, a subroutine call
to the OCP Interrupt vector, will take place. When the Over Current Protection Interrupt is serviced,
the EMI bit will be automatically cleared to disable other interrupts and the interrupt request flag
will be also automatically cleared.
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Multi-function Interrupt
Within this device there are up to three Multi-function interrupts. Unlike the other independent
interrupts, these interrupts have no independent source, but rather are formed from other existing
interrupt sources, namely the TM Interrupts, LVD interrupt and EEPROM Interrupt.
A Multi-function interrupt request will take place when any of the Multi-function interrupt request
flags, MF0F~MF2F are set. The Multi-function interrupt flags will be set when any of their included
functions generate an interrupt request flag. To allow the program to branch to its respective interrupt
vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one
of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of
the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared to
disable other interrupts.
However, it must be noted that, although the Multi-function Interrupt flags will be automatically
reset when the interrupt is serviced, the request flags from the original source of the Multifunction interrupts, namely the TM Interrupts, LVD interrupt and EEPROM Interrupt will not be
automatically reset and must be manually reset by the application program.
A/D Converter Interrupt
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/
D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF,
is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its
respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit,
ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion
process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the
interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI
bit will also be automatically cleared to disable other interrupts.
Time Base Interrupts
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source fTB. This fTB input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBC
register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB,
which in turn controls the Time Base interrupt period, can originate from several different sources,
as shown in the System Operating Mode section.
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Power Bank 8-Bit Flash MCU
TBC Register
Bit
7
6
5
4
3
2
1
0
Name
TBON
TBCK
TB11
TB10
—
TB02
TB01
TB00
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
1
1
—
1
1
1
Bit 7
TBON: TB0 and TB1 Control bit
0: Disable
1: Enable
Bit 6
TBCK: Select fTB Clock
0: fTBC
1: fSYS/4
Bit 5 ~ 4
TB11 ~ TB10: Select Time Base 1 Time-out Period
00: 4096/fTB
01: 8192/fTB
10: 16384/fTB
11: 32768/fTB
Bit 3
Unimplemented, read as "0"
Bit 2 ~ 0
TB02 ~ TB00: Select Time Base 0 Time-out Period
000: 256/fTB
001: 512/fTB
010: 1024/fTB
011: 2048/fTB
100: 4096/fTB
101: 8192/fTB
110: 16384/fTB
111: 32768/fTB
 Time Base Interrupt
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
EEPROM Interrupt
The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt
request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs
when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt
vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE,
and associated Multi-function interrupt enable bit, MF2E, must first be set. When the interrupt is
enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective
EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit
will be automatically cleared to disable other interrupts, however only the Multi-function interrupt
request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it
has to be cleared by the application program.
LVD Interrupt
The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD
Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs
when the Low Voltage Detector function detects a low power supply voltage. To allow the program
to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low
Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, MF2E, must
first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs,
a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is
serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the
Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be
automatically cleared, it has to be cleared by the application program.
TM Interrupts
The Standard Type TM has two interrupts while the Periodic Type TM also has two interrupts. All of
the TM interrupts are contained within the Multi-function Interrupts. For the Standard and Periodic
Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and
TnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation
which occurs when a TM comparator P or comparator A match situation happens.
To allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable
bit, MFnF (MF0F or MF1F), must first be set. When the interrupt is enabled, the stack is not full
and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector
locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically
cleared to disable other interrupts, however only the related MFnF flag (MF0F or MF1F) will be
automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have
to be cleared by the application program.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Interrupt Wake-up Function
Each of the interrupt functions has the capability of waking up the microcontroller when in the
SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to
high and is independent of whether the interrupt is enabled or not. Therefore, even though the device
is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge
transitions on the external interrupt pins, a low power supply voltage or comparator input change
may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care
must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up
function is to be disabled then the corresponding interrupt request flag should be set high before the
device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt
wake-up function.
Programming Considerations
By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by
the application program.
Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt
service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF2F, will
be automatically cleared, the individual request flag for the function needs to be cleared by the
application program.
It is recommended that programs do not use the “CALL” instruction within the interrupt service
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately.
If only one stack is left and the interrupt is not well controlled, the original control sequence will be
damaged once a CALL subroutine is executed in the interrupt subroutine.
Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE
Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is
required to prevent a certain interrupt from waking up the microcontroller then its respective request
flag should be first set high before enter SLEEP or IDLE Mode.
As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the
contents of the accumulator, status register or other registers are altered by the interrupt service
program, their contents should be saved to the memory at the beginning of the interrupt service routine.
To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI
instruction in addition to executing a return to the main program also automatically sets the EMI
bit high to allow further interrupts. The RET instruction however only executes a return to the main
program leaving the EMI bit in its present zero state and therefore disabling the execution of further
interrupts.
Rev. 1.10
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Low Voltage Detector – LVD
The device has a Low Voltage Detector function, also known as LVD. This enables the device to
monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated.
The Low Voltage Detector also has the capability of generating an interrupt signal.
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDC. Three
bits in this register, VLVD2~VLVD0, are used to select one of five fixed voltages below which a
low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is
set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value.
The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the
bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low
voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may
be desirable to switch off the circuit when not in use, an important consideration in power sensitive
battery powered applications.
LVDC Register
Rev. 1.10
Bit
7
6
5
4
3
2
1
0
Name
—
—
LVDO
LVDEN
—
VLVD2
VLVD1
VLVD0
R/W
—
—
R
R/W
—
R/W
R/W
R/W
POR
—
—
0
0
—
0
0
0
Bit 7 ~ 6
Unimplemented, read as "0"
Bit 5
LVDO: LVD Output Flag
0: No low voltage detect
1: Low voltage detect
Bit 4
LVDEN: Low Voltage Detector Control
0: Disable
1: Enable
Bit 3 Unimplemented, read as "0"
Bit 2~0
VLVD2 ~ VLVD0: Select LVD Voltage
000~010: reserved
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.0V
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HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a
pre-specified voltage level stored in the LVDC register. This has a range of between 2.7V and 4.0V.
When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the device is powered
down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the
LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that
of VLVD, there may be multiple bit LVDO transitions.
LVD Operation
The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the
LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set
high by a low voltage condition. When the device is powered down the Low Voltage Detector will
remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing
an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to
wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not
required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.
Rev. 1.10
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Power Bank 8-Bit Flash MCU
Application Circuits
1N5819
+
Lithium Battery
1
USB
I/P
IO
50m
OUTH
OUTL
VDD
IO
AN
OVP
OCP
50m
USB
O/P
IO
VDD
104
AN
105
HT45F4MA
DAPWR/VREF
1k
AN
IO
IO
IO
105
2.5V
IO
IO
TL431B
IO
IO
VSS
USB I/P
+
8.4V Battery
IO
AX/BX
CX/DX
OVP
USB O/P
IO
VDD
V5
AN
VDD
104
105
DAPWR/VREF
IO
IO
50 mΩ
OCP
IO
50 mΩ
VCC
AN
AN
1k
51k
HT45FH4MA
2.5V
IO
RT1
50k/25℃
t°
105
TL431B
IO
IO
IO
VSS
Rev. 1.10
127
IO
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
USB I/P
+
8.4V Battery
IO
AX/BX
CX/DX
OVP
USB O/P
VDD
IO
VDD
V5
AN
IO
50 mΩ
IO
OCP
IO
50 mΩ
VCC
AN
104
105
DAPWR/VREF
AN
1k
51k
HT45FH4MA-1
2.5V
IO
RT1
50k/25℃
t°
105
TL431B
IO
IO
IO
VSS
Rev. 1.10
128
IO
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Instruction Set
Introduction
Central to the successful operation of any microcontroller is its instruction set, which is a set of
program instruction codes that directs the microcontroller to perform certain operations. In the case
of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to
enable programmers to implement their application with the minimum of programming overheads.
For easier understanding of the various instruction codes, they have been subdivided into several
functional groupings.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch,
call, or table read instructions where two instruction cycles are required. One instruction cycle is
equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions
would be implemented within 0.5µs and branch or call instructions would be implemented within
1µs. Although instructions which require one more cycle to implement are generally limited to
the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other
instructions which involve manipulation of the Program Counter Low register or PCL will also take
one more cycle to implement. As instructions which change the contents of the PCL will imply a
direct jump to that new address, one more cycle will be required. Examples of such instructions
would be ″CLR PCL″ or ″MOV PCL, A″. For the case of skip instructions, it must be noted that if
the result of the comparison involves a skip operation then this will also take one more cycle, if no
skip is involved then only one cycle is required.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations. Making use of three kinds of MOV instructions, data can be transferred from registers to
the Accumulator and vice-versa as well as being able to move specific immediate data directly into
the Accumulator. One of the most important data transfer applications is to receive data from the
input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and data manipulation is a necessary feature of
most microcontroller applications. Within the Holtek microcontroller instruction set are a range of
add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care
must be taken to ensure correct handling of carry and borrow data when results exceed 255 for
addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC
and DECA provide a simple means of increasing or decreasing by a value of one of the values in the
destination specified.
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Power Bank 8-Bit Flash MCU
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR and CPL all have their own instruction
within the Holtek microcontroller instruction set. As with the case of most instructions involving
data manipulation, data must pass through the Accumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operation is zero. Another form of logical data manipulation comes from the rotate instructions such
as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different
rotate instructions exist depending on program requirements. Rotate instructions are useful for serial
port programming applications where data can be rotated from an internal register into the Carry
bit from where it can be examined and the necessary serial bit set high or low. Another application
where rotate data operations are used is to implement multiplication and division calculations.
Branches and Control Transfer
Program branching takes the form of either jumps to specified locations using the JMP instruction or
to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine
call, the program must return to the instruction immediately when the subroutine has been carried
out. This is done by placing a return instruction RET in the subroutine which will cause the program
to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is no requirement to jump back to the original
jumping off point as in the case of the CALL instruction. One special and extremely useful set
of branch instructions are the conditional branches. Here a decision is first made regarding the
condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and jump to the following instruction. These
instructions are the key to decision making and branching within the program perhaps determined
by the condition of certain input switches or by the condition of internal data bits.
Bit Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all
Holtek microcontrollers. This feature is especially useful for output port bit programming where
individual bits or port pins can be directly set high or low using either the ″SET [m].i″ or ″CLR [m].i″
instructions respectively. The feature removes the need for programmers to first read the 8-bit output
port, manipulate the input data to ensure that other bits are not changed and then output the port with
the correct new data. This read-modify-write process is taken care of automatically when these bit
operation instructions are used.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in
the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program
Memory to be setup as a table where data can be directly stored. A set of easy to use instructions
provides the means by which this fixed data can be referenced and retrieved from the Program
Memory.
Other Operations
In addition to the above functional instructions, a range of other instructions also exist such as
the ″HALT″ instruction for Power-down operations and instructions to control the operation of
the Watchdog Timer for reliable program operations under extreme electric or electromagnetic
environments. For their relevant operations, refer to the functional related sections.
Rev. 1.10
130
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Instruction Set Summary
The following table depicts a summary of the instruction set categorised according to function and
can be consulted as a basic instruction reference using the following listed conventions.
Table Conventions
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
1
1Note
Z
Z
Z
Z
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rev. 1.10
131
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Mnemonic
Description
Cycles
Flag Affected
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1Note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (specific page) to TBLH and Data Memory
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
2Note
None
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRD [m]
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the “CLR WDT1” and “CLR WDT2” instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both “CLR WDT1” and “CLR WDT2”
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.10
132
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Instruction Definition
ADC A,[m]
Description
Operation
Affected flag(s)
Add Data Memory to ACC with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added.
The result is stored in the Accumulator.
ACC ← ACC + [m] + C
OV, Z, AC, C
ADCM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory with Carry
The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m] + C
OV, Z, AC, C
Add Data Memory to ACC
ADD A,[m]
Description
The contents of the specified Data Memory and the Accumulator are added.
The result is stored in the Accumulator.
Operation
Affected flag(s)
ACC ← ACC + [m]
OV, Z, AC, C
ADD A,x
Description
Operation
Affected flag(s)
Add immediate data to ACC
The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator.
ACC ← ACC + x
OV, Z, AC, C
ADDM A,[m]
Description
Operation
Affected flag(s)
Add ACC to Data Memory
The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory.
[m] ← ACC + [m]
OV, Z, AC, C
AND A,[m]
Description
Operation
Affected flag(s)
Logical AND Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ [m]
Z
AND A,x
Description
Operation
Affected flag(s)
Logical AND immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator.
ACC ← ACC ″AND″ x
Z
ANDM A,[m]
Description
Operation
Affected flag(s)
Logical AND ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND
operation. The result is stored in the Data Memory.
[m] ← ACC ″AND″ [m]
Z
Rev. 1.10
133
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
CALL addr
Description
Operation
Affected flag(s)
Subroutine call
Unconditionally calls a subroutine at the specified address. The Program Counter then
increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Stack ← Program Counter + 1
Program Counter ← addr
None
CLR [m]
Description
Operation
Affected flag(s)
Clear Data Memory
Each bit of the specified Data Memory is cleared to 0.
[m] ← 00H
None
CLR [m].i
Description
Operation
Affected flag(s)
Clear bit of Data Memory
Bit i of the specified Data Memory is cleared to 0.
[m].i ← 0
None
CLR WDT
Description
Operation
Affected flag(s)
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT1
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in
conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have
effect. Repetitively executing this instruction without alternately executing CLR WDT2 will
have no effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CLR WDT2
Description
Operation
Affected flag(s)
Pre-clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction
with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect.
Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
WDT cleared
TO ← 0
PDF ← 0
TO, PDF
CPL [m]
Description
Operation
Affected flag(s)
Complement Data Memory
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa.
[m] ← [m]
Z
Rev. 1.10
134
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
CPLA [m]
Description
Operation
Affected flag(s)
Complement Data Memory with result in ACC
Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which
previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
ACC ← [m]
Z
DAA [m]
Description
Operation
Affected flag(s)
Decimal-Adjust ACC for addition with result in Data Memory
Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value
resulting from the previous addition of two BCD variables. If the low nibble is greater than 9
or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6
will be added to the high nibble. Essentially, the decimal conversion is performed by adding
00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag
may be affected by this instruction which indicates that if the original BCD sum is greater than
100, it allows multiple precision decimal addition.
[m] ← ACC + 00H or
[m] ← ACC + 06H or [m] ← ACC + 60H or
[m] ← ACC + 66H
C
DEC [m]
Description
Operation
Affected flag(s)
Decrement Data Memory
Data in the specified Data Memory is decremented by 1.
[m] ← [m] − 1
Z
DECA [m]
Description
Operation
Affected flag(s)
Decrement Data Memory with result in ACC
Data in the specified Data Memory is decremented by 1. The result is stored in the
Accumulator. The contents of the Data Memory remain unchanged.
ACC ← [m] − 1
Z
HALT
Description
Operation
Affected flag(s)
Enter power down mode
This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power
down flag PDF is set and the WDT time-out flag TO is cleared.
TO ← 0
PDF ← 1
TO, PDF
INC [m]
Description
Operation
Affected flag(s)
Increment Data Memory
Data in the specified Data Memory is incremented by 1.
[m] ← [m] + 1
Z
INCA [m]
Description
Operation
Affected flag(s)
Increment Data Memory with result in ACC
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator.
The contents of the Data Memory remain unchanged.
ACC ← [m] + 1
Z
Rev. 1.10
135
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
JMP addr
Description
Operation
Affected flag(s)
Jump unconditionally
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Program Counter ← addr
None
MOV A,[m]
Description
Operation
Affected flag(s)
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ← [m]
None
MOV A,x
Description
Operation
Affected flag(s)
Move immediate data to ACC
The immediate data specified is loaded into the Accumulator.
ACC ← x
None
MOV [m],A
Description
Operation
Affected flag(s)
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ← ACC
None
NOP
Description
Operation
Affected flag(s)
No operation
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Description
Operation
Affected flag(s)
Logical OR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise
logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ [m]
Z
OR A,x
Description
Operation
Affected flag(s)
Logical OR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
ACC ← ACC ″OR″ x
Z
ORM A,[m]
Description
Operation
Affected flag(s)
Logical OR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
[m] ← ACC ″OR″ [m]
Z
RET
Description
Operation
Affected flag(s)
Return from subroutine
The Program Counter is restored from the stack. Program execution continues at the restored
address.
Program Counter ← Stack
None
Rev. 1.10
136
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
RET A,x
Description
Operation
Affected flag(s)
Return from subroutine and load immediate data to ACC
The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address.
Program Counter ← Stack
ACC ← x
None
RETI
Description
Operation
Affected flag(s)
Return from interrupt
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the
EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Program Counter ← Stack
EMI ← 1
None
RL [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← [m].7
None
RLA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left with result in ACC
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0.
The rotated result is stored in the Accumulator and the contents of the Data Memory remain
unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← [m].7
None
RLC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
[m].(i+1) ← [m].i; (i=0~6)
[m].0 ← C
C ← [m].7
C
RLCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory left through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the
Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the
Accumulator and the contents of the Data Memory remain unchanged.
ACC.(i+1) ← [m].i; (i=0~6)
ACC.0 ← C
C ← [m].7
C
RR [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← [m].0
None
Rev. 1.10
137
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
RRA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0
rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the
Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← [m].0
None
RRC [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
[m].i ← [m].(i+1); (i=0~6)
[m].7 ← C
C ← [m].0
C
RRCA [m]
Description
Operation
Affected flag(s)
Rotate Data Memory right through Carry with result in ACC
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
ACC.i ← [m].(i+1); (i=0~6)
ACC.7 ← C
C ← [m].0
C
SBC A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry
The contents of the specified Data Memory and the complement of the carry flag are
subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
ACC ← ACC − [m] − C
OV, Z, AC, C
SBCM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with Carry and result in Data Memory
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m] − C
OV, Z, AC, C
SDZ [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is 0
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
[m] ← [m] − 1
Skip if [m]=0
None
Rev. 1.10
138
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
SDZA [m]
Description
Operation
Affected flag(s)
Skip if decrement Data Memory is zero with result in ACC
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0,
the program proceeds with the following instruction.
ACC ← [m] − 1
Skip if ACC=0
None
SET [m]
Description
Operation
Affected flag(s)
Set Data Memory
Each bit of the specified Data Memory is set to 1.
[m] ← FFH
None
SET [m].i
Description
Operation
Affected flag(s)
Set bit of Data Memory
Bit i of the specified Data Memory is set to 1.
[m].i ← 1
None
SIZ [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is 0
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
[m] ← [m] + 1
Skip if [m]=0
None
SIZA [m]
Description
Operation
Affected flag(s)
Skip if increment Data Memory is zero with result in ACC
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy
instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
ACC ← [m] + 1
Skip if ACC=0
None
SNZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is not 0
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this
requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.
Skip if [m].i ≠ 0
None
SUB A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − [m]
OV, Z, AC, C
Rev. 1.10
139
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
SUBM A,[m]
Description
Operation
Affected flag(s)
Subtract Data Memory from ACC with result in Data Memory
The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
[m] ← ACC − [m]
OV, Z, AC, C
SUB A,x
Description
Operation
Affected flag(s)
Subtract immediate data from ACC
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
ACC ← ACC − x
OV, Z, AC, C
SWAP [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 ↔ [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affected flag(s)
Swap nibbles of Data Memory with result in ACC
The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
ACC.3~ACC.0 ← [m].7~[m].4
ACC.7~ACC.4 ← [m].3~[m].0
None
SZ [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0
If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Skip if [m]=0
None
SZA [m]
Description
Operation
Affected flag(s)
Skip if Data Memory is 0 with data movement to ACC
The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
ACC ← [m]
Skip if [m]=0
None
SZ [m].i
Description
Operation
Affected flag(s)
Skip if bit i of Data Memory is 0
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires
the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle
instruction. If the result is not 0, the program proceeds with the following instruction.
Skip if [m].i=0
None
Rev. 1.10
140
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
TABRD [m]
Description
Operation
Affected flag(s)
Read table (specific page) to TBLH and Data Memory
The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDC [m]
Description
Operation
Affected flag(s)
Read table (current page) to TBLH and Data Memory
The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
TABRDL [m]
Description
Operation
Affected flag(s)
Read table (last page) to TBLH and Data Memory
The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH.
[m] ← program code (low byte)
TBLH ← program code (high byte)
None
XOR A,[m]
Description
Operation
Affected flag(s)
Logical XOR Data Memory to ACC
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ [m]
Z
XORM A,[m]
Description
Operation
Affected flag(s)
Logical XOR ACC to Data Memory
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
[m] ← ACC ″XOR″ [m]
Z
XOR A,x
Description
Operation
Affected flag(s)
Logical XOR immediate data to ACC
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator.
ACC ← ACC ″XOR″ x
Z
Rev. 1.10
141
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the package information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant
section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.10
142
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
16-pin NSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.012
—
0.020
C’
—
0.390 BSC
—
D
—
—
0.069
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
—
8°
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
—
A
—
6.0 BSC
B
—
3.9 BSC
—
C
0.31
—
0.51
C’
—
9.9 BSC
—
D
—
—
1.75
E
—
1.27 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
—
8°
143
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
20-pin SSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.155 BSC
—
C
0.008
—
0.012
C’
—
0.341 BSC
—
D
—
—
0.069
E
—
0.025 BSC
—
0.0098
F
0.004
—
G
0.016
—
0.05
H
0.004
—
0.01
α
0°
—
8°
Symbol
A
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
—
6 BSC
—
B
—
3.9 BSC
—
C
0.20
—
0.30
C’
—
8.66 BSC
—
D
—
—
1.75
E
—
0.635 BSC
—
F
0.10
—
0.25
G
0.41
—
1.27
H
0.10
—
0.25
α
0°
—
8°
144
August 08, 2014
HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank 8-Bit Flash MCU
Copyright© 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.10
145
August 08, 2014