M62463AFP Dolby Pro Logic Surround Decoder REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Description The M62463AFP is a single chip Dolby Pro Logic surround decoder. This LSI has all of required functions for Dolby Pro Logic surround. Note: Dolby and the double-D symbol are trademarks of Dolby laboratories licensing corporation. San Francisco, CA94103-4813, USA. This device available only to licensees of Dolby Lab. Licensing and application information may be obtained from Dolby Lab. Features • Includes all functions necessary for Dolby Pro Logic surround ⎯ Adaptive matrix ⎯ Input auto-balance ⎯ Noise sequencer ⎯ Center mode control ON/OFF, WIDE/NORMAL/PHANTOM ⎯ Modified Dolby B type noise reduction ⎯ 4 channel (Lch/Rch/Cch/Sch) / 3 channel (Lch/Rch/Cch) ⎯ Digital delay Delay time: 15.4 to 51.2 ms • Cch/Sch master volume: 0 to –87 dB / 1 dB step, –∞ • 3-lines MCU control • Space surround such as Disco, Hall and Live • Digital echo for Karaoke function Delay time: 123,184 ms • Current control oscillation circuit for system clock System Configuration M62463AFP L Lch IN Input autobalance control Rch IN Adaptive matrix L−R 7 kHz LPF L+R 2 MIC IN Rch OUT C S' Noise sequencer Lch OUT R Modified S Dolby B-NR Center/ operating mode control Center master volume MCU interface DATA SCK REQ REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 1 of 16 Lch Rch Surround master volume Digital delay Master volume Cch OUT Sch OUT CENTER SURROUND REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 2 of 16 12 MICIN RIN 58 SW6 L+R 2 1 2 SW4 4 1 MICOUT 18 MIC VOL 3 2 L−R Input balance 19 20 S' Selector A/D SW5 D/A F.B.VOL Logic 10 Kbit SRAM Digital delay Adaptive matrix 32 C R L 31 33 Modified BNR WIDE NORMAL PHANTOM OFF Center mode control 2 1 SW3 PROLOGIC 4 1 4 1 SCK DATA MCU interface 16 REQ Master volume Master volume SW2 3 2 15 MUTE +/− MUTE BY-PASS 3 2 SW1 14 SPACE SORROUND PROLOGIC BY-PASS SPACE SORROUND + LPF LIN 57 Noise sequencer 6 7 8 3 4 5 2 1 SVOLOUT CVOLOUT ROUT LOUT M62463AFP Block Diagram LPF M62463AFP LBPF2 51 RLC7 RLC4 RLC1 RLC2 RLC5 PSC4 PSC1 PSC5 PSC2 PSC6 PSC3 DBC3 DBC2 DBC1 BNR IN 45 44 43 42 41 40 39 38 37 36 35 34 33 L+R L−R LBPF1 52 53 RBPF1 54 Combining S' networks L C R D/A BPF RBPF2 VCA Modified B-type NR decoder Dual-time constant and threshold switches Log difference amplifiers Full wave rectifier LPF 50 46 10 Kbit SRAM RLC6 47 F.B. VOL 49 48 BPF RLC8 RLC3 Pin Arrangement Auto balance RT 56 VCA SW4 L−R L R C SERVO 57 L+R 2 LIN 22 kΩ RIN 2 1 3 4 A/D 55 Logic LT Center mode control SW5 Selector 58 32 FBIN 31 LPF2 OUT 30 LPF2 IN2 29 LPF2 IN1 28 DAINT OUT 27 DAINT IN 26 DACONT 25 ADCONT 24 ADINT OUT 23 ADINT IN 22 LPF1 OUT 21 LPF1 IN2 20 LPF1 IN1 19 DSEL OUT 18 MICOUT 17 DVss 22 kΩ 63 NGC1 64 Noise sequencer SW2 VOL MCU interface VOL DATA C REQ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ROUT CVOLOUT CVOLIN COUT SOUT SVOLIN SVOLOUT CMC VREFD AGND MICIN DVdd DATA SCK REQ S 1 LOUT R SCK DVdd AGND L LPF NGC2 4 1 SW1 REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 3 of 16 DVss 62 4 CLK NGC3 1 3 MIC VOL 61 +/− 2 2 3 2 IREF + SW3 1 60 2 SW6 VREF 1 AVcc VREF 59 IREF AVcc M62463AFP Functional Description Function 1 Fundamental function for Dolby Pro Logic surround decoder 2 3 RAM for digital delay Surround delay time 4 Circuit for space surround 5 6 Echo delay time Feedback volume 7 Microphone volume 8 9 10 11 Cch/Sch master volume Bypass switch Output mute MCU interface 12 Current control oscillation circuit REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 4 of 16 Description Adaptive matrix Input auto-balance Noise sequencer Center mode control ON/OFF WIDE/NORMAL/PHANTOM Modified Dolby B type noise reduction 4 ch (L, R, C, S), 3 ch (L, R, C) mode switch 10-Kbit RAM 15.4, 20.5, 25.6, 29.2 ms (for Dolby Pro Logic surround) 51.2 ms (for space surround) Digital delay circuit can be used for space surround such as a Disco, Hall or Live, and Karaoke echo 123,184 ms Delay signal feedback volume –3 to –21 dB / 3 dB step, and –∞ Internal microphone volume 0 to –18 dB / 3 dB step, and –∞ 0 to –87 dB / 1 dB step, and –∞ Bypass the decode circuit Mute the Lch and Rch output Controlled by 3-lines serial data from MCU Including the chip address (2-bit) Including the oscillation circuit without external parts M62463AFP Absolute Maximum Ratings (Ta = 25°C, unless otherwise noted) Item Symbol Supply voltage Ratings 10.5 6.5 1 –20 to +75 –40 to +125 Vcc Vdd Pd Topr Tstg Power dissipation Operating temperature Storage temperature Unit V V W °C °C Recommended Operating Condition Item Supply voltage Input voltage (L) Input voltage (H) Symbol Vcc Vdd VIL VIH REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 5 of 16 Min 8 4.5 0 Vdd – 1 Typ 9 5 — — Max 10 5.5 0.8 Vdd Unit V V V V Condition 14, 15, 16 pin 14, 15, 16 pin M62463AFP Electrical Characteristics (Ta = 25°C, Vcc = 9 V, Vdd = 5 V, Cch volume = 0 dB, at C-OUT 0 dBd = 300 mVrms, f = 1 kHz, unless otherwise noted) Item Total Circuit current Circuit current Auto-Balance Capture range Error correction Adaptive Matrix Symbol Min Typ Max Unit Test Conditions ICC IDD — — 25 13 40 25 mA mA CPR CER — — 5 4 — — dB dB ΔVoL –0.5 0 0.5 dB L, R, Sch output No signal No signal Output level accuracy relative to Cch Matrix rejection Head room Total harmonic distortion S/N ratio MR HRAM THDAM SNAM 25 15 — 70 40 17 0.05 80 — — 0.2 — dB dB % dB L, R, C, Sch output L, R, C, Sch output L, R, Cch output, 30 kHzLPF Noise Sequencer Output noise level Vno –15 –12.5 –10 dB L, R, C, Sch output Rg = 0 Ω, weighted CCIR/ARM, 4 ch mode –0.5 0 0.5 dB L, R, Sch output Noise level accuracy relative ΔVno to Cch Modified B Noise Reduction (Sch volume = 0 dB, 0 dB reference is 300 mVrms/100 Hz at S-Out) VGNR — 5.1 — dB Vin = 0 dBd, f = 100 Hz –1.6 –3.0 –4.9 –6.8 — –0.1 –1.5 –3.4 –5.3 0.07 1.4 0 –1.9 –3.8 0.3 dB Vin = 0 dBd, f = 1.0 kHz Vin = –15 dBd, f = 1.4 kHz Vin = –20 dBd, f = 1.4 kHz Vin = –40 dBd, f = 5.0 kHz % 15 68 17 78 — — dB dB Vin = 0 dBd, f = 1 kHz, 30 kHzLPF THD = 1% Rg = 0 Ω, weighted CCIR/ARM ATTmax ATTmin VOLS1 VOLS2 CTVOL VnoVOL — –3.0 0.5 0.2 68 — –95 0 1.0 1.0 83 2.6 –87 3.0 1.5 1.8 — 5.2 dB dB dB dB dB μVrms THDLN SNLN — 95 0.002 100 0.05 — % dB L, Rch output, 30 kHzLPF L, Rch output Line cross-talk CTLN 70 80 — dB L input/R output, R input/L output Input impedance Zi 11 22 44 kΩ Gain between input and output Decode character 1 Decode character 2 Decode character 3 Decode character 4 Total harmonic distortion DEC1 DEC2 DEC3 DEC4 THDNR Head room S/N ratio HRNR SNNR Cch/Sch Master Volume Maximum attenuator Minimum attenuator Volume step Volume cross-talk Output noise voltage Line (Bypass mode) Total harmonic distortion S/N ratio REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 6 of 16 ATT = –∞, Vi = 2 Vrms ATT = 0 dB ATT = 0 to –40 dB ATT = –40 to –87 dB R input/CVOL, SVOL output ATT = –∞ M62463AFP (Ta = 25°C, Vcc = 9 V, Vdd = 5 V, Vin = 200 mVrms, f = 1 kHz, unless otherwise noted) Item Digital Delay Input/output voltage gain Delay time Total harmonic distortion Symbol GvD Td THDD Output noise voltage NoD Maximum output voltage LPF cut-off frequency Vomax LPFfc Min Typ Max Unit –8.1 17.4 — — — — — — 0.7 6.0 –5.1 20.5 0.5 1.2 3.0 –92 –84 –80 1.0 7.0 –2.1 23.6 0.9 2.2 5.6 –80 –70 –65 — 8.0 dB ms % Vrms kHz — 3.0 — kHz dBV Test Conditions LIN-LPF2OUT, surround L – R Td = 20.5 ms 30 kHz LPF Td = 20.5 ms Td = 51.2 ms Td = 184 ms Vin = 0 Vrms Td = 20.5 ms JIS-A Td = 51.2 ms Td = 184 ms THD = 10% Td = 15.4 to 51.2 ms Gv = –3 dB (Dolby Pro Logic mode) Td = 123,184 ms (Echo mode) Gv = –3 dB Feedback Volume Maximum attenuation Minimum attenuation Volume step FBATTmax FBATTmin FBVOLS — –6.0 — –70 –3.0 3.0 –60 0 — dB dB dB ATT = –∞ ATT = –3 dB Microphone Volume Maximum attenuation Minimum attenuation Volume step Output noise voltage MICATTmax MICATTmin MICVOLS VnoMIC — –3.0 — — –70 0 3.0 2.0 –60 3.0 — 4.0 dB dB dB μVrms ATT = –∞ ATT = 0 dB REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 7 of 16 ATT = –∞ M62463AFP Serial Data Control Format (1) Data input format DATA is read at the rising edge of SCK, and loaded last 16 bits at the rising edge of REQ. DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 "H" SCK REQ D0 D1 L L D2 D3 D4 Mode set D5 Logic mode H H Delay time L H D6 D7 D8 D9 Center mode Pro Auto- set to balance "L" Noise sequencer D14 D15 Sch volume D10 D11 D12 D13 L H Cch volume Chip address Surround/echo mode Test mode (user inhibit) (2) Control condition No. 1 2 3 4 Control Mode Mode set Pro Logic mode Center mode Delay time 5 6 7 Auto-balance Noise sequencer Surround/echo mode 8 9 Cch/Sch volume Chip address Contents Normal stereo/Dolby Pro Logic/space surround or echo/mute 4 ch Pro Logic/3 ch stereo Wide/Normal/Phantom/OFF 15.4, 20.5, 25.6, 29.2, 51.2 ms (for surround) 123,184 ms (for echo) Input auto-balance ON/OFF ON/OFF Lch/Rch/Cch/Sch Delay input L – R/(L + R) / 2 /MICin Feedback volume, microphone volume, delay output mixing 0 to –87 dB / 1 dB step, and –∞ Input data effect or not (3) Set conditions Mode Setting (D0 = "L", D1 = "L") D2 L L H H D3 L H L H Pro Logic Mode Setting (D0 = "L", D1 = "L") D4 L H Condition 4 ch Pro Logic 3 ch stereo REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 8 of 16 Condition Normal stereo (bypass) Dolby Pro Logic surround Space surround/echo Output mute Center Mode Setting (D0 = "L", D1 = "L") D5 L L H H D6 L H L H Condition Wide Normal Phantom OFF M62463AFP Delay Time Setting (D0 = "L", D1 = "H") D2 L L L L H H H D3 L L H H L L H D4 L H L H L H L Delay Time 15.4 ms 20.5 ms 25.6 ms 29.2 ms 51.2 ms 123 ms 184 ms Sampling Frequency 500 kHz 500 kHz 400 kHz 333 kHz 200 kHz 83.3 kHz 55.6 kHz LPF Cutoff Frequency 7 kHz 3 kHz Auto-Balance Setting (D0 = "L", D1 = "H") D5 L H Condition Auto-balance OFF Auto-balance ON Noise Sequencer (D0 = "H", D1 = "L") D2 D3 D4 L H — L L — L H H H L H Condition Noise sequencer OFF Noise sequencer ON Lch Rch Cch Sch Surround/Echo Mode (D0 = "H", D1 = "L") Surround/Echo Mode Switch D5 L H Condition Surround Echo Delay Input Delay Mixing Polarity D6 L H Delay Input L–R (L + R) / 2 Feedback Volume D7 L H Mixing Polarity L+ delay signal/R+ delay signal L+ delay signal/R– delay signal Microphone Volume D8 L D9 L D10 L L L L H H H H L H H L L H H H L H L H L H Volume –3 dB –6 dB –9 dB –12 dB –15 dB –18 dB –21 dB –∞ REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 9 of 16 D11 L D12 L D13 L L L L H H H H L H H L L H H H L H L H L H Volume 0 dB –3 dB –6 dB –9 dB –12 dB –15 dB –18 dB –∞ M62463AFP Relation Between Mode Setting and Switch Condition Mode Setting Pro Logic Mode (D0 = L, D1 = L) D4 Normal stereo (bypass) Dolby Pro Logic surround Mute Switch Condition SW3 SW4 D5 D6 SW1 SW2 SW5 SW6 X X X 1 1 2 4 OFF 2 L X X 3 3 1 1 OFF 2 2 3 ON 2 2 4 OFF 1 2 4 OFF 2 H X Space surround/echo Surround/Echo Mode (D0 = H, D1 = L) L (Surround) L H X H (Echo) X 2 2 Delay mixing ON 1 1 X X X Delay mixing OFF 4 4 2 1 Note: X: L or H Sch Volume Setting (D0 = "L", D1 = "L"), Cch Volume Setting (D0 = "L", D1 = "H") Volume Level 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB –32 dB –34 dB –36 dB –40 dB –44 dB –48 dB –52 dB –56 dB –60 dB –64 dB –68 dB –72 dB –76 dB –80 dB –84 dB –∞ D7 L L L L L L L L L L L L L L L L H H H H H H H H H H H H H H H H D8 L L L L L L L L H H H H H H H H L L L L L L L L H H H H H H H H D9 L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H D10 L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H Chip Address D14 L D15 H Others REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 10 of 16 Data Read Enable Unable D11 L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H Volume Level 0 dB –1 dB –2 dB –3 dB D12 L L H H D13 L H L H M62463AFP (4) Data timing t1, t2 90% DATA 10% t6 t7 t1 t4 t2 90% SCK 10% t10 t5 t9 t3 t8 90% REQ 10% t1 Symbol Name Min Typ t2 Max Unit t1 Signal rise time — — 0.5 μs t2 t3 t4 t5 t6 t7 t8 t9 t10 Signal fall time SCK clock width SCK "H" pulse width SCK "L" pulse width DATA setup time DATA hold time REQ rise hold time REQ "H" pulse width SCK setup time — 2 0.8 0.8 0.8 0.8 1.6 0.8 1.6 — — — — — — — — — 0.5 — — — — — — — — μs μs μs μs μs μs μs μs μs REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 11 of 16 M62463AFP Level Diagram (1) Dolby Pro Logic surround mode Cch LIN Input balance Center mode control Adaptive matrix RIN Signal level −3 dB 0 dB Volume (ATT = 0 dB) Ladder Buffer −2.5 dB 0 dB CVOLOUT Vref = 4.5 V Vref = 2.5 V Sch S' LIN 1 Input balance SW4 Adaptive matrix Digital delay Modified BNR 1 SW3 Volume (ATT = 0 dB) Ladder Buffer RIN Signal level −3 dB −5.1 dB 0 dB −5.1 dB 0 dB −2.5 dB 0 dB Vref = 4.5 V Vref = 2.5 V Vref = 2.5 V Lch, Rch LIN Input balance Adaptive matrix RIN Signal level Center mode control LOUT ROUT 0 dB Vref = 4.5 V Signal level: 0 dB = 300 mVrms (Typ) REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 12 of 16 SVOLOUT M62463AFP (2) Space surround mode Sch LIN L−R RIN (L + R) / 2 Signal level SW4 2 Digital delay 3 −5.1 dB 0 dB SW3 Modified BNR −5.1 dB 0 dB Volume (ATT = 0 dB) Ladder Buffer −2.5 dB 0 dB SVOLOUT Vref = 4.5 V Vref = 2.5 V Vref = 2.5 V (3) Echo mode SW4 MICIN Digital delay 4 0 dB Signal level Vref = 2.5 V MIC volume (ATT = 0 dB) 0 dB MICOUT Signal level Signal level: 0 dB = 300 mVrms (Typ) Vref = 2.5 V Notice Relation AVcc and DVdd at power supply Digital Vdd must be supplied less than 0.7 seconds from analog Vcc supply. AVcc (AVcc ≥ DVdd) DVdd Internal reset signal Automatic reset cancel 0.7 s (Min) REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 13 of 16 M62463AFP Application Example CA18 0.01 μ R18 4.7 k 0.1 μ C25 C21 1000 p C20 4700 p C18 C19 0.22 μ 1μ + 37 MCU 16 C13 0.1 μ C12 1 μ + 8 6 4 + 3 C 2 + C3 10 μ R C57 10 μ + Lin 61 + C2 10 μ 1 L 60 AVcc IREF C58 + 10 μ Rin C59 100 μ AVcc +9 V + C1 10 μ 64 63 62 59 58 57 56 55 VREF R61 + 100 k C60 220 μ C56 0.01 μ C54 0.01 μ C4 10 μ 22 kΩ R54 75 k 54 53 R53 47 k RA53 150 k 52 R52 75 k C53 680 p C52 0.01 μ C55 0.01 μ R51 47 k RA51 150 k C51 680 p 50 51 22 kΩ 49 Noise sequencer BPF REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 14 of 16 + VOL + SW1 + BPF C50 0.1 μ S 7 VOL R C 1 3 2 Selector L+R L−R Full wave rectifier 47 48 5 Auto balance 3 2 +/− 1 C46 0.1 μ C49 0.022 μ C6 10 μ SW2 4 C48 0.022 μ Sout C8 10 μ 4 VCA SERVO Log difference amplifiers L C R Center mode control S' 42 Combining networks + 10 9 2 46 C45 0.047 μ C9 0.1 μ 1 43 44 45 C44 0.047 μ C10 100 μ SW3 C42 0.22 μ C43 0.1 μ L+R 2 L−R C41 0.22 μ MICin 3 L 41 C40 4.7 μ 4 2 SW4 VCA 39 + C39 4.7 μ Dual-time constant and threshold switches + 40 C38 0.22 μ 1 + 38 2 11 AGND 1 C37 0.22 μ C47 0.1 μ 15 SW6 SW5 DVdd +5 V + F.B. VOL MIC VOL 12 C36 0.68 μ Logic DVdd 10 Kbit SRAM CLK Modified B-type NR decoder 34 35 36 R36 330 k 14 LPF 13 A/D DATA SCK REQ D/A MCU interface 33 DVss LPF C34 5600 p C35 0.047 μ 17 18 20 22 23 24 26 27 0.1 μ 0.1 μ 28 29 30 31 32 C32 1μ C33 1μ C26 19 0.1 μ C29 4700 p 25 C30 1000 p C23 21 MICout C27 + C64 47 μ C62 R63 C63 4.7 μ 100 k 6800 p Units Resistance: Ω Capacitance: F Cout Rout Lout M62463AFP External Parts List Parts No. C1 C2 C3 C4 C6 C8 C9 C10 C12 C13 C18 CA18 C19 C20 C21 C23 C25 C26 C27 C29 C30 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 Values 10 10 10 10 10 10 0.1 100 10 0.1 0.22 0.01 1.0 4700 1000 0.1 0.1 0.1 0.1 4700 1000 1.0 1.0 5600 0.047 0.68 0.22 0.22 4.7 4.7 0.22 0.22 0.1 0.047 0.047 0.1 Unit μF μF μF μF μF μF μF μF μF μF μF μF μF pF pF μF μF μF μF μF pF μF μF pF μF μF pF pF μF μF μF μF μF μF μF μF REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 15 of 16 Tol. 10% non-polar 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 10% 10% 10% 20% 20% 10% 10% 20% 5% 5% 20% Parts No. C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C62 C63 C64 R18 R36 R51 RA51 R52 R53 RA53 R54 R61 R63 Values 0.1 0.022 0.022 0.1 680 0.01 680 0.01 0.01 0.01 10 10 100 220 4.7 6800 47 Unit μF μF μF μF pF μF pF μF μF μF μF μF μF μF μF pF μF 4.7 330 47 150 75 47 150 75 100 100 kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ Tol. 20% 5% 5% 20% 5% 5% 5% 5% 5% 5% 10% 5% 10% 10% 5% 5% 5% 5% 5% 5% 1% 5% M62463AFP Package Dimensions JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g HD *1 D 48 33 49 32 *2 E HE NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Symbol 17 1 ZD ZE 64 16 c A2 Index mark A A1 F L Detail F e y D E A2 HD HE A A1 bp c *3 b p REJ03F0275-0200 Rev.2.00 Jun 16, 2008 Page 16 of 16 e y ZD ZE L Dimension in Millimeters Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0° 10° 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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