M52791SP/FP AV Switch with I2C Bus Control REJ03F0188-0200 Rev.2.00 Sep 14 2006 Description The M52791 is AV switch semiconductor integrated circuit with I2C bus control. This IC contains 1-channels of 4-input audio switches and 1-channels of 4-input video switches. Each audio switches and video switches can be controlled independently. The video switches contain amplifiers can be controlled a gain of output 0 dB or 6 dB. Features • • • • Video and stereo sound switches in one package Wide frequency range (video switch): DC to 20 MHz High separation (video switch): Crosstalk –60 dB (Typ) at 1 MHz Two types of packages are provided: SDIP with a lead pitch of 1.778 mm (M52791SP); and SSOP with a lead pitch of 0.8 mm (M52791FP). Application Video equipment Recommended Operating Condition Supply voltage: 4.7 V to 9.3 V Rated supply voltage: 5 V, 9 V Maximum output current: 49 mA (at 9 V) Rev.2.00 Sep 14, 2006 page 1 of 13 M52791SP/FP Block Diagram VCC 1 + 36 + 2 + 7 + TUNER IN 12 VIDEO 2 IN VIDEO 3 IN VIDEO 4 IN V-SW 0/6 dB 31 Y/C SEPA C IN S 34 Y/C Sepa. 32 Y IN Y-SW + 6 + 11 + Y 2 IN 16 Y 3 IN Y 4 IN 0/6 dB N 0 dB 0 dB 9 C 4 IN 0 dB 14 + 33 + 5 + 10 + 15 + 35 + 3 + 8 + 13 + Rch T IN 18 Rch 2 IN Rch 3 IN Rch 4 IN Lch T IN Lch 2 IN Lch 3 IN Lch 4 IN 25 Y 2 OUT 30 V 1 OUT 24 V 2 OUT 28 C 1 OUT 23 C 2 OUT 27 Rch 1 OUT 29 Lch 1 OUT 21 SDA 20 SCL 0/6 dB N 4 C 3 IN Y 1 OUT 0/6 dB C-SW C 2 IN 26 R-SW R-MODE R 0 dB M L L-SW L-MODE L 0 dB M R BIAS I2C Control BIAS 19 GND Rev.2.00 Sep 14, 2006 page 2 of 13 17 DA 22 CHIP SELECT M52791SP/FP Pin Arrangement M52791SP M52791FP VCC 1 36 TUNER IN VIDEO 2 IN 2 35 Lch T IN Lch 2 IN 3 34 C IN C 2 IN 4 33 Rch T IN Rch 2 IN 5 32 Y IN Y 2 IN 6 31 Y/C SEPA VIDEO 3 IN 7 30 V 1 OUT Lch 3 IN 8 29 Lch 1 OUT C 3 IN 9 28 C 1 OUT 27 Rch 1 OUT Rch 3 IN 10 VCC 1 36 TUNER IN VIDEO 2 IN 2 35 Lch T IN Lch 2 IN 3 34 C IN C 2 IN 4 33 Rch T IN Rch 2 IN 5 32 Y IN Y 2 IN 6 31 Y/C SEPA VIDEO 3 IN 7 30 V 1 OUT Lch 3 IN 8 29 Lch 1 OUT C 3 IN 9 28 C 1 OUT 27 Rch 1 OUT Rch 3 IN 10 Y 3 IN 11 26 Y 1 OUT Y 3 IN 11 26 Y 1 OUT VIDEO 4 IN 12 25 Y 2 OUT VIDEO 4 IN 12 25 Y 2 OUT Lch 4 IN 13 24 V 2 OUT Lch 4 IN 13 24 V 2 OUT C 4 IN 14 23 C 2 OUT C 4 IN 14 23 C 2 OUT 22 CHIP SELECT Rch 4 IN 15 22 CHIP SELECT Rch 4 IN 15 Y 4 IN 16 21 SDA Y 4 IN 16 21 SDA DA 17 20 SCL DA 17 20 SCL 19 GND BIAS 18 19 GND BIAS 18 (Top view) (Top view) Outline: 36P4E Lead pitch: 1.778 mm Outline: PRSP0036GA-B (36P2R-D) Lead pitch: 0.8 mm Rev.2.00 Sep 14, 2006 page 3 of 13 M52791SP/FP Pin Description 3 5 8 10 13 15 33 35 Lch 2 IN Rch 2 IN Lch 3 IN Rch 3 IN Lch 4 IN Rch 4 IN Rch T IN Lch T IN 4 9 14 34 C 2 IN C 3 IN C 4 IN C IN Peripheral Circuit Pins DC Voltage (V) 9V 3.6 V — 40 k VCC VIDEO 2 IN Y 2 IN VIDEO 3 IN Y 3 IN VIDEO 4 IN Y 4 IN Y IN TUNER IN Remarks 5 to 9 V Clamp in 4.7 V 29.6 k Name 1 2 6 7 11 12 16 32 36 30 k 4.7 V 29.6 k Pin No. 20 k VOL max = 0.4 V 18 BIAS 4.2 V 29.6 k DA 30 k 13.9 k 17.1 k 17 19 20 GND SCL Rev.2.00 Sep 14, 2006 page 4 of 13 — — VIL max = 1.5 V VIH min = 3.0 V At lin = 1 mA M52791SP/FP Pin No. Name Peripheral Circuit Pins DC Voltage (V) 21 SDA VIL max. = 1.5 V VIH min. = 3.0 V VOL max. = 0.4 V 22 CHIP SELECT SLAVE ADDRESS 0 to 1.5 V: 90H 2.5 to VCC: 92H OPEN: 90H 70 k 30 k 26 28 30 Y 1 OUT C 1 OUT V 1 OUT C OUT 4.0 V V OUT Y OUT SYNC CHIP DC = 2.9 V 5k 5k 27 29 Rch 1 OUT Lch 1 OUT 4.0 V 31 Y/C SEPA SYNC CHIP DC = 2.9 V 5k Rev.2.00 Sep 14, 2006 page 5 of 13 1.5 k C OUT 3.3 V V OUT Y OUT SYNC CHIP DC = 2.2 V 1.5 k C 2 OUT V 2 OUT Y 2 OUT 1.5 k 23 24 25 5k Remarks At lin = 3 mA M52791SP/FP I2C Bus I2C Bus (Inter IC Bus) is multi master bus system developed by PHILIPS. Two wires (SDA-serial data, SCL-serial clock) realize functions of start, stop, transferring data, synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function. SDA A MSB LSB A MSB LSB SCL S P 1 Note: 2 3 4 5 6 7 8 9 1 2 9 S: Start condition, a high to low transition of the SDA line while SCL is high P: Stop condition, a low to high transition of the SDA line while SCL is high A: Acknowledge Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Control This IC controls 2-channel switches with 2-byte data (DATA1 and DATA2). Video switches are controlled by DATA1. Audio switches are controlled by DATA2. S SLAVE ADDRESS A DATA1 A DATA2 A P S: Start A: Acknowledge P: Stop Slave address R/W bit Usually "0" (W: Master transmitter transmits to slave receiver) 1 0 0 1 0 0 X 0 Possible to select 22 pin High: 1, Low: 0 Rev.2.00 Sep 14, 2006 page 6 of 13 M52791SP/FP Data Byte Format M52791 FUNCTION TABLE S SLAVE ADDRESS A DATA (D7 to D0) A DATA (DF to D8) A P SLAVE ADDRESS SLAVE ADDRESS A6 1 A5 0 A4 0 A3 1 A2 0 A1 0 A0 0/1 R/W 0 DATA1 (D7 to D0) CONT DATA CONT D7 0 FIX D6 0 FIX D5 SEPA AMP D4 Y/C AMP D3 V AMP1 D2 S/N D1 D0 VIDEO SW CONT VIDEO SW CONT DATA OUT S/N (S:1) D2 D1 V-SW D0 V OUT Y/C SEPA Y OUT C OUT 0 0 0 0 0 1 T IN V 2 IN Y IN Y IN C IN C IN 0 0 1 1 0 1 V 3 IN V 4 IN Y IN Y IN C IN C IN 1 1 0 0 0 1 Y/C MIX T Y/C MIX 2 Y IN Y 2 IN C IN C 2 IN 1 1 1 1 0 1 Y/C MIX 3 Y/C MIX4 Y 3 IN Y 4 IN C 3 IN C 4 IN AMP GAIN CONT DATA D5 AMP SEPA AMP DATA D4 AMP Y/C AMP DATA D3 AMP V AMP 0 1 0 dB 6 dB 0 1 0 dB 6 dB 0 1 0 dB 6 dB DATA2 (DF to D8) CONT DATA CONT DF DE AUDIO MODE DD 0 FIX DC 0 FIX DB 0 FIX DA I/O D9 D8 AUDIO SW CONT AUDIO SW CONT MODE MUTE R/R L/L NORMAL DATA OUT OUT OUT OUT D9 D8 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 0 0 0 1 MUTE MUTE MUTE MUTE Rch T IN Rch 2 IN Rch T IN Rch 2 IN Lch T IN Lch 2 IN Lch T IN Lch 2 IN Lch T IN Lch 2 IN Rch T IN Rch 2 IN 1 1 0 1 MUTE MUTE MUTE MUTE Rch 3 IN Rch 4 IN Rch 3 IN Rch 4 IN Lch 3 IN Lch 4 IN Lch 3 IN Lch 4 IN Lch 3 IN Lch 4 IN Rch 3 IN Rch 4 IN Rev.2.00 Sep 14, 2006 page 7 of 13 M52791SP/FP I/O CONT DATA OUT DA 0 DA OUT HIGH 1 LOW AUDIO MODE CONT DATA MODE DF 0 DE 0 0 1 1 0 R/R L/L 1 1 NORMAL Rev.2.00 Sep 14, 2006 page 8 of 13 MUTE M52791SP/FP Electrical Characteristics (Ta = 25°C, VCC = 9 V, unless otherwise noted) Item Supply voltage Symbol VCC Min 4.7 Typ — Max 9.3 Unit V Circuit current Video Voltage gain ICC — — 49 42 64 55 mA VCC = 9 V, Vin = 0 Vp-p, Rl = ∞Ω VCC = 5 V, Vin = 0 Vp-p, Rl = ∞Ω G –0.5 0 0.5 dB f = 100 kHz, 1 Vp-p (0 dB) (T→V1OUT) 5.5 –0.5 6 0 6.5 0.5 f = 100 kHz, 1 Vp-p (6 dB) (T→V1OUT) f = 100 kHz, 1 Vp-p (0 dB) (Y→V1OUT) 5.5 –2.0 6 0 6.5 2.0 f = 100 kHz, 1 Vp-p (6 dB) (Y→V1OUT) f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (T→V1OUT) –2.0 –2.0 0 0 2.0 2.0 –2.0 4 0 — 2.0 — 2 4 — — — — ZIC 2 14 — 20 — 26 ZIV ZIY — — — — — — Crosstalk Audio CT — –60 –54 dB f = 1 MHz, 1 Vp-p T→V1OUT (at V2 mode) Voltage gain G –0.5 –0.5 0 0 0.5 0.5 dB f = 1 kHz, 1 Vp-p (VCC 9 V) (RT→R1OUT) f = 1 kHz, 1 Vp-p (VCC 5 V) (RT→R1OUT) Frequency characteristics Total harmonic distortion F THD –1 — 0 0.01 1 0.05 dB % f = 100 kHz/1 kHz, 1 Vp-p (RT→R1OUT) f = 1 kHz, 2 Vp-p, at 400 Hz HPE + 30 kHz LPF (RT→R1OUT) Dynamic range D 5.5 6.0 — Vp-p Output DC offset voltage VOFF –20 0 20 mV f = 1 kHz, Maximum with distortion < 0.5% (RT→R1OUT) (MODE: RT, R2, R3, R4→R1OUT) Input impedance Crosstalk Z1 CT 22 — 30 -90 38 -84 kΩ dB (RT, R2, R3, R4, LT, L2, L3, L4) 1 kHz, 1 Vp-p RT→R1OUT (at R2 mode) V Frequency characteristics Dynamic range Input impedance F D dB Test Condition f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (T→V1OUT) f = 10 MHz/100 kHz, 1 Vp-p (0 dB) (Y→V1OUT) Vp-p kΩ f = 10 MHz/100 kHz, 1 Vp-p (6 dB) (Y→V1OUT) f = 100 kHz VCC = 9 V (0 dB) (T→V1OUT) Maximum with VCC = 5 V (0 dB) (T→V1OUT) distortion VCC = 9 V (0 dB) (Y→V1OUT) <1.0% VCC = 5 V (0 dB) (Y→V1OUT) (C, C2, C3, C4) Clamp in (T, V2, V3, V4) Clamp in (Y, Y2, Y3, Y4) 2 I C Bus control signal Max. input high voltage VIH 3.0 — 5.0 Min. input low voltage Low level output voltage (SDA) VIL VOL 0.0 0.0 — — 1.5 0.4 High level input current Low level input current IIH IIL –10 –10 — — 10 10 µA SCL clock frequency Time of bus must be free before a new transmission can start fSCL tBUF 0.0 4.7 — — 100 — kHz µs Hold time at start condition The low period of the clock tHD; STA tLOW 4.0 4.7 — — — — The high period of the clock Step-up time for start condition tHIGH 4.0 — — tSU; STA 4.7 — — Rev.2.00 Sep 14, 2006 page 9 of 13 SDA = 3 mA SDA, SCL = 4.5 V SDA, SCL = 0.4 V M52791SP/FP Electrical Characteristics (cont.) (Ta = 25°C, VCC = 9 V, unless otherwise noted) Item Hold time DATA Symbol tHD; DAT Min 5.0 Typ — Max — Setup time DATA Rise time of both SDA and SCL line tSU; DAT tR 250 — — — — 1000 Fall time of both SDA and SCL line Setup time for stop condition tF — — 300 tSU; STO 4.0 — — Unit ns Test Condition µs I2C Bus Control Signal SDA tBUF tR tF tHD; STA SCL tSU; STO P S tLOW tHD; STA Rev.2.00 Sep 14, 2006 page 10 of 13 tHD; DAT tHIGH tSU; DAT tSU; STA Sr P M52791SP/FP Application Circuit Example 0.01 µF 100 µF TUNER IN 36 0.47 µF + 2 VIDEO 2 IN 3 Lch 2 IN 4 C 2 IN Lch T IN 35 + 75 Ω 0.01 µF Y/C Sepa. 0.47 µF + 5 Rch 2 IN 6 Y 2 IN 7 VIDEO 3 IN Y IN 32 0.47 µF 0.47 µF + 75 Ω Lch 3 IN 9 C 3 IN 0.01 µF 10 µF + 75 Ω 10 Rch 3 IN 75 Ω Lch 1 OUT 29 C 1 OUT 28 + 75 Ω 75 Ω OUT 1 75 Ω Rch 1 OUT 27 0.47 µF 11 Y 3 IN + 8 75 Ω + + 10 µF V 1 OUT 30 + Y/C SEPA 31 Y 1 OUT 26 75 Ω + + 75 Ω 75 Ω + 12 VIDEO 4 IN Y 2 OUT 25 + 0.47 µF 13 Lch 4 IN V 2 OUT 24 + VIDEO 3 IN TUNER IN 10 µF Rch T IN 33 10 µF 75 Ω 10 µF 0.01 µF C IN 34 M52791SP VIDEO 2 IN 10 µF 75 Ω + 75 Ω VCC + 1 + 0.47 µF + VCC 14 C 4 IN C 2 OUT 23 + VIDEO 4 IN 10 µF 75 Ω 0.01 µF 10 µF + 75 Ω 15 Rch 4 IN CHIP SELECT 22 Slave address change (VCC/GND) 0.47 µF + I/O Expand OUT 2 220 Ω 16 Y 4 IN SDA 21 5V 10 kΩ 17 DA SCL 20 220 Ω 10 kΩ I2C IN 5V 10 µF 10 kΩ + 18 BIAS Rev.2.00 Sep 14, 2006 page 11 of 13 GND 19 M52791SP/FP Note How To Use This IC • • • • Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between VCC and GND near the pins if possible. Assign an area as large as possible for grounding. Power-on Reset • The M52791 has an internal power-on reset function that sets each control register to "0" during IC power ON. • The power-on reset VTH has 2.5 V. Rev.2.00 Sep 14, 2006 page 12 of 13 M52791SP/FP Package Dimensions JEITA Package Code P-SSOP36-8.4x15-0.80 RENESAS Code PRSP0036GA-B Previous Code 36P2R-D MASS[Typ.] 0.5g E 19 *1 HE 36 F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 18 1 Index mark c D A *2 A2 y *3 bp L e A1 Detail F Rev.2.00 Sep 14, 2006 page 13 of 13 Reference Symbol D E A2 A A1 bp c HE e y L Dimension in Millimeters Min Nom Max 14.8 15.0 15.2 8.2 8.4 8.6 2.05 2.35 0 0.1 0.2 0.3 0.35 0.45 0.18 0.2 0.25 0° 8° 11.63 11.93 12.23 0.65 0.8 0.95 0.10 0.3 0.5 0.7 Sales Strategic Planning Div. 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