Power Crystal Oscillator With Feedback Stabilized Duty Cycle TM March 1999 AN9825 Authors: Ron Mancini, Jeff Lies Most crystal oscillators suffer from three drawbacks, they can’t drive much of a load, the duty cycle is not adjustable, and the duty cycle drifts. This crystal oscillator circuit solves these problems: three parallel gates drive heavy loads (inverters can be used if the enable function isn’t required), the duty cycle is adjustable from 25% to 75%, and drift is minimized by feedback. The oscillator circuit consists of C1, C2, C3, R1, R2, R10, one gate and the crystal. R1 and R10 bias the gate in its linear region, while the capacitors form a π filter around the crystal. The π network preserves the crystal’s Q, provides the correct loading capacitance for the crystal, and prevents oscillations at spur frequencies. R2 limits the crystal’s power dissipation to 5mW. The difference between the output voltage (3.9V) and the input voltage (2V) is about 1.9V (Typical TTL threshold voltage), so although it is an optimistic approximation, Equation 1 can be used to select R2. 2 2 1.9 1.9 R 2 ≥ ---------------------------- = ----------- K = 722 Ω PCRYSTAL 5 (EQ. 1) FO R P CRYSTAL = 5mW, SELECT R 2 = 750Ω R2 and C3 form a low pass filter whose -3dB point should be set at fOSC/8 or higher, this choice prevents spurious high frequency oscillations. The -3dB point for this design is selected as fOSC/8 = 625kHz. C3 is calculated from Equation 2. C 3 = 1/ 2πf R = 1/2π(6.25)(10 5 )(750) = 339pF ≈ 300pF input impedance, large output swing, and it functions with a 5V supply. U2A sums the integrated signal with the duty cycle set point voltage to create an error signal. The feedback loop keeps the duty cycle constant by changing the oscillator gate bias point until the error signal reaches zero. The output gates are paralleled for increased drive capability. All gates are in the same IC so they can safely be paralleled, and the oscillator/output gate delays will match well under reasonable loading. The enable input gates the oscillator output when required with just a gate delay. Gating the oscillator by turning it off/on incurs an oscillator start-up delay which is microseconds or longer. Replace the NAND gates with inverters when the enable function is not used. If the output loading changes during operation, the feedback point can be taken from the output to compensate for varying loads. Beware, ringing resulting from poorly terminated transmission lines can cause duty cycle variations when the feedback point is taken from the output. If minimizing duty cycle drift is not important, feedback is not required, so R10 can be split into a 2.5K fixed and a 5K variable resistor connected to ground. This selection of R10 enables 25% to 75% duty cycle adjustment. For different logic families you must verify, and possibly reselect, the gate bias resistors. (EQ. 2) 2 C1 must be a large value to minimize the effects of stray capacitance changes, so C 1 is selected as 510pF. The series combination of C1, C2, and C3 must equal the specified load capacitance for a parallel resonant crystal so: (EQ. 3) 1/ C = 1/ C - 1/C - 1/C 2 L 1 3 The load capacitance for the selected crystal is 32pF, requiring a C2 of 38.5pF, thus C 2 is selected as 39pF. With the component values shown, the circuit oscillates at 5MHz with a parallel resonant crystal. The duty cycle is a function of the gate bias point resistors, therefore variations in logic gates cause variations in duty cycle, typically 30% to 65% with normal manufacturing tolerances. The duty cycle adjustment compensates for this variation, and the feedback provided by the op amps reduces drift to a fraction of a percent. U1A integrates the oscillator output into a DC level. The ICL7621A was chosen for this function because it has high 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved Application Note 9825 +5V R11 10K ENABLE OUTPUT SQUARE WAVE R1 5K R9 100K +5V 74ACT00E R2 750 +5V 6 + 5 C2 4.9MHz P11 RCS 39pF 100K R3 8 R4 100K 7 U - IA (NOTE) 2 3 4 - UIB (NOTE) 1 + -5V R10 2K C1 510pF C3 300pF 100K 0.1µF C4 DUTY CYCLE ADJUST 500 +5V R6 1K R7 390 R8 NOTE: 1/2 of ICL7621A FIGURE 1. POWER CRYSTAL OSCILLATOR WITH FEEDBACK STABILIZED DUTY CYCLE All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. 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