### AN551 : Recommended Test Procedures for Operational

```Recommended Test Procedures for
Operational Amplifiers
Application Note
November 1996
AN551.1
Introduction
The following text describes the basic test procedures that
can be used for most Intersil Op Amps. Note that all
measurement conversions have been taken into account in
the equations stated.
3. Open S1, S2 and S3.
4. Measuring voltage at E in volts (label as E4).
IIO = (E1 - E4) x 100 (nA) for RF = 50K, RS = 10K, or
IIO = (E1 - E4) x 10 (nA) for RF = 50K, RS = 100K
1. Offset Voltage
The offset voltage (VIO) of the amplifier under test (AUT) is
measured via Test Circuit 1 as follows:
1. Set V+ and V- supplies to values specified in Table 1,
Column (1) and VDC to 0V.
2. Close S1 and S2, open S3.
3. Choose: RF = 50K for non-precision amplifiers.
RF = 5M for precision amplifiers.
4. Measure voltage at E in volts (label as E1).
VIO = E1 (mV) for RF = 50K, or
VIO = E1 *10 (µV) for RF = 5M
4. Power Supply Rejection Ratio
Both positive and negative PSRRs are measured via Test
Circuit 1. For PSRR+:
1. Close S1 and S2, open S3.
2. Choose: RF = 50K
3. Set VDC = 0, V+ = 10V, and V- = -15V.
4. Measure voltage at E in volts (label as E5).
5. Change V+ to +20V.
6. Measure voltage at E in volts (label as E6).
4
10
PSRR + = 20 log 10 ------------------- (dB) for R F = 50K
E5 – E6
The gain of this circuit with RF = 50K (RF = 5M) requires the
output to be driven to 1000 (100,000) times the offset voltage
necessary to maintain the output of the AUT at 0V. Note that
the AUT output is always identical to VDC. Overall circuit stability is maintained by the adjustable feed-back capacitor CA.
Similarly for PSRR-:
2. Input Bias Current
2. Set VDC = 0V, V+ = +15V, V- = -10.
3. Measure voltage at E in volts (label as E7).
The bias current flowing in or out of the positive terminal of
the AUT (IB+) is obtained using Test Circuit 1 by:
4. Change V- to -20V.
1. Measuring E1 as in procedure 1 (use RS = 100K for JFET
input devices).
2. Maintain VDC at 0V.
3. Close S2, open S1 and S3.
4. Measuring voltage at E in volts (label as E2).
IB+ = (E1 - E2) x 100 (nA) for RF = 50K, RS = 10K, or
IB+ = (E1 - E2) x 10 (nA) for RF = 50K, RS = 100K
The bias current flowing in or out of the negative terminal
(IB-) is found by:
1. Following steps 1 and 2 for IB+.
2. Close S1, open S2 and S3.
3. Measuring voltage at E in volts (label as E3).
IB- = (E1 - E3) x 100 (nA) for RF = 50K, RS = 10K, or
IB- = (E1 - E3) x 10 (nA) for RF = 50K, RS = 100K
1. Follow steps 1 and 2 for PSRR+ above.
5. Measure voltage at E in volts (label as E8).
4
10
PSRR - = 20 log 10 ------------------- (dB) for R F = 50K
E7 – E8
5. Common Mode Rejection Ratio
The CMRR is determined by adjusting Test Circuit 1 as
follows:
1. Close S1 and S2, open S3.
1. Choose: RF = 50K
2. Set V+ = +5V, V- = -25V, and VDC = -10V.
3. Measure voltage at E in volts (label as E9).
4. Set V+ = 25V, V- = -5V, and VDC = 10V.
5. Measure voltage at E in volts (label as E10).
4
2 × 10 (dB) for R = 50K
CMRR = 20 log 10 ---------------------F
E 9 – E 10
3. Input Offset Current
Using Test Circuit 1, the input offset current (IIO) of the AUT
is determined by:
1. Measuring E1 as in procedure 1.
6. Output Voltage Swing
Test Circuit 2 is adjusted to measure VOUT+ and VOUT- the
procedure is:
1. Select appropriate V+ and V- supply values from Table 1,
Column 1.
2. Maintaining VDC at 0V.
1
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© Intersil Corporation 1999
Application Note 551
2. Select specified RL from Table 1, Column 2.
9. Slew Rate
3. Set VIN = 0.5V.
4. Measure voltage at E in volts. VOUT+ = E (V)
Test Circuit 3 is used for measurement of positive and
negative slew rate. For SR+:
Similarly VOUT- is found by:
1. Select specified RL, ACL, and CL from Table 1, Columns
4, 5 and 6.
1. Selecting specified RL from Table 1, Column 1.
2. Setting VIN = -0.5V.
3. Measuring voltage at E in volts.
VOUT- = E (V)
7. Output Current
The output current corresponding to the output voltage of
procedure 6 is found by:
1. Measuring VOUT- and VOUT+ as in procedure 6.
V OUT+
I OUT = ------------------- where R L is from Table 1, Column 2.
RL
V OUTI OUT = ------------------ where R L is from Table 1, Column 2.
RL
2. Apply a positive step voltage to VAC (refer to data book
for test waveform).
3. Observe ∆V and ∆t at E. A standard approach is to use
the 10% and 90% points or else the 25% and 75% points
on the waveform.
OUTPUT
100%
90%
75%
50%
∆V
25%
10%
0%
∆t
∆V
SR = -------∆t
For SR- repeat above procedure with negative input pulse.
8. Open Loop Gain
Both positive (AVOL+) and negative (AVOL-) open loop gain
measurements are determined by adjusting Test Circuit 1.
∆V
SR- = -------∆t
For AVOL+:
10. Full Power Bandwidth
1. Close S1, S2 and S3.
Full power bandwidth is calculated by:
2. Select specified RL from Table 1, Column 3.
1. Measuring slew rate as above in procedure 9.
3. Set RF = 50K.
2. Measuring VOUT+ as in procedure 6. (Typically VOUT+ is
assumed to be the guaranteed minimum VOUT, usually
10V.)
4. Set VDC = 0V, V+ = +15V, and V- = -15V.
5. Measure voltage at E in volts (label as E13).
6. Set VDC = 10V.
7. Measure voltage at E in volts (label as E14).
10
A VOL+ = -------------------------- (V/mV) for R F = 50K
E 14 – E 13
For AVOL-:
1. Follow steps 1, 2, 3, 4, and 5 above.
2. Set VDC = -10V.
3. Measure voltage at E in volts (label as E15).
10
A VOL - = -------------------------- (V/mV) for R F = 50K
E 13 – E 15
SR+
FPBW = ------------------------------------------2πV OUT ( PEAK )
11. Rise Time, Fall Time and Overshoot
The small signal step response of the AUT is determined via
Test Circuit 3. The procedure requires:
1. Selecting the appropriate RL, ACL, and CL from Table 1,
Columns 4, 5 and 6.
2. Applying a positive input step voltage for rise time tR and
positive overshoot OS+.
Applying a negative input step voltage for fall time tF and
negative overshoot OS-.
(Refer to data book for input waveforms.)
3. Observe output of AUT noting the key points as shown.
2
Application Note 551
GAIN (dB)
OVERSHOOT
VFINAL
90%
VPEAK
(TYP. = 200mV)
f1
0dB, 0o
10%
FREQUENCY
P1
tR1 tR2
tF1 tF2
VPEAK - VFINAL
OS =
x 100(%)
VFINAL
tR = tR2 -tR1
tF = tF2 - tF1
12. Settling Time
Test Circuit 6 is appropriate for settling time (tS) measurement, the procedure is:
1. Select R1 and R2 such that AUT is at the ACL stated in
Table 1, Column 5.
2. Select R3 and R4 so that R3 ≥ 2R1 and R4 ≥ 2R2 with the
condition that the ratio
R1
R3
------- = ------- be maintained.
R2
R4
PHASE MARGIN
180o
PHASE
3. At a gain of 0dB (if ACL = 1 in Table 1, column 5), record
frequency f1 and corresponding phase P1.
Phase margin = 180 degrees - P1 degrees.
15. Input Noise Voltage
Test Circuit 5 is designed for measuring input noise voltage.
Use of the Quantec Noise Analyzer is recommended to
obtain measurements at 1Hz bandwidth around a specific
center frequency. The procedure is:
1. Set RG = 0
2. Set circuit card to gain of 10.
3. Apply step voltage as specified in data book.
3. Select measurement frequency of interest.
4. Measure the time from t1 (time input step applied) to t2
(the time ES settles to within a specified percentage of
VOUT - see data book). tS = t2 - t1
4. Record noise voltage (label as En1). Units are nV/√Hz.).
NOTE: Clipping diodes of Test Circuit 6 prevent overdrive of oscilloscope. (Recommend fast Schottky diodes.)
Using Test Circuit 5, the input noise current is obtained by:
16. Input Noise Current
13. Gain Bandwidth Product
1. Measure En1 as above for the desired frequency of
interest.
Test Circuit 4 is used for measuring GBP. The procedure is:
2. Adjust RG so that VO > 2En1 (label VO as En2).
1. Sweep VIN thru the required frequency range.
2. With a network analyzer view gain (dB) versus frequency
as below.
GAIN (dB)
2
In =
2
( E n2 ) – ( E n1 ) – 4kTR G
--------------------------------------------------------------------2
RG
Where K = 1.38 x 10-23 (Boltzmann's Constant)
T = 300oC (27oC)
AV
17. Channel Separation (Crosstalk)
FREQUENCY (Hz)
fC
3. At the voltage gain of interest (AV) determine the corresponding frequency fC. Note that chosen AV must be
greater than or equal to that stated in column 5 of Table 1.
GBP = AV x fC (Hz) where AV is in V/V.
14. Phase Margin (Network Analyzer Method)
Test Circuit 4 is used to obtain phase margin measurement.
The procedure is:
1. Sweep VIN thru the required frequency range.
2. Display gain in dB and phase in degrees versus
frequency on analyzer as shown.
3
Test Circuit 7 is used to measure channel separation (CS).
The procedure is as follows:
1. Apply VIN at the frequency of interest to input of
channel 1.
2. Select RL from Table 1, column 4.
3. Measure VO1.
4. Measure VO2 of channel 2.
V O2
CS = 20 log 10 -------------------- dB
100V O1
Application Note 551
TABLE 1.
PARAMETERS TO MEASURE
SLEW RATE, OS, tR, tF
(1)
SUPPLY VOLTAGE (VS)
(2)
VOUT
RL(kΩ)
(3)
AVOL
RL(kΩ)
(4)
RL(kΩ)
(5)
ACL
(6)
CL(pF)
HA-2400/04/05
±15
2
2
2
1
50
HA-2500/02/05
±15
2
2
2
1
50
HA-2510/12/15
±15
2
2
2
1
50
HA-2520/02/05
±15
2
2
2
3
50
HA-2539
±15
1
1
1
10
10
HA-2540
±15
1
1
1
10
10
HA-2541
±15
2
2
2
1
10
HA-2542
±15
1
1
1
2
10
HA-2600/02/05
±15
2
2
2
1
100
HA-2620/02/05
±15
2
2
2
5
50
HA-2640/05
±40
5
5
5
1
50
HA-4741
±15
10
2
2
1
50
HA-5101
±15
2
2
2
1
50
HA-5102/04
±15
2
2
2
1
50
HA-5111
±15
2
2
2
10
50
HA-5112/14
±15
2
2
2
10
50
HA-5127
±15
0.6
2
2
1
50
HA-5130/05
±15
0.6
2
2
1
100
HA-5134
±15
2
2
2
1
50
HA-5137
±15
0.6
2
2
5
50
HA-5141/12/14
+5/0
50
50
50
1
50
HA-5147
±15
0.6
2
2
10
50
HA-5151/12/14
±15
10
10
10
1
50
HA-5160/62
±15
2
2
2
10
50
HA-5170
±15
2
2
2
1
50
HA-5180
±15
2
2
2
1
50
HA-5190/95
±15
0.2
0.2
2
5
10
PART NUMBER
4
Application Note 551
Test Circuits
RF
S2
V+
V-
VDC
-1
RS = 10kΩ
-
500Ω
-
AUT
100Ω
S3
+
-
-1
RS = 10kΩ
+
BUFF
RL
S1
100Ω
CA
500Ω
+
X2
E
TEST CIRCUIT 1
V+
V+
-
VAC
V-
E
-
50
AUT
VIN
+
RF
E
+
RL
RL
CL
VRF
ACL = 1 + R
I
RI
RL(EFF) = (RF + RI)||RL
TEST CIRCUIT 2
V+
HP8601A
SWEEP GENERATOR
OR EQUIV.
VIN
TEST CIRCUIT 3
V+
V-
RG
+
+
HP8412A
ANALYZER
OR EQUIV.
AUT
-
V-
QUANTEC NOISE
ANALYZER
220Ω
AUT
NOTCH
FILTER
9kΩ
100kΩ
RL
CL
1kΩ
100Ω
TEST CIRCUIT 4
5
TEST CIRCUIT 5
VO
Application Note 551
Test Circuits
(Continued)
CHANNEL 1
(INPUT CHANNEL)
100kΩ
ES
R3
R4
CHANNEL 2
(LEAKAGE CHANNEL)
100kΩ
R1
V+
V+
V-
R2
VIN
VIN
VO
AUT
V-
V+
1kΩ
+
TEST CIRCUIT 6
V-
1kΩ
-
AUT
+
VO1
1kΩ
RL
VO2
AUT
+
RL
TEST CIRCUIT 7
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6
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