Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators ® Technical Brief December 2003 TB417.1 Author: Doug Mattingly Assumptions Output Filter This Technical Brief makes the following assumptions: The output filter consists of the output inductor and all of the output capacitance. It is important to include the DC resistance (DCR) of the output inductor and the total Equivalent Series Resistance (ESR) of the output capacitor bank. The input to the output filter is the PHASE node and the output is the regulator output. Figure 3 shows the equivalent circuit of the output filter and its transfer function. 1. The power supply designer has already designed the power stage of the single phase buck converter. The last step to the design is the compensation network. 2. The designer has at least a basic understanding of control systems theory. 3. The designer has a basic understanding of Bode plots. LO Introduction Synchronous and non-synchronous buck regulators have three basic blocks that contribute to the closed loop system. These blocks consist of the modulator, the output filter, and the compensation network which closes the loop and stabilizes the system. ERROR AMPLIFIER + REFERENCE OUTPUT OUTPUT FILTER MODULATOR _ VOUT DCR PHASE CO ESR GAIN FILTER 1 + s ⋅ ES R ⋅ C OUT = ---------------------------------------------------------------------------------------------------------------------------------------2 1 + s ⋅ ( ESR + DCR ) ⋅ C +s ⋅L ⋅C OUT OUT OUT FIGURE 3. THE OUTPUT FILTER COMPENSATION NETWORK FIGURE 1. BASIC BLOCKS OF THE BUCK REGULATOR Modulator The modulator is shown in Figure 2. The input to the modulator is the output of the error amplifier, which is used to compare the output to the reference. VIN The transfer function for the output filter shows the well known double pole of an LC filter. It is important to note that the ESR of the capacitor bank and the DCR of the inductor both influence the damping of this resonant circuit. It is also important to notice the single zero that is a function of the output capacitance and its ESR. Open Loop System Figure 4 illustrates the open loop system and presents the transfer function. DRIVER OSC PWM COMPARATOR ∆VOSC LO PHASE + OUTPUT OF ERROR AMPLIFIER E/A OUTPUT DRIVER DCR VOUT + CO ESR FIGURE 2. THE MODULATOR The output of the modulator is the PHASE node. The gain of the modulator is simply the input voltage to the regulator, VIN, divided by the peak-to-peak voltage of the oscillator, ∆VOSC, or: V 1 + s ⋅ ESR ⋅ C IN OUT GAINOPENLOOP = ---------------------- ⋅ --------------------------------------------------------------------------------------------------------------------------------------∆V 2 OSC 1 + s ⋅ ( ESR + DCR ) ⋅ C +s ⋅L ⋅C OUT OUT OUT FIGURE 4. THE OPEN LOOP SYSTEM V IN GAIN MODULATOR = ---------------------∆V OSC The peak to peak voltage of the oscillator can be obtained from the data sheet for the controller IC. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Technical Brief 417 Figure 5 shows the asymptotic Bode plot of the open loop system gain. V IN 20 ⋅ log ---------------∆V pp GAIN (dB) 0 Figure 7 shows the closed loop system with a Type II compensation network and presents the closed loop transfer function. The following guidelines will help calculate the poles and zeroes, and from those the component values, for a Type II network. FESR FLC 1. Choose a value for R1, usually between 2k and 5kΩ. -40dB/DEC -20dB/DEC FREQUENCY (Hz) FIGURE 5. OPEN LOOP SYSTEM GAIN Figure 5 represents a generic open loop system. Specific systems will have different double pole and ESR zero frequencies. For systems with very low DCR and ESR parameters, the phase will experience a very sharp slope downward at the double pole while the gain will have a rather high peak at the double pole. Systems that have such resonant output filters will be more difficult to compensate since the phase will need an extra boost to provide the necessary phase margin for stability. Systems such as this will typically need a Type III compensation, which will be discussed later in this brief. Closing The Loop - The Compensation Network Closing the control loop allows the regulator to adjust to load perturbations or changes in the input voltage which may adversely affect the output. Proper compensation of the system will allow for a predictable bandwidth with unconditional stability. In most cases, a Type II or Type III compensation network will properly compensate the system. The ideal Bode plot for the compensated system would be a gain that rolls off at a slope of -20dB/decade, crossing 0db at the desired bandwidth and a phase margin greater than 45o for all frequencies below the 0dB crossing. For synchronous and non-synchronous buck converters, the bandwidth should be between 20 to 30% of the switching frequency. Type II Compensation Figure 6 shows a generic Type II compensation, its transfer function and asymptotic Bode plot. The Type II network helps to shape the profile of the gain with respect to frequency and also gives a 90o boost to the phase. This boost is necessary to counteract the effects of the resonant output filter at the double pole. If the output voltage of the regulator is not the reference voltage then a voltage programming resistor will be connected between the inverting input to the error amplifier and ground. This resistor is used to offset the output voltage to a level higher than the reference. This resistor, if present, has no effect on the compensation and can be ignored. 2 2. Pick a gain (R2/R1) that will shift the Open Loop Gain up to give the desired bandwidth. This will allow the 0dB crossover to occur in the frequency range where the Type II network has a flat gain. The following equation will calculate an R2 that will accomplish this given the system parameters and a chosen R1. F ESR 2 DBW ∆V OSC R 2 = ----------------- ⋅ ----------------- ⋅ ---------------------- ⋅ R 1 V IN F LC F ESR 3. Calculate C2 by placing the zero a decade below the output filter double pole frequency: 10 C 2 = -----------------------------------2π ⋅ R 2 ⋅ F LC 4. Calculate C1 by placing the second pole at half the switching frequency: C2 C 1 = ----------------------------------------------------π ⋅ R 2 ⋅ C 2 ⋅ F sw – 1 Figure 8 shows the asymptotic Bode gain plot and the actual gain and phase equations for the Type II compensated system. It is recommended that the actual gain and phase plots be generated through the use of commercially available analytical software. Some examples of software that can be used are Mathcad, Maple, and Excel. The asymptotic plot of the gain and phase does not portray all the necessary information that is needed to determine stability and bandwidth. The compensation gain must be compared to the open loop gain of the error amplifier. The compensation gain should not exceed the error amplifier open loop gain because this is the limiting factor of the compensation. Once the gain and phase plots are generated and analyzed, the system may need to be changed somewhat in order adjust the bandwidth or phase margin. Adjust the location of the pole and/or zero to modify the profile of the plots. If the phase margin proves too difficult to correct, then a Type III system may be needed. Technical Brief 417 . C1 C2 R2 1 s + ------------------ R ⋅C 2 2 1 = -------------------- ⋅ -------------------------------------------------------GAIN TYPEII R ⋅C C +C 1 1 1 2 s ⋅ s + -------------------------------- R ⋅C ⋅C 2 1 2 R1 VOUT - GAIN (dB) REFERENCE -20dB/DEC VCOMP + 1 ------------------------------2π ⋅ R 2 ⋅ C 2 1 -------------------------------------------------- C1 ⋅ C2 2π ⋅ R ⋅ ---------------------- 2 C + C 1 2 1 ------------------------------2π ⋅ R 1 ⋅ C 1 R2 20 ⋅ log ------R 1 FREQUENCY (Hz) 0 -20dB/DEC FREQUENCY (Hz) 0 PHASE -30 90o PHASE “BOOST” -60 -90 FIGURE 6. GENERIC TYPE II NETWORK 3 Technical Brief 417 . VIN DRIVER OSC PWM COMPARATOR ∆VOSC LO + PHASE CO C1 C2 VOUT DCR ESR DRIVER R2 R1 VCOMP + REFERENCE 1 s + ------------------ V IN 1 + s ⋅ ESR ⋅ C OUT R 2 ⋅ C 2 1 = -------------------- ⋅ -------------------------------------------------------- ⋅ ---------------------- ⋅ ---------------------------------------------------------------------------------------------------------------------------------------GAIN SYSTEM ∆V 2 R1 ⋅ C1 C + C OSC 1 + s ⋅ ( ESR + DCR ) ⋅ C 1 2 +s ⋅L ⋅C OUT OUT OUT s ⋅ s + -------------------------------- R ⋅ C ⋅ C 2 1 2 FIGURE 7. CLOSED LOOP SYSTEM WITH TYPE II NETWORK ERROR AMP DC GAIN GAIN (dB) OPEN LOOP ERROR AMP GAIN GAIN BANDWIDTH PRODUCT 0.1FLC 0.5 FSW 0 -20dB/DEC MODULATOR & FILTER GAIN CONVERTER GAIN FLC FESR BANDWIDTH COMPENSATION GAIN FREQUENCY GAIN dB(f) = GAIN MODULATOR + GAIN FILTER + GAIN TYPEII PHASE(f) = PHASE MODULATOR + PHASE FILTER + PHASE TYPEII V IN Where: GAIN ---------------------- MODULATOR = 20 ⋅ log ∆V OSC GAIN FILTER = 10 ⋅ log 1 + ( 2πf ⋅ ESR ⋅ C OUT ) 2 2 2 2 + ( 2πf ⋅ ( ESR + DCR ) ⋅ C – 10 ⋅ log 1 – ( 2πf ) ⋅ L ⋅ OUT ) OUT C OUT 2πf ⋅ ESR + DCR ⋅ C OUT PHASE FILTER = atan [ 2πf ⋅ ESR ⋅ C OUT ] + atan ---------------------------------------------------------------------2 2πf ⋅ L OUT ⋅ C OUT – 1 C1 ⋅ C2 2 – 20 ⋅ log [ 2πf ⋅ R ⋅ ( C + C ) ] – 10 ⋅ log 1 + 2πf ⋅ R ⋅ ---------------------- 1 1 2 2 C 1 + C 2 C1 ⋅ C2 o PHASE TYPEII = – 90 + atan [ 2πf ⋅ R 2 ⋅ C 2 ] – atan 2πf ⋅ R2 ⋅ ---------------------- C 1 + C 2 GAIN TYPEII = 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C ) 2 2 2 FIGURE 8. TYPE II COMPENSATED NETWORK 4 Technical Brief 417 Type III Compensation Figure 9 shows a generic Type III compensation, its transfer function and asymptotic Bode plot. The Type III network shapes the profile of the gain with respect to frequency in a similar fashion to the Type II network. The Type III network, however, utilizes two zeroes to give a phase boost of 180o. This boost is necessary to counteract the effects of an under damped resonance of the output filter at the double pole. Figure 10 shows the closed loop system with a Type III compensation network and presents the closed loop transfer function. The guidelines for positioning the poles and zeroes and for calculating the component values are similar to the guidelines for the Type II network. 1. Choose a value for R1, usually between 2k and 5kΩ. 2. Pick a gain (R2/R1) that will shift the Open Loop Gain up to give the desired bandwidth. This will allow the 0dB crossover to occur in the frequency range where the Type III network has its second flat gain. The following equation will calculate an R2 that will accomplish this given the system parameters and a chosen R1. DBW ∆V OSC R 2 = -------------- ⋅ ---------------------- ⋅ R 1 V IN F LC 3. Calculate C2 by placing the zero at 50% of the output filter double pole frequency: 1 C 2 = --------------------------------π ⋅ R 2 ⋅ FLC 4. Calculate C1 by placing the first pole at the ESR zero frequency: C2 C 1 = --------------------------------------------------------------------2 ⋅ π ⋅ R 2 ⋅ C 2 ⋅ F ESR – 1 5. Set the second pole at half the switching frequency and also set the second zero at the output filter double pole. This combination will yield the following component calculations: R1 R 3 = -----------------------------F SW -------------------- – 1 2 ⋅ F LC 1 C 3 = ----------------------------------π ⋅ R 3 ⋅ FSW 5 Figure 11 shows the asymptotic Bode gain plot for the Type III compensated system and the gain and phase equations for the compensated system. As with the Type II compensation network, it is recommended that the actual gain and phase plots be generated through the use of a commercially available analytical software package that has the capability to plot. The compensation gain must be compared to the open loop gain of the error amplifier. The compensation gain should not exceed the error amplifier open loop gain because this is the limiting factor of the compensation. Once the gain and phase plots are generated the system may need to be changed after it is analyzed. Adjust the poles and/or zeroes in order to shape the gain profile and insure that the phase margin is greater than 45o. Technical Brief 417 C1 C3 R3 VOUT C2 R2 R1 REFERENCE VCOMP + 1 1 s + ------------------- ⋅ s + ------------------------------------ R ⋅C ( R 1 + R 3 ) ⋅ C 3 R +R 2 2 1 3 GAIN - ⋅ ----------------------------------------------------------------------------------------TYPEIII = ---------------------------R ⋅R ⋅C C +C 1 3 1 1 2 1 s ⋅ s + ----------------------------- ⋅ s + ------------------ R ⋅C R ⋅ C ⋅ C 3 3 2 1 2 1 --------------------------------------------------2π ⋅ ( R 1 + R 3 ) ⋅ C 3 1 -------------------------------------------------- C1 ⋅ C2 2π ⋅ R ⋅ ---------------------- 2 C + C 1 2 GAIN (dB) 1 ------------------------------------------------- R 1 ⋅ R 3 ⋅ C 1 2π ⋅ -------------------------------- R1 + R3 R2 20 ⋅ log ------R1 FREQUENCY (Hz) 0 1 ------------------------------2π ⋅ R 2 ⋅ C 2 1 ------------------------------2π ⋅ R 3 ⋅ C 3 180 PHASE 90 180o PHASE “BOOST” FREQUENCY (Hz) 0 -90 FIGURE 9. GENERIC TYPE III NETWORK 6 Technical Brief 417 VIN DRIVER OSC PWM COMPARATOR ∆VOSC LO + PHASE CO C1 C2 VOUT DCR ESR DRIVER C3 R2 R3 R1 VCOMP + REFERENCE 1 1 s + ------------------- ⋅ s + --------------------------------------- V IN 1 + s ⋅ ESR ⋅ C OUT R1 + R3 R 2 ⋅ C 2 ( R1 + R3 ) ⋅ C3 = -------------------------------- ⋅ ------------------------------------------------------------------------------------------------ ⋅ ---------------------- ⋅ ---------------------------------------------------------------------------------------------------------------------------------------GAIN SYSTEM ∆V OSC 2 R1 ⋅ R3 ⋅ C1 C1 + C2 1 1 + s ⋅ ( ESR + DCR ) ⋅ C OUT + s ⋅ L OUT ⋅ C OUT s ⋅ s + -------------------------------- ⋅ s + -------------------- R 2 ⋅ C 1 ⋅ C 2 R 3 ⋅ C 3 FIGURE 10. CLOSED LOOP SYSTEM WITH TYPE III NETWORK . FZ1=0.5FLC FP1=FESR FZ2=FLC FP2=.5FSW ERROR AMP DC GAIN CONVERTER GAIN GAIN (dB) OPEN LOOP ERROR AMP GAIN GAIN BANDWIDTH PRODUCT 0 -20dB/DEC MODULATOR & FILTER GAIN COMPENSATION GAIN FESR FLC BANDWIDTH FREQUENCY GAIN dB(f) = GAIN MODULATOR + GAIN FILTER + GAIN TYPEIII PHASE(f) = PHASE Where: MODULATOR + PHASE FILTER V IN GAIN MODULATOR = 20 ⋅ log ---------------------- ∆V OSC + PHASE GAIN FILTER = 10 ⋅ log 1 + ( 2πf ⋅ ESR ⋅ C OUT ) 2 TYPEIII 2 2 2 + ( 2πf ⋅ ( ESR + DCR ) ⋅ C – 10 ⋅ log 1 – ( 2πf ) ⋅ L ⋅ OUT ) OUT C OUT 2πf ⋅ ESR + DCR ⋅ C OUT PHASE FILTER = atan [ 2πf ⋅ ESR ⋅ C OUT ] + atan ---------------------------------------------------------------------2 2πf ⋅ L ⋅C –1 OUT OUT GAIN TYPEIII = 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C ) 2 2 2 C1 ⋅ C2 2 – 20 ⋅ log [ 2πf ⋅ R ⋅ ( C + C ) ] – 10 ⋅ log 1 + 2πf ⋅ R ⋅ ---------------------- 1 1 2 2 C + C 1 2 2 2 + 10 ⋅ log 1 + ( 2πf ⋅ ( R + R ) ⋅ C ) – 10 ⋅ log 1 + ( 2πf ⋅ R ⋅ C ) 1 3 3 3 3 C1 ⋅ C2 o PHASE TYPEIII = – 90 + atan [ 2πf ⋅ R 2 ⋅ C 2 ] – atan 2πf ⋅ R 2 ⋅ ---------------------- + atan [ 2πf ⋅ ( R 1 + R 3 ) ⋅ C 3 ] – atan [ 2πf ⋅ R 3 ⋅ C 3 ] C 1 + C 2 FIGURE 11. TYPE III COMPENSATED NETWORK 7 Technical Brief 417 Example The following example will illustrate the entire process of compensation design for a synchronous buck converter. Converter Parameters Input Voltage: Output Voltage: Controller IC: Osc. Voltage: Switching Frequency: Total Output Capacitance: Total ESR: Output Inductance: Inductor DCR: Desired Bandwidth: VIN VOUT IC ∆VOSC fSW COUT ESR LOUT DCR DBW 5V 3.3V ISL6520A 1.5V 300kHz 990µF 5mΩ 900nH 3mΩ 90kHz First, a Type II compensation network will be attempted. The low ESR of the output capacitance and the low DCR of the output inductor may make the implementation of a Type II network difficult. The guidelines given for designing a Type II network were followed in order to calculate the following component values: R1 = 4.12kΩ (chosen as the feedback component) R2 = 125.8kΩ C1 = 8.464pF C2 = 2.373nF These calculated values need to be replaced by standard resistor values before the gain and phase plots can be plotted and examined. R1 = 4.12kΩ R2 = 124kΩ C1 = 8.2pF C2 = 2.2nF Upon analysis of the bode plots in Figure 12, it can be seen that the system does not meet the stability criteria previously set. The bode plot for the gain is acceptable. The gain rolls off at 20dB/decade with a perturbation at the resonant point of the LC filter. After the perturbation, the gain again begins to roll off about 20dB/decade until it crosses 0dB right around 90kHz. The phase plot shows the problem with this Type II system. The low ESR and DCR values create a very sharp slope downward at the double pole of the LC filter. The dive in the phase is so sharp that the 90o phase boost of the Type II network does not compensate the phase enough to have sufficient phase margin. At approximately 6kHz, the phase margin goes below 45o and never recovers. There is nothing more that the Type II system can do to improve the phase. The Phase of the compensation is at it’s peak when the phase of the filter is at it’s minimum. Another problem with the Type II compensation network in this example is that the compensation gain intersects and then exceeds the gain of the error amplifier open loop gain. As the open loop gain of the error amplifier is the limiting factor to the compensation gain, the actual gain and phase is affected by the limit and will not exceed it. Due to these issues, a Type III network will need to be implemented to compensate for the phase properly. The guidelines for the Type III network were then followed to produce the following component values: R1 = 4.12kΩ (chosen as the feedback component) R2 = 20.863kΩ R3 = 151.85Ω C1 = 0.2587nF C2 = 2.861nF C3 = 6.987nF Again, these calculated values need to be replaced by standard resistor values before the gain and phase plots can be plotted and examined. R1 = 4.12kΩ R2 = 20.5kΩ R3 = 150Ω C1 = 0.22nF C2 = 2.7nF C3 = 6.8nF The gain plot of the Type III compensated system in Figure 13 looks very good. The gain rolls off at -20dB/decade from low frequency all the way to the 0dB crossover with a small perturbation from the LC filter double pole resonant point. The phase plot shows a system that is unconditionally stable. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 Technical Brief 417 100 ERROR AMP OPEN LOOP 80 GAIN COMPENSATION 60 GAIN COMPENSATION GAIN ENCROACHING ON ERROR AMP Gain [dB] 40 OPEN LOOP GAIN MODULATOR & FILTER GAIN 20 0 BANDWIDTH -20 SYSTEM GAIN -40 -60 10 100 1000 10000 100000 1000000 Frequency 0 COMPENSATION PHASE -20 SYSTEM PHASE -40 Phase [degrees] -60 -80 MODULATOR & FILTER -100 PHASE -120 -140 45° PHASE MARGIN -160 -180 10 100 1000 10000 100000 Frequency FIGURE 12. BODE PLOT OF THE TYPE II SYSTEM EXAMPLE 9 1000000 Technical Brief 417 100 ERROR AMP 80 OPEN LOOP GAIN 60 40 COMPENSATION GAIN 20 BANDWIDTH 0 -20 MODULATOR & FILTER GAIN SYSTEM GAIN -40 -60 10 100 1000 10000 100000 1000000 70 COMPENSATION PHASE MODULATOR & FILTER 20 PHASE -30 SYSTEM PHASE -80 -130 45° PHASE MARGIN -180 10 100 1000 10000 100000 FIGURE 13. BODE PLOT OF THE TYPE III SYSTEM EXAMPLE 10 1000000