FN7970 - Intersil

DATASHEET
40V, Low Quiescent Current, 50mA Linear Regulator
ISL80136
Features
The ISL80136 is a high voltage, low quiescent current linear
regulator ideally suited for “always-on” and “keep alive”
applications. The ISL80136 operates from an input voltage of
+6V to +40V under normal operating conditions, consuming
only 18µA of quiescent current at no load.
• Wide VIN range of 6V to 40V
The ISL80136 offers adjustable output voltages from 2.5V to
12V. It features an EN pin that can be used to put the device
into a low-quiescent current shutdown mode where it draws
only 1.8µA of supply current. The device features overtemperature shutdown and current limit protection.
• Low 1.8µA of typical shutdown current
The ISL80136 is rated over the -40°C to +125°C temperature
range and is available in an 8 lead EPSOIC with an exposed
pad package.
• Stable operation with 10µF output capacitor
TABLE 1. KEY DIFFERENCES IN FAMILY OF 40V LDO PARTS
PART NUMBER
MINIMUM IOUT
IC PACKAGE
ISL80136
50mA
8 Ld EPSOIC
ISL80138
150mA
14 Ld HTSSOP
• Adjustable output voltage from 2.5V to 12V
• Guaranteed 50mA output current
• Ultra low 18µA typical quiescent current
• ±1% accurate voltage reference
• Low dropout voltage of 120mV at 50mA
• 40V tolerant logic level (TTL/CMOS) enable input
• 5kV ESD HBM rated
• Thermal shutdown and current limit protection
Applications
• Industrial
• Networking
• Telecom
Related Literature
• ISL80138, “40V, Low Quiescent Current, 150mA Linear
Regulator”
• AN1784, “ISL80136EVAL1Z, ISL80138EVAL1Z Evaluation
Boards User Guide”
OUT
IN
CIN
0.1µF
R1
EN
PAD
(GND)
ADJ
R2
GND
COUT
10µF
QUIESCENT CURRENT (µA)
70
60
40
30
20
August 11, 2015
FN7970.2
1
LOAD = 0mA
10
0
-50
FIGURE 1. TYPICAL APPLICATION
LOAD = 50mA
50
0
50
100
TEMPERATURE (°C)
150
FIGURE 2. QUIESCENT CURRENT vs LOAD CURRENT (AT UNITY
GAIN), VIN = 14V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80136
Block Diagram
VIN
EN
CONTROL
LOGIC
+
FET DRIVER
WITH CURRENT
LIMIT
EA
REFERENCE
+
SOFT-START
THERMAL
SENSOR
VOUT
ADJ
GND
Pin Configuration
ISL80136
(8 LD EPSOIC)
TOP VIEW
IN
1
NC
2
8
OUT
7
ADJ
6
NC
5
GND
PAD
NC
3
EN
4
(GND)
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1
IN
Input voltage pin. A minimum 0.1µF X5R/X7R capacitor is required for proper operation. Range: 6V to 40V
2, 3, 6
NC
Pins have internal termination and can be left not connected. Connection to ground is optional.
4
EN
5
GND
High on this pin enables the device. Range: 0V to VIN
Ground pin.
7
ADJ
This pin is connected to the external feedback resistor divider, which sets the LDO output voltage.
8
OUT
Regulated output voltage. A 10µF X5R/X7R output capacitor is required for stability. Range: 0V to 12V
-
PAD
It is recommended to solder the PAD to the ground plane.
Submit Document Feedback
2
FN7970.2
August 11, 2015
ISL80136
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL80136IBEAJZ
80136 IBEAJZ
ISL80136EVAL1Z
Evaluation Platform
TEMP. RANGE
(°C)
ENABLE
PIN
OUTPUT VOLTAGE
(V)
-40 to +125
Yes
ADJ
PACKAGE
(RoHS Compliant)
8 Ld EPSOIC
PKG.
DWG. #
M8.15B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80136. For more information on MSL please see techbrief TB363.
Submit Document Feedback
3
FN7970.2
August 11, 2015
ISL80136
Absolute Maximum Ratings
Thermal Information
IN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +45V
OUT Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 16V
EN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to IN
ADJ Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to3V
Output Short-circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 5kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 2.2kV
Latch-up (Tested per JESD78B; Class II, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld EPSOIC Package (Notes 4, 5). . . . . . . .
50
9
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +175°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
IN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to +40V
OUT Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V to +12V
EN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, TA = TJ = -40°C to
+125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to
+125°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
6
Input Voltage Range
VIN
Guaranteed Output Current
IOUT
VIN = VOUT + VDO
VREF
EN = High, VIN = 14V, IOUT = 0.1mA to 50mA
MAX
(Note 8) UNITS
40
50
1.223
1.235
V
Line Regulation
(VOUT low line - VOUT high
line)/VOUT low line
6V < VIN < 40V, IOUT = 1mA
0.04
0.115
%
Load Regulation
(VOUT no load - VOUT high
load)/VOUT no load
VIN = 14V, IOUT = 100µA to 50mA
0.25
0.5
%
IOUT = 1mA, VOUT = 2.5V
10
38
mV
IOUT = 50mA, VOUT = 2.5V
ADJ Reference Voltage
VDO
Dropout Voltage (Note 6)
Shutdown Current
ISHDN
Quiescent Current
IQ
Power Supply Rejection Ratio
1.211
V
mA
130
340
mV
IOUT = 1mA, VOUT = 5V
10
48
mV
IOUT = 50mA, VOUT = 5V
120
350
mV
EN = LOW
1.8
3.64
µA
EN = HIGH, IOUT = 0mA
18
24
µA
EN = HIGH, IOUT = 1mA
22
42
µA
EN = HIGH, IOUT = 10mA
34
60
µA
EN = HIGH, IOUT = 50mA
56
82
µA
PSRR
f = 100Hz; VIN_RIPPLE = 500mVP-P; Load = 50mA
58
VEN_H
VOUT = Off to On
VEN_L
VOUT = On to Off
dB
EN FUNCTION
EN Threshold Voltage
EN Pin Current
IEN
EN to Regulation Time
(Note 7)
tEN
Submit Document Feedback
4
VOUT = 0V
1.485
0.935
V
V
0.026
1.65
µA
1.93
ms
FN7970.2
August 11, 2015
ISL80136
Electrical Specifications
Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, TA = TJ = -40°C to
+125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to
+125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8) UNITS
PROTECTION FEATURES
Output Current Limit
ILIMIT
VOUT = 0V
Thermal Shutdown
TSHDN
Junction Temperature Rising
Thermal Shutdown Hysteresis
THYST
60
118
mA
+165
°C
+20
°C
NOTES:
6. Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT.
7. Enable to Regulation is the time the output takes to reach 95% of its final value with VIN = 14V and EN is taken from VIL to VIH in 5ns. The output
voltage is set at 5V.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Submit Document Feedback
5
FN7970.2
August 11, 2015
ISL80136
Typical Performance Curves
VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25 °C unless otherwise specified.
80
30
+125°C
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (µA)
70
60
50
40
+25°C
30
-40°C
20
10
0
0
10
20
30
40
20
+25°C
10
5
0
10
20
30
40
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (NO LOAD)
FIGURE 3. QUIESCENT CURRENT vs LOAD CURRENT
3.0
0.010
% OUTPUT VOLTAGE VARIATION
SHUTDOWN CURRENT (µA)
-40°C
15
0
50
+125°C
25
2.5
VIN = 40V
2.0
1.5
VIN = 14V
1.0
0.5
0
-50
0
50
100
150
TEMPERATURE (°C)
0.005
VOUT = 5V
0
-0.005
-0.010
-50
VOUT = 3.3V
0
50
100
150
TEMPERATURE (°C)
FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE (EN = 0)
FIGURE 6. OUTPUT VOLTAGE vs TEMPERATURE (LOAD = 50mA)
5.100
OUTPUT VOLTAGE (V)
5.075
EN AT 500mV/DIV
5.050
+125°C
+25°C
5.025
5.000
-40°C
4.975
4.950
VOUT AT 1V/DIV
4.925
4.900
TIME AT 500µs/DIV
0
10
20
30
40
50
LOAD CURRENT (mA)
FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT
Submit Document Feedback
6
FIGURE 8. START-UP WAVEFORM
FN7970.2
August 11, 2015
ISL80136
Typical Performance Curves
VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25 °C unless otherwise specified. (Continued)
80
VOUT = 3.3V
70
IOUT = 0A
60
PSRR (dB)
VOUT AT 100mV/DIV
IOUT = 25mA
50
40
30
IOUT = 50mA
50mA
IOUT
20
0mA
10
TIME AT 5ms/DIV
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 10. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENT,
VOUT = 3.3V
FIGURE 9. LOAD TRANSIENT RESPONSE
90
70
IOUT = 0A
PSRR (dB)
60
NOISE (µV/√Hz)
80
10
VOUT = 5V
IOUT = 25mA
50
40
30
IOUT = 50mA
1
0.1
20
10
0
100
VIN = 14V
VOUT= 3.3V
COUT = 10µF
IOUT = 10mA
1k
10k
100k
0.01
10
1M
100
1k
10k
100k
FREQUENCY (Hz)
BW = 100<f<100kHz output noise voltage ~26 µVRMS
FREQUENCY (Hz)
FIGURE 11. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENT,
VOUT = 5V
FIGURE 12. OUTPUT NOISE SPECTRAL DENSITY, IOUT = 10mA
NOISE (µV/√Hz)
10
1
0.1
VIN = 14V
VOUT = 3.3V
COUT = 10µF
IOUT = 50mA
0.01
10
100
1k
10k
100k
FREQUENCY (Hz)
BW = 100<f<100kHz output noise voltage ~33 µVRMS
FIGURE 13. OUTPUT NOISE SPECTRAL DENSITY, IOUT = 50mA
Submit Document Feedback
7
FN7970.2
August 11, 2015
ISL80136
Functional Description
Output Voltage Setting
Functional Overview
The output voltage is programmed using an external resistor
divider, as shown in Figure 14.
The ISL80136 is a high performance, high voltage, low-dropout
regulator (LDO) with 50mA sourcing capability. The part is rated
to operate across the -40°C to +125°C temperature range.
Featuring ultra-low quiescent current, it makes an ideal choice
for “always-on” applications. It works well under a “load dump
condition” where the input voltage could rise up to 40V. The
device also features current limit and thermal shutdown
protection.
Enable Control
OUT
IN
CIN
0.1µF
R1
EN
COUT
10µF
ADJ
(ISL80136)
R2
GND
FIGURE 14. SETTING OUTPUT VOLTAGE
The ISL80136 features an Enable pin. When it is pulled low, the
IC goes into shutdown mode. In this condition, the device draws
less than 2µA. Driving the pin high turns the device on. For
always on operation, the EN pin can be tied directly to IN.
Current Limit Protection
The ISL80136 has internal current limit functionality to protect
the regulator during fault conditions. During current limit, the
output sources a fixed amount of current largely independent of
the output voltage. If the short or overload is removed from VOUT,
the output returns to normal voltage regulation mode.
Thermal Fault Protection
In the event that the die temperature exceeds typically +165°C,
the output of the LDO will shut down until the die temperature
cools down to typically +145°C. The level of power dissipated,
combined with the ambient temperature and the thermal
impedance of the package, will determine if the junction
temperature exceeds the thermal shutdown temperature. Also
see the section on “Power Dissipation”.
The output voltage is calculated using Equation 1:
R1
V OUT = 1.223V   -------- + 1
 R2

(EQ. 1)
Power Dissipation
The junction temperature must not exceed the range specified in
“Recommended Operating Conditions” on page 4. The power
dissipation can be calculated using Equation 2:
P D =  V IN – V OUT   I OUT + V IN  I GND
(EQ. 2)
The maximum allowable junction temperature, TJ(MAX) and the
maximum expected ambient temperature, TA(MAX) will determine
the maximum allowable junction temperature rise (TJ), as shown
in Equation 3:
T J = T J  MAX  – T A  MAX 
(EQ. 3)
To calculate the maximum ambient operating temperature, use
the junction-to-ambient thermal resistance (JA), as shown in
Equation 4:
Application Information
T J  MAX  = P D  MAX  x  JA + T A
Input and Output Capacitors
Board Layout Recommendations
For the output, a ceramic capacitor (X5R or X7R) with a
capacitance of 10µF is recommended for the ISL80136 to
maintain stability. The ground connection of the output capacitor
should be routed directly to the GND pin of the device and also
placed close to the IC. A minimum of 0.1µF (X5R or X7R) is
recommended at the input.
A good PCB layout is important to achieve expected
performance. Consideration should be taken when placing the
components and routing the trace to minimize the ground
impedance, and keep the parasitic inductance low. The input and
output capacitors should have a good ground connection and be
placed as close to the IC as possible. The ADJ feedback trace
should be away from other noisy traces. Connect the exposed
pad to the ground plane using as many vias as possible within
the pad for the best thermal relief.
Submit Document Feedback
8
(EQ. 4)
FN7970.2
August 11, 2015
ISL80136
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
August 11, 2015
FN7970.2
Removed DFN package option throughout the datasheet.
On page 1, updated Key Differences Table, Replaced “ADJ OR FIXED VOUT” Column with “IC PACKAGE” column.
On page 2, updated Block Diagram, removed two resistors and switched polarity of EA.
Electrical spec table on page 4:
-Removed “CIN = 0.1μF, COUT = 10μF” from the Electrical Specification heading.
-Updated the ADJ Reference Voltage Test Condition IOUT value from “IOUT = 0.1mA” to “IOUT = 0.1mA to
50mA”
-Updated the Line Regulation
*Symbol, from “VOUT/VIN” to “(VOUT low line - VOUT high line)/VOUT low line”.
*Test Conditions, from “3V ≤ VIN ≤ 40V, IOUT = 1mA” to “6V < VIN  40V, IOUT = 1mA”
-Updated the Load Regulation
*Symbol, from “VOUT/IOUT” to “(VOUT no load - VOUT high load)/VOUT no load”
*Test Conditions from “VIN = VOUT +VDO” to “VIN = 14V”
-Updated Dropout Voltage Test Condition VOUT value (First two rows only) from “VOUT = 3.3V” to
“VOUT = 2.5V”.
Updated Note 6 from “Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT when
VIN = VOUT + 3V.” to “Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT.”
Removed Figure 9, “POWER SUPPLY REJECTION RATIO (LOAD = 50mA)”
Added figures 10 through 13 on page 7.
January 31, 2012
FN7970.1
Added DFN package option throughout the datasheet.
December 15, 2011
FN7970.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
9
FN7970.2
August 11, 2015
ISL80136
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15B
N
INDEX
AREA
H
0.25(0.010) M
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
SIDE VIEW
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e

MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N

8
0°
8
7
8°
-
P
-
0.094
-
2.387
11
P1
-
0.094
-
2.387
11
Rev. 5 8/10
NOTES:
1
2
3
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
N
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
P
BOTTOM VIEW
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
Submit Document Feedback
10
FN7970.2
August 11, 2015