Application Note 1954
ISL70003SEH PSPICE Average Model
Introduction
Before using this macromodel, the Licensee should read this
license. If the Licensee does not accept these terms,
permission to use the model is not granted.
The ISL70003SEH is a radiation and SEE hardened
synchronous buck regulator capable of operating over an input
voltage range of 3.0V to 13.2V. The ISL70003SEH uses voltage
mode control architecture with feed-forward and switches at a
selectable frequency of 500kHz or 300kHz. Compensation is
externally adjustable to allow for an optimum balance
between stability and output dynamic performance. With
integrated MOSFETs and class leading radiation performance,
this highly efficient single chip power solution is an ideal
choice in many space point of load applications.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macromodel for use within
their company only.
This macromodel is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE.”
The PSPICE average model for the ISL700003SEH was
developed to help system designers evaluate the operation of
this IC prior to or in conjunction with prototyping a system
design. This model accurately simulates typical performance
characteristics such as loop analysis and transient analysis at
room temperature (+25°C). Functionality has been verified on
Cadence Orcad 16.6.
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with or
arising out of the use of this macromodel. Intersil reserves the
right to make changes to the product and the macromodel
without prior notice.
Reference Documents
Project File
• ISL70003SEH Data Sheet
The zip folder isl70003seh-pspice-files.zip contains all the
necessary files to simulate the average model including the
project file (isl70003seh.opj) and the model library
(isl70003seh_avg.lib). The application schematic mimics the
evaluation board, which is designed for 12V input to 3.3V
output conversion, see Figure 1. Three simulation profiles are
preset to run an AC loop analysis, start-up and 3A load
transient for rapid analysis of the ISL70003SEH, see Figures 4
through 9 for performance curves.
• ISL70003SEH SMD 5962-14203
License Statement
The information in this macromodel is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macromodel hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model as
long as the Licensee abides by the terms of this agreement.
ISL70003SEH_AVG
LOUT
U3
+
R11
VIN
PVIN
R13
{6m/4}
V1
R8
{29.1m/5}
AVDD
C5
{1u*5}
0
C1
1u
L2
{1.44n/5}
L5
{2.1n/4}
FB
FB
0
1
1
R14
10
D1
DMBR2045CTP/ON
C10
1000p
R3
1
12.0
C6
{100u*4}
LX
0
VERR
5m
VC_INDUCTOR
12p
R15
51.1k
ENABLE
ENABLE
REF
NI
0
FSEL
RLOAD
1.1
C11
0.1u
1
2
2700p
1000p
R12
3.3
I1
0
L4
1.44n
0
0
0
I2
TD = 10u
TF = 0.3us
PW = 100u
PER = 200u
I1 = 0
I2 = 3
TR = 0.3u
2
R6
V3
0
0
1
VOUT
RRT in kOhm
RCT
0.37
ICT
RRT
22
IRT
1
CT
VOUT
1Vac
0Vdc
R16
5.49k
0
CT
357
0
0
RT
RT
R5
25k
REF
REF
C15
0.22u
FSEL
C9
1u
VOUT2
C19
220n
0
C7
{150u*3}
C18
C16
1
VEN
R10
29.1m
L3
{2.1n/3}
LOUT
LOUT
R9
{6m/3}
1
0
0
V1 = 5
V2 = 5
TD = 10u
TR = 1u
TF = 1u
PW = 1
PER = 2
VOUT
0
COMP
2
0
OUT
L_1V = 1u
C17
PGND
2
-
U2
IN
0
RCT in nf
0
SEL2
SEL2
DE
V4
0
0
SEL1
SEL1
SS
0
C12
100n
0
0
FIGURE 1. ISL70003SEH AVERAGE MODEL APPLICATION SCHEMATIC
August 20, 2014
AN1954.0
1
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Application Note 1954
Pin Connections
Output Voltage - VOUT
The average model is an equation based model, which needs the
operating conditions of the buck regulator in order to properly
compute the response of the ISL70003SEH. In order to feed the
necessary inputs, the model has been modified to accept the
values for LOUT and VOUT.
Sawtooth Ramp - RT/CT
Inductor - LOUT
The model library, isl70003seh_avg.lib, contains the sub circuit
file vc_inductor.subckt. This four terminal inductor must be used
to appropriately set the output inductance value used within the
model. The IN pin of the inductor must be connected to the LX pin
of the ISL70003_AVG model and the OUT pin connects to the
output capacitors. A series resistor may be added in line with any
of these pins to mimic the DCR of the inductor. The “+” pin should
connect the LOUT pin of the ISL70003_AVG model and the “-” pin
connects to ground, see Figure 2.
ISL70003SEH_AVG
LOUT
U3
+
R11
PVIN
AVDD
LX
FB
R14
10
D1
DMBR2045CTP/ON
C10
1000p
FB
0
-
U2
IN
OUT
0
L_1V = 1u
5m
VC_INDUCTOR
VERR
12p
51.1k
LOUT
RT
RT
0
0
1
L4
1.44n
0
2
R6
CT
0
RRT
22
IRT
1
2
2700p
C16
1000p
R12
3.3
I1
RRT in kOhm
CT
RT
R5
357
25k
REF
C15
0.22u
RT
C9
1u
VOUT2
REF
FSEL
C7
{150u*3}
On the ISL70003SEH the RT/CT pin is connected to a resistor
and capacitor, which generates the sawtooth ramp that is the
input to the comparator that creates the PWM pulse train driving
the LX node. In the model, this pin is broken up into two pins
(RT and CT) in order to accurately model the feed-forward affect
of the regulator. A voltage source is needed at these two pins to
set the value for RT and CT. For the RT pin, 1V is equivalent to a
resistor of 1kΩ and for the CT pin, 1V is equivalent to a capacitor
of 1nF. Figure 3 demonstrates the connection to the RT and CT
pins. Note that a current source and resistor are used to generate
the voltage on these pins. This allows for easy parametric sweep
analysis as PSPICE does not allow tolerances on fixed DC voltage
sources.
C18
LOUT
1
NI
R10
29.1m
L3
{2.1n/3}
COMP
R15
ENABLE
R9
{6m/3}
1
0
C17
PGND
Another pin added to the ISL7003SEH_AVG model is the VOUT
pin. This pin is used to sense the output voltage of the regulator
and pass the information down into model to compute the
operating point. VOUT must be connected to the output voltage of
the regulator for the model to work properly.
0
0
0
FIGURE 2. VC_INDUCTOR.SUBCKT CONNECTION WITH DCR
To set the output inductor value, a voltage source must be added
to the LOUT pin of the ISL70003_AVG model. This voltage is then
converted to an inductance value by the equation within the
vc_inductor.subckt. The equation is L_1V = 1µ, which translates
to 1V is equal to 1µH of inductance. As an example, a 3.3V
voltage source connected to the LOUT pin would equal to 3.3µH
of the output inductance. In Figure 1, a DC current source and
resistor R12 are used to create the voltage on the LOUT pin. This
allows the user to easily analyze the effects of the inductor’s
tolerance by setting R12 as a parameter and performing a
parametric sweep simulation.
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1
R16
5.49k
2
VOUT
VOUT
RCT
0.37
ICT
0
RCT in nf
0
FIGURE 3. RT AND CT PIN CONNECTION
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August 20, 2014
Application Note 1954
Simulation Performance Curves
8.0
ENABLE, 5V/DIV
AVERAGE CURRENT
6.0
ENABLE
INDUCTOR CURRENT, 2A/DIV
4.0
OUTPUT VOLTAGE
OUTPUT VOLTAGE, 2V/DIV
2.0
PGOOD, 10V/DIV
0
0s
V(VOUT)
FIGURE 4. CHARACTERIZED SOFT-START WITH 6A LOAD
2ms
V(U3.ENABLE)
I(R11)
4ms
6ms
8ms
10ms
Time
FIGURE 5. SIMULATED SOFT-START WITH 6A LOAD
3.0A
AVERAGE CURRENT
INDUCTOR CURRENT, 2A/DIV
2.0A
1.0A
0A
3.45V
I(ILOAD)
3.40V
3.35V
OUTPUT VOLTAGE
3.30V
OUTPUT VOLTAGE, 50mV/DIV
SEL>>
3.25V
0.5ms
V(VOUT)
100
50
GAIN
0
0
-20
-50
-40
-100
-60
-150
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 8. CHARACTERIZED LOOP RESPONSE
1M
-200
150
40
GAIN (dB)
20
-80
10
200
PHASE
PHASE (°)
GAIN (dB)
40
2.5ms
80
150
PHASE
2.0ms
Time
100
50
GAIN
0
0
-50
PHASE (°)
200
60
1.5ms
FIGURE 7. SIMULATED 6A LOAD TRANSIENT RESPONSE
FIGURE 6. CHARACTERIZED 6A LOAD TRANSIENT RESPONSE
80
1.0ms
-100
-40
-150
-80
10
100
1k
10k
-200
1M
100k
FREQUENCY (Hz)
FIGURE 9. SIMULATED LOOP RESPONSE
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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