Total dose testing of the ISL7124SRH Radiation Hardened Quad operational amplifier Nick van Vonno Intersil Corporation Revision 0 18 August 2010 Table of Contents 1. 2. 3. 4. 5 6 7 8 9 Introduction Reference Documents Part Description Test Description 4.1 Irradiation facility 4.2 Test fixturing 4.3 Characterization equipment and procedures 4.4 Experimental Matrix 4.5 Downpoints Results 5.1 Test results 5.2 Variables data Discussion Conclusion Appendices Document revision history 1 1. Introduction This report reports the results of a low and high dose rate total dose test of the ISL7124SRH quad operational amplifier. The test was conducted in order to determine the sensitivity of the part to the total dose environment and to determine if dose rate and bias sensitivity exist. 2. Reference Documents MIL-STD-883G test method 1019.7 ISL7124SRH data sheet DSCC Standard Microcircuit Drawing (SMD) 5962-02542 3: Part Description The single-event radiation hardened ISL7124SRH consists of four independent internally frequency compensated operational amplifiers, specifically designed to operate from a single power supply over a wide range of voltages. The device is functionally equivalent to industry standard 124 types, offering improvements in supply current and power supply rejection ratio. Constructed with Intersil's dielectrically isolated, radiation hardened silicon gate (RSG) BiCMOS process, this device is immune to single event latchup. Additionally, the design has been hardened to prevent single event transients (SETs) in excess of 1V for LETs up to 36MeV/mg/cm2. The ISL7124SRH has been specifically designed and manufactured to provide reliable performance in harsh radiation environments. It is total dose hardened to 300krad(Si) at high dose rate and offers guaranteed performance over the full -55oC to +125oC military temperature range. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed electrical specifications for this device are contained in SMD 5962-02542. A "hot-link" is provided on the Intersil website for downloading. Figure 1: ISL7124SRH block diagram. 2 4: Test Description 4.1 Irradiation Facilities High dose rate testing was performed using a Gammacell 220 60Co irradiator located in the Palm Bay, Florida Intersil facility. Low dose rate testing was performed on a subcontract basis at White Sands Missile Range (WSMR) Survivability, Vulnerability and Assessment Directorate (SVAD), White Sands, NM, using a vault-type 60Co irradiator. The high dose rate irradiations were done at 55rad(Si)/s and the low dose rate work was performed at 0.010rad(Si)/s, both per MIL-STD883 Method 1019.7. Dosimetry for both tests was performed using Far West Technology radiochromic dosimeters and readout equipment. 4.2 Test Fixturing Figure 2 shows the configuration used for biased irradiation in conformance with Standard Microcircuit Drawing (SMD) 5962-02542. Figure 2: Irradiation bias configuration for the ISL7124SRH per Standard Microcircuit Drawing (SMD) 5962-02542. 4.3 Characterization equipment and procedures All electrical testing was performed outside the irradiator using the production automated test equipment (ATE) with datalogging at each downpoint. Downpoint electrical testing was performed at room temperature. Performing low dose rate testing at a remote site introduces some challenges, and shipping had to be done in a foam container with a frozen Gelpack™ along with a strip chart temperature recorder in order to remain well within the temperature limits imposed by MIL-STD-883 Test Method 1019.7. Close coordination between the two organizations is required, and support by WSMR is gratefully acknowledged. 3 4.4 Experimental matrix Total dose irradiations proceeded in accordance with the guidelines of MIL-STD-883 Test Method 1019.7. The experimental matrix consisted of five samples irradiated at high dose rate with all pins grounded, five samples irradiated at high dose rate under bias, five samples irradiated at low dose rate with all pins grounded and five samples irradiated at low dose rate under bias. One control unit was used. Samples of the ISL7124SRH die were drawn from wafer 3 of production lot DCR6TFA and were packaged in the standard hermetic 14-pin solder-sealed flatpack (CDFP4-F14) production package. Samples were processed through the standard burnin cycle before irradiation, as required by MIL-STD-883, and were screened to the SMD 5962-02542 limits at room, low and high temperatures prior to the test. 4.5 Downpoints Downpoints for the tests were zero, 50krad(Si), 100krad(Si) and 150krad(Si) for the high dose rate test and zero, 10krad(Si), 25krad(Si), 50krad(Si), 100krad(Si), 125krad(Si) and 150krad(Si) for the low dose rate test. 5: Results 5.1 Test results Testing at both dose rates to 150krad(Si) of the ISL7124SRH is complete. The part was found to be dose rate sensitive, with unbiased low dose rate irradiation worst case as expected. The input offset voltage was outside the +/-10mV SMD post-irradiation specification at the 100krad(Si) downpoint. The positive input bias current was close to the +/-400nA postirradiation limit at the 125krad(Si) downpoint but recovered somewhat at 150krad(Si). The cause of the bias current degradation is considered to be the gradually degradation of the current gain (‘beta’) of the input PNP transistor pair. The negative input bias current was outside the +/-400nA limit after 125krad(Si). The input offset current remained very stable, indicating that the input pair current gain remains well-matched in spite of the degradation in absolute value. Open-loop voltage gain was outside the 20V/mV (86dB) minimum limit at the 100krad(Si) downpoint. Common-mode rejection ratio data for Channel 3 was of doubtful quality, as was the positive and negative slew rate data for Channels 2 and 4. We have plotted this anomalous data for information only. The part is considered low dose rate sensitive but remains within the SMD post-irradiation limits to a maximum of 50krad(Si) in this environment. Similarly, we observed some bias sensitivity in the low dose rate results. 5.2 Variables data The plots in Figures 3 through 59 show data at all downpoints. The plots show the median of key parameters as a function of total dose for each of the four irradiation conditions. We chose to plot the median for these parameters due to the relatively small sample sizes. 4 15 Input offset voltage, channel 1, mV High dose rate, unbiased 10 High dose rate, biased Low dose rate, unbiased 5 Low dose rate, biased 0 -5 -10 -15 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 3: ISL7124SRH input offset voltage, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased (all pins grounded) and the biased (per Figure 2) cases. The low dose rate was 0.01rad(Si)/s and the high dose rate 55rad(Si)/s. Sample size for each cell was 5. The post-irradiation SMD limits are -10mV to +10mV. 15 Input offset voltage, channel 2, mV High dose rate, unbiased 10 High dose rate, biased Low dose rate, unbiased 5 Low dose rate, biased 0 -5 -10 -15 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 4: ISL7124SRH input offset voltage, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased (all pins grounded) and the biased (per Figure 2) cases. The low dose rate was 0.01rad(Si)/s and the high dose rate 55rad(Si)/s. Sample size for each cell was 5. The post-irradiation SMD limits are -10mV to +10mV. 5 15 Input offset voltage, channel 3, mV High dose rate, unbiased 10 High dose rate, biased Low dose rate, unbiased 5 Low dose rate, biased 0 -5 -10 -15 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 5: ISL7124SRH input offset voltage, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -10mV to +10mV. 15 Input offset voltage, channel 4, mV High dose rate, unbiased 10 High dose rate, biased Low dose rate, unbiased 5 Low dose rate, biased 0 -5 -10 -15 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 6: ISL7124SRH input offset voltage, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -10mV to +10mV. 6 Positive input bias current, channel 1, nA 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased Low dose rate, biased 100 0 -100 -200 -300 -400 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 7: ISL7124SRH positive input bias current, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. Positive input bias current, channel 2, nA 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased Low dose rate, biased 100 0 -100 -200 -300 -400 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 8: ISL7124SRH positive input bias current, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. 7 Positive input bias current, channel 3, nA 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased Low dose rate, biased 100 0 -100 -200 -300 -400 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 9: ISL7124SRH positive input bias current, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. Positive input bias current, channel 4, nA 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased Low dose rate, biased 100 0 -100 -200 -300 -400 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 10: ISL7124SRH positive input bias current, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. 8 Negative input bias current, channel 1, nA 500 400 High dose rate, unbiased High dose rate, biased 300 Low dose rate, unbiased 200 Low dose rate, biased 100 0 -100 -200 -300 -400 -500 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 11: ISL7124SRH negative input bias current, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. Negative input bias current, channel 2, nA 500 400 High dose rate, unbiased 300 High dose rate, biased Low dose rate, unbiased 200 Low dose rate, biased 100 0 -100 -200 -300 -400 -500 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 12: ISL7124SRH negative input bias current, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. 9 Negative input bias current, channel 3, nA 500 400 High dose rate, unbiased High dose rate, biased 300 Low dose rate, unbiased 200 Low dose rate, biased 100 0 -100 -200 -300 -400 -500 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 13: ISL7124SRH negative input bias current, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. Negative input bias current, channel 4, nA 500 400 High dose rate, unbiased 300 High dose rate, biased Low dose rate, unbiased 200 Low dose rate, biased 100 0 -100 -200 -300 -400 -500 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 14: ISL7124SRH negative input bias current, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -400nA to +400nA. 10 150 Input offset current, channel 1, nA High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 50 Low dose rate, biased 0 -50 -100 -150 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 15: ISL7124SRH input offset current, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -150nA to +150nA. 150 Input offset current, channel 2, nA High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 50 Low dose rate, biased 0 -50 -100 -150 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 16: ISL7124SRH input offset current, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -150nA to +150nA. 11 150 Input offset current, channel 3, nA High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 50 Low dose rate, biased 0 -50 -100 -150 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 17: ISL7124SRH input offset current, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -150nA to +150nA. 150 Input offset current, channel 4, nA High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 50 Low dose rate, biased 0 -50 -100 -150 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 18: ISL7124SRH input offset current, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limits are -150nA to +150nA. 12 Large signal voltage gain, channel 1, V/mV 120 110 High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 90 Low dose rate, biased 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 19: ISL7124SRH large signal open-loop voltage gain, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 20V/mV minimum (86dB). Large signal voltage gain, channel 2, V/mV 120 High dose rate, unbiased 110 High dose rate, biased 100 Low dose rate, unbiased 90 Low dose rate, biased 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 20: ISL7124SRH large signal open-loop voltage gain, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 20V/mV minimum (86dB). 13 Large signal voltage gain, channel 3, V/mV 120 110 High dose rate, unbiased 100 High dose rate, biased 90 Low dose rate, unbiased 80 Low dose rate, biased 70 60 50 40 30 20 10 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 21: ISL7124SRH large signal open-loop voltage gain, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 20V/mV minimum (86dB). Large signal voltage gain, channel 4, V/mV 120 110 High dose rate, unbiased 100 High dose rate, biased Low dose rate, unbiased 90 Low dose rate, biased 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 22: ISL7124SRH large signal open-loop voltage gain, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 20V/mV minimum (86dB). 14 Output low voltage, channel 1, mV 900 800 700 600 500 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased 100 Low dose rate, biased 0 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 23: ISL7124SRH output low voltage, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 900mV maximum. 900 Output low voltage, channel 2, mV 800 700 600 500 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased Low dose rate, biased 100 0 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 24: ISL7124SRH output low voltage, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 900mV maximum. 15 900 Output low voltage, channel 3, mV 800 700 600 500 400 High dose rate, unbiased 300 High dose rate, biased 200 Low dose rate, unbiased 100 Low dose rate, biased 0 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 25: ISL7124SRH output low voltage, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 900mV maximum. Output low voltage, channel 4, mV 900 800 700 600 500 400 300 High dose rate, unbiased High dose rate, biased 200 Low dose rate, unbiased 100 Low dose rate, biased 0 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 26: ISL7124SRH output low voltage, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 900mV maximum. 16 30 Output high voltage, channel 1, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 27: ISL7124SRH output high voltage, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 23V minimum. 30 Output high voltage, channel 2, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 28: ISL7124SRH output high voltage, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 23V minimum. 17 30 Output high voltage, channel 3, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 29: ISL7124SRH output high voltage, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 23V minimum. 30 Output high voltage, channel 4, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 30: ISL7124SRH output high voltage, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 23V minimum. 18 30 Output voltage swing, channel 1, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 31: ISL7124SRH output voltage swing, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 22V minimum. 30 Output voltage swing, channel 2, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 32: ISL7124SRH output voltage swing, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 22V minimum. 19 30 Output voltage swing, channel 3, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 33: ISL7124SRH output voltage swing, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 22V minimum. 30 Output voltage swing, channel 4, V High dose rate, unbiased 29 High dose rate, biased Low dose rate, unbiased 28 Low dose rate, biased 27 26 25 24 23 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 34: ISL7124SRH output voltage swing, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 22V minimum. 20 Quiescent power supply current, mA 3.00 High dose rate, unbiased 2.50 High dose rate, biased Low dose rate, unbiased 2.00 Low dose rate, biased 1.50 1.00 0.50 0.00 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 35: ISL7124SRH quiescent power supply current as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 3mA maximum. Positive power supply rej. ratio, ch 1, dB 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 36: ISL7124SRH positive power supply rejection ratio, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 21 Positive power supply rej. ratio, ch 2, dB 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 37: ISL7124SRH positive power supply rejection ratio, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. Positive power supply rej. ratio, ch 3, dB 120 115 High dose rate, unbiased 110 High dose rate, biased Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 38: ISL7124SRH positive power supply rejection ratio, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 22 Positive power supply rej. ratio, ch 4, dB 120 High dose rate, unbiased 115 High dose rate, biased 110 Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 39: ISL7124SRH positive power supply rejection ratio, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. Negative power supply rej. ratio, ch 1, dB 120 High dose rate, unbiased 115 High dose rate, biased 110 Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 40: ISL7124SRH negative power supply rejection ratio, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 23 Negative power supply rej. ratio, ch 2, dB 120 High dose rate, unbiased 115 High dose rate, biased 110 Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 41: ISL7124SRH negative power supply rejection ratio, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. Negative power supply rej. ratio, ch 3, dB 120 High dose rate, unbiased 115 High dose rate, biased 110 Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 42: ISL7124SRH negative power supply rejection ratio, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 24 Negative power supply rej. ratio, ch 4, dB 120 High dose rate, unbiased 115 High dose rate, biased 110 Low dose rate, unbiased 105 Low dose rate, biased 100 95 90 85 80 75 70 0 25 50 75 100 125 150 Total dose, krad(Si) Common mode rejection ratio, channel 1, dB Figure 43: ISL7124SRH negative power supply rejection ratio, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 44: ISL7124SRH common mode rejection ratio, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 25 Common mode rejection ratio, channel 2, dB 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Common mode rejection ratio, channel 3, dB Figure 45: ISL7124SRH common mode rejection ratio, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 46: ISL7124SRH common mode rejection ratio, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. 26 Common mode rejection ratio, channel 4, dB 120 115 110 105 100 95 90 High dose rate, unbiased 85 High dose rate, biased 80 Low dose rate, unbiased 75 Low dose rate, biased 70 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 47: ISL7124SRH common mode rejection ratio, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is 70dB minimum. Positive slew rate, channel 1, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 48: ISL7124SRH positive slew rate, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. 27 Positive slew rate, channel 2, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 49: ISL7124SRH positive slew rate, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. Positive slew rate, channel 3, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 50: ISL7124SRH positive slew rate, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. 28 Positive slew rate, channel 4, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased 3.4 Low dose rate, biased 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 51: ISL7124SRH positive slew rate, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. Negative slew rate, channel 1, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 52: ISL7124SRH negative slew rate, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. 29 Negative slew rate, channel 2, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 53: ISL7124SRH negative slew rate, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. Negative slew rate, channel 3, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 54: ISL7124SRH negative slew rate, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. 30 Negative slew rate, channel 4, V/µs 4.9 High dose rate, unbiased 4.4 High dose rate, biased 3.9 Low dose rate, unbiased Low dose rate, biased 3.4 2.9 2.4 1.9 1.4 0.9 0.4 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 55: ISL7124SRH negative slew rate, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is .4V/µs. Output short circuit current, channel 1, mA -20 -25 -30 -35 -40 -45 High dose rate, unbiased High dose rate, biased -50 Low dose rate, unbiased -55 Low dose rate, biased -60 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 56: ISL7124SRH output short circuit current, channel 1, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is -60mA maximum. 31 Output short circuit current, channel 2, mA -20 -25 -30 -35 -40 -45 High dose rate, unbiased High dose rate, biased -50 Low dose rate, unbiased -55 Low dose rate, biased -60 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 57: ISL7124SRH output short circuit current, channel 2, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is -60mA maximum. Output short circuit current, channel 3, mA -20 -25 -30 -35 -40 -45 High dose rate, unbiased -50 High dose rate, biased Low dose rate, unbiased -55 Low dose rate, biased -60 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 58: ISL7124SRH output short circuit current, channel 3, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is -60mA maximum. 32 Output short circuit current, channel 4, mA -20 -25 -30 -35 -40 -45 High dose rate, unbiased High dose rate, biased -50 Low dose rate, unbiased -55 Low dose rate, biased -60 0 25 50 75 100 125 150 Total dose, krad(Si) Figure 59: ISL7124SRH output short circuit current, channel 4, as a function of total dose irradiation at low and high dose rate for the unbiased and biased cases. The post-irradiation SMD limit is -60mA maximum. 6: Conclusion This document reports results of a total dose test of the ISL7124SRH quad operational amplifier. Parts were tested at low and high dose rate under biased and unbiased conditions as outlined in MIL-STD-883 Test Method 1019.7, to a maximum total dose of 150krad(Si). The part was found to be dose rate sensitive, with unbiased low dose rate irradiation worst case as expected. The input offset voltage was outside the +/-10mV SMD post-irradiation specification at the 100krad(Si) downpoint. The positive input bias current was close to the +/-400nA postirradiation limit at the 125krad(Si) downpoint but recovered somewhat at 150krad(Si). The cause of the bias current degradation is considered to be the gradually degradation of the gain (‘beta’) of the input PNP transistor pair. The negative input bias current was outside the +/-400nA limit after 125krad(Si). The input offset current remained very stable, indicating that the input pair gain remains well-matched in spite of the degradation in absolute value. Open-loop voltage gain was outside the 20V/mV (86dB) limit at the 100krad(Si) downpoint. Common-mode rejection ratio data for Channel 3 was of doubtful quality, as was the positive and negative slew rate data for Channels 2 and 4. We have plotted this anomalous data for information only. The part is considered low dose rate sensitive but remains within the SMD post-irradiation limits to a maximum of 50krad(Si) in this environment. Similarly, we observed some bias sensitivity in the low dose rate results. 33 7: Appendices 7.1: Reported parameters. Figure 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Parameter Input offset voltage Input offset voltage Input offset voltage Input offset voltage Positive input bias current Positive input bias current Positive input bias current Positive input bias current Negative input bias current Negative input bias current Negative input bias current Negative input bias current Input offset current Input offset current Input offset current Input offset current Large signal voltage gain Large signal voltage gain Large signal voltage gain Large signal voltage gain Output low voltage Output low voltage Output low voltage Output low voltage Output high voltage Output high voltage Output high voltage Output high voltage Output voltage swing Output voltage swing Output voltage swing Output voltage swing Quiescent power supply current Positive power supply rejection ratio Positive power supply rejection ratio Positive power supply rejection ratio Limit, low -10 -10 -10 -10 -400 -400 -400 -400 -400 -400 -400 -400 -150 -150 -150 -150 20 20 20 20 Limit, high +10 +10 +10 +10 +400 +400 +400 +400 +400 +400 +400 +400 +150 +150 +150 +150 900 900 900 900 23 23 23 23 24 24 24 24 3 70 70 70 34 Units mV mV mV mV nA nA nA nA nA nA nA nA nA nA nA nA dB dB dB dB mV mV mV mV V V V V V V V V mA dB dB dB Notes Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 Positive power supply rejection ratio Negative power supply rejection ratio Negative power supply rejection ratio Negative power supply rejection ratio Negative power supply rejection ratio Common mode rejection ratio Common mode rejection ratio Common mode rejection ratio Common mode rejection ratio Positive slew rate Positive slew rate Positive slew rate Positive slew rate Negative slew rate Negative slew rate Negative slew rate Negative slew rate Output short circuit current Output short circuit current Output short circuit current Output short circuit current 70 70 70 70 70 70 70 70 70 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 -60 -60 -60 -60 dB dB dB dB dB dB dB dB dB V/µs V/µs V/µs V/µs V/µs V/µs V/µs V/µs mA mA mA mA Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 Note 1: Limits are taken from Standard Microcircuit Drawing (SMD) 5962-02542. 8: Document revision history Revision Date 0 18 August 2010 Pages All Comments Original issue 35