ISL59445/EL4342E1 Evaluation Board User’s Guide ® Application Note April 21, 2005 AN1193.0 Introduction High Frequency Layout Considerations The ISL59445/EL4342E1 evaluation board contains all the circuitry needed to characterize critical performance parameters of the ISL59445 and EL4342 triple 4:1 MUXamplifiers, over a variety of applications. At frequencies of 500MHz and higher, circuit board layout may limit performance. The following layout guidelines are implemented on the evaluation board: The ISL59445 (1GHz) and EL4342 (500MHz) each contain 3 separate 4:1 input multiplexers, each followed by a unity gain buffer controlled by common set of logic inputs (Figure 1, Table 1). Control features include a high speed (20ns) HIZ output control for individual selection of MUX amps that share a common video output line. The ENABLE control can be used to save power by powering the device down. The evaluation board circuit and layout is optimized for either 50Ω or 75Ω terminations, and implements a basic RG-B video 2 input MUX-amp. The board is supplied with 75Ω input signal terminations and a 75Ω back-termination resistor on each of the 3 outputs, making it suitable for driving video cable. The user has the option of replacing the 75Ω resistors with 50Ω resistors for other applications. The control lines contain 50Ω resistors to match the 50Ω output impedance of high speed pulse generators. Control line termination resistors are recommended for rise and fall times under 10ns to minimize unwanted transients. If DC is used for the control logic, the resistors may be removed; or the applied DC voltage can be reduced to 2.5V to reduce the dissipation in the termination resistor. The layout contains component options to include an output series resistor (RS) followed by a parallel resistor (RL) capacitor (CL) network to ground. This option allows the user to select several different output configurations. Examples are shown in Figures 2A, 2B, and 2C. The evaluation board is supplied with the 75Ω back termination resistors shown in Figure 2C. • Signal I/O lines are the same lengths and widths to match propagation delay and trace parasitics. • No series connected vias are used in signal I/O lines, as they can add unwanted inductance. • Signal trace lengths are minimized to reduce transmission line effects and the need for strip-line tuning of the signal traces. • High frequency decoupling caps are placed as close to the device power supply pin as possible - without series vias between the capacitor and the device pin. Power Sequencing Proper power supply sequencing is -V first, then +V. In addition, the +V and -V supply pin voltage rate-of-rise must be limited to ±1V/µs or less. The evaluation board contains parallel-connected low VON Schottky diodes on each supply terminal to minimize the risk of latch up due to incorrect sequencing. In addition, extra 10µF decoupling capacitors are added to each supply to aid in reducing the applied voltage rate-of-rise. Reference Documents • ISL59445 Data Sheet, FN7456 • EL4342 Data Sheet, FN7421 S0 EN1 S1 IN1(A, B, C) DECODE EN2 Amplifier Performance and Output Configurations The EL4342 output amplifiers are designed for maximum gain-bandwidth performance when loaded with ~500Ω (RL) in parallel with ~5pF (CL) to ground, directly at the output pin (Figure 2A). They are ideally suited for driving high impedance high speed selectable-gain buffers when gain compensation is needed. In these applications, output trace capacitance to 5pF actually optimizes AC performance. For trace capacitance below 5pF, an additional capacitor between the output pin to ground may be added to achieve the 5pF optimum. GBW decreases slightly at the lower output load impedances typical of back-terminated cable driving applications. Additional performance data can be found in the data sheet references. 1 IN0(A, B, C) OUT IN2(A, B, C) IN3(A, B, C) EN3 AMPLIFIER BIAS HIZ ENABLE FIGURE 1. EL4342 FUNCTIONAL BLOCK DIAGRAM (1 OF 3 CHANNELS) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1193 TABLE 1. Logic Table VIN S0 S1 HIZ ENABLE OUTA, B, C 0 0 0 0 IN0A, B, C 1 0 0 0 IN1A, B, C 0 1 0 0 IN2A, B, C 1 1 0 0 IN3A, B, C - - 1 0 HIZ - - - 1 Power down ISL59445/EL4342 RS, 0Ω 50Ω or 75Ω TEST EQUIPMENT ISL59445/EL4342 RS VIN *Cb2 ~3pF *Cb1 ~0.5pF CL RL 500Ω 1.5pF 50Ω or 75Ω 475Ω RL 50Ω or 75Ω 50Ω or 75Ω * Cb1 is approximate PCB trace capacitance * Cb1, Cb2 are approximate PCB trace capacitances FIGURE 2B. TEST CIRCUIT FOR 50Ω OR 75Ω TERMINATIONS FIGURE 2A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD ISL59445/EL4342 RS VIN 50Ω or 75Ω ^Cb1 ~.5pF Cb1 ~0.5pF 50Ω or 75Ω TEST EQUIPMENT 50Ω or 75Ω * Cb1 is approximate PCB trace capacitance FIGURE 2C. BACK-TERMINATED TEST CIRCUIT FOR CABLE APPLICATION ISL59445/EL4342E1 Top View 2 AN1193.0 April 21, 2005 Application Note 1193 ISL59445/EL4342E1 Schematic Diagram ISL59445, EL4342 IN1A 1 IN1A R2-75Ω GNDA 32 IN0A 31 2 NIC IN1B NIC 30 3 IN1B R10-75Ω IN1C R11-75Ω 4 NIC IN0B 29 5 IN1C NIC 28 R1-75Ω IN2B 7 IN2A HIZ 26 8 GND EN 25 NIC 24 9 IN2B R3-75Ω IN2C R9-75Ω IN0B R8-75Ω JHIZ IN0C IN0C 27 6 GNDB IN2A IN0A R7-75Ω HIZ R12 - 49.9Ω ENBAR R14 - 49.90Ω JENBAR V+ 23 10 IN2C RSA - 75Ω R4-75Ω IN3A 11 GDNC OUTA 22 12 IN3A V- 21 C11 OUTA R22 RSB - 75Ω R5-75Ω 13 NIC 14 IN3B IN3B OUTB OUTB 20 RSC - 75Ω OUTC 19 C9 S0 R6-75Ω 15 NIC S0 18 R20 S1 IN3C 16 IN3C R19 49.9Ω S1 17 R13-75Ω R18 49.9Ω D1 C2 C1 C7 C3 10µF 0.1µF 10nF 1nF D2 GND. V- C10 OUTC R21 JSO JSO + C8 C4 C5 C6 10µF 0.1µF 10nF 1nF V+ TABLE 1. COMPONENTS PARTS LIST Device # Description Comments C7, C8 CAP, SMD, 0603, 1000pF, 25V, 10%, X7R Power Supply Decoupling C1, C4 CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R Power Supply Decoupling C2, C5 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R Power Supply Decoupling C3, C6 CAP, SMD, 0805, 10µF, 6.3V, 10%, X5R Power Supply Decoupling D1, D2 Diode-Schottky, 2 Pin, 45V, 7.5A MBR0550T (Motorola) Reverse Polarity Protection R1-R11, R13, RSA, RSB, RSC Resistor, SMD, 0603, 75Ω, 1/10W, 1% Signal Input/output Termination R12, R14, R18, R19 Resistor, SMD, 0603, 49.9Ω, 1/16W, 1% Logic Input Termination C9, C10, C11 Capacitor, SMD, 0603 Optional, not populated R20, R21, R22 Resistor, SMD, 0603 Optional, not populated U1 ISL5945IU -1GHz Multiplexing Amplifier, 32P, QFN EL4342IL - 500MHz Multiplexing Amplifier, 32P, QFN Device Under Test Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1193.0 April 21, 2005