M62364FP 8-bit 8ch Multiplying D/A Converter with Buffer Amplifiers REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Description The M62364FP is a CMOS 8-bit 8ch D/A converter having a multiplying function and output buffer amplifiers. It has a serial data input and can easily communicate with a microcontroller by the simple three-wiring method (DI, CLK, LD). The output buffer amplifiers operating in AB-class has both sinking and driving capabilities of 1.0 mA or more and can operate in a whole supply range from VDD to GND. The IC is suitable for a use in automatic adjustment applications in conjunction with a MCU by utilizing the terminal DO for a cascading connection. Features • • • • Three-wiring serial data transmission Doubled precision 8ch D/A converter employing an R-2R with higher-order segment method 8 buffer amplifiers operating in a whole supply voltage range from VDD to GND 4 quadrant multiplication Application Digital to analog conversion for consumer and industrial equipment. Gain setting and automatic adjustment of display-monitor and CTV. Block Diagram VDD 5 DI 8 CLK 7 12-bit shift register D0 D1 D2 D3 D4 D5 D6 D7 17 Do D8 D9 D10 D11 6 LD Address decoder RESET 19 8-bit latch ............. 8-bit latch D/A converter ............. D/A converter 18 VDAref + − + − ............. 1 VIN1 2 VOUT1 REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 1 of 7 ............. 24 VIN8 23 20 VOUT8 GND M62364FP Pin Arrangement M62364FP VIN1 1 24 VIN8 VOUT1 2 23 VOUT8 VOUT2 3 22 VOUT7 VIN2 4 21 VIN7 VDD 5 20 GND LD 6 19 RESET CLK 7 18 VDAref DI 8 17 Do VIN3 9 16 VIN6 VOUT3 10 15 VOUT6 VOUT4 11 14 VOUT5 VIN4 12 13 VIN5 (Top view) Outline: PRSP0024GA-A (24P2Q-A) Pin Description Pin No. 8 17 7 Pin Name DI DO CLK 6 LD 19 2 3 10 11 14 15 22 RESET VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 23 5 20 1 4 9 12 13 16 21 24 18 VOUT8 VDD GND VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VDAref Function Serial data input Serial data output Shift clock input. Input data of DI are taken into the 12-bit shift register on a rising edge of the clock. A low state enables data loading to the 12-bit shift register. During a rising edge of LD, the data will be loaded to the output register. Reset 8-bit latches D/A converter output with 8-bit resolution Power supply Ground D/A converter input D/A converter reference voltage input REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 2 of 7 M62364FP Absolute Maximum Ratings Item Supply voltage Digital input voltage Analog input voltage Analog output voltage D/A reference voltage Operating temperature Storage temperature Symbol VDD VIND VIN VOUT VDAref Topr Tstg Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –20 to +75 –40 to +125 Unit V V V V V °C °C Electrical Characteristics <Ana/Dig Common Part> (VDD = 5 V ± 10%, VDD ≥ VIN, GND, VDAref = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Supply voltage VDD 2.7 5.0 5.5 V Supply current IDD — — 3.5 mA Conditions CLK = 1 MHz, VCC = 3 V, IAO = 0 μA <Digital Part> (VDD = 5 V ± 10%, VDD ≥ VIN, GND, VDAref = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Input leak current Digital input "Low" voltage Digital input "High" voltage DO terminal output "Low" voltage DO terminal output "High" voltage IILK VIL VIH VOL VOH Min Limits Typ Max Unit –10 — 0.8 VDD — VDD – 0.4 — — — — — 10 0.2 VDD — 0.4 — μA V V V V Conditions VIN = 0 to VDD IOL = 2.5 mA IOH = –400 μA <Analog Part> (VDD = 5 V ± 10%, VDD ≥ VIN, GND, VDAref = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Item Symbol Min Limits Typ Max Unit Conditions — — 0.30 mA VIN = 5 V, VDAref = 0 V Proportional to Max. input current condition (VIN – VDAref) and digital data of each channels VIN = 5 V, VDAref = 0 V Proportional to Max. input current condition (VIN – VDAref) and digital data of each channels Input current IIN D/A reference input current IDAref –2.40 — — mA Resolution Differential nonlinearity Nonlinearity RES DNL NL Buffer amplifier output voltage range VAO IAO 8 — — — — — — 1 1 VCC – 0.1 VCC – 0.2 1 bit LSB LSB V Buffer amplifier output current range — –1 –1 0.1 0.2 –1 — — — 5 0.1 — μF Ω Output capacitive load CO Buffer amplifier output impedance RO REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 3 of 7 mA VDAref = 0.050 V (10 mV/LSB) Without load (IAO = ±0) IAO = ±100 μA IAO = ±500 μA Upper saturation voltage = 0.4 V Lower saturation voltage = 0.4 V M62364FP AC Characteristics (VDD = 5 V ± 10%, VDD ≥ VIN, GND, VDAref = 0 V, Ta = –20 to +85°C, unless otherwise noted.) Item Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse duration time Data output delay time D/A output setting time Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD Min Limits Typ Max Unit 200 200 — — 60 100 200 100 100 70 — — — — — — — — — — — — — — 200 200 — — — — — 350 300 ns ns ns ns ns ns ns ns ns ns μs Conditions CL = 100 pF CL ≤ 100 pF, VAO: 0.1 ↔ 2.6 V This time until the output becomes the final value of 1/2 LSB Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tCHD tCHL tLDH tLDC LD tLDD D/A output tDO Do output REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 4 of 7 M62364FP Digital Data Format 12-bit serial data DATA 1 2 3 4 5 6 7 8 9 10 11 (LSB) 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK Data Assignment D0 (LSB) D8 D1 D2 D3 D9 D10 D11 D4 D5 D6 D7 (MSB) : DAC data : DAC select data DAC Data D0 0 D1 0 D2 0 D3 0 D4 0 D5 0 D6 0 D7 0 1 0 1 : 1 0 1 1 : 1 0 0 0 : 1 0 0 0 : 1 0 0 0 : 1 0 0 0 : 1 0 0 0 : 1 0 0 0 : 1 D/A Output VDAref (VIN – VDAref) / 256 × 1 + VDAref (VIN – VDAref) / 256 × 2 + VDAref (VIN – VDAref) / 256 × 3 + VDAref : (VIN – VDAref) / 256 × 255 + VDAref DAC Select Data D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 5 of 7 DAC Selection Don't care VOUT1 selection VOUT2 selection VOUT3 selection VOUT4 selection VOUT5 selection VOUT6 selection VOUT7 selection VOUT8 selection Don't care Don't care Don't care Don't care Don't care Don't care Don't care M62364FP Timing Chart (Model) RESET MSB DI D11 LSB D10 CLK D9 ............ D0 ............ LD Vo Note: Input data is carried out LD signal low besides CLK signal positive edge. CLK, LD is keep generally high level. REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 6 of 7 M62364FP Package Dimensions JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g E 13 *1 HE 24 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. F 1 12 Index mark c A2 A1 D L A *2 *3 e y bp Detail F REJ03D0875-0300 Rev.3.00 Mar 25, 2008 Page 7 of 7 Reference Dimension in Millimeters Symbol D E A2 A A1 bp c HE e y L Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 2.1 0.1 0.2 0 0.3 0.35 0.45 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 0.65 0.8 0.95 0.10 0.4 0.6 0.8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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