Multiformat 216 MHz Video Encoder with Six NSV® 14-Bit DACs ADV7324 High definition (HD) input formats 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with: SMPTE 274M (1080i, 1080p @ 74.25 MHz) SMPTE 296M (720p) SMPTE 240M (1035i) RGB in 3-bit × 10-bit 4:4:4 input format HDTV RGB supported: RGB, RGBHV Other HD formats using async timing mode Enhanced definition (ED) input formats 8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb SMPTE 293M (525p) BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) RGB in 3-bit × 10-bit 4:4:4 input format Standard definition (SD) input formats CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input HD output formats YPrPb HDTV (EIA 770.3) RGB, RGBHV CGMS-A (720p/1080i) ED output formats Macrovision Rev 1.2 (525p/625p) CGMS-A (525p/625p) YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2) RGB, RGBHV SD output formats Composite NTSC M/N Composite PAL M/N/B/D/G/H/I, PAL-60 SMPTE 170M NTSC-compatible composite video ITU-R BT.470 PAL-compatible composite video S-video (Y/C) EuroScart RGB Component YPrPb (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1.L1 CGMS/WSS Closed captioning GENERAL FEATURES Simultaneous SD/HD or PS/SD inputs and outputs Oversampling up to 216 MHz Programmable DAC gain control Sync outputs in all modes On-board voltage reference Six 14-bit NSV (noise shaped video) precision video DACs 2-wire serial I2C® interface, open-drain configuration Dual I/O supply 2.5 V/3.3 V operation Analog and digital supply 2.5 V On-board PLL 64-lead LQFP package Lead (Pb) free product APPLICATIONS EVD (enhanced versatile disk) players High-end SD/PS DVD recorders/players SD/PS/HDTV display devices SD/HDTV set top boxes Professional video systems ADV7324 SD CONTROL BLOCK COLOR CONTROL BRIGHTNESS DNR GAMMA PROGRAMMABLE FILTERS SD TEST PATTERN Y9–Y0 C9–C0 S9–S0 D E M U X PROGRAMMABLE RGB MATRIX HD CONTROL BLOCK 14-BIT DAC 14-BIT DAC O V E R S A M P L I N G 14-BIT DAC 14-BIT DAC 14-BIT DAC HD TEST PATTERN HSYNC VSYNC BLANK CLKIN_A CLKIN_B TIMING GENERATOR 14-BIT DAC COLOR CONTROL ADAPTIVE FILTER CTRL SHARPNESS FILTER I2C INTERFACE PLL 05220-001 FEATURES Figure 1. Simplified Functional Block Diagram GENERAL DESCRIPTION The ADV®7324 is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed NSV video DACs with TTL-compatible inputs. It has separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept data in high definition (HD) and/or standard definition (SD) video format. For all standards, external horizontal, vertical, and blanking signals, or EAV/SAV timing codes, control the insertion of appropriate synchronization signals into the digital data stream and, therefore, the output signal. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADV7324 TABLE OF CONTENTS Specifications..................................................................................... 6 Gamma Correction .................................................................... 53 Dynamic Specifications ............................................................... 7 HD Sharpness Filter and Adaptive Filter Controls................ 55 Timing Specifications .................................................................. 8 HD Sharpness Filter and Adaptive Filter Application Examples ................................................................ 56 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 16 Thermal Characteristics ............................................................ 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 19 MPU Port Description................................................................... 23 Register Access................................................................................ 25 Register Programming............................................................... 25 Subaddress Registers (SR7 to SR0)........................................... 25 Input Configuration ....................................................................... 38 SD Only........................................................................................ 38 PS Only or HDTV Only ............................................................ 38 Simultaneous SD/PS or SD/HDTV.......................................... 38 PS at 27 MHz (Dual Edge) or 54 MHz .................................... 39 Features ............................................................................................ 41 Output Configuration................................................................ 41 HD Async Timing Mode ........................................................... 42 HD Timing Reset........................................................................ 43 SD Real-Time Control, Subcarrier Reset, and Timing Reset ............................................................................... 43 SD Digital Noise Reduction...................................................... 57 Coring Gain Border ................................................................... 58 Coring Gain Data ....................................................................... 58 DNR Threshold .......................................................................... 58 Border Area................................................................................. 58 Block Size Control...................................................................... 58 DNR Input Select Control......................................................... 58 DNR Mode Control ................................................................... 59 Block Offset Control .................................................................. 59 SD Active Video Edge................................................................ 59 SAV/EAV Step-Edge Control ................................................... 59 Hsync/Vsync Output Control .................................................. 61 Board Design and Layout.............................................................. 62 DAC Termination and Layout Considerations ...................... 62 Video Output Buffer and Optional Output Filter.................. 62 PCB Board Layout...................................................................... 63 Appendix 1—Copy Generation Management System .............. 65 PS CGMS..................................................................................... 65 HD CGMS................................................................................... 65 SD CGMS .................................................................................... 65 Reset Sequence............................................................................ 45 CGMS Functionality.................................................................. 65 SD VCR FF/RW Sync................................................................. 45 Appendix 2—SD Wide-Screen Signaling.................................... 68 Vertical Blanking Interval ......................................................... 46 Appendix 3—SD Closed Captioning ........................................... 70 Subcarrier Frequency Registers ................................................ 46 Appendix 4—Test Patterns............................................................ 71 Square Pixel Timing Mode........................................................ 47 Appendix 5—SD Timing Modes .................................................. 74 Filters............................................................................................ 48 Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) ........................... 74 Color Controls and RGB Matrix .............................................. 49 Programmable DAC Gain Control .......................................... 53 Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = X X X X X 0 0 1) ........................... 75 Rev. 0 | Page 2 of 92 ADV7324 Mode 1—Slave Option (Timing Register 0 TR0 = X X X X X 0 1 0) ............................77 Mode 1—Master Option (Timing Register 0 TR0 = X X X X X 0 1 1) ............................78 Appendix 6—HD Timing ..............................................................82 Appendix 7—Video Output Levels...............................................83 HD YPrPb Output Levels ..........................................................83 Mode 2— Slave Option (Timing Register 0 TR0 = X X X X X 1 0 0) ............................79 RGB Output Levels .....................................................................84 Mode 2—Master Option (Timing Register 0 TR0 = X X X X X 1 0 1) ............................80 Appendix 8—Video Standards ......................................................87 Mode 3—Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) .......................................................................................................81 YPrPb Levels—SMPTE/EBU N10............................................85 Outline Dimensions........................................................................89 Ordering Guide ...........................................................................89 REVISION HISTORY 11/04—Revision 0: Initial Version Rev. 0 | Page 3 of 92 ADV7324 Table 1. Standards Directly Supported1 DETAILED FEATURES HD programmable features (720p/1080i/1035i) 2× oversampling (148.5 MHz) Internal test pattern generator Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i) ED programmable features (525p/625p) 8× oversampling (216 MHz output) Internal test pattern generator Color hatch, black bar, flat frame Individual Y and PrPb output delay Gamma correction Programmable adaptive filter control Fully programmable YCrCb to RGB matrix Undershoot limiter Macrovision Rev 1.2 (525p/625p) CGMS-A (525p/625p) SD programmable features 16× oversampling (216 MHz) Internal test pattern generator Color bars, black bar Controlled edge rates for start and end of active video Individual Y and PrPb output delay Undershoot limiter Gamma correction Digital noise reduction (DNR) Multiple chroma and luma filters Luma-SSAF™ filter with programmable gain/attenuation PrPb SSAF™ Separate pedestal control on component and composite/S-video output VCR FF/RW sync mode Macrovision Rev 7.1.L1 CGMS/WSS Closed captioning Resolution 720 × 480 Interlace/ PS I Frame Rate (Hz) 29.97 Clock Input (MHz) 27 720 × 576 I 25 27 720 × 480 I 29.97 24.54 720 × 576 I 25 29.5 720 × 483 P 59.94 27 720 × 483 720 × 483 P P 59.94 59.94 27 27 720 × 576 P 50 27 720 × 483 P 59.94 27 720 × 576 P 50 27 1920 × 1035 I 1280 × 720 P 30 29.97 60, 50, 30, 25, 24 23.97, 59.94, 29.97 30, 25 29.97 30, 25, 24 23.98, 29.97 74.25 74.1758 74.25 1920 × 1080 I 1920 × 1080 P 1 SMPTE 296M 74.1758 74.25 74.1758 74.25 74.1758 Other standards are supported in async timing mode. Rev. 0 | Page 4 of 92 Standard ITU-R BT.656 ITU-R BT.656 NTSC Square Pixel PAL Square Pixel SMPTE 293M BTA T-1004 ITU-R BT.1358 ITU-R BT.1358 ITU-R BT.1362 ITU-R BT.1362 SMPTE 240M SMPTE 274M SMPTE 274M ADV7324 HD PIXEL INPUT CLKIN_B Y DEINTER- CR LEAVE CB TEST PATTERN SHARPNESS AND ADAPTIVE FILTER CONTROL Y COLOR CR COLOR CB COLOR 4:2:2 TO 4:4:4 PS 8× HDTV 2× DAC DAC TIMING GENERATOR S_HSYNC S_VSYNC S_BLANK CLKIN_A SD PIXEL INPUT CLOCK CONTROL AND PLL DAC U V TIMING GENERATOR UV SSAF RGB MATRIX DAC SD 16× CB DEINTER- CR LEAVE Y TEST PATTERN DNR GAMMA COLOR CONTROL SYNC INSERTION LUMA AND CHROMA FILTERS 2× OVERSAMPLING FSC MODULATION CGMS WSS DAC DAC Figure 2. Detailed Functional Block Diagram TERMINOLOGY HDTV: high definition television video, conforming to SMPTE 274M, or SMPTE 296M and SMPTE 240M. SD: standard definition video, conforming to ITU-R BT.601/ITU-R BT.656. YCrCb SD, PS, or HD component: digital video. HD: high definition video, i.e., 720p/1080i/1035i. YPrPb SD, PS, or HD component: analog video. EDTV: enhanced definition television (525p/625p). PS: progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTA T-1004 EDTV2, or ITU-R BT.13621362. Rev. 0 | Page 5 of 92 05220-002 P_HSYNC P_VSYNC P_BLANK ADV7324 SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 150 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE1 Resolution Integral Nonlinearity Differential Nonlinearity,2 +ve Differential Nonlinearity,2 −ve DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range DAC-to-DAC Matching Output Compliance Range, VOC Output Capacitance, COUT VOLTAGE REFERENCE Internal Reference Range, VREF External Reference Range, VREF VREF Current4 POWER REQUIREMENTS Normal Power Mode IDD5 IDD_IO IAA7, 8 Sleep Mode IDD IAA IDD_IO POWER SUPPLY REJECTION RATIO Min Typ Max 14 2.0 1.0 3.0 0.4 [0.4]3 ±1.0 2 2 0.8 10 2 0 1.15 1.15 4.33 4.33 1.0 1.0 7 4.6 4.6 1.235 1.235 ±10 1.3 1.3 137 78 73 140 1.0 37 Test Conditions Bits LSB LSB LSB 2.4 [2.0]3 4.1 4.1 Unit 1.4 1906 45 80 7 250 0.01 1 V V µA pF V V µA pF ISINK = 3.2 mA ISOURCE = 400 µA VIN = 0.4 V, 2.4 V VIN = 2.4 V mA mA % V pF V V µA mA mA mA mA mA mA SD only (16×) PS only (8×) HDTV only (2×) SD (16×, 10-bit) + PS (8×, 20-bit) µA µA µA %/% Oversampling disabled. Static DAC performance improves with increased oversampling ratios. DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for −ve DNL, the actual step value lies below the ideal step value. 3 For values in brackets, VDD_IO = 2.375 V to 2.75 V. 4 External current required to overdrive internal VREF. 5 IDD, the circuit current, is the continuous current required to drive the digital core. 6 Guaranteed maximum by characterization. 7 All DACs on. 8 IAA is the total current required to supply all DACs, including the VREF circuitry and the PLL circuitry. 2 Rev. 0 | Page 6 of 92 ADV7324 DYNAMIC SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 150 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 3. Parameter PS MODE Luma Bandwidth Chroma Bandwidth SNR HDTV MODE Luma Bandwidth Chroma Bandwidth SD MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain Differential Phase SNR Min Typ Max Unit Test Conditions 12.5 5.8 65.6 72 MHz MHz dB dB Luma ramp unweighted Flat field full bandwidth 30 13.75 MHz MHz 0.44 0.20 0.84 −0.2 0 97.5 0 0.1 84 75.3 0.09 0.12 63.5 77.7 Degrees % ±% ±Degrees ±% ±% ns ±% dB dB % Degrees dB dB Rev. 0 | Page 7 of 92 Referenced to 40 IRE NTSC NTSC Luma ramp Flat field full bandwidth ADV7324 TIMING SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 150 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 4. Parameter MPU PORT1 SCLOCK Frequency SCLOCK High Pulse Width, t1 SCLOCK Low Pulse Width, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 RESET Low Time ANALOG OUTPUTS Analog Output Delay2 Output Skew CLOCK CONTROL AND PIXEL PORT3 fCLK fCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t111 Data Hold Time, t121 SD Output Access Time, t13 SD Output Hold Time, t14 HD Output Access Time, t13 HD Output Hold Time, t14 PIPELINE DELAY4 Min Typ 0 0.6 1.3 0.6 Max Unit 400 kHz µs µs µs 0.6 100 300 300 0.6 100 7 1 29.5 40 40 2.0 2.0 15 5.0 14 63 76 35 41 36 First clock generated after this period relevant for repeated start condition µs ns ns ns µs ns ns ns 81 5.0 Test Conditions MHz MHz % of one clock cycle % of one clock cycle ns ns ns ns ns ns Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles 1 SD PAL square pixel mode PS/HD async mode SD (2×, 16×) SD component mode (16×) PS (1×) PS (8×) HD (2×, 1×) Guaranteed by characterization. Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: C[9:0]; Y[9:0], S[9:0]; Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK. 4 SD, PS = 27 MHz, HD = 74.25 MHz. 2 Rev. 0 | Page 8 of 92 ADV7324 TIMING DIAGRAMS CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 Y2 Y3 Y4 Y5 C9–C0 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 t11 t13 CONTROL OUTPUTS t14 05220-003 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME Figure 3. HD Only 4:2:2 Input Mode (Input Mode 010); PS Only 4:2:2 Input Mode (Input Mode 001) CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 Y2 Y3 Y4 Y5 C9–C0 Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cr2 Cr3 Cr4 Cr5 t11 S9–S0 Cr0 Cr1 CONTROL OUTPUTS t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME 05220-004 t13 Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001) Rev. 0 | Page 9 of 92 ADV7324 CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 G0 G1 G2 G3 G4 G5 C9–C0 B0 B1 B2 B3 B4 B5 R2 R3 R4 R5 t11 R0 S9–S0 R1 CONTROL OUTPUTS t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME 05220-005 t13 Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010) CLKIN_B* t9 CONTROL INPUTS t10 P_HSYNC, P_VSYNC, P_BLANK Y0 Cb0 Y9–Y0 Cr0 Crxxx Y1 t12 Yxxx t12 t11 t11 t13 CONTROL OUTPUTS 05220-006 t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME *CLKIN_B MUST BE USED IN THIS PS MODE Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz HSYNC/VSYNC Input Mode (Input Mode 100) CLKIN_A t9 CONTROL INPUTS t10 P_VSYNC, P_HSYNC, P_BLANK Cb0 Y9–Y0 t11 t12 Y0 Cr0 Y1 Crxxx Yxxx t13 t14 CONTROL OUTPUTS 05220-007 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz HSYNC /VSYNC Input Mode (Input Mode 111) Rev. 0 | Page 10 of 92 ADV7324 CLKIN_B* t9 3FF Y9–Y0 t10 00 00 XY t12 Cb0 Y0 Cr0 Y1 t12 t11 t11 t13 CONTROL OUTPUTS 05220-008 t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME *CLKIN_B USED IN THIS PS ONLY MODE Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100) CLKIN_A t9 Y9–Y0 t10 00 3FF t11 00 Y0 Cb0 XY Cr0 Y1 t13 t12 t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01, BIT 1 05220-009 CONTROL OUTPUTS Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111) CLKIN_B t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 C9–C0 Cb0 Cr0 Y2 Y3 Y4 Y5 Cb2 Cr2 Cb4 Cr4 HD INPUT t11 CLKIN_A S_HSYNC, S_VSYNC, S_BLANK S9–S0 t9 t12 t10 SD INPUT Cb0 Y0 Cr0 Y1 Cb1 Y2 t11 Figure 10. HD 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled) Rev. 0 | Page 11 of 92 05220-010 CONTROL INPUTS ADV7324 CLKIN_B t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 Y2 Y3 Y4 Y5 C9–C0 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 PS INPUT t11 CLKIN_A t9 S_HSYNC, S_VSYNC, S_BLANK t12 t10 SD INPUT S9–S0 Cr0 Y0 Cb0 Y1 Cb1 Y2 05220-011 CONTROL INPUTS t11 Figure 11. PS 4:2:2 and SD 10-Bit Simultaneous Input Mode (Input Mode 011) CLKIN_B t9 CONTROL INPUTS t10 P_HSYNC, P_VSYNC, P_BLANK PS INPUT Y9–Y0 Cb0 Cr0 Y0 Crxxx Y1 t12 Yxxx t12 t11 t11 CLKIN_A S_HSYNC, S_VSYNC, S_BLANK t9 t12 t10 SD INPUT S9–S0 Cb0 Y0 Cr0 Y1 Cb1 Y2 t11 Figure 12. PS 10-Bit and SD 10-Bit Simultaneous Input Mode (Input Mode 100) Rev. 0 | Page 12 of 92 05220-012 CONTROL INPUTS ADV7324 CLKIN_A t9 CONTROL INPUTS t12 t10 S_HSYNC, S_VSYNC, S_BLANK S9–S0/Y9–Y0* IN SLAVE MODE Cr0 Cb0 Cb2 Cr2 t11 Cr4 Cb4 t13 CONTROL OUTPUTS IN MASTER/SLAVE MODE 05220-013 t14 *SELECTED BY ADDRESS 0x01, BIT 7 Figure 13. 10-/8-Bit SD Only Pixel Input Mode (Input Mode 000) CLKIN_A CONTROL INPUTS t12 t10 S_HSYNC, S_VSYNC, S_BLANK S9–S0/Y9–Y0* C9–C0 IN SLAVE MODE Y0 Cb0 t11 Y1 Y2 Y3 Cr0 Cb2 Cr2 t13 CONTROL OUTPUTS IN MASTER/SLAVE MODE t14 *SELECTED BY ADDRESS 0x01, BIT 7 Figure 14. 20-/16-Bit SD Only Pixel Input Mode (Input Mode 000) Rev. 0 | Page 13 of 92 05220-014 t9 ADV7324 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y0 Y1 Y2 Y3 C9–C0 Cb0 Cr0 Cr1 Cb1 05220-015 Y9–Y0 b a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATIONS SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRILEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 15. HD 4:2:2 Input Timing Diagram P_HSYNC P_VSYNC a P_BLANK Y9–Y0 Cb Y Cr Y b 05220-016 a = 32 CLOCK CYCLES FOR 525p a = 24 CLOCK CYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLOCK CYCLES FOR 525p b(MIN) = 264 CLOCK CYCLES FOR 625p Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram Rev. 0 | Page 14 of 92 ADV7324 S_HSYNC S_VSYNC PAL = 24 CLOCK CYCLES NTSC = 32 CLOCK CYCLES S_BLANK Cb Y Cr PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES *SELECTED BY ADDRESS 0x01, BIT 7 Figure 17. SD Timing Input for Timing Mode 1 t3 t5 t3 SDA SCLK t2 t4 t7 Figure 18. MPU Port Timing Diagram Rev. 0 | Page 15 of 92 t8 05220-018 t1 t6 Y 05220-017 S9–S0/Y9–Y0* ADV7324 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter1 VAA to AGND VDD to DGND VDD_IO to GND_IO Digital Input Voltage to DGND VAA to VDD AGND to DGND DGND to GND_IO AGND to GND_IO Ambient Operating Temperature (TA) Storage Temperature (TS) Infrared Reflow Soldering (20 s) Value −0.3 V to +3.0 V −0.3 V to +3.0 V −0.3 V to +4.6 V −0.3 V to VDD_IO +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V 0°C to 70°C –65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS θJC = 11°C/W θJA = 47°C/W 1 Analog output short circuit to any power supply or common can be of an indefinite duration. The ADV7324 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering up to 255°C (±5°C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 16 of 92 ADV7324 64 63 62 61 60 59 58 S_VSYNC S_HSYNC S0 S1 S2 S3 S4 VDD DGND S5 S6 S7 S8 S9 CLKIN_B GND_IO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 VDD_IO 1 Y0 2 48 S_BLANK Y1 3 46 VREF Y2 4 45 COMP1 Y3 5 44 DAC A Y4 6 Y5 7 Y6 8 Y7 9 PIN 1 47 RSET1 43 DAC B ADV7324 42 DAC C TOP VIEW (Not to Scale) 41 VAA 40 AGND VDD 10 39 DAC D DGND 11 38 DAC E Y8 12 37 DAC F Y9 13 36 COMP2 C0 14 35 RSET2 C1 15 34 EXT_LF C2 16 33 RESET 05220-019 CLKIN_A RTC_SCR_TR C9 C8 C7 C6 C5 P_BLANK P_VSYNC P_HSYNC SCLK SDA ALSB I2C C4 C3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 19. Pin Configuration Table 6. Pin Function Descriptions Pin No. 11, 57 40 32 63 Mnemonic DGND AGND CLKIN_A CLKIN_B Input/Output G G I I 45, 36 44 43 42 39 COMP1, 2 DAC A DAC B DAC C DAC D O O O O O 38 DAC E O 37 DAC F O 23 24 25 48 49 50 13,12, 9 to 2 30 to 26, 18 to 14 62 to 58, 55 to 51 P_HSYNC P_VSYNC P_BLANK S_BLANK S_VSYNC S_HSYNC Y9 to Y0 I I I I/O I/O I/O I C9 to C0 I S9 to S0 I Description Digital Ground. Analog Ground. Pixel Clock Input for HD Only (74.25 MHz), PS Only (27 MHz), and SD Only (27 MHz). Pixel Clock Input. Requires a 27 MHz reference clock for PS mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes. Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA. CVBS/Green/Y/Y Analog Output. Chroma/Blue/U/Pb Analog Output. Luma/Red/V/Pr Analog Output. In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green [HD] Analog Output. In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output. In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pb/Blue [HD] Analog Output. Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for SD Only. Video Vertical Sync Control Signal for SD Only. Video Horizontal Sync Control Signal for SD Only. SD or PS/HDTV Input Port for Y Data. Input port for interleaved PS data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2. PS/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2. SD or PS/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2. Rev. 0 | Page 17 of 92 ADV7324 Pin No. 33 Mnemonic RESET Input/Output I 47, 35 RSET1, RSET2 I 22 21 20 SCLK SDA ALSB I I/O I 1 10, 56 41 46 34 31 19 64 VDD_IO VDD VAA VREF EXT_LF RTC_SCR_TR I2C GND_IO P P P I/O I I I Description This input resets the on-chip timing generator and sets the ADV7324 to its default register setting. RESET is an active low signal. A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. I2C Port Serial Interface Clock Input. I2C Port Serial Data Input/Output. TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low, the I2C filter is activated, which reduces noise on the I2C interface. Power Supply for Digital Inputs and Outputs. Digital Power Supply. Analog Power Supply. Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). External Loop Filter for the Internal PLL. Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input. This input pin must be tied high (VDD_IO) for the ADV7324 to interface over the I2C port. Digital Input/Output Ground. Rev. 0 | Page 18 of 92 ADV7324 TYPICAL PERFORMANCE CHARACTERISTICS PS Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 Y PASS BAND IN PS OVERSAMPLING MODE 1.0 0 0.5 –10 0 –0.5 –30 GAIN (dB) –40 –1.5 –50 –2.0 05220-020 –60 –70 –80 –1.0 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 05220-023 GAIN (dB) –20 –2.5 –3.0 200 Figure 20. PS—UV 8× Oversampling Filter (Linear) 0 –10 –20 –20 –30 –30 –40 –50 –60 –60 –70 60 80 100 120 140 FREQUENCY (MHz) 160 180 –70 –80 200 0 Figure 21. PS—UV 8× Oversampling Filter (SSAF) –10 –20 –20 –30 –30 –40 –50 –60 –60 –70 60 80 100 120 140 FREQUENCY (MHz) 160 180 120 140 –40 –50 40 60 80 100 FREQUENCY (MHz) 05220-025 GAIN (dB) –10 20 40 Y RESPONSE IN HDTV OVERSAMPLING MODE 0 05220-022 GAIN (dB) Y RESPONSE IN PS OVERSAMPLING MODE 0 20 Figure 24. HDTV—UV 2× Oversampling Filter 0 –80 12 –40 –50 40 10 05220-024 GAIN (dB) –10 05220-021 GAIN (dB) 0 20 6 8 FREQUENCY (MHz) Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE PS Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 4 Figure 23. PS—Y 8× Oversampling Filter (Pass Band) 0 –80 2 –70 –80 200 Figure 22. PS—Y 8× Oversampling Filter 0 20 40 60 80 100 FREQUENCY (MHz) 120 Figure 25. HDTV—Y 2× Oversampling Filter Rev. 0 | Page 19 of 92 140 0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 05220-029 MAGNITUDE (dB) 0 05220-026 MAGNITUDE (dB) ADV7324 –70 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 2 Figure 26. Luma NTSC Low-Pass Filter 4 6 8 FREQUENCY (MHz) 10 12 Figure 29. Luma PAL Notch Filter 0 –10 –10 –20 –20 GAIN (dB) –30 –40 –30 –40 –50 –50 –60 05220-027 –60 –70 –70 –80 0 2 4 6 8 FREQUENCY (MHz) 10 05220-030 MAGNITUDE (dB) Y RESPONSE IN SD OVERSAMPLING MODE 0 12 0 0 –10 –10 –20 –20 –30 –40 160 180 200 –40 –50 –60 –60 –70 4 6 8 FREQUENCY (MHz) 80 100 120 140 FREQUENCY (MHz) –30 –50 2 60 10 05220-031 MAGNITUDE (dB) 0 0 40 Figure 30. Y—16× Oversampling Filter 05220-028 MAGNITUDE (dB) Figure 27. Luma PAL Low-Pass Filter 20 –70 0 12 2 4 6 8 FREQUENCY (MHz) Figure 31. Luma SSAF Filter up to 12 MHz Figure 28. Luma NTSC Notch Filter Rev. 0 | Page 20 of 92 10 12 ADV7324 4 0 2 –10 MAGNITUDE (dB) –2 –4 –6 –20 –30 –40 –50 –8 –60 05220-032 –10 –70 –12 0 1 2 3 4 FREQUENCY (MHz) 5 6 05220-035 MAGNITUDE (dB) 0 0 7 Figure 32. Luma SSAF Filter—Programmable Responses 2 4 6 8 FREQUENCY (MHz) 10 12 10 12 10 12 Figure 35. Luma CIF Low-Pass Filter 5 4 –10 3 –20 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 1 –30 –40 –50 –1 0 1 2 3 4 FREQUENCY (MHz) 5 6 05220-036 –60 05220-033 0 –70 0 7 Figure 33. Luma SSAF Filter—Programmable Gain 2 4 6 8 FREQUENCY (MHz) Figure 36. Luma QCIF Low-Pass Filter 1 0 –10 MAGNITUDE (dB) –1 –2 –3 –20 –30 –40 –50 –60 –5 05220-037 –4 05220-034 MAGNITUDE (dB) 0 –70 0 1 2 3 4 FREQUENCY (MHz) 5 6 7 0 Figure 34. Luma SSAF Filter—Programmable Attenuation 2 4 6 8 FREQUENCY (MHz) Figure 37. Chroma 3.0 MHz Low-Pass Filter Rev. 0 | Page 21 of 92 0 0 –10 –10 –20 –20 MAGNITUDE (dB) –30 –40 –50 –30 –40 –50 05220-038 –60 –70 0 2 4 6 8 FREQUENCY (MHz) 10 –60 05220-041 MAGNITUDE (dB) ADV7324 –70 12 0 0 0 –10 –10 –20 –20 –30 –40 –50 6 8 FREQUENCY (MHz) 10 12 –30 –40 –50 05220-039 –70 0 2 4 6 8 FREQUENCY (MHz) 10 –60 05220-042 –60 –70 12 0 Figure 39. Chroma 1.3 MHz Low-Pass Filter 2 4 6 8 FREQUENCY (MHz) 10 12 10 12 Figure 42. Chroma CIF Low-Pass Filter 0 –10 –10 –20 –20 MAGNITUDE (dB) 0 –30 –40 –50 –30 –40 –50 –60 –70 0 2 4 6 8 FREQUENCY (MHz) 10 05220-043 –60 05220-040 MAGNITUDE (dB) 4 Figure 41. Chroma 0.65 MHz Low-Pass Filter MAGNITUDE (dB) MAGNITUDE (dB) Figure 38. Chroma 2.0 MHz Low-Pass Filter 2 –70 12 0 Figure 40. Chroma 1.0 MHz Low-Pass Filter 2 4 6 8 FREQUENCY (MHz) Figure 43. Chroma QCIF Low-Pass Filter Rev. 0 | Page 22 of 92 ADV7324 MPU PORT DESCRIPTION The ADV7324 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7324. Each slave device is recognized by a unique address. The ADV7324 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 44. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is enabled by setting the ALSB pin of the ADV7324 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater input bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to 0, there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems. 1 1 0 1 0 1 A1 X ADDRESS CONTROL SET UP BY ALSB PIN 05220-044 WRITE READ Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause the device to immediately jump to the idle condition. During a given SCL high period, the user should only issue a start condition, a stop condition, or a stop condition followed by a start condition. If an invalid subaddress is issued by the user, the ADV7324 does not issue an acknowledge and returns to the idle condition. If the user utilizes the auto-increment method of addressing the encoder and exceeds the highest subaddress, the following actions are taken: • In read mode, the highest subaddress register contents are output until the master device issues a no acknowledge. This indicates the end of a read. A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse. READ/WRITE CONTROL 0 1 The ADV7324 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit address plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence, starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all of the registers. Figure 44. ADV7324 Slave Address = 0xD4 To control the various devices on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines, waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. • In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7324, and the part returns to the idle condition. Before writing to the subcarrier frequency registers, it is required to reset ADV7324 at least once after power-up. The four subcarrier frequency registers must be updated, starting with Subcarrier Frequency Register 0 and ending with Subcarrier Frequency Register 3. The subcarrier frequency will only update after the last subcarrier frequency register byte has been received by the ADV7324. Figure 45 illustrates an example of data transfer for a write sequence and the start and stop conditions. Figure 46 shows bus write and read sequences. Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. Rev. 0 | Page 23 of 92 ADV7324 SCLOCK S 9 1–7 8 START ADRR R/W ACK 9 1–7 8 SUBADDRESS ACK 1–7 DATA 8 9 ACK P STOP 05220-045 SDATA Figure 45. Bus Data Transfer S SLAVE ADDR A(S) SUBADDR A(S) DATA S SLAVE ADDR A(S) S = START BIT P = STOP BIT A(S) P LSB = 1 LSB = 0 READ SEQUENCE DATA A(S) SUBADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER Figure 46. Read and Write Sequences Rev. 0 | Page 24 of 92 DATA A(M) P 05220-046 WRITE SEQUENCE ADV7324 REGISTER ACCESS REGISTER PROGRAMMING The MPU can write to or read from all registers of the ADV7324 except the subaddress registers, which are write only registers. The subaddress register selected determines which register the next read or write operation will access. All communication with the part through the bus starts with an access to the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until a stop command is performed on the bus. The following tables describe the functionality of each register. All registers can be read from and written to, unless otherwise stated. SUBADDRESS REGISTERS (SR7 TO SR0) Each subaddress register is an 8-bit, write only register. After the encoder’s bus is accessed and a read or write operation is selected, the subaddress is set up. The subaddress register determines to or from which register the operation takes place. Table 7. Registers 0x00 to 0x01 SR7– SR0 0x00 Register Power Mode Register Bit Description Sleep Mode. With this control enabled, the current consumption is reduced to µA level. All DACs and the internal PLL cct are disabled. I2C registers can be read from and written to in sleep mode. PLL and Oversampling Control. This control allows the internal PLL cct to be powered down and the oversampling to be switched off. DAC F: Power On/Off. Bit 7 Bit 6 Bit 5 Bit 4 0 1 0 1 0 1 Reserved. 0 Clock Edge. 0 1 Reserved. Clock Align. Register Setting Sleep mode off. Sleep mode on. Reset Value (Shaded) 0xFC PLL on. PLL off. 0 1 DAC B: Power On/Off. DAC F off. DAC F on. DAC E off. DAC E on. DAC D off. DAC D on. DAC C off. DAC C on. DAC B off. DAC B on. DAC A off. DAC A on. Reserved. Cb clocked upon rising edge. Y clocked upon rising edge. Only for PS interleaved input at 27 MHz. Must be set if the phase delay between the two input clocks is <9.25 ns or >27.75 ns. SD input only. PS input only. HDTV input only. SD and PS (20-bit). SD and PS (10-bit). SD and HDTV (SD oversampled). SD and HDTV (HDTV oversampled). PS only (at 54 MHz). Allows data to be applied to data ports in various configurations (SD feature only). Only if two input clocks are used. 0 0 1 Input Mode. Y/C/S Bus Swap. Bit 0 0 1 0 1 DAC C: Power On/Off. Mode Select Register Bit 1 0 1 DAC D: Power On/Off. 0x01 Bit 2 0 1 DAC E: Power On/Off. DAC A: Power On/Off. Bit 3 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 Rev. 0 | Page 25 of 92 0x38 See Table 21. ADV7324 Table 8. Registers 0x02 to 0x0F SR7– SR0 0x02 Register Mode Register 0 Bit Description Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 x x x x x x 0 x x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 x x x x x 0 Register Setting Zero must be written to these bits. Disabled. Enabled. Disable manual RGB matrix adjust. Enable manual RGB matrix adjust. No sync. Sync on all RGB outputs. RGB component outputs. YPrPb component outputs. No sync output. Output SD syncs on S_HSYNC, S_VSYNC, S_BLANK pins. No sync output. Output HD, ED, syncs on S_HSYNC, S_VSYNC. LSB for GY. LSB for RV. LSB for BU. LSB for GV. LSB for GU. Bit 9 to Bit 2 for GY. Bit 9 to Bit 2 for GU. Bit 9 to Bit 2 for GV. Bit 9 to Bit 2 for BU. Bit 9 to Bit 2 for RV. 0% 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 … 1 0 0 +0.018% +0.036% … +7.382% +7.5% −7.5% 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 … 1 0 −7.382% −7.364% … −0.018% 0% 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 … 1 0 0 +0.018% +0.036% … +7.382% +7.5% −7.5% 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 0 0 1 0 0 1 1 0 1 0 … 1 1 0 −7.382% −7.364% … −0.018% Test Pattern Black Bar Bit 2 Bit 1 0 Bit 0 0 0 1 Manual RGB Matrix Adjust 0 1 Sync on RGB1 0 1 RGB/YPrPb Output 0 1 SD Sync HD Sync 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A RGB Matrix 2 RGB Matrix 3 RGB Matrix 4 RGB Matrix 5 RGB Matrix 6 DAC A, B, C Output Level2 Positive Gain to DAC Output Voltage DAC D, E, F Output Level Positive Gain to DAC Output Voltage Negative Gain to DAC Output Voltage 0x0C3 0x0D3 0x0E 0x0F 0 1 RGB Matrix 0 RGB Matrix 1 Negative Gain to DAC Output Voltage 0x0B 0 1 x x x x x x x x Reserved Reserved 1 For more detail, refer to Appendix 7. For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section. 3 The register setting value must be written after power-up/reset. 2 Rev. 0 | Page 26 of 92 Reset Value 0x20 0x11, Bit 2 must also be enabled. 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C 0x00 0x00 0x00 0x00 0x00 0x00 ADV7324 Table 9. Registers 0x10 to 0x11 SR7– SR0 0x10 Register HD Mode Register 1 Bit Description HD Output Standard Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Input Sync Format HD/ED Input Mode Bit 2 Bit 1 0 Bit 0 0 Register Setting EIA770.2 output 0 1 1 0 1 1 EIA770.1 output Output levels for full input range Reserved 0 HSYNC, VSYNC, BLANK 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 EAV/SAV codes SMPTE 293M, ITUBT. 1358 Async mode BTA-1004, ITUBT. 1362 ITU-BT. 1358 0 0 1 0 0 ITU-BT. 1362 0 0 1 0 1 SMPTE 296M-1, -2 0 0 1 1 0 SMPTE 296M-3 0 0 1 1 1 SMPTE 296M-4, -5 0 1 0 0 0 SMPTE 296M-6 0 1 0 0 1 SMPTE 296M-7, -8 0 1 0 1 0 SMPTE 240M 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 Reserved Reserved SMPTE 274M-4, -5 0 1 1 1 0 SMPTE 274M-6 0 1 1 1 1 SMPTE 274M-7, -8 1 0 0 0 0 SMPTE 274M-9 1 0 0 0 1 SMPTE 274M-10, -11 10010–11111 0x11 HD Mode Register 2 0 HD Pixel Data Valid 1 0 0 HD Test Pattern Enable 1 0 HD Test Pattern Hatch/Field 1 HD VBI Open 0 1 HD Undershoot Limiter HD Sharpness Filter 0 0 0 1 1 1 0 1 Rev. 0 | Page 27 of 92 525p @ 59.94 Hz 625p @ 50 Hz 625p @ 50 Hz 720p @ 60/59.94 Hz 720p @ 50 Hz 720p @ 30/29.97 Hz 720p @ 25 Hz 720p @ 24/23.98 Hz 1035i @ 60/59.94 Hz 1080i @ 30/29.97 Hz 1080i @ 25 Hz 1080p @ 30/29.97 Hz 1080p @ 25 Hz 1080p @ 24/23.98 Hz 0x00 Pixel data valid on Reserved HD test pattern off HD test pattern on Hatch Field/frame Disabled Enabled Disabled Reset Value 0x00 525p @ 59.94 Hz Reserved Pixel data valid off −11 IRE −6 IRE −1.5 IRE Disabled Enabled 0 1 Note Only available in EDTV (525p/625p) ADV7324 Table 10. Register 0x12 SR7– SR0 0x12 Register HD Mode Register 3 Bit Description HD Y Delay with Respect to Falling Edge of HSYNC Bit 7 Bit 6 HD Color Delay with Respect to Falling Edge of HSYNC HD CGMS Bit 5 Bit 4 Bit 3 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Bit 4 Bit 3 Bit 2 0 0 0 0 1 Bit 1 0 0 1 1 0 Bit 2 Bit 1 Bit 0 0 1 0 1 0 0 1 HD CGMS CRC 0 1 Register Setting 0 clock cycles 1 clock cycles 2 clock cycles 3 clock cycles 4 clock cycles 0 clock cycles 1 clock cycle 2 clock cycles 3 clock cycles 4 clock cycles Disabled Enabled Disabled Enabled Reset Value 0x00 Table 11. Registers 0x13 to 0x14 SR7– SR0 0x13 Register HD Mode Register 4 Bit Description HD Cr/Cb Sequence Bit 7 Bit 6 Bit 5 Bit 0 0 1 Reserved HD Input Format 0 0 1 Sinc Filter on DAC D, E, F 0 1 Reserved HD Chroma SSAF 0 0 1 HD Chroma Input HD Double Buffering 0x14 HD Mode Register 5 0 1 0 1 HD Timing Reset x HD Hsync Generation1 0 1 HD Vsync Generation1 0 1 HD Blank Polarity HD Macrovision for 525p and 625p Reserved Horizontal/Vertical Counters2 1 2 Refer to the HSYNC/VSYNC Output Control section. BLANK active high. 1 BLANK active low. 0 Macrovision disabled. 1 Macrovision enabled. 0 must be written to these bits. 0 0 = field input. 1 1 = VSYNC input. 0 Update field/line counter. 1 Field/line counter free running. Used in conjunction with HD SYNC in Register 0x02, Bit 7, set to 1. When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so. Rev. 0 | Page 28 of 92 Reset Value 0x4C Cr after falling edge of HSYNC. 0 must be written to this bit. 8-bit input. 10-bit input. Disabled. Enabled. 0 must be written to this bit. Disabled. Enabled. 4:4:4 4:2:2 Disabled. Enabled. A low-high-low transition resets the internal HD timing counters. 0 0 HD VSYNC/Field Input Register Setting Cb after falling edge of HSYNC. 0x00 ADV7324 Table 12. Register 0x15 SR7– SR0 0x15 Register HD Mode Register 6 Bit Description Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 HD RGB Input 0 1 HD Sync on PrPb 0 1 HD Color DAC Swap 0 1 HD Gamma Curve A HD Gamma Curve B HD Gamma Curve Enable 0 1 0 1 HD Adaptive Filter Mode HD Adaptive Filter Enable Bit 1 0 1 0 1 Rev. 0 | Page 29 of 92 Bit 0 0 Register Setting 0 must be written to this bit. Disabled. Enabled. Disabled. Enabled. DAC E = Pb; DAC F = Pr. DAC E = Pr; DAC F = Pb. Gamma Curve A. Gamma Curve B. Disabled. Enabled. Mode A. Mode B. Disabled. Enabled. Reset Value 0x00 ADV7324 Table 13. Registers 0x16 to 0x37 SR7– SR0 0x16 0x17 Register HD Y Level1 0x18 HD Cb Level1 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 Bit Description HD Cr Level1 HD Sharpness Filter Gain 1 HD CGMS Data 0 HD CGMS Data 1 HD CGMS Data 2 HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B Bit 6 x x Bit 5 x x Bit 4 x x Bit 3 x x Bit 2 x x Bit 1 x x Bit 0 x x Register Setting Y level value Cr level value Reset Value 0xA0 0x80 x x x x x x x x Cb level value 0x80 Reserved Reserved Reserved Reserved Reserved Reserved Reserved HD Sharpness Filter Gain Value A HD Sharpness Filter Gain Value B 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Bit 7 x x HD CGMS Data Bits HD CGMS Data Bits HD CGMS Data Bits HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points 0 0 … 0 1 … 1 0 C15 C7 x x x x x x x x x x x x x x x x x x x x 0 0 … 1 0 … 1 0 C14 C6 x x x x x x x x x x x x x x x x x x x x 0 0 … 1 0 … 1 0 C13 C5 x x x x x x x x x x x x x x x x x x x x 0 1 … 1 0 … 1 0 C12 C4 x x x x x x x x x x x x x x x x x x x x For use with internal test pattern only. Rev. 0 | Page 30 of 92 0 0 0 0 Gain A = 0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 C19 C11 C3 x x x x x x x x x x x x x x x x x x x x C18 C10 C2 x x x x x x x x x x x x x x x x x x x x C17 C9 C1 x x x x x x x x x x x x x x x x x x x x C16 C8 C0 x x x x x x x x x x x x x x x x x x x x Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 CGMS 19 to 16 CGMS 15 to 8 CGMS 7 to 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ADV7324 Table 14. Registers 0x38 to 0x3D SR7– SR0 0x38 Register HD Adaptive Filter Gain 1 Bit Description HD Adaptive Filter Gain 1, Value A HD Adaptive Filter Gain 1, Value B 0x39 HD Adaptive Filter Gain 2 HD Adaptive Filter Gain 3 0x3C 0x3D HD Adaptive Filter Threshold A HD Adaptive Filter Threshold B HD Adaptive Filter Threshold C Bit 5 Bit 4 0 0 0 0 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 0 0 0 0 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 HD Adaptive Filter Gain 3, Value A HD Adaptive Filter Gain 3 Value B 0x3B Bit 6 HD Adaptive Filter Gain 2, Value A HD Adaptive Filter Gain 2, Value B 0x3A Bit 7 HD Adaptive Filter Threshold A HD Adaptive Filter Threshold B HD Adaptive Filter Threshold C Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 0 0 0 0 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 0 0 0 0 0 … 0 1 … 1 0 … 1 0 … 1 0 … 1 0 … 1 1 … 1 0 … 1 Register Setting Gain A = 0 Reset Value 0x00 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Gain A = 0 0x00 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Gain A = 0 0x00 0 0 0 0 Gain A = +1 … Gain A = +7 Gain A = −8 … Gain A = −1 Gain B = 0 0 … 0 1 … 1 x 0 … 1 0 … 1 x 0 … 1 0 … 1 x 1 … 1 0 … 1 x x x x x Gain B = +1 … Gain B = +7 Gain B = −8 … Gain B = −1 Threshold A 0x00 x x x x x x x x Threshold B 0x00 x x x x x x x x Threshold C 0x00 Rev. 0 | Page 31 of 92 ADV7324 Table 15. Registers 0x3E to 0x43 SR7– SR0 0x3E 0x3F 0x40 Register SD Mode Register 0 Bit Description Reserved Reserved SD Standard Bit 7 Bit 6 Bit 5 SD Luma Filter SD Chroma Filter 0x41 0x42 SD Mode Register 1 Bit 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit 3 0 0 1 1 0 0 1 1 Bit 2 Bit 1 Bit 0 Register Setting 0 0 1 1 0 1 0 1 NTSC. PAL B, D, G, H, I. PAL M. PAL N. LPF NTSC. LPF PAL. Notch NTSC. Notch PAL. SSAF luma. Luma CIF. Luma QCIF. Reserved. 1.3 MHz. 0.65 MHz. 1.0 MHz. 2.0 MHz. Reserved. Chroma CIF. Chroma QCIF. 3.0 MHz. 0 1 Disabled. Enabled. Refer to the Output Configuration section. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved SD PrPb SSAF SD DAC Output 1 0 Reset Value 0x00 0x00 0x00 0x00 0x08 1 SD DAC Output 2 0 Refer to the Output Configuration section. 1 SD Pedestal 0 1 SD Square Pixel 0 1 SD VCR FF/RW Sync 0 1 SD Pixel Data Valid 0x43 SD Mode Register 2 SD SAV/EAV Step Edge Control SD Pedestal YPrPb Output SD Output Levels Y 0 1 0 1 0 1 0 1 SD Output Levels PrPb SD VBI Open 0 1 SD CC Field Control Reserved 0 0 1 1 0 1 0 1 0 Rev. 0 | Page 32 of 92 0 0 0 1 1 1 0 1 Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. No pedestal on YUV. 7.5 IRE pedestal on YUV. Y = 700 mV/300 mV. Y = 714 mV/286 mV. 700 mV p-p (PAL); 1000 mV p-p (NTSC). 700 mV p-p. 1000 mV p-p. 648 mV p-p. Disabled. Enabled. CC disabled. CC on odd field only. CC on even field only. CC on both fields. Reserved. 0x00 ADV7324 Table 16. Registers 0x44 to 0x49 SR7– SR0 0x44 Register SD Mode Register 3 Bit Description SD VSYNC-3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SD RTC/TR/SCR SD Active Video Length 0x47 SD Mode Register 5 0 0 1 1 0 1 0 1 NTSC Color Subcarrier Adjust (Falling Edge of HS to Start of Color Burst)1 0 1 0 1 Reserved Reserved Reserved Reserved Reserved SD Double Buffering 0 1 0 0 0 0 0 0 1 SD Input Format 0 0 1 1 SD Digital Noise Reduction SD Gamma Control SD Gamma Curve 0 1 0 1 0 1 0 1 0 1 SD Undershoot Limiter 0 0 1 1 Reserved SD Black Burst Output on DAC Luma SD Chroma Delay Reserved Reserved 1 1 0 1 0 1 SD Luma SSAF Gain SD Mode Register 7 1 5.17 μs. 5.31 μs (default). 5.59 μs (must be set for Macrovision compliance). Reserved. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. Disabled. Enabled. 0 must be written to this bit. 0 must be written to this bit. 0 must be written to this bit. SD PrPb Scale SD Brightness 0x49 0 1 0 0 1 SD Hue Adjust SD Mode Register 6 0 0 1 0 1 SD Y Scale 0x48 Register Setting Disabled. VSYNC= 2.5 lines (PAL), VSYNC= 3 lines (NTSC). Genlock disabled. Subcarrier Reset. Timing Reset. RTC enabled. 720 pixels. 710 (NTSC)/702 (PAL). Chroma enabled. Chroma disabled. Enabled. Disabled. Disabled. Enabled. DAC A = luma, DAC B = chroma. DAC A = chroma, DAC B = luma. 0 1 SD Color Bars Reserved SD Mode Register 4 Bit 0 0 1 0 1 SD Burst 0x45 0x46 Bit 1 0 1 SD Chroma SD DAC Swap Bit 2 0 0 1 0 0 1 1 0 1 0 1 0 0 NTSC color bar adjust should be set to 10 b for Macrovision compliance. Rev. 0 | Page 33 of 92 0 1 0 1 Reset Value 0x00 0x00 0x01 0x00 0x00 0 must be written to this bit. Disabled. Enabled. 8-bit input. 16-bit input. 10-bit input. 20-bit input. Disabled. Enabled. Disabled. Enabled. Gamma Curve A. Gamma Curve B. Disabled. −11 IRE. −6 IRE. −1.5 IRE. 0 must be written to this bit. Disabled. Enabled. Disabled. 4 clock cycles. 8 clock cycles. Reserved. 0 must be written to this bit. 0 must be written to this bit. 0x00 ADV7324 Table 17. Registers 0x4A to 0x58 SR7– SR0 0x4A Register SD Timing Register 0 Bit Description SD Slave/Master Mode SD Timing Mode Bit 7 Bit 6 Bit 5 Bit 4 SD BLANK Input 0x4B SD Timing Register 1 x 0 1 0 0 0 1 1 0 1 0 1 0 0 0x54 0x55 0x56 0x57 0x58 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 x x 0 1 0 0 1 1 0 1 0 1 0 1 0 1 Register Setting Slave mode. Master mode. Mode 0. Mode 1. Mode 2. Mode 3. Enabled. Disabled. No delay. 2 clock cycles. 4 clock cycles. 6 clock cycles. −40 IRE. −7.5 IRE. A low-high-low transition resets the internal SD timing counters. Ta = 1 clock cycle. Ta = 4 clock cycles. Ta = 16 clock cycles. Ta = 128 clock cycles. Tb = 0 clock cycle. Tb = 4 clock cycles. Tb = 8 clock cycles. Tb = 18 clock cycles. Tc = Tb. Tc = Tb + 32 µs. Reset Value 0x08 0x00 0 0 1 1 x x x x x x 0 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Extended Data Bit 15 to Bit 8. 0x00 x x x x x x x x Data Bit 7 to Bit 0. 0x00 Data on Odd Fields x x x x x x x x Data Bit 15 to Bit 8. 0x00 Setting any of these bits to 1 disables pedestal on the line number indicated by the bit settings. 0x00 SD FSC Register 01 SD FSC Register 1 SD FSC Register 2 SD FSC Register 3 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 Extended Data on Even Fields Extended Data on Even Fields Data on Odd Fields Pedestal on Odd Fields 17 16 15 14 13 12 11 10 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3 Pedestal on Odd Fields Pedestal on Even Fields Pedestal on Even Fields 25 24 23 22 21 20 19 18 0x00 17 16 15 14 13 12 11 10 0x00 25 24 23 22 21 20 19 18 0x00 For precise NTSC Fsc, this register should be programmed to 0x1F. LINE 1 HSYNC LINE 313 LINE 314 Ta Tc Tb 05220-047 1 Bit 0 0 1 1 clock cycle. 4 clock cycles. 16 clock cycles. 128 clock cycles. 0 clock cycles. 1 clock cycle. 2 clock cycles. 3 clock cycles. Subcarrier Frequency Bit 7 to Bit 0. Subcarrier Frequency Bit 15 to Bit 8. Subcarrier Frequency Bit 23 to Bit 16. Subcarrier Frequency Bit 31 to Bit 24. Subcarrier Phase Bit 9 to Bit 2. Extended Data Bit 7 to Bit 0. HSYNC to Pixel Data Adjust 0x53 0 0 0 1 1 SD HSYNC to VSYNC Rising Edge Delay (Mode 1 Only) VSYNC Width (Mode 2 Only) 0x52 Bit 1 SD HSYNC Width SD HSYNC to VSYNC Delay 0x4C 0x4D 0x4E 0x4F 0x50 0x51 Bit 2 0 1 SD Luma Delay SD Min. Luma Value SD Timing Reset Bit 3 VSYNC Figure 47. Timing Register 1 in PAL Mode Rev. 0 | Page 34 of 92 0x1E1 0x7C 0xF0 0x21 0x00 0x00 ADV7324 Table 18. Registers 0x59 to 0x64 SR7– SR0 0x59 Register SD CGMS/WSS 0 Bit Description SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS Bit 7 SD CGMS/WSS 2 SD CGMS/WSS Data 0x5C SD LSB Register SD LSB for Y Scale Value SD LSB for Cb Scale Value SD LSB for Cr Scale Value SD LSB for FSC Phase SD Y Scale Value x x SD Cb Scale Value 0x60 0x61 Bit 0 16 15 7 14 6 13 12 11 10 9 8 5 4 3 2 1 0 x x x x Register Setting CGMS Data Bit C19 to Bit C16 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled CGMS Data Bit C13 to Bit C8, or WSS Data Bit C13 to Bit C8 CGMS Data Bit C15 to Bit C14 CGMS/WSS Data Bit C7 to Bit C0 SD Y Scale Bit 1 to Bit 0 Reset Value 0x00 0x00 0x00 0x00 SD Cb Scale Bit 1 to Bit 0 x x x x x x x x x Subcarrier Phase Bit 1 to Bit 0 SD Y Scale Bit 7 to Bit 2 0x00 x x x x x x x x SD Cb Scale Bit 7 to Bit 2 0x00 SD Cr Scale Value x x x x x x x x SD Cr Scale Bit 7 to Bit 2 0x00 SD Hue Adjust Value SD Brightness Value SD Blank WSS Data x x x x x x x x x x x x x x x 0x00 0x00 Line 23 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 … 1 1 0 0 … 1 1 0 0 … 1 1 0 1 … 0 1 SD Hue Adjust Bit 7 to Bit 0 SD Brightness Bit 6 to Bit 0 Disabled Enabled −4 dB 0 dB +4 dB No gain +1/16 [–1/8] +2/16 [–2/8] +3/16 [–3/8] +4/16 [–4/8] +5/16 [–5/8] +6/16 [–6/8] +7/16 [–7/8] +8/16 [–1] No gain +1/16 [–1/8] +2/16 [–2/8] +3/16 [–3/8] +4/16 [–4/8] +5/16 [–5/8] +6/16 [–6/8] +7/16 [–7/8] +8/16 [–1] 0 1 … 62 63 2 pixels 4 pixels 8 pixels 16 pixels SD Luma SSAF SD Luma SSAF Gain/Attenuation 0x63 SD DNR 0 Coring Gain Border Coring Gain Data SD DNR 1 Bit 1 17 x 0x62 0x64 Bit 2 18 0 1 0x5B 0x5F Bit 3 19 0 1 SD CGMS/WSS Data 0x5E Bit 4 0 1 SD CGMS/WSS 1 SD Y Scale Register SD Cb Scale Register SD Cr Scale Register SD Hue Register SD Brightness/ WSS Bit 5 0 1 0x5A 0x5D Bit 6 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 DNR Threshold Border Area Block Size Control 0 0 1 1 0 0 1 1 0 0 0 … 1 1 0 1 0 1 0 1 0 1 0 0 0 … 1 1 SD Cr Scale Bit 1 to Bit 0 0 1 0 1 Rev. 0 | Page 35 of 92 0x00 0x00 In DNR mode, the values in brackets apply. 0x00 ADV7324 Table 19. Registers 0x65 to 0x7C SR7– SR0 0x65 Register SD DNR 2 Bit Description DNR Input Select Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0 0 0 1 Bit 1 0 1 1 0 Bit 0 1 0 1 0 0 0 … 1 1 x x x x x x x x x x x x x x x x x x x x x 0 1 0 1 … 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x DNR Mode DNR Block Offset 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Brightness Detect Field Count Register SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Brightness Value Field Count Reserved Reserved Reserved Revision Code Reserved 0 0 … 1 1 x x x x x x x x x x x x x x x x x x x x x 0 0 … 1 1 x x x x x x x x x x x x x x x x x x x x x 0 0 0 1 0 Rev. 0 | Page 36 of 92 Register Setting Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset 1 pixel offset … 14 pixel offset 15 pixel offset A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only Read only Reserved Reserved Reserved Read only Reserved Reset Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8x 0x00 ADV7324 Table 20. Registers 0x7D to 0x91 SR7SR0 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 Register Reserved Reserved Reserved Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bit x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x 0 x x x x x x x x x x x x x x x x x x Rev. 0 | Page 37 of 92 Register Setting Reset Value Bit 1 to Bit 7 must be 0. 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ADV7324 INPUT CONFIGURATION When 10-bit input data is applied, the following bits must be set to 1: PS ONLY OR HDTV ONLY Address 0x13, Bit 2 (HD 10-bit enable) Address 0x48, Bit 4 (SD 10-bit enable) YCrCb PS, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pin Y9 to Pin Y0, and the CrCb data is input on Pin C9 to Pin C0. In 4:4:4 input mode, Y data is input on Pin Y9 to Pin Y0, Cb data is input on Pin C9 to Pin C0, and Cr data is input on Pin S9 to Pin S0. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004/1362, the async timing mode must be used. RGB data can only be input in 4:4:4 format in PS or HDTV input modes when HD RGB input is enabled. G data is input on Pin Y9 to Pin Y0, R data is input on Pin S9 to Pin S0, and B data is input on Pin C9 to Pin C0. The clock signal must be input on Pin CLKIN_A. Note that the ADV7324 defaults to simultaneous SD and PS upon power-up (Address[0x01]: Input Mode = 011). SD ONLY Address[0x01]: Input Mode = 000 In 8-/10-bit input mode, multiplexed data is input on Pin S9 to Pin S0 (or Pin Y9 to Pin Y0, depending on Register Address 0x01, Bit 7), with S0 being the LSB in 10-bit input mode (see Table 21). Input standards supported are ITU-R BT.601/656. In 16-/20-bit input mode, the Y pixel data is input on Pin S9 to Pin S2, and CrCb data is input on Pin Y9 to Pin Y2 (see Table 21). Address[0x01]: Input Mode = 001 or 010, Respectively MPEG2 DECODER 16-/20-Bit Mode Operation ADV7324 When Register 0x01, Bit 7 = 0, CrCb data is input on the Y bus, and Y data is input on the S bus. When Register 0x01, Bit 7 = 1, CrCb data is input on the C bus, and Y data is input on Y bus. 27MHz YCrCb CLKIN_A Cr 10 INTERLACED TO PS The 27 MHz clock input must be input on Pin CLKIN_A. Input sync signals are input on the S_VSYNC, S_HSYNC, and S_BLANK pins. Y 10 3 C[9:0] S[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK 05220-049 Cb 10 Figure 49. PS Input Mode Table 21. SD 8-/10-Bit and 16-/20-Bit Configurations Parameter Register 0x01, Bit 7 = 0 Y Bus S Bus C Bus Register 0x01, Bit 7 = 1 Y Bus S Bus C Bus Configuration 8-/10-Bit Mode 16-/20-Bit Mode 656/601, YCrCb 656/601, YCrCb CrCb Y Y CrCb ADV7324 27MHz YCrCb 10 S_VSYNC, S_HSYNC, S_BLANK CLKIN_A S[9:0] OR Y[9:0]* *SELECTED BY ADDRESS 0x01, BIT 7 Figure 48. SD Only Input Mode 05220-048 3 MPEG2 DECODER SIMULTANEOUS SD/PS OR SD/HDTV Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit), Input Mode 101 (SD and HD, SD Oversampled), or Input Mode 110 (SD and HD, HD Oversampled) YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2 input format, the HD Y data is input on Pin Y9 to Pin Y0, and the HD CrCb data is input on Pin C9 to Pin C0. If PS 4:2:2 data is inter-leaved onto a single 10-bit bus, Pin Y9 to Pin Y0 are used for the input port. The input data is input at 27 MHz, with the data being clocked upon the rising and falling edges of the input clock. The input mode register at Address 0x01 is set accordingly. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004, the async timing mode must be used. The 8- or 10-bit SD data must be compliant with ITU-R BT.601/656 in 4:2:2 format. SD data is input on Pin S9 to Pin S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pin S9 to Pin S2. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are optional. SD syncs are Rev. 0 | Page 38 of 92 ADV7324 input on Pin S_VSYNC, Pin S_HSYNC, and Pin S_BLANK. HD syncs are input on Pin P_VSYNC, Pin P_HSYNC, and Pin P_BLANK. PS AT 27 MHZ (DUAL EDGE) OR 54 MHZ Address[0x01]: Input Mode 100 or 111, Respectively ADV7324 CrCb 10 INTERLACED TO Y PS 10 3 27MHz CLKIN_A S[9:0] Table 22 provides an overview of all possible input configurations. Figure 53, Figure 54, and Figure 55 show the possible conditions: Cb data on the rising edge, and Y data on the rising edge. C[9:0] Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B CLKIN_B Y9–Y0 3FF 00 00 XY Cb0 Y0 Cr0 Y1 Figure 50. Simultaneous SD and PS Input CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 0 IN THIS CASE. ADV7324 3 SDTV DECODER 27MHz YCrCb 10 1080i OR 720p OR 1035i Figure 53. Input Sequence in PS Bit Interleaved Mode (EAV/SAV) S_VSYNC, S_HSYNC, S_BLANK CLKIN_B CLKIN_A S[9:0] Y9–Y0 CrCb 10 Y 10 3 74.25MHz 3FF 00 00 XY Y0 Cb0 Y1 Cr0 C[9:0] CLOCK EDGE ADDRESS 0x00, BIT 1, SHOULD BE SET TO 1 IN THIS CASE. Y[9:0] P_VSYNC, P_HSYNC, P_BLANK CLKIN_B Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV) 05220-051 HDTV DECODER 05220-053 10 05220-054 27MHz YCrCb 05220-050 3 MPEG2 DECODER YCrCb PS data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-/10-bit bus and is input on Pin Y9 to Pin Y0. When a 27 MHz clock is supplied, the data is clocked upon the rising and falling edges of the input clock, and the clock edge bit [Address 0x01, Bit 1] must be set accordingly. S_VSYNC, S_HSYNC, S_BLANK CLKIN_B Figure 51. Simultaneous SD and HD Input PIXEL INPUT DATA 3FF 00 00 XY Cb0 Y0 Cr0 WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE. Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV) MPEG2 DECODER CLKIN_A ADV7324 27MHz OR 54MHz CLKIN_A 05220-052 CLKIN_B Figure 52. Clock Phase with Two Input Clocks INTERLACED TO PS YCrCb 10 3 Y[9:0] P_VSYNC, P_HSYNC, P_BLANK Figure 56. 10-Bit PS at 27 MHz or 54 MHz Rev. 0 | Page 39 of 92 05220-056 YCrCb tDELAY < 9.25ns OR tDELAY > 27.75ns Y1 05220-055 In simultaneous SD/HD input mode, if the two clock phases differ by less than 9.25 ns or by more than 27.75 ns, the clock align bit [Address 0x01, Bit 3] must be set accordingly. If the application uses the same clock source for both SD and PS, the clock align bit must be set because the phase difference between both inputs is less than 9.25 ns. ADV7324 Table 22. Input Configurations Input Format ITU-R BT.656 (See Table 21) Total Bits 8 4:2:2 Input Video YCrCb Input Pins S9 to S2 (MSB = S9) 10 4:2:2 YCrCb S9 to S0 (MSB = S9) 16 4:2:2 20 4:2:2 8 4:2:2 Y CrCb Y CrCb YCrCb S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) Y9 to Y2 (MSB = Y9) 10 4:2:2 YCrCb Y9 to Y0 (MSB = Y9) 8 (27 MHz clock) 4:2:2 YCrCb Y9 to Y2 (MSB = Y9) 10 (27 MHz clock) 4:2:2 YCrCb Y9 to Y0 (MSB = Y9) 8 (54 MHz clock) 4:2:2 YCrCb Y9 to Y2 (MSB = Y9) 10 (54 MHz clock) 4:2:2 YCrCb Y9 to Y0 (MSB = Y9) 16 4:2:2 20 4:2:2 24 4:4:4 30 4:4:4 16 4:2:2 20 4:2:2 24 4:4:4 30 4:4:4 24 4:4:4 30 4:4:4 ITU-R BT.656 and PS 8 (SD) 8 (PS) 4:2:2 4:2:2 Y CrCb Y CrCb Y Cb Cr Y Cb Cr Y CrCb Y CrCb Y Cb Cr Y Cb Cr G B R G B R YCrCb YCrCb Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S2 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) S9 to S0 (MSB = S9) S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) ITU-R BT.656 and PS 10 (SD) 10 (PS) 4:2:2 4:2:2 YCrCb YCrCb S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) ITU-R BT.656 and PS or HDTV 8 16 4:2:2 4:2:2 ITU-R BT.656 and PS or HDTV 10 20 4:2:2 4:2:2 YCrCb Y CrCb YCrCb Y CrCb S9 to S2 (MSB = S9) Y9 to Y2 (MSB = Y9) C9 to C2 (MSB = C9) S9 to S0 (MSB = S9) Y9 to Y0 (MSB = Y9) C9 to C0 (MSB = C9) PS Only HDTV Only HD RGB Rev. 0 | Page 40 of 92 Subaddress 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x48 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 0x01 0x13 Register Setting 0x00 0x00 0x00 0x10 0x00 0x08 0x00 0x18 0x80 0x00 0x80 0x10 0x10 0x40 0x10 0x44 0x70 0x40 0x70 0x44 0x10 0x40 0x10 0x44 0x10 0x00 0x01 0x13 0x10 0x04 0x01 0x13 0x01 0x13 0x01 0x13 0x20 0x40 0x20 0x44 0x20 0x00 0x01 0x13 0x20 0x04 0x01 0x13 0x15 0x01 0x13 0x15 0x01 0x13 0x48 0x01 0x13 0x48 0x01 0x13 0x48 0x01 0x13 0x48 0x10 or 0x20 0x00 0x02 0x10 or 0x20 0x04 0x02 0x40 0x40 0x00 0x40 0x44 0x10 0x30, 0x50, or 0x60 0x40 0x00 0x30, 0x50, or 0x60 0x44 0x10 ADV7324 FEATURES OUTPUT CONFIGURATION Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. Table 23. Output Configuration in SD Only Mode RGB/YUV Output 0x02, Bit 5 0 0 0 0 1 1 1 1 SD DAC Output 1 0x42, Bit 2 0 0 1 1 0 0 1 1 SD DAC Output 2 0x42, Bit 1 0 1 0 1 0 1 0 1 DAC A CVBS G G CVBS CVBS Y Y CVBS DAC B Luma B Luma B Luma U Luma U DAC C Chroma R Chroma R Chroma V Chroma V DAC D G CVBS CVBS G Y CVBS CVBS Y DAC E B Luma B Luma U Luma U Luma DAC F R Chroma R Chroma V Chroma V Chroma Luma/Chroma Swap 0x44, Bit 7 0 Table as above 1 Table as above, but with all luma/chroma instances swapped Table 24. Output Configuration in HD Only or PS Only Mode Input Format YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB Input 0x15, Bit 1 0 0 0 0 0 0 0 0 1 1 1 1 RGB/YPrPb Output 0x02, Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 Color Swap 0x15, Bit 3 0 1 0 1 0 1 0 1 0 1 0 1 DAC A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC B N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC C N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A DAC D G G Y Y G G Y Y G G G G DAC E B R Pb Pr B R Pb Pr B R B R DAC F R B Pr Pb R B Pr Pb R B R B Table 25. Output Configuration in Simultaneous SD/PS or SD/HD Mode Input Formats ITU-R.BT656 and HD/PS YCrCb in 4:2:2 ITU-R.BT656 and HD/PS YCrCb in 4:2:2 ITU-R.BT656 and HD/PS YCrCb in 4:2:2 ITU-R.BT656 and HD/PS YCrCb in 4:2:2 RGB/YPrPb Output 0x02, Bit 5 0 HD/PS Color Swap 0x15, Bit 3 0 DAC A CVBS DAC B Luma DAC C Chroma DAC D G DAC E B DAC F R 0 1 CVBS Luma Chroma G R B 1 0 CVBS Luma Chroma Y Pb Pr 1 1 CVBS Luma Chroma Y Pr Pb Rev. 0 | Page 41 of 92 ADV7324 In async mode, the PLL must be turned off [Subaddress 0x00, Bit 1 = 1]. Register 0x10 should be programmed to 0x01. HD ASYNC TIMING MODE [Subaddress 0x10, Bits 3 and 2] Figure 57 and Figure 58 show examples of how to program the ADV7324 to accept an HD standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358. For any input data that does not conform to the standards selectable in input mode (Subaddress 0x10), asynchronous timing mode can be used to interface to the ADV7324. Timing control signals for HSYNC, VSYNC, and BLANK must be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode. Follow the specifications in Table 26 when programming the control signals in async timing mode. For standards that do not require a trisync level, P_BLANK must be tied low at all times. Table 26. Async Timing Mode Truth Table P_HSYNC P_VSYNC P_BLANK1 1→0 0 0→1 1 1 0 0→1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 0→1 1→0 Reference in Figure 57 and Figure 58 a b c d e When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low using Address 0x10, Bit 6. CLK P_HSYNC PROGRAMMABLE INPUT TIMING P_VSYNC P_BLANK SET ADDRESS 0x14, BIT 3 = 1 ACTIVE VIDEO HORIZONTAL SYNC 81 66 a 66 b 243 c 05220-057 ANALOG OUTPUT 1920 d e Figure 57. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility CLK P_HSYNC 0 P_VSYNC 1 P_BLANK SET ADDRESS 0x14 BIT 3 = 1 HORIZONTAL SYNC ACTIVE VIDEO ANALOG OUTPUT a b c d Figure 58. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal Rev. 0 | Page 42 of 92 e 05220-058 1 Reference 50% point of falling edge of trilevel horizontal sync signal 25% point of rising edge of trilevel horizontal sync signal 50% point of falling edge of trilevel horizontal sync signal 50% start of active video 50% end of active video ADV7324 b. HD TIMING RESET A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. This reset signal must be held high for a minimum of one clock cycle. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only. Because the field counter is not reset, it is recommended that the reset signal is applied in Field 7 (PAL) or Field 3 (NTSC). The reset of the phase will then occur on the next field, i.e., Field 1, lined up correctly with the internal counters. The field count register at Address 0x7B can be used to identify the number of active fields. SD REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET [Subaddress 0x44, Bit 2 and Bit 1] Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 0x44, Bit 1 and Bit 2], the ADV7324 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) RTC mode. c. A timing reset is achieved after a low-to-high transition on the RTC_SCR_TR pin (Pin 31). In this state, the horizontal and vertical counters remain reset. Upon releasing this pin (set to low), the internal counters resume counting, starting with Field 1, and the subcarrier phase is reset. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only. DISPLAY 307 In RTC mode, the ADV7324 can be used to lock to an external video source. The real-time control mode allows the ADV7324 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device, such as an ADV7402A video decoder (see Figure 61), that outputs a digital data stream in RTC format, it automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide, and the subcarrier is contained in Bit 0 to Bit 21. Each bit is two clock cycles long. Write 0x00 into all four subcarrier frequency registers when this mode is used. START OF FIELD 4 OR 8 310 FSC PHASE = FIELD 4 OR 8 313 320 NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 307 1 2 3 4 FSC PHASE = FIELD 1 5 6 7 21 TIMING RESET PULSE TIMING RESET APPLIED Figure 59. Timing Reset Timing Diagram Rev. 0 | Page 43 of 92 05220-059 a. In subcarrier phase reset, a low-to-high transition on the RTC_SCR_TR pin (Pin 31) resets the subcarrier phase to 0 on the field following the subcarrier phase reset when the SD RTC/TR/SCR control bits at Address 0x44 are set to 01. ADV7324 DISPLAY 307 START OF FIELD 4 OR 8 310 FSC PHASE = FIELD 4 OR 8 313 320 NO FSC RESET APPLIED 307 START OF FIELD 4 OR 8 310 FSC PHASE = FIELD 1 313 320 FSC RESET PULSE FSC RESET APPLIED 05220-060 DISPLAY Figure 60. Subcarrier Reset Timing Diagram ADV7324 CLKIN_A DAC A DAC B LCC1 COMPOSITE VIDEO1 RTC_SCR_TR GLL DAC C DAC D ADV7402A P19–P10 VIDEO DECODER Y9–Y0/S9–S05 DAC E DAC F 4 BITS RESERVED 14 BITS H/L TRANSITION COUNT START SUBCARRIER LOW PHASE 128 13 0 SEQUENCE BIT3 21 FSC PLL INCREMENT2 RESET BIT4 RESERVED 0 RTC 14 6768 19 VALID INVALID SAMPLE SAMPLE 8/LINE LOCKED CLOCK 5 BITS RESERVED NOTES 1FOR EXAMPLE, VCR OR CABLE. 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7324 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7324. 3SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE. 4RESET ADV7324 DDS. 5SELECTED BY REGISTER ADDRESS 0x01, BIT 7. Figure 61. RTC Timing and Connections Rev. 0 | Page 44 of 92 05220-061 TIME SLOT 01 ADV7324 In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync signal usually occurs after the total number of lines/fields are reached. Conventionally, this means that the output video will have corrupted field signals, because one signal is generated by the incoming video and another is generated when the internal lines/field counters reach the end of a field. RESET SEQUENCE A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the timing specifications, and the ADV7324 reverts to the default output configuration. Figure 62 illustrates the RESET timing sequence. SD VCR FF/RW SYNC [Subaddress 0x42, Bit 5] When the VCR FF/RW sync control is enabled, the line/field counters are updated according to the incoming VSYNC signal, and the analog output matches the incoming VSYNC signal. In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit [Subaddress 0x42, Bit 5] can be used for nonstandard input video, i.e., in fast forward or rewind modes. This control is available in all slave timing modes except Slave Mode 0. RESET XXXXXX DIGITAL TIMING XXXXXX OFF DIGITAL TIMING SIGNALS SUPPRESSED VALID VIDEO TIMING ACTIVE 05220-062 DACs A, B, C PIXEL DATA VALID Figure 62. RESET Timing Sequence Rev. 0 | Page 45 of 92 ADV7324 VERTICAL BLANKING INTERVAL SUBCARRIER FREQUENCY REGISTERS The ADV7324 accepts input data that contains VBI data (such as CGMS, WSS, VITS) in SD and HD modes. [Subaddresses 0x4C to 0x4F] For the SMPTE 293M (525p) standard, VBI data can be inserted on Line 13 to Line 42 of each frame, or on Line 6 to Line 43 for the ITU-R BT.1358 (625p) standard. Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the equation Subcarrier Frequency Register = Number of subcarrier periods in one video line This data can be present on Line 10 to Line 20 for SD NTSC and on Line 7 to Line 22 for PAL. Number of 27 MHz clock cycles in one video line If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43, Bit 4 for SD], VBI data is not present at the output, and the entire VBI is blanked. These control bits are valid in all master and slave modes. In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten. It is possible to use VBI in this timing mode as well. In Slave Mode 1 or 2, the BLANK control bit [Address 0x4A, Bit 3] must be enabled to allow VBI data to pass through the ADV7324. Otherwise, the ADV7324 automatically blanks the VBI to standard. If CGMS is enabled and VBI is disabled, the CGMS data will nevertheless be available at the output. × 2 32 where the sum is rounded to the nearest integer. For example, in NTSC mode 227.5 ⎞ 32 Subcarrier Register Value = ⎛⎜ ⎟ × 2 = 569408543 ⎝ 1716 ⎠ where: Subcarrier Register Value = 0x21F07C1F SD FSC Register 0: 0x1F SD FSC Register 1: 0x7C SD FSC Register 2: 0xF0 SD FSC Register 3: 0x21 See the MPU Port Description section for more details on accessing the subcarrier frequency registers. Programming the FSC See Appendix 1—Copy Generation Management System. The subcarrier register value is divided into four FSC registers, as shown above. To load the value into the encoder, users must write to the FSC registers in sequence, starting with FSC0. The value is not loaded until the FSC4 write is complete. Note that the ADV7324 power-up value for FSC0 is 0x1E. For precise NTSC FSC, write 0x1F to this register. Rev. 0 | Page 46 of 92 ADV7324 SQUARE PIXEL TIMING MODE [Address 0x42, Bit 4] In square pixel mode, the following timing diagrams apply. ANALOG VIDEO EAV CODE NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) 4 CLOCK 0 F F A A A 0 F F B B B C C 8 1 8 1 F 0 0 X C Y C Y C Y r Y b b 0 0 0 0 F 0 0 Y b r ANCILLARY DATA (HANC) 4 CLOCK 272 CLOCK 1280 CLOCK 4 CLOCK 4 CLOCK 344 CLOCK 1536 CLOCK 05220-063 INPUT PIXELS SAV CODE C F 0 0 X 8 1 8 1 Y Y r F 0 0 Y 0 0 0 0 START OF ACTIVE VIDEO LINE END OF ACTIVE VIDEO LINE Figure 63. EAV/SAV Embedded Timing HSYNC FIELD PAL = 44 CLOCK CYCLES NTSC = 44 CLOCK CYCLES BLANK Cb Y Cr Y PAL = 308 CLOCK CYCLES NTSC = 236 CLOCK CYCLES Figure 64. Active Pixel Timing Rev. 0 | Page 47 of 92 05220-064 PIXEL DATA ADV7324 EXTENDED UV FILTER MODE FILTERS 0 Table 27 shows an overview of the programmable filters available on the ADV7324. –10 Table 27. Selectable Filters Subaddress 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x42 0x13 0x13 0x13 GAIN (dB) –20 –30 –40 –50 05220-065 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD UV SSAF HD Chroma Input HD Sinc Filter HD Chroma SSAF –60 0 1 2 3 4 FREQUENCY (MHz) 5 6 Figure 65. UV SSAF Filter If this filter is disabled, one of the chroma filters shown in Table 28 can be selected and used for the CVBS or luma/ chroma signal. Table 28. Internal Filter Specifications SD Internal Filter Response [Subaddress 0x40 [7:2]; Subaddress 0x42, Bit 0] The Y filter supports several frequency responses, including two low-pass responses, two notch responses, an extended SSAF response with or without gain boost attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including six low-pass responses, a CIF response, and a QCIF response, as shown in Figure 35 and Figure 36. If SD SSAF gain is enabled, there are 12 response options in the range −4 dB to +4 dB [Subaddress 0x47, Bit 4]. Choose the desired response by programming the correct value via the I2C [Subaddress 0x62]. The variation of frequency responses are shown in Figure 32 and Figure 33. Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF 1 Pass-Band Ripple1 (dB) 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic 3 dB Bandwidth2 (MHz) 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5 Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the −3 dB points. 2 3 dB bandwidth refers to the −3 dB cutoff frequency. In addition to the chroma filters listed in Table 27, the ADV7324 contains an SSAF filter specifically designed for the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and a gain of –40 dB at 3.8 MHz, as shown in Figure 65. This filter can be controlled with Address 0x42, Bit 0. Rev. 0 | Page 48 of 92 ADV7324 PS/HD Sinc Filter Table 29 shows sample color values that can be programmed into the color registers when the output standard selection is set to EIA 770.2. [Subaddress 0x13, Bit 3] 0.5 Table 29. Sample Color Values for EIA 770.2 Output Standard Selection 0.4 0.3 Sample Color White Black Red Green Blue Yellow Cyan Magenta GAIN (dB) 0.2 0.1 0 –0.1 –0.2 05220-066 –0.3 –0.4 –0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30 Cr Value 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE) Cb Value 128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA) RGB Matrix [Subaddresses 0x03 to 0x09] Figure 66. HD Sinc Filter Enabled The internal RGB matrix automatically performs all YCrCb to RGB scaling according to the input standard programmed in the device, as selected by input mode Register 0x01 [6:4]. Table 30 shows the options available in this matrix. 0.5 0.4 0.3 Note that it is not possible to do a color space conversion from RGB-in to YPrPb-out. Also, it is not possible to input SD RGB. 0.2 GAIN (dB) Y Value 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A) 0.1 Table 30. Matrix Conversion Options 0 HDTV/SD/PS –0.1 –0.2 –0.3 Input YCrCb YCrCb RGB 05220-067 –0.4 –0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 67. HD Sinc Filter Disabled Output YPrPb RGB RGB Reg. 0x02,Bit 5 (YUV/RGB OUT) 1 0 0 Reg. 0x15, Bit 1 (RGB IN/YCrCb IN, PS/HD Only) 0 0 1 Manual RGB Matrix Adjust Feature COLOR CONTROLS AND RGB MATRIX HD Y Level, HD Cr Level, HD Cb Level [Subaddresses 0x16 to 0x18] Three 8-bit registers at Address 0x16, Address 0x17, and Address 0x18 are used to program the output color of the internal HD test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls for external pixel data input. For this purpose, the RGB matrix is used. The values for Y and the color difference signals used to obtain white, black, and saturated primary and complementary colors conform to the ITU-R BT.601-4 standard. Normally, there is no need to enable this feature in Register 0x02, Bit 3, because the RGB matrix automatically performs color space conversion depending on the input mode chosen (SD/PS, HD) and the polarity of RGB/YPrPb output in Register 0x02, Bit 5 (see Table 30). For this reason, the manual RGB matrix adjust feature is disabled by default. However, For HDTV YCrCb-to-RGB conversion, the RGB matrix must be enabled to invoke the correct coefficients for this color space. The coefficients do not need to be adjusted. The manual RGB matrix adjust feature provides custom coefficient manipulation and is used in PS and HD modes only. Rev. 0 | Page 49 of 92 ADV7324 When the manual RGB matrix adjust feature is enabled, the default values in Registers 0x05 to 0x09 are correct for HDTV color space only. The color components are converted according to the 1080i and 720p standards (SMPTE 274M, SMPTE 296M): If RGB output is selected, the RGB matrix scaler uses the following equations: G = GY × Y + GU × Pb + GV × Pr B = GY × Y + BU × Pb R = Y + 1.575Pr R = GY × Y + RV × Pr G = Y − 0.468Pr − 0.187Pb If YPrPb output is selected, the following equations are used: B = Y + 1.855Pb Y = GY × Y This is reflected in the preprogrammed values GY = 0x13B, GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0. U = BU × Pb If the RGB matrix is enabled and another input standard (such as SD or PS) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values. For example, SMPTE 293M uses the following equations for conversion: R = Y + 1.402Pr G = Y – 0.714Pr – 0.344Pb B = Y + 1.773Pb The manual RGB matrix adjust feature can be used to control the HD output levels in cases where the video output does not conform to the standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for external HD/PS data and is not functional when internal test patterns are enabled. To adjust Registers 0x05 to 0x09, the manual RGB matrix adjust must be enabled [Register 0x02, Bit 3 = 1]. Programming the RGB Matrix If custom manipulation of coefficients is required, enable the RGB matrix in Address 0x02, Bit 3, set the output to RGB [Address 0x02, Bit 5], and disable sync on PrPb (default) [Address 0x15, Bit 2]. Enabling sync on RGB is optional [Address 0x02, Bit 4]. GY at Address 0x03 and Address 0x05 controls the green signal output levels. BU at Address 0x04 and Address 0x08 controls the blue signal output levels, and RV at Address 0x04 and Address 0x09 controls the red signal output levels. To control YPrPb output levels, enable the YUV output [Address 0x02, Bit 5]. In this case, GY [Address 0x05; Address 0x03, Bit 0 and Bit 1] is used for the Y output, RV [Address 0x09; Address 0x04, Bit 0 and Bit 1] is used for the Pr output, and BU [Address 0x08; Address 0x04, Bit 2 and Bit 3] is used for the Pb output. V = RV × Pr Upon power-up, the RGB matrix is programmed with the default values listed in Table 31. Table 31. RGB Matrix Default Values Address 0x03 0x04 0x05 0x06 0x07 0x08 0x09 Default 0x03 0xF0 0x4E 0x0E 0x24 0x92 0x7C When the manual RGB matrix adjust feature is not enabled, the ADV7324 automatically scales YCrCb inputs to all standards supported by this part, as selected by the input mode, Register 0x01 [6:4]. SD Luma and Color Control [Subaddresses 0x5C, 0x5D, 0x5E, 0x5F] SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit-wide control registers that scale the Y, Cb, and Cr output levels. Each of these registers represents the value required to scale the Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of its initial level. The value of these 10 bits is calculated using the following equation: Y, Cr, or Cb Scalar Value = Scale Factor × 512 For example, Scale Factor = 1.18 Y, Cb, or Cr Scale Value = 1.18 × 512 = 665.6 Y, Cb, or Cr Scale Value = 665 (rounded to the nearest integer) Y, Cb, or Cr Scale Value = 1010 0110 01b Rev. 0 | Page 50 of 92 ADV7324 SD Brightness Control Address 0x5C, SD LSB Register = 0x15 Address 0x5D, SD Y Scale Register = 0xA6 Address 0x5E, SD Cb Scale Register = 0xA6 Address 0x5F, SD Cr Scale Register = 0xA6 [Subaddress 0x61] Note that this feature affects all interlaced output signals, i.e., CVBS, Y-C, YPrPb, and RGB. SD Hue Adjust Value [Subaddress 0x60] The hue adjust value is used to adjust the hue on the composite and chroma outputs. The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and for PAL, the setup can vary from −7.5 IRE to +15 IRE. The brightness control register is an 8-bit register. Seven bits of this 8-bit register are used to control the brightness level, which can be a positive or negative value. These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7324 provides a range of ±22.5° increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits, respectively, of attainable adjustment. For example, Hue Adjust (°) = 0.17578125° (HCRd − 128) for positive hue adjust value. 2. To add –7 IRE brightness level to a PAL signal, write 0x72 to Address 0x61, SD brightness. 1. To add +20 IRE brightness level to an NTSC signal with pedestal, write 0x28 to Address 0x61, SD brightness. 0x[SD Brightness Value] = 0x[IRE Value × 2.015631] = 0x[20 × 2.015631] = 0x[40.31262] = 0x28 For example, to adjust the hue by +4°, write 0x97 to the hue adjust value register: [IRE Value| × 2.075631 [7 × 2.015631] = [14.109417] = 0001110b 4 ⎛ ⎞ + 128 = 105d = 0 x97 ⎜ ⎟ ⎝ 0.17578125 ⎠ where the sum is rounded to the nearest integer. To adjust the hue by −4°, write 0x69 to the hue adjust value register: −4 ⎛ ⎞ + 128 = 105d = 0 x69 ⎜ ⎟ 0 . 17578125 ⎝ ⎠ [0001110] into twos complement = [1110010]b = 0x72 Table 32. Brightness Control Values1 Setup Level in NTSC with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE Setup Level in NTSC without Pedestal 15 IRE 7.5 IRE 0 IRE –7.5 IRE Setup Level in PAL 15 IRE 7.5 IRE 0 IRE –7.5 IRE SD Brightness 0x1E 0x0F 0x00 0x71 where the sum is rounded to the nearest integer. 1 Values in the range of 0x3F to 0x44 might result in an invalid output signal. Rev. 0 | Page 51 of 92 ADV7324 SD Brightness Detect Double buffering can be activated on the following HD registers: HD Gamma Curve A, HD Gamma Curve B, and HD CGMS registers. [Subaddress 0x7A] The ADV7324 allows monitoring the brightness level of the incoming video data. Brightness detect is a read-only register. Double Buffering [Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2] Double buffering can be activated on the following SD registers: SD Gamma Curve A, SD Gamma Curve B, SD Y scale, SD U scale, SD V scale, SD brightness, SD closed captioning, and SD Macrovision (Bits 5 to 0). Double-buffered registers are updated once per field upon the falling edge of the Vsync signal. Double buffering improves the overall performance, because modifications to register settings will not be made during active video, but take effect upon the start of the active video. NTSC WITHOUT PEDESTAL +7.5 IRE 100 IRE 0 IRE NO SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED Figure 68. Examples of Brightness Control Values Rev. 0 | Page 52 of 92 05220-068 –7.5 IRE POSITIVE SETUP VALUE ADDED ADV7324 PROGRAMMABLE DAC GAIN CONTROL Table 33. DAC Gain Control DAC A, DAC B, and DAC C are controlled by Register 0A. Reg. 0x0A or 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 % Gain +7.5000% +7.3820% +7.3640% ... ... +0.0360% +0.0180% +0.0000% 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) 4.25 4.23 ... ... 4.018 4.013 4.008 −0.0180% −0.0360% ... ... −7.3640% −7.3820% −7.5000% DAC D, DAC E, and DAC F are controlled by Register 0B. The I2C control registers will adjust the output signal gain up or down from its absolute level. CASE A GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESSES 0x0A, 0x0B 700mV 300mV CASE B Note (I2C Reset Value, Nominal) NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESSES 0x0A, 0x0B GAMMA CORRECTION 700mV [Subaddresses 0x24 to 0x37 for HD, Subaddresses 0x66 to 0x79 for SD] 05220-069 300mV Figure 69. Programmable DAC Gain—Positive and Negative Gain In Case A, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal. In Case B, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal. The range of this feature is specified for ±7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC tune feature can change this output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%). The reset value of the vid_out_ctrl registers is 0x00; therefore, nominal DAC current is output. Table 33 is an example of how the output current of the DACs varies for a nominal 4.33 mA output current. Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit-wide registers. They are used to program Gamma Correction Curve A and Gamma Correction Curve B. HD Gamma Curve A is programmed at Address 0x24 to Address 0x2D, and HD Gamma Curve B is programmed at Address 0x2E to Address 0x37. SD Gamma Curve A is programmed at Address 0x66 to Address 0x6F, and SD Gamma Curve B is programmed at Address 0x70 to Address 0x79. Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function Signal OUT = (Signal IN )γ where γ = gamma power factor. Gamma correction is performed on the luma data only. The user may choose either of two curves: Curve A or Curve B. At any one time, only one of these curves can be used. The response of the curve is programmed at 10 predefined locations. By changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. If the curve has a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. Rev. 0 | Page 53 of 92 ADV7324 For lengths of 16 to 240 points, the gamma correction curve is calculated as follows: ⎡ x ⎤ yn = ⎢ (n −16) ⎥ γ × (240 − 16) + 16 ⎣ (240 − 16) ⎦ SIGNAL OUTPUT 200 0.5 150 100 SIGNAL INPUT 50 0 where: x(n − 16) = value for x along x-axis at points n. n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224. yn = value for y along the y-axis, which must be written into the gamma correction register. y24 = [(8/224)0.5 × 224] + 16 = 58 y32 = [(16/224)0.5 × 224] + 16 = 76 y48 = [(32/224)0.5 × 224] + 16 = 101 y64 = [(48/224)0.5 × 224] + 16 = 120 y80 = [(64/224)0.5 × 224] + 16 = 136 y96 = [(80/224)0.5 × 224] + 16 = 150 50 100 150 LOCATION 200 250 GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES 300 250 0.3 200 0.5 150 100 S L NA IG PU IN T 1.5 1.8 50 0 y128 = [(112/224)0.5 × 224] + 16 = 174 0 Figure 70. Signal Input (Ramp) and Signal Output for Gamma 0.5 GAMMA-CORRECTED AMPLITUDE For example, 05220-070 To program the gamma correction registers, calculate the seven values for y using the following formula: 250 05220-071 where: y = gamma corrected output. x = linear input signal. γ = gamma power factor. GAMMA-CORRECTED AMPLITUDE y = xγ GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT 300 0 50 100 150 LOCATION 200 250 Figure 71. Signal Input (Ramp) and Selectable Output Curves y160 = [(144/224)0.5 × 224] + 16 = 195 y192 = [(176/224)0.5 × 224] + 16 = 214 y224 = [(208/224)0.5 × 224] + 16 = 232 where the sum of each equation is rounded to the nearest integer. The gamma curves in Figure 70 and Figure 71 are only examples; any user-defined curve is acceptable in the range of 16 to 240. Rev. 0 | Page 54 of 92 ADV7324 The derivative of the incoming signal is compared to the three programmable threshold values: HD Adaptive Filter Threshold A, HD Adaptive Filter Threshold B, and HD Adaptive Filter Threshold C. The recommended threshold range is 16 to 235, but any value between 0 and 255 can be used. HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS [Subaddresses 0x20, 0x38 to 0x3D] There are three filter modes available on the ADV7324: a sharpness filter mode and two adaptive filter modes. The edges can then be attenuated with the settings in HD Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, HD Adaptive Filter Gain 3 registers, and HD sharpness filter gain register. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 72, the HD sharpness filter must be enabled, and the HD adaptive filter enable must be disabled. According to the settings of the HD adaptive filter mode control, there are two adaptive filter modes available: • Mode A is used when adaptive filter mode is set to 0. In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, and HD Adaptive Filter Gain 3 are applied when needed. The Gain A values are fixed and cannot be changed. • Mode B is used when adaptive filter mode is set to 1. In this mode, a cascade of Filter A and Filter B is used. Settings for Gain A and Gain B in the HD sharpness filter gain and HD Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, and HD Adaptive Filter Gain 3 become active when needed. The HD Adaptive Filter Threshold A, HD Adaptive Filter Threshold B, and HD Adaptive Filter Threshold C registers; the HD Adaptive Filter Gain 1, HD Adaptive Filter Gain 2, and HD Adaptive Filter Gain 3 registers; and the HD sharpness gain register are used in adaptive filter mode. To activate the adaptive filter control, the HD sharpness filter and the HD adaptive filter must be enabled. SHARPNESS AND ADAPTIVE FILTERS CONTROL BLOCK 1.5 1.4 1.4 1.3 1.3 1.2 1.2 MAGNITUDE INPUT SIGNAL: STEP MAGNITUDE 1.5 1.1 1.0 0.9 1.1 1.0 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain KA) FREQUENCY (MHz) FILTER B RESPONSE (Gain KB) 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 2 6 8 10 4 FREQUENCY (MHz) 12 FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH KA = 3 AND KB = 7 Figure 72. Sharpness and Adaptive Filters Control Block Rev. 0 | Page 55 of 92 05220-072 HD Adaptive Filter Mode MAGNITUDE RESPONSE (Linear Scale) To select one of the 256 individual responses, the corresponding gain values, which range from –8 to +7, for each filter must be programmed into the HD sharpness filter gain register at Address 0x20. ADV7324 HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings listed in Table 34 were used to achieve the results shown in Figure 73. Input data was generated by an external signal source. Table 34. Sharpness Control Address 0x00 0x01 0x02 0x10 0x11 0x20 0x20 0x20 0x20 0x20 0x20 Reference1 a b c d e f See Figure 73. d a R2 1 e b R4 R1 c 1 f R2 CH1 500mV REF A 500mV 4.00µs M 4.00µs 1 9.99978ms CH1 ALL FIELDS CH1 500mV REF A 500mV 4.00µs 1 M 4.00µs 9.99978ms Figure 73. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Values Rev. 0 | Page 56 of 92 CH1 ALL FIELDS 05220-073 1 Register Setting 0xFC 0x10 0x20 0x00 0x81 0x00 0x08 0x04 0x40 0x80 0x22 ADV7324 Adaptive Filter Control Application 05220-074 05220-076 Figure 74 and Figure 75 show how a typical signal is processed by the adaptive filter control block in Mode A. When changing the adaptive filter mode to Mode B [Address 0x15, Bit 6], the output shown in Figure 76 can be obtained from the input signal shown in Figure 74. Figure 76. Output Signal with Adaptive Filter Control (Mode B) Figure 74. Input Signal to Adaptive Filter Control SD DIGITAL NOISE REDUCTION [Subaddresses 0x63, 0x64, 0x65] 05220-075 DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute value of the filter output is compared to a programmable threshold value (DNR threshold control). There are two DNR modes available: DNR mode and DNR sharpness mode. Figure 75. Output Signal with Adaptive Filter Control (Mode A) The register settings in Table 35 were used to obtain the results shown in Figure 75, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source. Table 35. Register Settings for Figure 75 Address 0x00 0x01 0x02 0x10 0x11 0x15 0x20 0x38 0x39 0x3A 0x3B 0x3C 0x3D Register Setting 0xFC 0x38 0x20 0x00 0x81 0x80 0x00 0xAC 0x9A 0x88 0x28 0x3F 0x64 In DNR mode, if the absolute value of the filter output is less than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal will be subtracted from the original signal. Likewise, in DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise. If the level exceeds the threshold and is identified as a valid signal, a fraction of the signal (coring gain border, coring gain data) will be added to the original signal to boost high frequency components and sharpen the video image. In MPEG systems, it is common to process the video information in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels × 16 pixels for MPEG1 systems (block size control). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing. Rev. 0 | Page 57 of 92 ADV7324 In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal. DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER APPLY DATA CORING GAIN INPUT FILTER BLOCK OXXXXXXOOXXXXXXO FILTER OUTPUT < THRESHOLD? Y DATA INPUT APPLY BORDER CORING GAIN FILTER OUTPUT > THRESHOLD SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING 05220-078 DNR MODE DNR27 – DNR24 = 0x01 O X X X X X X O O X X X X X X O – + DNR OUT MAIN SIGNAL PATH DNR SHARPNESS MODE Figure 78. DNR Offset Control DNR THRESHOLD DNR CONTROL [Address 0x64, Bit 5 to Bit 0] BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value. GAIN NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER BORDER AREA INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD + + MAIN SIGNAL PATH DNR OUT 05220-077 Y DATA INPUT [Address 0x64, Bit 6] ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL FILTER OUTPUT > THRESHOLD? When this bit is set to Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz. 720 × 485 PIXELS (NTSC) Figure 77. DNR Block Diagram 2-PIXEL BORDER DATA CORING GAIN BORDER These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal. CORING GAIN DATA [Address 0x63, Bit 7 to Bit 4] These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal. 8 × 8 PIXEL BLOCK 8 × 8 PIXEL BLOCK 05220-079 [Address 0x63, Bit 3 to Bit 0] Figure 79. DNR Border Area BLOCK SIZE CONTROL [Address 0x64, Bit 7] This bit is used to select the size of the data blocks to be processed. Setting the block size control function to Logic 1 defines a 16-pixel × 16-pixel data block, and Logic 0 defines an 8-pixel × 8-pixel data block, where one pixel refers to two clock cycles at 27 MHz. DNR INPUT SELECT CONTROL [Address 0x65, Bit 2 to Bit 0] Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter will be DNR processed. Figure 80 shows the filter responses selectable with this control. Rev. 0 | Page 58 of 92 ADV7324 not noise. The overall effect is that the signal will be boosted (similar to using an extended SSAF filter). 1.0 FILTER D BLOCK OFFSET CONTROL MAGNITUDE 0.8 FILTER C [Address 0x65, Bit 7 to Bit 4] 0.6 0.4 Four bits are assigned to this control, which allows a maximum shift of 15 pixels in a data block. Consider the fixed coring gain positions. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. FILTER B 05220-080 0.2 FILTER A 0 0 1 2 3 4 FREQUENCY (Hz) 5 SD ACTIVE VIDEO EDGE 6 [Subaddress 0x42, Bit 7] Figure 80. DNR Input Select DNR MODE CONTROL [Address 0x65, Bit 4] This bit is used to select the DNR mode. Logic 0 selects DNR mode; Logic 1 selects DNR sharpness mode. When the active video edge feature is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8. All other active video passes through unprocessed. SAV/EAV STEP-EDGE CONTROL DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. The ADV7324 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. An algorithm monitors SAV and EAV and determines when the edges are rising or falling too fast. The result is reduced ringing at the start and end of active video for fast transitions. Subaddress 0x42, Bit 7 = 1, enables this feature. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED 100 IRE 87.5 IRE 0 IRE 12.5 IRE 0 IRE Figure 81. Example of Active Video Edge Functionality Rev. 0 | Page 59 of 92 05220-081 50 IRE ADV7324 VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 0 2 4 6 8 10 12 05220-082 0 Figure 82. Address 0x42, Bit 7 = 0 VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 –2 0 2 4 6 8 Figure 83. Address 0x42, Bit 7 = 1 Rev. 0 | Page 60 of 92 10 12 05220-083 0 ADV7324 HSYNC/VSYNC OUTPUT CONTROL The ADV7324 has the ability to accept either embedded time codes in the input data or external Hsync and Vsync signals on P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins. Table 36. Hsync Output Control1 HD/ED2 Slave Mode (0x10, Bit 2) x x HD/ED Sync Output Enable (0x02, Bit 7) 0 0 SD Sync Output Enable (0x02, Bit 6) 0 1 I2C_Hsync_gen_sel (0x14, Bit 1) x x Signal on S_HSYNC Pin Tristate Pipelined SD Hsync External Hsync & Vsync /Field Mode EAV/SAV Mode 1 x 0 External pipelined HD/ED Hsync 1 x 0 x 1 x 1 Pipelined HD/ED Hsync based on AV Code H bit Pipelined HD/ED Hsync based on horizontal counter Duration – See Appendix 5—SD Timing Modes As per Hsync timing Same as line blanking interval Same as embedded Hsync ______________________________ 1 2 In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video. ED = enhanced definition. Table 37. Vsync Output Control1 HD/ED2 Slave Mode (0x10, Bit 2) x x HD/ED Sync Output Enable (0x02, Bit 7) 0 0 SD Sync Output Enable (0x02, Bit 6) 0 1 I2C_Vsync_gen_sel (0x14, Bit 2) x x Video Standard x Interlaced External Hysnc & Vsync/Field Mode EAV/SAV Mode 1 x 0 x 1 x 0 All HD interlace standards EAV/SAV Mode 1 x 0 x 1 x 1 All HD/ED progressive standards All HD/ED standards except 525p x 1 x 1 1 2 525p Signal on S_VSYNC Pin Tristate Pipelined SD Vsync/ field External pipelined HD/ED Vsync or field signal External pipelined field signal based on AV Code F bit Pipelined Vsync based on AV Code V bit External pipelined HD/ED Vsync based on vertical counter External pipelined HD/ED Vsync based on vertical counter Duration See Appendix 5— SD Timing Modes As per external Vsync or field signal Field Vertical blanking interval Aligned with serration lines Vertical blanking interval In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video. ED = enhanced definition = progressive scan 525p or 625p. Rev. 0 | Page 61 of 92 ADV7324 BOARD DESIGN AND LAYOUT CIRCUIT FREQUENCY RESPONSE 0 0 16n MAGNITUDE (dB) –30 –5 The ADV7324 contains an on-board voltage reference. The ADV7324 can be used with an external VREF (AD1580). 14n –60 –10 GAIN (dB) The RSET resistors are connected between the RSET pins and AGND and are used to control the full-scale output current and, therefore, the DAC voltage output levels. For full-scale output, RSET must have a value of 3040 Ω. The RSET values should not be changed. RLOAD has a value of 150 Ω for half-scale output. 12n –15 PHASE (Degrees) 10n –20 –120 8n –25 –150 6n –30 VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER –90 –180 4n GROUP DELAY (Seconds) –210 2n –35 Output buffering on all six DACs is necessary to drive output devices, such as SD or HD monitors. Analog Devices, Inc., produces a range of suitable op amps for this application, e.g., the AD8061. More information on line-driver buffering circuits is given in the relevant op amps’ data sheets. –40 1M 10M FREQUENCY (Hz) –240 0 100M 05220-085 DAC TERMINATION AND LAYOUT CONSIDERATIONS Figure 85. Filter Plot for Output Filter for SD, 16× Oversampling DAC OUTPUT 3.3µH 3 An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7324 is connected to a device that requires this filtering. 22pF 300Ω BNC OUTPUT 300Ω 22pF 1 75Ω 4 05220-086 1.8kΩ 600Ω The filter specifications vary with the application. Figure 86. Example of Output Filter for PS, 8× Oversampling Table 38. External Filter Requirements DAC OUTPUT Oversampling 2× 16× 1× 8× 1× 2× Attenuation –50 dB @ (MHz) 20.5 209.5 14.5 203.5 44.25 118.5 2.2µH 3 300Ω 22pF 75Ω 300Ω BNC OUTPUT Figure 84. Example of Output Filter for SD, 16× Oversampling 05220-084 4 1.8kΩ 3 1 300Ω 4 75Ω 470nH 220nH 33pF 82pF 3 BNC OUTPUT 75Ω 1 4 500Ω 500Ω Figure 87. Example of Output Filter for HDTV, 2× Oversampling Table 39. Possible Output Rates from the ADV7324 Input Mode Address 0x01, Bit 6 to Bit 4 SD Only 1 600Ω DAC OUTPUT PS Only HDTV Only Rev. 0 | Page 62 of 92 PLL Address 0x00, Bit 1 Off On Off On Off On Output Rate (MHz) 27 (2×) 216 (16×) 27 (1×) 216 (8×) 74.25 (1×) 148.5 (2×) 05220-087 Application SD SD PS PS HDTV HDTV Cutoff Frequency (MHz) >6.5 >6.5 >12.5 >12.5 >30 >30 ADV7324 CIRCUIT FREQUENCY RESPONSE 0 20n 158 –6 18n 118 –12 16n 77.6 14n 37.6 GROUP DELAY (Seconds) 12n MAGNITUDE (dB) –30 –36 –42 –48 PHASE (Degrees) –54 –60 1M 10M 100M FREQUENCY (Hz) 0 10n –42.4 8n –82.4 6n –122 4n –162 2n –202 0 1G 05220-088 GAIN (dB) –18 –24 198 Figure 88. Filter Plot for Output Filter for PS, 8× Oversampling CIRCUIT FREQUENCY RESPONSE 0 MAGNITUDE (dB) 15n 240 12n The analog and digital power planes should be individually connected to the common power plane at a single point through a suitable filtering device, such as a ferrite bead. DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB’s ground plane. As well as minimizing reflections, short analog output traces reduce noise pickup from neighboring digital circuitry. 9n 0 –40 6n –120 3n PHASE (Degrees) –60 1M 10M 100M FREQUENCY (Hz) –240 0 1G To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible is left between the tracks of the individual DAC output pins. The addition of ground tracks between outputs is also recommended. Supply Decoupling 120 05220-089 GAIN (dB) 360 GROUP DELAY (Seconds) –30 –50 Each power plane should encompass a digital power plane and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, VREF circuitry. The digital power plane should contain all logic circuitry. 18n –10 –20 480 There should be separate analog and digital ground planes. Figure 89. Filter Plot for Output Filter for HDTV, 2× Oversampling PCB BOARD LAYOUT The ADV7324 is optimally designed for lowest noise performance of both radiated and conducted noise. To complement the excellent noise performance of the ADV7324, it is imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7324 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND, VDD and DGND, and VDD_IO and GND_IO pins should be kept as short as possible to minimized inductive ringing. It is recommended that a 4-layer, printed circuit board is used, with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Component placement should be carefully considered to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 10 nF and 0.1 µF ceramic capacitors. Each group of VAA, VDD, or VDD_IO pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. A 1 µF tantalum capacitor is recommended across the VAA supply in addition to 10 nF ceramic. See the circuit layout in Figure 90. Digital Signal Interconnect The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates, avoid long clock lines to the ADV7324 to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane, not the analog power plane. Analog Signal Interconnect Locate the ADV7324 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. Rev. 0 | Page 63 of 92 ADV7324 For optimum performance, each analog output should be source- and load-terminated, as shown in Figure 90. The termination resistors should be as close as possible to the ADV7324 to minimize reflections. For optimum performance, it is recommended that all decoupling and external components relating to the ADV7324 are located on the same side of the PCB and as close as possible to the ADV7324. Unused inputs should be tied to ground. POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP + VAA VAA 0.1µF VAA 10nF 1µF 10nF 0.1µF 0.1µF VDD VDD_IO 10, 56 5kΩ 45 36 COMP1, 2 19 I2C 41 VAA VAA VDD_IO 1 0.1µF 10nF 1.1kΩ VDD VDD_IO VREF 46 ADV7324 RECOMMENDED EXTERNAL AD1580 FOR OPTIMUM PERFORMANCE 100nF S0–S9 DAC A 44 150Ω 50 S_HSYNC 49 S_VSYNC DAC B 43 150Ω 48 S_BLANK DAC C 42 C0–C9 UNUSED INPUTS SHOULD BE GROUNDED 150Ω Y0–Y9 DAC D 39 63 CLKIN_B DAC E 38 150Ω 150Ω 23 P_HSYNC VAA 24 P_VSYNC DAC F 37 150Ω 25 P_BLANK 4.7kΩ 33 RESET 4.7µF + SCLK 22 32 CLKIN_A VAA 820pF SDA 21 34 EXT_LF VDD_IO 100Ω 5kΩ 3040Ω 64 AGND DGND RSET1 47 I2C BUS VDD_IO RSET2 35 GND_ IO 5kΩ 100Ω ALSB 20 680Ω 3.9nF VDD_IO 5kΩ SELECTION HERE DETERMINES DEVICE ADDRESS 3040Ω 40 ALL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SIDE OF THE PCB AS THE ADV7324 AND AS CLOSE AS POSSIBLE TO THE ADV7324. Figure 90. ADV7324 Circuit Layout Rev. 0 | Page 64 of 92 05220-090 11, 57 ADV7324 APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS SD CGMS Data Registers 2 to 0 Data Registers 2 to 0 [Subaddresses 0x21, 0x22, 0x23] [Subaddresses 0x59, 0x5A, 0x5B] 525p Using the vertical blanking interval 525p system, 525p CGMS conforms to the CGMS-A EIA-J CPR1204-1 (March 1998) transfer method of video identification information and to the IEC61880 (1998) 525p/60 video system’s analog interface for the video and accompanying data. When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 41. The 525p CGMS data registers are at Address 0x21, Address 0x22, and Address 0x23. The ADV7324 supports the copy generation management system (CGMS), conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of the even fields. Bit C/W05 and Bit C/W06 control whether CGMS data is output on odd or even fields. CGMS data can only be transmitted when the ADV7324 is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 93. 720p System CGMS data is applied to Line 24 of the luminance vertical blanking interval. 625p The 625p CGMS conforms to the IEC62375 (2004) 625p/50 video system’s analog interface for the video and accompanying data using the vertical blanking interval. 1080i System When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS data is inserted on Line 43. The 625p CGMS data registers are at Address 0x22 and Address 0x23. CGMS FUNCTIONALITY HD CGMS [Address 0x12, Bit 6] The ADV7324 supports the copy generation management system (CGMS) in HDTV mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. The HD CGMS data registers are found at Address 0x021, Address 0x22, and Address 0x23. CGMS data is applied to Line 19 and Line 582 of the luminance vertical blanking interval. If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC [Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to C14, which compose the 6-bit CRC check sequence, are automatically calculated on the ADV7324. This calculation is based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC [Address 0x59, Bit 4] and PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0, all 20 bits (C0 to C19) are output directly from the CGMS registers (CRC must be manually calculated by the user). Rev. 0 | Page 65 of 92 ADV7324 CRC SEQUENCE +700mV REF 70% ± 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV 21.2µs ± 0.22µs 22T 5.8µs ± 0.15µs 6T 05220-091 T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns Figure 91. PS 525p CGMS Waveform (Line 41) R = RUN-IN S = START CODE PEAK WHITE 500mV ± 25mV R S C0 C1 LSB SYNC LEVEL C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 MSB 05220-092 13.7µs 5.5µs ± 0.125µs Figure 92. PS 625p CGMS-A Waveform (Line 43) +100 IRE CRC SEQUENCE REF +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 –40 IRE 49.1µs ± 0.5µs 11.2µs 2.235µs ± 20ns Figure 93. SD CGMS Waveform Rev. 0 | Page 66 of 92 05220-093 0 IRE ADV7324 CRC SEQUENCE +700mV REF 70% ± 10% C0 C1 0mV C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T ± 30ns 17.2µs ± 160ns 22T T = 1/(fH × 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H 4T 3.128µs ± 90ns 05220-094 –300mV C2 Figure 94. HDTV 720p CGMS Waveform CRC SEQUENCE +700mV REF 70% ± 10% C0 0mV C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T ± 30ns 4T 4.15µs ± 60ns 22.84µs ± 210ns 22T T = 1/(fH × 2200/77) = 1.038µs fH = HORIZONTAL SCAN FREQUENCY 1H Figure 95. HDTV 1080i CGMS Waveform Rev. 0 | Page 67 of 92 05220-095 –300mV C1 ADV7324 APPENDIX 2—SD WIDE-SCREEN SIGNALING WSS data is preceded by a run-in sequence and a start code (see Figure 96). If SD WSS [Address 0x59, Bit 7] is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s after the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 0x61, Bit 7. [Subaddresses 0x59, 0x5A, 0x5B] The ADV7324 supports wide screen signaling (WSS) conforming to the ETS 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each bit is shown in Table 40. The 500mV RUN-IN START SEQUENCE CODE W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 ACTIVE VIDEO 11.0µs 05220-096 38.4µs 42.5µs Figure 96. WSS Waveform Diagram Rev. 0 | Page 68 of 92 ADV7324 Table 40. Function of WSS Bits Bit Bit 0 to Bit 2 Bit 3 B0 0 1 0 1 0 1 0 1 1 B4 0 1 B5 0 1 B6 0 1 B7 B8 0 1 B9 0 1 0 1 B11 0 1 B12 B13 B1 0 0 1 1 0 0 1 1 1 B2 0 0 0 0 1 1 1 1 1 B3 1 0 0 1 0 1 1 0 0 Description Aspect ratio/format/position Odd parity check of Bit 0 to Bit 2 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 16:9 Camera mode Film mode Standard coding Motion adaptive color plus No helper Modulated helper Reserved No teletext subtitles Teletext subtitles B10 0 0 1 1 No open subtitles Subtitles in active image area Subtitles out of active image area Reserved No surround sound information Surround sound mode Reserved Reserved Rev. 0 | Page 69 of 92 Format Full format Letterbox Letterbox Letterbox Letterbox Letterbox Full format N/A Position N/A Center Top Center Top Center Center N/A ADV7324 APPENDIX 3—SD CLOSED CAPTIONING FCC Code of Federal Regulations (CFR) 47, section 15.119, and EIA608 describe the closed captioning information for Line 21 and Line 284. [Subaddresses 0x51 to 0x54] The ADV7324 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. The ADV7324 uses a single-buffering method. This means that the closed captioning buffer is only 1 byte deep; therefore, there will be no frame delay in outputting the closed captioning data, unlike other 2-byte-deep buffering systems. The data must be loaded one line before it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (2 bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes, on Line 21, or a TV will not recognize them. If there is a message such as “Hello World” that has an odd number of characters, it is important to add a blank character at the end so that the end-of-caption, 2-byte control code lands in the same field. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency- and phase-locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers [Address 0x53 to Address 0x54]. The ADV7324 also supports the extended closed captioning operation, which is active during even fields and encoded on Line 284. The data for this operation is stored in the SD closed captioning registers [Address 0x51 to Address 0x52]. All clock run-in signals and timing to support closed captioning on Line 21 and Line 284 are generated automatically by the ADV7324. All pixels inputs are ignored during Line 21 and Line 284 if closed captioning is enabled. 10.5 ± 0.25µs 12.91µs 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T 50 IRE P A R I T Y D0–D6 BYTE 0 D0–D6 P A R I T Y BYTE 1 40 IRE 10.003µs 27.382µs 33.764µs Figure 97. Closed Captioning Waveform (NTSC) Rev. 0 | Page 70 of 92 05220-097 REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE ADV7324 APPENDIX 4—TEST PATTERNS The ADV7324 can generate SD and HD test patterns. T 05220-098 2 CH2 200mV M 10.0µs A CH2 T 30.6000µs 05220-101 T 2 1.20V CH2 100mV Figure 98. NTSC Color Bars M 10.0µs CH2 1.82600ms T EVEN Figure 101. PAL Black Bar (–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV) T 05220-099 2 CH2 200mV M 10.0µs A CH2 30.6000µs T 05220-102 T 2 1.21V CH2 200mV M 4.0µs CH2 1.82944ms T EVEN Figure 102. 525p Hatch Pattern Figure 99. PAL Color Bars 2 CH2 100mV M 10.0µs CH2 1.82380ms T 05220-103 T 05220-100 T 2 EVEN CH2 200mV Figure 100. NTSC Black Bar (–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV,18 mV, 23 mV) M 4.0µs CH2 1.84208ms T Figure 103. 625p Hatch Pattern Rev. 0 | Page 71 of 92 EVEN ADV7324 2 CH2 200mV M 4.0µs CH2 1.82872ms T 05220-106 T 05220-104 T 2 EVEN CH2 100mV M 4.0µs CH2 1.82936ms T EVEN Figure 106. 525p Black Bar (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV) Figure 104. 525p Field Pattern 05220-105 2 CH2 200mV M 4.0µs CH2 1.84176ms T 05220-107 T T 2 CH2 100mV EVEN Figure 105. 625p Field Pattern M 4.0µs CH2 1.84176ms T EVEN Figure 107. 625p Black Bar (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV) Rev. 0 | Page 72 of 92 ADV7324 The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed with the appropriate values for NTSC. All other registers are set as normal/default. Table 41. NTSC Test Pattern Register Writes Subaddress 0x00 0x40 0x42 0x44 0x4A Register Setting 0xFC 0x10 0x40 0x40 (internal test pattern on) 0x08 For PAL CVBS output on DAC A, the same settings are used, except Subaddress 0x40 is programmed to 0x11 and the FSC registers are programmed as shown in Table 42. The register settings in Table 43 are used to generate a 525p hatch pattern on DAC D, E, and F. All other registers are set as normal/default. Table 43. 525p Test Pattern Register Writes Subaddress 0x00 0x01 0x10 0x11 0x16 0x17 0x18 For 625p hatch pattern on DAC D, the same register settings are used, except Subaddress 0x10 = 0x18. Table 42. PAL FSC Register Writes Subaddress 0x4C 0x4D 0x4E 0x4F Description FSC0 FSC1 FSC2 FSC3 Register Setting 0xFC 0x10 0x00 0x05 0xA0 0x80 0x80 Register Setting 0xCB 0x8A 0x09 0x2A Note that when programming the FSC registers, the user must write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full FSC value is only accepted after the FSC3 write is complete. Rev. 0 | Page 73 of 92 ADV7324 APPENDIX 5—SD TIMING MODES [Subaddress 0x4A] MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 0) The ADV7324 is controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. If Pin S_VSYNC, Pin S_HSYNC, and Pin S_BLANK are not used, they should be tied high during this mode. Blank output is available. ANALOG VIDEO EAV CODE 4 CLOCK 0 F F A A A 0 F F B B B ANCILLARY DATA (HANC) 4 CLOCK 268 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) 1440 CLOCK 4 CLOCK 4 CLOCK PAL SYSTEM (625 LINES/50Hz) C C 8 1 8 1 F 0 0 X C Y C Y C Y r Y b b 0 0 0 0 F 0 0 Y b r 280 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE END OF ACTIVE VIDEO LINE Figure 108. SD Slave Mode 0 Rev. 0 | Page 74 of 92 05220-108 INPUT PIXELS SAV CODE C F 0 0 X 8 1 8 1 Y Y r F 0 0 Y 0 0 0 0 ADV7324 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 1) The ADV7324 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H, V, and F bits are output on S_HSYNC, S_BLANK, and S_VSYNC, respectively. DISPLAY DISPLAY VERTICAL BLANK 522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 H V EVEN FIELD F ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 H F ODD FIELD 05220-109 V EVEN FIELD Figure 109. SD Master Mode 0 (NTSC) Rev. 0 | Page 75 of 92 ADV7324 DISPLAY DISPLAY VERTICAL BLANK 622 623 624 625 1 2 3 4 5 6 21 7 22 23 H V EVEN FIELD F ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 310 311 312 313 314 315 316 317 318 319 320 334 335 336 H ODD FIELD F 05220-110 V EVEN FIELD Figure 110. SD Master Mode 0 (PAL) ANALOG VIDEO H 05220-111 F V Figure 111. SD Master Mode 0 (Data Transitions) Rev. 0 | Page 76 of 92 ADV7324 MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 0) In this mode, the ADV7324 accepts horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7324 automatically blanks all normally blank lines as per CCIR-624. HSYNC, BLANK, and FIELD are input on S_HSYNC, S_BLANK, and S_VSYNC, respectively. DISPLAY DISPLAY 522 523 VERTICAL BLANK 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY 260 261 DISPLAY VERTICAL BLANK 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 HSYNC FIELD ODD FIELD 05220-112 BLANK EVEN FIELD Figure 112. SD Slave Mode 1 (NTSC) Rev. 0 | Page 77 of 92 ADV7324 MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 1) In this mode, the ADV7324 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7324 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC, BLANK, and FIELD are output on S_HSYNC, S_BLANK, and S_VSYNC, respectively. DISPLAY DISPLAY 622 623 VERTICAL BLANK 624 625 1 3 2 4 5 6 7 21 22 23 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 HSYNC ODD FIELD FIELD 05220-113 BLANK EVEN FIELD Figure 113. SD Slave Mode 1 (PAL) HSYNC FIELD PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 BLANK Cb Y PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 114. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave Rev. 0 | Page 78 of 92 Cr Y 05220-114 PIXEL DATA ADV7324 MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7324 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, ADV7324 automatically blanks all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are input on S_HSYNC, S_BLANK, and S_VSYNC, respectively. DISPLAY 522 DISPLAY VERTICAL BLANK 523 524 525 1 4 3 2 5 7 6 8 10 9 20 11 21 22 HSYNC BLANK VSYNC ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 283 274 285 284 HSYNC VSYNC 05220-115 BLANK EVEN FIELD ODD FIELD Figure 115. SD Slave Mode 2 (NTSC) DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 HSYNC BLANK VSYNC EVEN FIELD ODD FIELD DISPLAY 309 310 DISPLAY VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 HSYNC VSYNC ODD FIELD EVEN FIELD Figure 116. SD Slave Mode 2 (PAL) Rev. 0 | Page 79 of 92 05220-116 BLANK ADV7324 MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7324 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7324 automatically blanks all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are output on S_HSYNC, S_BLANK, and S_VSYNC, respectively. HSYNC VSYNC PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 BLANK PIXEL DATA Y Cr Y 05220-117 Cb PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 117. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave HSYNC VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 PAL = 12 × CLOCK/2 NTSC = 16 × CLOCK/2 BLANK Cb Y Cr PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 118. SD Timing Mode 2 Odd-to-Even Field Transition Rev. 0 | Page 80 of 92 Y Cb 05220-118 PIXEL DATA ADV7324 MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 1 0 OR X X X X X 1 1 1) In this mode, the ADV7324 accepts or generates horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7324 automatically blanks all normally blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are output in master mode and input in slave mode on S_VSYNC, S_BLANK, and S_VSYNC, respectively. DISPLAY DISPLAY 522 523 VERTICAL BLANK 524 525 1 2 4 3 5 6 8 7 9 10 20 11 21 22 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY 260 DISPLAY VERTICAL BLANK 261 262 263 264 265 266 267 268 269 270 271 272 273 283 274 285 284 HSYNC FIELD ODD FIELD 05220-119 BLANK EVEN FIELD Figure 119. SD Timing Mode 3 (NTSC) DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 HSYNC BLANK FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 HSYNC FIELD EVEN FIELD 05220-120 BLANK ODD FIELD Figure 120. SD Timing Mode 3 (PAL) Rev. 0 | Page 81 of 92 ADV7324 APPENDIX 6—HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 P_VSYNC P_HSYNC DISPLAY VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 05220-121 P_VSYNC P_HSYNC Figure 121. 1080i HSYNC and VSYNC Input Timing Rev. 0 | Page 82 of 92 ADV7324 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb OUTPUT LEVELS INPUT CODE EIA-770.2 STANDARD FOR Y INPUT CODE OUTPUT VOLTAGE 940 EIA-770.3 STANDARD FOR Y OUTPUT VOLTAGE 940 700mV 700mV 64 64 300mV 300mV EIA-770.3 STANDARD FOR Pr/Pb EIA-770.2 STANDARD FOR Pr/Pb OUTPUT VOLTAGE OUTPUT VOLTAGE 960 960 600mV 512 700mV 64 64 Figure 122. EIA 770.2 Standard Output Signals (525p/625p) INPUT CODE EIA-770.1 STANDARD FOR Y 05220-124 700mV 05220-122 512 Figure 124. EIA 770.3 Standard Output Signals (1080i/720p) OUTPUT VOLTAGE 782mV INPUT CODE Y OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE 1023 940 700mV 714mV 64 64 300mV 286mV INPUT CODE OUTPUT VOLTAGE OUTPUT VOLTAGE 1023 960 700mV 700mV 64 64 05220-123 512 Pr/Pb OUTPUT LEVELS FOR FULL INPUT SELECTION 300mV Figure 123. EIA 770.1 Standard Output Signals (525p/625p) Figure 125. Output Levels for Full Input Selection Rev. 0 | Page 83 of 92 05220-125 EIA-770.1 STANDARD FOR Pr/Pb ADV7324 RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars 700mV 525mV 700mV 300mV 300mV 700mV 525mV 300mV 700mV 525mV 700mV 525mV 05220-126 525mV 300mV Figure 126. PS RGB Output Levels 700mV Figure 128. SD RGB Output Levels—RGB Sync Disabled 525mV 700mV 300mV 300mV 0mV 0mV 700mV 525mV 300mV 300mV 0mV 0mV 700mV 525mV 300mV 525mV 700mV 525mV 700mV 525mV 05220-127 300mV 0mV 05220-129 300mV 05220-128 300mV 700mV 0mV 525mV Figure 129. SD RGB Output Levels—RGB Sync Enabled Figure 127. PS RGB Output Levels—RGB Sync Enabled Rev. 0 | Page 84 of 92 05220-132 05220-135 700mV Figure 132. Pr Levels (NTSC) Rev. 0 | Page 85 of 92 Figure 135. Y Levels (PAL) Figure 134. Y Levels (NTSC) 05220-134 RED MAGENTA GREEN CYAN BLACK 300mV BLACK 700mV BLUE 700mV BLUE RED MAGENTA GREEN Figure 131. Pb Levels (PAL) YELLOW WHITE Figure 130. Pb Levels (NTSC) CYAN 05220-131 BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE 05220-133 05220-130 700mV YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE ADV7324 YPrPb LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV Figure 133. Pr Levels (PAL) 700mV 300mV ADV7324 VOLTS VOLTS IRE:FLT 0.6 100 0.4 0.5 50 0.2 0 F1 L76 10 0 –0.2 20 30 40 MICROSECONDS 50 60 05220-139 –50 0 05220-136 0 L608 30 40 50 60 20 MICROSECONDS PRECISION MODE OFF NOISE REDUCTION: 0.00dB SYNCHRONOUS SOUND-IN-SYNC OFF APL = 39.1% FRAMES SELECTED 1, 2, 3, 4 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72µs 0 PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC = A 525 LINE NTSC FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V AT 6.72µs 10 Figure 136. NTSC Color Bars 75% Figure 139. PAL Color Bars 75% VOLTS VOLTS IRE:FLT 0.4 50 0.5 0.2 0 0 0 –0.2 –50 –0.4 0 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL NEEDS SYNC SOURCE SYNCHRONOUS SYNC = B 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72µs 05220-140 –0.5 05220-137 F1 L76 L575 10 20 30 40 50 60 MICROSECONDS APL NEEDS SYNC SOURCE NO BUNCH SIGNAL 625 LINE PAL NO FILTERING PRECISION MODE OFF SLOW CLAMP TO 0.00 AT 6.72µs SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 Figure 137. NTSC Chroma Figure 140. PAL Chroma VOLTS VOLTS IRE:FLT 0.6 0.5 0.4 50 0 0.2 0 F2 L238 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 15.05dB PRECISION MODE OFF APL = 44.3% SYNCHRONOUS SYNC = SOURCE 525 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00 AT 6.72µs 05220-141 –0.2 05220-138 0 0 L575 70 30 40 50 60 MICROSECONDS NO BUNCH SIGNAL APL NEEDS SYNC SOURCE PRECISION MODE OFF 625 LINE PAL NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF SLOW CLAMP TO 0.00 AT 6.72µs FRAMES SELECTED 1 0 10 20 Figure 141. PAL Luma Figure 138. NTSC Luma Rev. 0 | Page 86 of 92 ADV7324 APPENDIX 8—VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 272T 4T EAV CODE F F INPUT PIXELS ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T 1920T SAV CODE DIGITAL ACTIVE LINE F 0 0 F C V b Y C r F 0 0 H* 0 0 F 0 0 V H* 4 CLOCK SAMPLE NUMBER 2112 C Y r 4 CLOCK 0 2199 2116 2156 44 188 192 2111 05220-142 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV: LINE 21–560; 584–1123: V = 0 FOR A FRAME RATE OF 30Hz: 40 SAMPLES FOR A FRAME RATE OF 25Hz: 480 SAMPLES Figure 142. EAV/SAV Input Data Timing Diagram (SMPTE 274M) SMPTE 293M ANALOG WAVEFORM ANCILLARY DATA (OPTIONAL) EAV CODE F F 0 0 V F 0 0 H* INPUT PIXELS F 0 0 F V F 0 0 H* 4 CLOCK 719 C C b Y r C Y r Y 4 CLOCK 723 736 0HDATUM 799 853 857 0 719 DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43–525 = 200H SAV: LINE 1–42 = 2AC EAV: LINE 43–525 = 274H EAV: LINE 1–42 = 2D8 05220-143 SAMPLE NUMBER DIGITAL ACTIVE LINE SAV CODE Figure 143. EAV/SAV Input Data Timing Diagram (SMPTE 293M) Rev. 0 | Page 87 of 92 ADV7324 522 523 ACTIVE VIDEO VERTICAL BLANK 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 05220-144 ACTIVE VIDEO 44 Figure 144. SMPTE 293M (525p) 622 623 ACTIVE VIDEO VERTICAL BLANK 624 625 1 2 5 4 6 7 8 9 10 11 12 13 43 44 45 05220-145 ACTIVE VIDEO Figure 145. ITU-R BT.1358 (625p) DISPLAY 747 748 749 1 750 4 3 2 6 5 7 8 25 26 27 744 745 05220-146 VERTICAL BLANKING INTERVAL Figure 146. SMPTE 296M (720p) DISPLAY VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 DISPLAY VERTICAL BLANKING INTERVAL 561 562 563 564 565 566 567 568 569 Figure 147. SMPTE 274M (1080i) Rev. 0 | Page 88 of 92 570 583 584 585 1123 05220-147 FIELD 2 ADV7324 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.00 BSC SQ 1.60 MAX 64 49 1 48 PIN 1 10.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BCD Figure 148. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model ADV7324KSTZ1 EVAL-ADV7324EB 1 Temperature Range 0°C to 70°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Z = Pb-free part. Rev. 0 | Page 89 of 92 Package Option ST-64-2 ADV7324 NOTES Rev. 0 | Page 90 of 92 ADV7324 NOTES Rev. 0 | Page 91 of 92 ADV7324 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05220–0–11/04(0) Rev. 0 | Page 92 of 92