256, S11866-64-02

Photodiode arrays with amplifiers
S11865-64/-128/-256
S11866-64-02/-128-02
Photodiode arrays combined with signal
processing IC
The S11865/S11866 series are Si photodiode arrays combined with a signal processing IC chip. X-ray tolerance has been improved compared to the previous products (S8865/S8866 series). The signal processing IC chip is formed by CMOS process
and incorporates a timing generator, shift register, charge amplifier array, clamp circuit and hold circuit, making the external
circuit configuration simple. A long, narrow image sensor can also be configured by arranging multiple arrays in a row. For Xray detection applications, types with phosphor sheet affixed on the photosensitive area are also available.
As the dedicated driver circuit, the C9118 series (sold separately) is provided (this circuit does not support the S11865-256).
Features
Applications
Data rate: 1 MHz max.
Long and narrow line sensors
Element pitch: 5 types available
S11865-64: 0.8 mm pitch × 64 ch
S11865-128: 0.4 mm pitch × 128 ch
S11865-256: 0.2 mm pitch × 256 ch
S11866-64-02: 1.6 mm pitch × 64 ch
S11866-128-02: 0.8 mm pitch × 128 ch
Line sensors for X-ray detection
5 V power supply operation
Simultaneous integration by using a charge amplifier array
Sequential readout with a shift register
Low dark current due to zero-bias photodiode operation
Integrated clamp circuit allows low noise and wide dynamic range
Integrated timing generator allows operation at two
different pulse timings
Types with phosphor sheet affixed on the photosensitive
area are available for X-ray detection
(S11865-64G/-128G/-256G, S11866-64G-02/-128G-02)
Structure
Parameter
Symbol*1
Element pitch
P
Element width
W
Element height
H
Number of elements
Effective photosensitive area length
Board material
-
S11865-64
0.8
0.7
0.8
64
51.2
S11865-128
0.4
0.3
0.6
128
51.2
S11865-256
0.2
0.1
0.3
256
51.2
Glass epoxy
S11866-64-02 S11866-128-02
1.6
0.8
1.5
0.7
1.6
0.8
64
128
102.4
102.4
Unit
mm
mm
mm
mm
-
*1: Refer to following figure.
H
Enlarged drawing of photosensitive area
Photodiode
W
P
KMPDC0072EA
www.hamamatsu.com
1
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Absolute maximum ratings (Ta=25 °C, unless otherwise noted)
Parameter
Supply voltage
Reference voltage
Photodiode voltage
Gain selection terminal voltage
Master/slave selection voltage
Clock pulse voltage
Reset pulse voltage
External start pulse voltage
Operating temperature*2
Storage temperature*2
Symbol
Vdd
Vref
Vpd
Vgain
Vms
V(CLK)
V(RESET)
V(EXTSP)
Topr
Tstg
Value
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-0.3 to +6
-5 to +60
-10 to +70
Unit
V
V
V
V
V
V
V
V
°C
°C
*2: No condensation
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
Recommended terminal voltage (Ta=25 °C)
Parameter
Supply voltage
Reference voltage
Photodiode voltage
High gain
Low gain
High level*3
Master/slave selection voltage
Low level*4
High level
Clock pulse voltage
Low level
High level
Reset pulse voltage
Low level
High level
External start pulse voltage
Low level
Gain selection terminal voltage
Symbol
Vdd
Vref
Vpd
Vgain
Vms
V(CLK)
V(RESET)
V(EXTSP)
Min.
4.75
4
Vdd - 0.25
0
Vdd - 0.25
0
3.3
0
3.3
0
Vdd - 0.25
0
Typ.
5
4.5
Vref
Vdd
Vdd
Vdd
Vdd
Vdd
-
Max.
5.25
4.6
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Vdd + 0.25
0.4
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
Max.
4000
14678
7568
3844
-
Unit
kHz
*3: Parallel
*4: Serial at 2nd or later stages
Electrical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V]
Parameter
Clock pulse frequency*5
S11865-64, S11866-64-02
Line rate*6
S11865-128, S11866-128-02
S11865-256
Output impedance
S11865-64, S11866-64-02
S11865-128, S11866-128-02
Current consumption
S11865-256
High gain
Charge amp feedback capacitance
Low gain
Symbol
f(CLK)
LR
Zo
I
Cf
Min.
40
-
Typ.
3
16
30
60
0.5
1
lines/s
kΩ
mA
pF
*5: Video data rate is 1/4 of clock pulse frequency f(CLK).
*6: The values depend on the clock pulse frequency.
2
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Electrical and optical characteristics [Ta=25 °C, Vdd=5 V, V(CLK)=V(RESET)=5 V, Vgain=5 V (High gain), 0 V (Low gain)]
S11865-64/-128/-256
Parameter
Spectral response range
Peak sensitivity wavelength
High gain
Dark output voltage*7
Low gain
Saturation output voltage
High gain
Saturation exposure*8
Low gain
High gain
Photosensitivity
Low gain
Photoresponse nonuniformity*9
High gain
Noise*10
Low gain
Output offset voltage*11
Symbol
λ
λp
Vd
Vsat
Esat
S
PRNU
N
Vo
S11865-64
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
0.8
1.0
1.6
2.0
3520
4400
1760
2200
±10
1.3
2.0
0.7
1.1
Vref
Min.
S11865-128
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
2.4
3.0
4.8
6.0
1200
1500
600
750
±10
1.0
1.5
0.6
0.9
Vref
Min.
S11865-256
Typ.
Max.
200 to 1000
720
0.01
0.2
0.005
0.1
3.0
3.5
15
19
30
37.5
200
250
100
125
±10
0.8
1.2
0.5
0.75
Vref
-
Min.
Unit
nm
nm
mV
V
mlx · s
V/lx · s
%
mV rms
V
S11866-64-02/-128-02
Parameter
Symbol
S11866-64-02
Typ.
200 to 1000
720
0.01
0.005
3
3.5
0.2
0.4
14400
18000
7200
9000
2.0
1.1
Vref
Min.
Max.
S11866-128-02
Typ.
200 to 1000
720
0.01
0.005
3
3.5
0.8
1.6
3520
4400
1760
2200
1.3
0.7
Vref
Min.
Max.
Unit
Spectral response range
λ
nm
Peak sensitivity wavelength
λp
nm
High gain
0.2
0.2
Dark output voltage*7
Vd
mV
Low gain
0.1
0.1
Saturation output voltage
Vsat
V
High
gain
0.25
1.0
Esat
mlx · s
Saturation exposure*8
Low gain
0.5
2.0
High gain
Photosensitivity
S
V/lx · s
Low gain
9
PRNU
±10
±10
%
Photoresponse nonuniformity*
High
gain
3.0
2.0
Noise*10
N
mV rms
Low gain
1.7
1.1
Vo
V
Output offset voltage*11
*7: Integration time Ts=1 ms
*8: Measured with a 2856 K tungsten lamp.
*9: Photoresponse nonuniformity (PRNU) is the output nonuniformity that occurs when the photosensitive area is uniformly illuminated
by light which is approx. 50% of the saturation level. PRNU is defined as follows:
PRNU = ∆X/X × 100 [%]
X: average output of all elements, ∆X: difference between X and the maximum or minimum output, whichever is larger.
*10: Measured with a video data rate of 50 kHz and Ts=1 ms in dark state.
*11: Video output is negative-going output with respect to the output offset voltage.
3
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Output waveform of one element
Dark state
Saturation
output voltage
Vsat=3.5 V typ.
1 V/div.
Output offset
voltage
Vref=4.5 V typ.
1 V typ.
Saturation state
GND
Trigger
10 V/div.
GND
CLK
GND
100 ns/div.
Spectral response (typical example)
Silicone resin coating
(Ta=25 °C)
0.5
0.4
Photosensitivity (A/W)
0.4
Photosensitivity (A/W)
(Ta=25 °C)
0.5
0.3
0.2
0.1
0.3
0.2
0.1
0
200 300 400 500 600 700 800 900 1000 1100 1200
0
200 300 400 500 600 700 800 900 1000 1100 1200
Wavelength (nm)
Wavelength (nm)
KMPDB0220EB
KMPDB0421EA
When the fluorescent screen is attached, the spectral response
becomes smooth due to the effects of the adhesive resin.
4
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Output offset voltage vs. ambient temperature
(measurement example)
Dark output voltage vs. ambient temperature
(typical example)
4.505
(Ts=1 ms)
1
4.504
Dark output voltage (mV)
Output offset voltage (V)
4.503
4.502
4.501
4.500
4.499
4.498
0.1
0.01
4.497
4.496
4.495
0.001
0
10
20
30
40
50
60
Ambient temperature (°C)
0
10
20
30
40
50
60
Ambient temperature (°C)
KMPDB0288EA
KMPDB0289EB
5
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Block diagram
S11865-64/-128, S11866-64-02/-128-02
RESET
1
CLK
2
EXTSP
Vms
Vdd
GND
4
5
6
7
Timing generator
3
Trig
Shift register
8
EOS
9
Video
Vref
10
Hold circuit
Vgain
11
Charge amp array
Vpd
12
1
2
3
4
5
N-1
N
Photodiode array
KMPDC0153EA
S11865-256
RESET 2, 15
EXTSP
Vms
Vdd
GND
5, 18
6, 19
7, 20
8, 21
4, 17 Trig
Timing generator
CLK 3, 16
Shift register
Charge amp array
Vgain 12, 25
1, 13
14, 26
10, 23 Video
Hold circuit
Vref 11, 24
Vpd
9, 22 EOS
1
2
3
4
5
255
256
Photodiode array
KMPDC0506EA
6
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Timing chart
1 2 3
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3
CLK
tpw(RESET1)
RESET
tpw(RESET2)
8 clocks
8 clocks
Integration time
Video output period
1
Video
2
3
n-1
n
Trig
EOS
tf(CLK)
tr(CLK)
t2
tpw(CLK)
t1
tpw(RESET1)
tpw(RESET2)
KMPD
tf(RESET)
tr(RESET)
KMPDC0289EC
Parameter
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
Symbol
tpw(CLK)
tr(CLK), tf(CLK)
tpw(RESET1)
tpw(RESET2)
tr(RESET), tf(RESET)
t1
t2
Min.
250
0
21
20
0
-20
-20
Typ.
20
20
0
0
Max.
25000
30
30
20
20
Unit
ns
ns
CLK
CLK
ns
ns
ns
1. The internal timing circuit starts operation at the falling edge of CLK immediately after a RESET pulse goes Low.
2. When the falling edge of each CLK is counted as “1 clock”, the video signal of the 1st channel appears between “18.5 clocks and
20.5 clocks”. Subsequent video signals appear every 4 clocks.
3. The trigger pulse for the 1st channel rises at a timing of 19.5 clocks and then rises every 4 clocks. The rising edge of each trigger
pulse is the recommended timing for data acquisition.
4. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the rise
of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the RESET
pulse.
After the RESET pulse next changes from High to Low, signals integrated within this period are sequentially read out as time-series
signals by the shift register operation. The rise and fall of a RESET pulse must be synchronized with the rise of a CLK pulse, but the
rise of a RESET pulse must be set outside the video output period. One cycle of RESET pulses cannot be set shorter than the time
equal to “16.5 + 4 × N (number of elements)” clocks.
5. The video signal after an EOS signal output becomes a high impedance state, and the video output will be indefinite.
7
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Dimensional outlines (unit: mm, tolerance unless otherwise noted: ±0.2)
S11865-64/-128
+0.2
51.2 -0
1.27
(× 12) ɸ0.76
1.6
5.0
12
Photosensitive area
12.0
2.54
5.6
3.0
8.0*
40.0
1.6
(× 4) ɸ2.2
Photodiode 1 ch
Direction of scan
* Distance from board bottom to photosensitive area center
Board: G10 glass epoxy
Connector: PRECI-DIP DURTAL 800-10-012-20-001101
KMPDA0164EF
S11865-256
+0.2
51.2-0
(× 26) 0.64 × 0.64
34.02
1
25
2
26
CMOS1
CMOS2
(× 4) ϕ2.2
Photosensitive
area
2.28
6.9 6.0
2.54
6.6
17.0
2.54
40.0
Photodiode 1 ch
3.0
40.0 ± 0.15
10.0
P2.54 × 12 = 30.48
8.0*
25.0 ± 0.1
1
5.0
Signal processing IC chip
2.95
P2.54 × 11 = 27.94
1.6
Signal processing IC chip
Direction of scan
* Length from board bottom to photosensitive area center
Board: G10 glass epoxy
Connector: JAE (Japan Aviation Electronics lndustry, Limited)
PS-26PE-D4LT1-PN1
KMPDA0191ED
8
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
S11866-64-02/-128-02
+0.3
-0
1.27
P2.54 × 11 = 27.94
1.6
(× 12) ɸ0.76
5.0
1
2.95
Signal processing
IC chip
5.0
102.4
12
11.2
3.0
A*
12.0
25.0 ± 0.1
2.54
80.0
Photodiode 1 ch
Photosensitive area
1.6
(4 ×) ɸ2.2
Direction of scan
Type no.
A
S11866-64-02 8.2
S11866-128-02 8.0
* Distance from board bottom to photosensitive area center
Board: G10 glass epoxy
Connector: PRECI-DIP DURTAL 800-10-012-20-001101
KMPDA0291EA
Pin connections
S11865-64/-128, S11866-64-02/-128-02
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
Symbol
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Name
Reset pulse
Clock pulse
Trigger pulse
External start pulse
Master/slave selection supply voltage
Supply voltage
Ground
End of scan
Video output
Reference voltage
Gain selection terminal voltage
Photodiode voltage
Note
Pulse input
Pulse input
Positive-going pulse output
Pulse input
Voltage input
Voltage input
Negative-going pulse output
Negative-going output with respect to Vref
Voltage input
Voltage input
Voltage input
S11865-256
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
13
CMOS1
Vpd
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Pin no.
14
15
16
17
18
19
20
21
22
23
24
25
26
CMOS2
Vpd
RESET
CLK
Trig
EXTSP
Vms
Vdd
GND
EOS
Video
Vref
Vgain
Vpd
Name
Photodiode voltage
Reset pulse
Clock pulse
Trigger pulse
External start pulse
Master/slave selection voltage
Supply voltage
Ground
End of scan
Video output
Reference voltage
Gain selection voltage
Photodiode voltage
Note
Voltage input
Pulse input
Pulse input
Positive-going pulse output
Pulse input
Voltage input
Voltage input
Negative-going pulse output
Negative-going output from Vref
Voltage input
Voltage input
Voltage input
9
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Gain selection terminal voltage setting
Vdd: High gain (Cf=0.5 pF) GND: Low gain (Cf=1 pF)
Setting for each readout method
S11865-64/-128, S11866-64-02/-128-02
Set to A in the table below in most cases.
To serially read out signals from two or more sensors linearly connected, set the 1st sensor to A and the 2nd or later sensors to B.
The CLK and RESET pulses should be shared with each sensor and the video output terminal of each sensor connected together.
Connection example (parallel readout)
12
Vpd
11
Vgain
10
Vref
9
Video
8
EOS
7
GND
6
Vdd
5
Vms
4
EXTSP
Trig
3
Trig
CLK
2
CLK
RESET
1
RESET
Vgain
+4.5 V
EOS
10 µF
0.1 µF
+5 V
-
Video
+
High impedance amplifier
KMPDC0288EB
Setting
Readout method
A
All stages of parallel readout, serial readout at 1st sensor
B
Serial readout at 2nd and later sensors
Vms
Vdd
GND
EXTSP
Vdd
Preceding sensor EOS should be input
10
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
S11865-256
Signals of channels 1 through 126 are output from CMOS1, while signals of channels 129 through 256 are output from CMOS2. The following two readout methods are available.
(1) Serial readout method
CMOS1 and CMOS2 are connected in serial and the signals of channels 1 through 256 are sequentially read out from one output line.
Set CMOS1 as in “A” in the table below, and set CMOS2 as in “B”. CMOS1 and CMOS2 should be connected to the same CLK and RESET
lines, and their video output terminals to one line.
(2) Parallel readout method
128 channel signals are output in parallel respectively from the output lines of CMOS1 and CMOS2. Set both CMOS1 and CMOS2 as in “A”
in the table below.
Connection examples
· Serial readout method
· Parallel readout method
CMOS1
CMOS1
1 Vpd
1 Vpd
RESET
2 RESET (1)
RESET
2 RESET (1)
CLK
3 CLK (1)
CLK
3 CLK (1)
4 Trig (1)
Trig (1)
4 Trig (1)
5 EXTSP (1)
5 EXTSP (1)
6 Vms (1)
6 Vms (1)
Vdd
7 Vdd
Vdd
7 Vdd
GND
8 GND
GND
8 GND
9 EOS (1)
EOS (1)
10 Video (1)
Video (1)
10 Video (1)
Vref
11 Vref
Vref
11 Vref
Vgain
12 Vgain
Vgain
12 Vgain
13 Vpd
13 Vpd
CMOS2
14 Vpd
Trig
OR Logic IC
74HC32
9 EOS (1)
CMOS2
15 RESET (2)
14 Vpd
16 CLK (2)
15 RESET (2)
17 Trig (2)
18 EXTSP (2)
16 CLK (2)
Trig (2)
17 Trig (2)
19 Vms (2)
18 EXTSP (2)
20 Vdd
19 Vms (2)
21 GND
20 Vdd
EOS
22 EOS (2)
Video
23 Video (2)
EOS (2)
22 EOS (2)
24 Vref
Video (2)
23 Video (2)
21 GND
25 Vgain
24 Vref
26 Vpd
25 Vgain
KMPDC0222EA
26 Vpd
KMPDC0223EB
Setting
A
B
Vms
Vdd
GND
EXTSP
Vdd
Preceding sensor EOS should be input
11
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Readout circuit
Check that pulse signals meet the required pulse conditions before supplying them to the input terminals.
Video output should be amplified by an operational amplifier that is connected close to the sensor.
Precantions
(1) The signal processing IC chip is protected against static electricity. However, in order to prevent possible damage to the IC chip,
take electrostatic countermeasures such as grounding yourself, as well as workbench and tools. Also protect the IC chip from surge
voltages from peripheral equipment.
(2) Gold wires for wire bonding are very thin, so they easily break if subjected to mechanical stress. The signal processing IC chip and
wire bonding section are covered with resin for protection. However, never touch these portions. Excessive force, if applied, may
break the wires or cause malfunction.
Blow air to remove dust or debris if it gets on the protective resin. Never wash them with solvent.
Signals may not be obtained if dust or debris is left or a scratch is made on the protective resin, or the signal processing IC chip or
photodiode array chip is nicked.
(3) The photodiode array characteristics may deteriorate when operated at high humidity, so put it in a hermetically sealed enclosure or case.
When installing the photodiode array on a board, be careful not to cause the board to warp.
Related information
www.hamamatsu.com/sp/ssd/doc_en.html
Precautions
∙ Notice
∙ Image sensors/Precautions
12
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Driver circuit C9118 series (sold separately)
The CMOS driver circuit is designed for S11865/S11866 series photodiode arrays with amplifier. The C9118 series operates a photodiode
by just inputting two signals (M-CLK and M-RESET) and a signal +5 V supply. The C9118 is intended for single use or parallel connections, while the C9118-01 is suitable for cascade connections.
Features
Single power supply (+5 V) operation
Operation with two input signals (M-CLK and M-RESET)
Compact: 46 × 56 × 5.2 t mm
Block diagram
+Vcc
S11865/
S11866 series
+Vcc
SW1
CN1
CLK
RESET
Trig
EOS
EXTSP
Vms
Vg
Vdd
GND
Video
Vref
Vp
1: TOP
2: END
1
+Vcc
CN2
M-CLK
M-RESET
TRIGGER
L-EOS
IN-START
GAIN
+5 V
GND
VIDEO
GND
2
Controller
+Vcc
+Vp
VR1
SW2
CN3
+Vcc
+
+Vp
+
+
+
+Vcc
REF
M-CLK
M-RESET
TRIGGER
L-EOS
EXTSP2
GAIN
+5 V
GND
VIDEO
GND
C9118-01 only
KACCC0643EA
13
Photodiode arrays with amplifiers
S11865-64/-128/-256, S11866-64-02/-128-02
Connection examples
Single or parallel readout example (C9118)
Cascade readout example (C9118-01)
Simultaneous integration/output
(effective for high-speed processing)
Simultaneous integration/serial output
(Simplifies external processing circuit)
S11865/
S11866 series
S11865/
S11866 series
C9118
CN2
C9118-01
External
controller
CN2
External
controller
CN3
Scan
direction
S11865/
S11866 series
S11865/
S11866 series
C9118
CN2
Accessory
cable
C9118-01
External
controller
CN2
Scan
direction
CN3
S11865/
S11866 series
C9118
CN2
S11865/
S11866 series
External
controller
C9118-01
CN2
Scan
direction
Scan
direction
CN3
KACCC0644EA
KACCC0645EA
Information described in this material is current as of November, 2014.
Product specifications are subject to change without prior notice due to improvements or other reasons. This document has been carefully prepared and the
information contained is believed to be accurate. In rare cases, however, there may be inaccuracies such as text errors. Before using these products, always
contact us for the delivery specification sheet to check the latest specifications.
Type numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
The product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, Bridgewater, N.J. 08807, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Torshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.r.l.: Strada della Moia, 1 int. 6, 20020 Arese (Milano), Italy, Telephone: (39) 02-93581733, Fax: (39) 02-93581741
China: Hamamatsu Photonics (China) Co., Ltd.: B1201, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866
Cat. No. KMPD1134E04 Nov. 2014 DN
14