CYPRESS CY2SSTU877BVXI-43

CY2SSTU877
PRELIMINARY
1.8V, 500-MHz, 10-Output JEDEC-Compliant
Zero Delay Buffer
Features
distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential
pair of feedback clock outputs (FBOUT, FBOUT#).
• Operating frequency: 125 MHz to 500 MHz
The input clocks (CK, CK#), the feedback clocks (FBIN,
FBIN#), the LVCMOS (OE, OS), and the analog power input
(AVDD) control the clock outputs.
• Supports DDRII SDRAM
• 1 to 10 differential clock buffer (SSTL_18)
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): 40 ps
• Very low output-to-output skew: 40 ps
• Auto power-down feature when input is low
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-8)
• 52-ball BGA
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter
zero delay buffer designed to distribute differential clocks in
high-speed applications.
This phase-locked loop (PLL) clock buffer is designed for a
VDD of 1.8V, an AVDD of 1.8V and SSTL18 differential data
input and output levels. This device is a zero delay buffer that
The PLL in the CY2SSTU877 clock driver uses the input
clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to
provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able
to track Spread Spectrum Clocking (SSC) for reduced EMI.
When AVDD is grounded, the PLL is turned off and bypassed
for test purposes. When both clock signals (CK, CK#) are logic
low, the device will enter a low-power mode. An input logic
detection circuit on the differential inputs, independent from
the input buffers, will detect the logic low level and perform a
low-power state where all outputs, the feedback, and the PLL
are OFF. When the inputs transition from both being logic low
to being differential signals, the PLL will be turned back on, the
inputs and outputs will be enabled and the PLL will obtain
phase lock between the feedback clock pair (FBIN, FBIN#)
and the input clock pair (CK, CK#) within the specified stabilization time tL.
Pin Configuration
Block Diagram
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
CLKT1
CLKT0
CLKC0
CLKC5
CLKT5
CLKT6
CLKC1
GND
GND
GND
GND
CLKC6
CLKC2
GND
NB
NB
GND
CLKC7
CLKT2
VDDQ
VDDQ
VDDQ
OS
CLKT7
CLK_INT
VDDQ
NB
NB
VDDQ
FB_INT
CLK_INC
VDDQ
NB
NB
OE
FB_INC
AGND
VDDQ
VDDQ
VDDQ
VDDQ
FB_OUTC
FB_OUTT
AVDD
GND
NB
NB
GND
CLKT3
GND
GND
GND
GND
CLKT8
CLKC3
CLKC4
CLKT4
CLKT9
CLKC9
CLKC8
52 BGA
Cypress Semiconductor Corporation
Document #: 38-07575 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 27, 2006
CY2SSTU877
PRELIMINARY
Pin Description
Pin No.
Name
Description
G1
AGND
Ground for 1.8V analog supply
H1
AVDD
1.8V analog supply
E1, F1
CLK_INT, CLK_INC Differential clock input with a (10K–100KΩ) pull-down resistor
E6, F6
FB_INT, FB_INC
Feedback differential clock input
H6, G6
FB_OUTT,
FB_OUTC
Feedback differential clock output
B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, GND
J5
Ground
F5
OE
Output enable (ASYNC) for CLKT[0:9] and CLKC [0:9]
D5
OS
Output Select (Tied to GND or VDDQ)
D2, D3, D4, E2, E5, F2, G2, G3, G4, G5
VDDQ
1.8V supply
A2, A1, D1, J1, K3, A5, A6, D6, J6, K4,
CLKT [0:9]
Buffered output of input clock, CLK
A3, B1, C1, K1, K2, A4, B6, C6, K6, K5
CLKC [0:9]
Buffered output of input clock, CLK
Table 1. Function Table
Inputs
Outputs
AVDD
OE
OS
GND
H
X
CLK_INT CLK_INC
L
GND
H
X
H
L
GND
L
H
L
H
GND
L
L
H
L
Lz,CLKT7
Active
VDD
L
H
L
H
Lz
VDD
L
L
H
L
Lz,CLKT7
Active
VDD
H
X
L
H
L
H
VDD
H
X
H
L
H
L
VDD
X
X
L
L
Lz
Lz
X
X
X
H
H
H
CLKT
CLKC
L
H
FB_OUTT FB_OUTC
L
H
L
H
L
Bypassed/Off
Lz
Lz
L
H
Bypassed/Off
Lz,CLKC7
Active
H
L
Bypassed/Off
Lz
L
H
On
Lz,CLKC7
Active
H
L
On
L
H
On
H
L
On
Lz
Lz
Off
H
PLL
Bypassed/Off
Reserved
Recommended Operating Conditions
Parameter
Description
TA (Com.)
Ambient Operating Temp
VDD, AVDD
Operating Voltage
Document #: 38-07575 Rev. *E
Condition
Min.
Max.
Unit
0
70
°C
1.7
1.9
V
Page 2 of 9
CY2SSTU877
PRELIMINARY
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VIN
Input Voltage Range
–0.5
VDDQ + 0.5
V
VOUT
Output Voltage Range
–0.5
VDDQ + 0.5
V
TS
Storage Temperature
–65
150
°C
VCC, AVCC
Supply Voltage Range
–0.5
2.5
V
IIK
Input Clamp Current
–50
50
mA
IOK
Output Clamp Current
–50
50
mA
IO
Continuous Output Current
–50
50
mA
Continuous Current through VDD/GND
–100
100
mA
DC Electrical Specifications
Parameter
Description
VIK
Input Clamping Voltage
VOD
Output Differential Voltage
VOX
Output Differential Crossing Voltage
VIX
Input Differential Crossing Voltage
Conditions
Min.
II = –18 mA
Max.
Unit
–1.2
V
0.5
V
VDDQ/2 – 0.08
VDDQ/2 + 0.08
V
(VDDQ/2) – 0.15
(VDDQ/2) + 0.15
V
VID DC
Input Differential Voltage (DC Values)
0.3
VDDQ + 0.4
V
VID AC
Input Differential Voltage (AC Values)
0.6
VDDQ + 0.4
V
VIL
Input Low Voltage
(OE, OS, CLK_INT,
CLK_INC)
0.35 * VDDQ
V
VIH
Input High Voltage
(OE, OS, CLK_INT,
CLK_INC)
VOL
Output Low Voltage
IOL = 100 µA
0.1
V
IOL = 9 mA
0.6
V
VOH
Output High Voltage
IOH = –100 µA
IOH = –9 mA
0.65 * VDDQ
V
VDDQ – 0.2
V
1.1
V
IIH
Input High Current
VIN = VDDQ or GND
–250
250
µA
IIL
Input Low Current
VIN = VDDQor GND
–10
10
µA
IODL
Output disabled low current
VODL= 100 mV
OE = GND
100
IDDLD
Static Supply current
IDDQ + IADD, CLK_INT =
CLK_INC = GND
500
µA
CL = 0 @ 270 MHz
300
mA
–9
mA
9
mA
3
pF
IDD
Dynamic Supply Current
IOH
Output High Current
IOL
Output Low Current
CIN
Input Capacitance
COUT
CIN(DELTA)
Document #: 38-07575 Rev. *E
(Input Capacitance of
CLK_INT, CLK_INC,
FB_INT, FB_INC) VI =
VDDQ or GND
2
Ci(delta) (CLK_INT,
CLK_INC, FB_INT,
FB_INC) VI = VDDQ or
GND
–0.25
µA
pF
0.25
pF
Page 3 of 9
CY2SSTU877
PRELIMINARY
AC Timing Specifications
Parameter
FCLK
[1,2]
Description
Conditions
Min.
Max.
Unit
Clock Frequency (Max)
Room temp and nominal VDDQ
125
500
MHz
Clock Frequency (Application)
Room temp and nominal VDDQ
250
500
MHz
TDC
Input Duty Cycle
40
60
%
TODC
Output Duty Cycle
48
52
%
TLOCK
PLL Lock Time
–
15
µs
TOENB
Output Enable Time
OE to any CLKT/ CLKC[0:9]
–
8
ns
TODIS
Output Disable Time
OE to any CLKT/ CLKC[0:9]
–
8
ns
Tjitt (cc)
Cycle-to-cycle jitter
–40
40
ps
Tjit (Period)
Period jitter
–30
30
ps
Tjit (H-Period)
Half Period Cycle-to-cycle jitter
Above 270 MHz
–45
45
ps
Below 270 MHz
–60
60
ps
Average 1000 cycles
–50
50
ps
–40
40
ps
T(φ)
Static Phase Offset
T(φ)DYN
Dynamic Phase Offset
TSKEW
Clock Skew
–
40
ps
SLR(O)
Output Slew Rate
CLKT/ CLKC[0:9], FB_OUTT,
FB_OUTC
1.5
4
V/ns
SLR(I)
Input Slew Rate
CLK_INT, CLK_INC, FB_INT,
FB_INC
1
4
V/ns
OE
0.5
V/ns
Figure 1. Test Loads for Timing Measurement
Notes:
1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for
low speed system debug).
2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.
Document #: 38-07575 Rev. *E
Page 4 of 9
CY2SSTU877
PRELIMINARY
-
Figure 2. Cycle-to-cycle Jitter
tjit(per)
-
Figure 3. Period Jitter
-
Figure 4. Half Period Jitter
Document #: 38-07575 Rev. *E
Page 5 of 9
PRELIMINARY
CY2SSTU877
Figure 5. Static Phase Offset (Differential Probes)
Figure 6. Dynamic Phase Offset (Differential Probes)
Figure 7. Output Skew
Document #: 38-07575 Rev. *E
Page 6 of 9
CY2SSTU877
PRELIMINARY
CLKT/CLKC
CLKT
CLKC
Figure 8. Output Enable and Disable Times
CLKT
CLKC
Figure 9. Input/Output Slew Rates
CARD
VIA
R1
Bead
AVDD
VDDQ
1Ω
4.7 pF
1206
0.1 µF
0603
2200 pF
0603
PLL
GND
AGND
CARD
VIA
Figure 10. AVDD Filtering[3,4,5]
Ordering Information
Part Number
Package Type
Product Flow
Lead-free and ROHS Compliant
CY2SSTU877BVXC-32
52-pin VFBGA for DDR400
Commercial, 0° to 70°C
CY2SSTU877BVXC-32T
52-pin VFBGA for DDR400 – Tape& Reel Commercial, 0° to 70°C
CY2SSTU877BVXI-32
52-pin VFBGA for DDR400
CY2SSTU877BVXI-32T
52-pin VFBGA for DDR400 – Tape& Reel Industrial, –40° to 85°C
CY2SSTU877BVXC-43
52-pin VFBGA for DDR533
Industrial, –40° to 85°C
Commercial, 0° to 70°C
CY2SSTU877BVXC-43T
52-pin VFBGA for DDR533 – Tape& Reel Commercial, 0° to 70°C
CY2SSTU877BVXI-43
52-pin VFBGA for DDR533
CY2SSTU877BVXI-43T
52-pin VFBGA for DDR533 – Tape& Reel Industrial, –40° to 85°C
Industrial, –40° to 85°C
Notes:
3. Place the 2200-pF capacitor close to the PLL.
4. Use a wide trace for the PLL analog power and ground. Connect PLL & Caps to AGND trace & connect trace to one GND via (farthest from PLL).
5. Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.9 ohm DC max, 600 [email protected] MHz).
Document #: 38-07575 Rev. *E
Page 7 of 9
CY2SSTU877
PRELIMINARY
Package Drawing
52 VFBGA 4.5 × 7.0 × 1.0 MM BV52A
TOP VIEW
BOTTOM VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
Ø0.30±0.05(52X)
A1 CORNER
1
2
3
4
5
6
6
3
2
1
B
C
C
0.65
A
B
E
F
F
G
2.925
G
D
E
5.85
7.00±0.10
D
7.00±0.10
4
5
A
H
H
J
J
K
K
1.625
A
A
B
4.50±0.10
0.65
3.25
DIMENSION IN MM
REFERENCE JEDEC MO-225
SEATING PLANE
C
1.00 MAX
0.26 MAX.
4.50±0.10
0.15 C
0.21±0.05
0.55 MAX.
0.25 C
B
0.15(4X)
51-85192-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07575 Rev. *E
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2SSTU877
PRELIMINARY
Document History Page
Document Title:CY2SSTU877 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Document Number: 38-07575
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
129198
08/22/03
RGL
New Data Sheet
*A
204389
See ECN
RGL
Added more Information. Deleted 4 rows from the bottom of the Pin
description.
*B
310414
See ECN
RGL
Changed Advance Info. to Preliminary status
Added Lead-free devices
*C
324113
See ECN
RGL
Data sheet re-write
*D
404547
See ECN
RGL
Added speed bins to part number
*E
424024
See ECN
RGL
Swap pins 6G and 6H
Document #: 38-07575 Rev. *E
Page 9 of 9