Data Sheet for CPC5903 (Rev 2)

2
CPC5903
Optically Isolated I C Bus Repeater
INTEGRATED CIRCUITS DIVISION
Features
Description
• Bidirectionally Buffers I2C SDA Signal
• Extends and Isolates I2C Interfaces
• Standard-mode and Fast-mode I2C
Side B Fast-mode Compatible VDDB > 4.5V
• Operates on 2.7V to 5.5V
• Voltage Level Translation
• Slew-Limited Drivers Reduce EMI
• Powerdown to Hi-Z Does Not Load I2C
• 3750Vrms Galvanic Isolation
• Single 8-pin Surface-Mount Package
The CPC5903 is a dual, optically isolated, logic-bus
repeater. It isolates two open-drain logic signals while
providing 3750Vrms of galvanic isolation. When the
two sides are powered by different supply voltages, it
also functions as a logic level translator for levels as
low as 2.7V or as high as 5.5V. Because the CPC5903
provides an isolated bidirectional buffer for the I2C
data signal and a unidirectional buffer for the I2C clock
signal, it is best suited for applications where clock
stretching is not required. This configuration also
requires the I2C bus master to be on the Side A bus.
Applications
•
•
•
•
•
Unlike transformer or capacitive isolators, optical
isolation passes DC signals and does not require
continuous clocking to ensure the proper state is
maintained. The CPC5903 always returns the buffered
signals to their proper state after transient
interruptions on either side.
Isolated Control and Signal Monitoring
Power-over-Ethernet
Power Supply High Side Interface
I2C Bus Length Extenders
I2C Logic Level Translation
Approvals
Ordering Information
• UL 1577 Certified Component: File E76270
• EN/IEC 60950 Certified Component:
TUV Certificate: B 11 10 49410 007
e3
Pb
Part
Description
CPC5903G
8-Pin DIP (50 / Tube)
CPC5903GS
8-Pin Surface Mount (50 / Tube)
CPC5903GSTR
8-Pin Surface Mount (1000 / Reel)
Figure 1. CPC5903 Functional Block Diagram
VDDA
IA
VDDB
VDDA
1
VDDB
8
B
LED
B
VDDB
GNDA
2
7
OB
6
GNDB
A
VDDB
VDDA
LED
A
3
IOA
VDDB
D
Q
B
CLR
VDDA
VDDB
LED
VDDA
4
VDDA
B
5
IOB
A
DS-CPC5903-R02
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1
CPC5903
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Side A to Side B Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 IOB to IOA Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
3
4
4
5
6
6
2. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Fast-mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Logic Input Thresholds and Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Pull-Up Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Pulse Propagation, Stretching and Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Power Supply Decoupling and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Design Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Side A Pull-Up Resistors: RPUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Side B Pull-Up Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.1 OB Pull-Up resistor: RPU-OB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2.2 IOB Pull-Up Resistor: RPUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Moisture Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1 CPC5903G 8-Pin DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2 CPC5903GS 8-Pin Surface Mount Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3 CPC5903GSTR Tape & Reel Information for Surface Mount Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
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R02
CPC5903
INTEGRATED CIRCUITS DIVISION
1 Specifications
1.1 Package Pinout
1
2
3
4
1.2 Pin Description
8
7
6
5
Pin#
Name
Description
1
2
3
4
5
6
7
8
IA
GNDA
Input Unidirectional Buffer - Side A
IOA
VDDA
Bidirectional Input/Output - Side A
IOB
GNDB
Bidirectional Input/Output - Side B
OB
VDDB
Output Unidirectional Buffer - Side B
Supply Return - Side A
Supply Voltage - Side A
Supply Return - Side B
Supply Voltage - Side B
1.3 Absolute Maximum Ratings
Electrical absolute maximum ratings are at 25°C.
Voltages with respect to local ground: GNDA or GNDB.
Parameter
Supply Voltage A
Supply Voltage B
Input Voltage
Power Dissipation 1
Isolation Voltage, Side A to Side B
60 Seconds
2 Seconds
Operating Temperature
Operating Relative Humidity
Storage Temperature
1
Symbol
Min
Max
Units
VDDA
VDDB
-0.5
+6.5
V
-0.5
+6.5
V
VIOx, VIA
-0.3
VDDx + 0.3
V
PTOT
-
800
mW
3750
-
4500
-
TA
-40
+85
°C
RH
TSTG
5
85
%
-50
+125
°C
Vrms
Derate total power by 7.5mW / °C above 25°C.
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device.
Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not
implied.
1.4 ESD Rating
ESD Rating (Human Body Model)
4000V
1.5 Thermal Characteristics
Parameter
Thermal Resistance, Junction to Ambient
R02
Conditions
Symbol
Typ
Units
Free Air
RJA
114
°C/W
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CPC5903
INTEGRATED CIRCUITS DIVISION
1.6 General Conditions
Unless otherwise specified, minimum and maximum values are guaranteed by production testing requirements or by
design. Typical values are characteristic of the device at 25°C, and are the result of engineering evaluations. They are
provided for information purposes only, and are not part of the manufacturing testing requirements.
Specifications cover the operating temperature range TA = -40°C to +85°C.
1.7 Electrical Specifications
Parameter
Conditions
Symbol
Min
Typ
Max
Units
IIOA=6mA
VDDA
2.7
-
5.5
V
-
7.5
-
-
7.85
-
-
8.1
10
-
0.01
10
Side A
Supply Voltage
Supply Current
VDDA=3.3V, IIOA=0
IDDA
IIOA=6mA
VDDA=5.5V, IIOA=0, TA=25°C
Leakage Current
VIA=VIOA=VDDA
ILEAKA
CIN
Input Capacitance
Falling Input Low Threshold
VDDA=2.7V to 5.5V
VILA
Rising Input High Threshold
VDDA=2.7V to 5.5V
VIHA
Hysteresis
VDDA=2.7V to 5.5V
HYSTA
Output Drive
VDDA=2.7V, IIOA=3mA
VOLA
VDDA=2.7V, IIOA=6mA
Output Temperature Coefficient
Side B
Supply Voltage
Supply Current
-
-
0.15VDD
-
-
0.21
0.35
-
0.42
0.7
IOB=IIOB=3mA
VDDB
2.7
-
5.5
V
-
8.4
-
-
8.75
-
-
9.3
11.3
-
0.01
10
VDDB=3.3V, IOB=IIOB=0
IDDB
VIA=VIOA=VDDB
ILEAKB
CIN
VDDB = 2.7V
VDDB=2.7V to 5.5V
mA
A
pF
3
0.48
0.54
0.6
VILB
0.2VDDB
- 60mV
0.2VDDB
0.2VDDB
+ 60mV
V
HYSTB
-
0.01VDDB
-
V
0.63
0.72
0.81
-
0.62
-
-
0.23VDDB
0.23VDDB
+ 190mV
VDDB=2.7V, IOB=IIOB=3mA
VOLB
VDDB4.5V, IOB=IIOB=6mA
4
V
mV/°C
VDDB = 2.7V to 5.5V,
IOB=IIOB=3mA
Output Temperature Coefficient
V
-
VDDB=2.7V, IOB=IIOB=0.1mA
Self-Drive Margin
V
+1.2
VDDB = 2.7V to 5.5V
Output Drive
-
-
Input Capacitance
Hysteresis
0.7VDD
TCA
VDDB=5.5V, IOB=IIOB=0, TA=25°C
Falling Input Low Threshold
-
VDDA=2.7V to 5.5V, IIOA=6mA
IOB=IIOB=3mA
Leakage Current
A
pF
3
0.3VDD
mA
V
0.3VDDB
VDDB=2.7V, IIOB=0.1mA
(Self_Out-In) VDIFFERENCE
VOLB - VILB
25
-
-
mV
VDDB=2.7V to 5.5V, IOB=IIOB=3mA
TCB
-
+0.4
-
mV/°C
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R02
CPC5903
INTEGRATED CIRCUITS DIVISION
1.8 Switching Specifications
Parameter
I2C Clock Frequency
Conditions
IIOA=6mA,
CLOADA=400pF
Propagation Delay A to B 1
Falling
Rising
Propagation Delay IOB to IOA
Falling
Rising
Propagation Delay IOB to IOA to IOB
Rising
1
VDDA=VDDB=3.3V,
RPUA=475,
RPUB=825
CI_A=CI_B=20pF
Symbol
Min
Typ
Max
Units
fMAX
500
-
-
kHz
tPHL_AB
-
60
135
ns
tPLH_AB
-
122
270
tPHL_BA
-
90
170
tPLH_BA
-
165
275
tPLH_BAB
-
290
480
IOB=IIOB=3mA, CLOADB=200pF
IOB=IIOB=6mA, CLOADB=400pF,
VDDB  4.5V
0.5VDDA to 0.5VDDB
0.2VDDB to 0.5VDDA
0.2VDDB to 0.5VDDB
ns
ns
Refer to “Side A to Side B Switching Waveforms” on page 6
2 Refer to “IOB to IOA Switching Waveforms” on page 6
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5
CPC5903
INTEGRATED CIRCUITS DIVISION
1.9 Side A to Side B Switching Waveforms
4V
IA, IOA In
VDDA=3.3V
tPHL_AB
3V
2V
0.5 • VDDA = 1.65V
1V
0V
0ns
4V
500ns
1000ns
OB, IOB Out
VDDB=3.3V
3V
tPLH_AB
2V
0.5 • VDDB = 1.65V
1V
0V
0ns
500ns
1000ns
1.10 IOB to IOA Switching Waveforms
4V
IOB In
VDDB=3.3V
3V
tPLH_BAB
2V
tPHL_BA
0.5 • VDDB = 1.65V
1V
tPLH_BA
0V
0ns
4V
500ns
0.2 • VDDB = 0.66V
1000ns
IOA Out
VDDA=3.3V
3V
2V
0.5 • VDDA = 1.65V
1V
0V
0ns
6
500ns
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1000ns
R02
CPC5903
INTEGRATED CIRCUITS DIVISION
2 Typical Performance Characteristics
1.8
1.4
1.6
VIL (V)
1.0
VOLB _3mA
0.8
VOLB _0.1mA
0.6
0.4
0.2
0.2
3.5
4.0
4.5
VDD (V)
5.0
5.5
0.45
Side A Output (V)
0.35
0.30
0.25
0.20
0.15
0.10
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
6.0
2.5
Output Voltage (VOLA) Side A
vs. Temperature
(ISINKA=6mA)
0.55
Margin 0.1mA
Margin 3mA
Margin 6mA
0.40
2.5
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
VDDA=2.7V
VDDA=3.3V
VDDA=5.5V
0.45
0.40
0.35
Output Voltage vs. Temperature
Side B
(VDDB=4.5V, ISINKB=6mA)
1.40
Propagation Delay (ns)
1.35
1.30
1.25
VOLB
1.20
1.15
-20
0
20
40
60
Temperature (ºC)
80
0
20
40
60
Temperature (ºC)
80
0.90
VOLB
0.85
0.80
100
80
tPHL_AB
60
-20
0
20
40
60
Temperature (ºC)
80
100
Propagation Delay B to A
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
190
120
170
tPLH_BA
150
130
110
tPHL_BA
90
70
-60
-40
-20
0
20
40
60
Temperature (ºC)
80
100
-60
-40
-20
0
20
40
60
Temperature (ºC)
80
100
Propagation Delay Low to High
B to A to B
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
340
Propagation Delay (ns)
6.0
0.3VDDB
-40
Propagation Delay A to B
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
tPLH_AB
100
5.5
0.95
100
40
1.10
5.0
0.70
140
0.3VDDB
4.0
4.5
VDD (V)
0.75
-40
6.0
3.5
1.00
0.50
0.25
0.00
3.0
Output Voltage (VOLB) - Side B
vs. Temperature
(VDDB=3.3V, ISINKB=3mA)
1.05
0.30
0.05
Margin 100μA
0.00
2.5
6.0
Noise Margin - Side B
VIL_external = 0.3VDD
Margin 3mA
0.15
0.05
Side B Output (V)
3.0
0.20
0.10
0.0
2.5
Margin (V)
0.8
0.6
0.0
Side B Output (V)
VILB
1.0
0.4
Margin 6mA
0.25
1.2
1.2
0.30
0.3 • VDD
1.4
Self Drive Margin - Side B
(VOLB - VILB)
0.35
Propagation Delay (ns)
Output Level (V)
1.8
0.3 • VDD
VOLB _6mA
1.6
Logic Low Input Levels - Side B
(VILB)
Margin (V)
Logic Low Output Levels - Side B
(VOLB)
320
300
280
260
240
220
-60
-40
-20
0
20
40
60
Temperature (ºC)
80
100
The performance data shown in the graphs above is typical of device performance. For guaranteed parameters not
indicated in the written specifications, please contact our application department.
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7
CPC5903
INTEGRATED CIRCUITS DIVISION
3 Functional Description
3.1 Introduction
3.2 Fast-mode Operation
The CPC5903 combines the features of multiple logic
optoisolators and an I2C bus repeater in a single 8-pin
package. It offers excellent isolation (3750Vrms) and
Fast-mode operation of the CPC5903 bidirectional
interface on Side A is available over the full operational
range of the device. While Side B operation is
Standard-mode compliant over the full operational
range of the device, it is Fast-mode speed capable
whenever the bus loading is limited to 200pF. Full
Fast-mode compatible operation of the Side B bus is
available whenever VDDB is 4.5V or greater.
speed sufficient to support I2C Fast-mode at 400kbps.
It bidirectionally buffers the I2C data signal across the
isolation barrier, and unidirectionally buffers the clock
from Side A to Side B. If different supply voltage levels
are used at each side, then the part, in conjunction
with its external pull-up resistors, will perform logic
level translation for VDD between 2.7V and 5.5V at
either side. Due to the unidirectional nature of the
clock buffer it is required that the bus master be
connected to Side A of the CPC5903.
Configured with one bidirectional channel and one
unidirectional channel, the CPC5903 is ideal for
systems that do not implement clock stretching or
have bus masters on the Side B bus. This provides a
savings in supply current compared with using a dual
bidirectional isolator, but at the cost of losing the ability
to implement a Side B bus master or clock-stretching
in the future.
Like available non-galvanically isolating I2C bus
repeaters, the CPC5903 has a full-drive side (Side A)
and a limited-drive side (Side B).
On Side B, IOB is a voltage-limited output driver with a
reduced logic low input voltage threshold (VIL). An
internally set voltage limit prevents IOB from driving to
a VOL level it will accept as a input logic low. This
guarantees the bidirectional buffer cannot drive itself
into a latched logic low condition, which would cause
I2C bus contention. IOB is specified with a minimum
VOL-VIL margin of 25mV at minimum VDDB, and
exhibits a proportionately larger self-drive margin with
larger VDDB.
IOA, the bidirectional buffer on Side A, is rated as a full
strength (6mA), FAST-mode driver over the full VDDA
range with input thresholds specified as FAST-mode
compliant; thus the IOA output will drive the full 400pF
Fast-mode CLOAD and is allowed to drive its own input
to a logic low.
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3.3 Logic Input Thresholds and Output Levels
Because Side A is Fast-mode compliant, it’s inputs
IOA and IA have logic threshold levels and frequency
performance compliant with traditional I2C bus
interface devices. Additionally, the output capability of
IOA is Fast-mode compliant over the entire operational
range.
The output levels of OB and IOB are compatible with
traditional I2C bus interface devices, but are
voltage-limited. The input logic low threshold level of
IOB is configured lower than traditional I2C devices
and lower than it’s own output logic low level. This
eliminates the possibility of the IOB output driver
acquiring an IOB input logic low, which would result in
a latched logic low state.
Because Side B of the CPC5903 utilizes a modified
logic low threshold level, only one such device is
allowed on the Side B bus. Side A has no such
restriction as this side of the CPC5903 uses traditional
logic thresholds. This allows for cascaded isolation by
connecting the Side B of one CPC5903 to Side A of
the next.
Devices meeting the I2C specification are easily able
to drive the IOB input below the CPC5903’s lower VIL
(0.2VDDB) threshold at the Side B input, and will
correctly accept the Side B driven data, thereby
enabling Side B bidirectional communication.
3.4 Pull-Up Resistor Selection
Pull-up resistors are required on both sides of the
barrier. Selecting the value of the pull-up resistors is
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CPC5903
INTEGRATED CIRCUITS DIVISION
dependent on the end product’s design criteria and the
operational characteristics of the CPC5903.
On Side A of the CPC5903, pull-ups chosen for
Fast-mode (up to 6mA) drivers can be used with no
loss of noise margin.
At the Side B outputs, OB and IOB, pull-up resistor
values should be chosen for Standard-mode 3mA
pull-up current or less when VDDB < 4.5V. Additionally,
because VIL at Side B is 0.2VDDB , the pull-up resistor
on IOB must be large enough that the weakest driver
on the Side B bus can pull the voltage reliably below
0.2VDDB . When VDDB > 4.5V, the CPC5903 Side B
outputs will drive up to 6mA, and resistor pull-ups
chosen for up to 6mA can be used, provided all the
other devices on the bus have sufficient drive.
Side A, arriving at the Side A output after a delay
largely determined by tOPLH_BA at time:
tENDA = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA
Thus a valid Side B pulse having a width less than
80ns is stretched at Side A to a typical width of 125ns.
The duration of the pulse width output onto the Side A
bus is given by:
tPWA_min = (tOPHL_AB + tOPLH_BA)
When Side A is deasserted, the output rises at a slew
rate determined by the RC load on IOA, and passes
the logic threshold after time tSLEWA. The deasserted
(logic HIGH) input propagates through the optics and
deasserts the Side B output after a delay largely
determined by tOPLH_AB. Side B deassertion occurs at
time tENDB given by:
tENDB = tENDA + tSLEWA + tOPLH_AB
3.5 Pulse Propagation, Stretching and Delays
Due to glitch protection circuitry within the CPC5903
applying a pulse at the IOB input inherently involves
the use of the output driver at that I/O. Once an
asserted signal at IOB is determined to be valid, it is
stretched until it’s transmission through the optics has
been verified. This insures that there will be no extra
edges generated at either side due to optic delays. If a
Side B asserted-low pulse is long enough to be
accepted and passed to Side A, then the flip-flop at
Side B is set and remains set until the signal returns
through the optics from Side A. While the flip-flop is
set, IOB will output a voltage limited logic low, thereby
holding the bus at a logic low.
In operation, a valid asserted pulse of less than 80ns
applied at IOB appears at Side A after a delay largely
determined by the low-pass filter delay (tFIL) and the
optics delay (tOPHL_BA). After this initial delay the
Side A driver IOA is activated and a logic low is
asserted at time:
tSTARTA = tFIL + tOPHL_BA
That assertion is returned across the optics to Side B
after a delay largely determined by tOPHL_AB. Upon
arriving at Side B, the flip-flop is cleared with the
incoming signal from Side A sustaining the IOB
voltage limited logic low. With the prior loss of the
asserted logic low by the external I2C device, and
because the IOB input does not accept it’s own output
low as valid, a deassertion is sent through the optics to
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Consequently at Side B input, an applied pulse of less
than 80ns is stretched to:
tPWB_min = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA + tSLEWA + tOPLH_AB
which is typically 330ns. More importantly, only one
pulse is seen at both ports, with no extra or missing
clock or data edges, assuring bus integrity.
Pulses of width larger than approximately 80ns
applied to the Side B input do not utilize the flip-flop to
terminate the pulse, but do need to propagate to
Side A and then back to Side B when returning high
after being asserted low. The Side A pulse width is
given by the usual pulse width distortion relation:
tPWA_nom = tPULSE + tPLH_BA - tPHL_BA
which is typically tPULSE + 75ns. Note that tPLH_BA and
tPHL_BA are observed at the external pins, and are
provided in the table, “Electrical Specifications” on
page 4. The pulse at Side B is asserted by an
external driver pulling low, and lasts for time tPULSE. At
the end of the pulse, the rising edge passes through
the internal filter with delay tFIL, then is applied to the
LED and received at Side A tOPLH_BA later. After time
tSLEWA the output at Side A crosses the logic high
threshold causing the Side A LED drive to deactivate,
which propagates the deasserted state back to Side B
with a delay of tOPLH_AB.
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CPC5903
INTEGRATED CIRCUITS DIVISION
Thus normal-width pulses of width tPULSE applied at
IOB exhibit a stretched pulse width of:
tPWB_nom = tPULSE + tFIL + tOPLH_BA + tSLEWA + tOPLH_AB
at IOB, which is also given by:
tPWB_nom = tPULSE + tPHL_BAB
and is typically tPULSE + 290ns.
Side A receivers have been designed to exhibit a
significant amount of hysteresis, which helps to
eliminate false clocking. They have not been internally
low-pass filtered beyond the filtering inherent within
the optical channel. When the I2C bus is terminated
for maximum bandwidth (6mA pullups and minimal
capacitance), the receivers typically will respond to
pulses greater than 12ns. If additional filtering is
desired, then externally increasing the load
capacitance of the I2C lines, until the amount of time
the offending signal spends above/below VDD /2 is
less than 10ns, will reject the signal at the expense of
increasing rise and fall times.
The Side B receiver does implement some hysteresis
and low-pass filtering in addition to the optics. An
asserted pulse typically needs to be held below
0.2VDD for 15ns before it is accepted at the Side B
input. This may require a 30ns pulse applied by a
typical driver with just 20pF loading the I2C lines.
reduction feature and is especially useful on the side
with nonstandard levels, it does need to be considered
when assigning Side A and Side B ports. If Side A is
not powered up, then the signal back from Side A will
not appear until after Side A has been powered, and
the signal at Side B will be stretched until that time.
Side A uses filtered hysteresis at its standard inputs,
not pulse stretching, to defeat sub-minimum-size
pulses. Thus that side of the isolation barrier, which
will be the bus master at power-up, should be
assigned to Side A.
3.6 Start-Up
Upon startup and with loss of VDDx, internal circuitry
place the outputs in the deasserted Hi-Z state.
3.7 Power Supply Decoupling and Noise
There are no special power supply decoupling
requirements for the CPC5903. Additionally, because
the CPC5903 uses optical coupling to transfer clock
and data across the barrier there are no internal
clocking circuits requiring special layout or noise
reduction techniques to maintain EMI and RFI
compliance.
While any very short pulse stretched to the minimum
time above would seem to cause a large amount of
pulse width distortion, within 400kHz Fast-mode I2C,
the shortest allowable signal or clock asserted low
time is 1.3s. Neither Standard-mode nor Fast-mode
variants include any legal signals that are less than
80ns (typ); thus the tPWA_nom and tPWB_nom equations
above always apply. The pulse width on valid longer
pulses receives less stretching and is proportionally
less noticeable. For example the Fast-mode minimum
clock low time of 1.3S when applied at Side B would
typically be seen as a 1.375S pulse at Side A and will
be stretched to a length of 1.59s for other devices on
the Side B bus.
Internal filtering and the flip-flop at IOB are used to
ensure that an equal number of pulse edges are seen
at both sides of the isolation barrier when Side B is
driven. When a signal at IOB is asserted low, the
flip-flop self-drives the IOB pin until the optical channel
back from Side A proves that Side A has successfully
been asserted. While this is generally a welcome error
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CPC5903
INTEGRATED CIRCUITS DIVISION
4 Design Considerations
The minimum value of the pull-up resistor, RPU, on the
I2C
bus is chosen based upon the expected VDD
supply voltage range and the weakest load current
sinking device on the bus. Note: Systems that do not
need maximum bandwidth and busses with lower
capacitive loading can use a higher value for the
pull-up resistor to reduce power consumption.
4.1 Side A Pull-Up Resistors: RPUA
The weakest I2C compliant device on the Side A bus,
with RPUA to VDDA, must be able to pull the Side A
inputs below 0.4V for outputs rated at 3mA or 0.6V for
outputs rated at 6mA when VDDA is at its maximum.
For example, if the weakest device is only guaranteed
to sink 3mA then the maximum allowed logic low
output voltage will be 0.4V. For designs with
VDDA_max = 3.6V, the minimum voltage across the
pull-up resistor is:
Minimum RPUA Voltage = 3.6 - 0.4 = 3.2V
For the I2C minimum current sink requirement of 3mA,
the minimum value of the pull-up resistor is easily
calculated as:
RPUA_min = 3.2V / 3mA = 1066.7
Chose a standard value resistor that will not violate
this minimum value over tolerance and temperature,
such as a 1.1k, 1% tolerance, 100ppm/C
temperature coefficient resistor.
If all the non-CPC5903 devices on the Side A bus are
Fast-mode compliant (400pF capacitive loading
capable) with the required 6mA current sink capability,
then the bus can be configured for Fast-mode.
Resistor selection for Fast-mode is similar to the
example given above but because the logic low output
level is greater (0.6V) then the voltage across the
pull-up resistor will be less. Calculation of the
compliant Fast-mode bus minimum pull-up resistor
value is given by:
RPUA_min = (3.6 - 0.6)V / 6mA = 500
The minimum E96 standard value 1% tolerance,
100ppm/C temperature coefficient resistor is 511.
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4.2 Side B Pull-Up Resistors
Calculating the pull-up resistor for Side B is similar to
the process used for Side A but with some additional
considerations.
Before proceeding, it must be pointed out that Side B
of the CPC5903 is Fast-mode compliant with
VDDB  4.5V. This means the CPC5903 Side B
outputs are 6mA capable, allowing bus operation of
400kb/s with up to 400pF of capacitive loading. For
VDDB supply levels below 4.5V the CPC5903 outputs
are only rated for 3mA, but can be operated at
Fast-mode speeds of 400kb/s whenever the bus
capacitive loading CLOAD  200pF. Greater capacitive
loading of the Side B bus limits the CPC5903 to data
rates of 100kb/s.
First, it must be determined if the Side B bus will be
configured for 3mA or 6mA operation. This is done by
evaluating the external (non-CPC5903) devices on the
Side B bus and the operational capabilities of the
CPC5903. There are three possibilities:
1) One or more of the external devices is limited to
3mA of output current sink.
2) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage VDDB  4.5V.
3) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage VDDB  4.5V.
For conditions 1 and 2 above the bus must be
configured for 3mA. Condition 3 is the only situation
where the bus can be configured for 6mA, a
Fast-mode requirement when capacitive bus loading is
an issue.
4.2.1 OB Pull-Up resistor: RPU-OB
Selecting the pull-up resistor for the OB bus is based
upon the manner in which the bus is expected to
operate within the restrictions listed above. Although
the additional design considerations discussed below
for selecting the IOB pull-up resistor, RPUB , are not
applicable to the OB pull-up resistor, the Side B
pull-up resistors should have the same value to
minimize skew between the clock and data. Therefore,
setting RPU-OB = RPUB is recommended.
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CPC5903
INTEGRATED CIRCUITS DIVISION
4.2.2 IOB Pull-Up Resistor: RPUB
For the bidirectional buffer, it is necessary to configure
the IOB bus to be compatible with the CPC5903’s
lower logic low input threshold:
VILB = 0.2 • VDDB - 60mV
As discussed earlier, this lower input threshold
requirement is to ensure the CPC5903 can drive a
logic low output that is recognized by the other I2C
devices on the bus, but will not accept it’s own logic
low output. This prevents latching of the CPC5903.
Additionally, this implies there can be no more than
one limited drive (Side B) CPC5903 interface on the
IOB bus, and that all other devices on the bus must
have VIL = 0.3 • VDDB logic low input thresholds.
Because the CPC5903 Side A inputs are compatible
with this requirement, any number of CPC5903 Side A
devices may be connected to the Side B bus.
For all modes, the minimum required voltage drop
across the IOB pull-up resistor at VDDB_max by the
external non-CPC5903 I2C bus drivers is:
Minimum RPUB Voltage = VDDB_max - (0.2 • VDDB_max - 60mV)
= 0.8 • VDDB_max + 60mV
which gives the calculation for the minimum value of
the pull-up resistor as:
RPUB_min = (0.8 • VDDB_max + 60mV) / IOL
where IOL is the guaranteed logic low drive current of
the non-CPC5903 bus drivers.
For Standard-mode designs, with output drivers rated
at 3mA and a maximum supply voltage of 3.6V, the
minimum value of the pull-up resistor is:
RPUB_min = (0.8 • 3.6 + 60mV) / 3mA = 980
The minimal standard value 1% resistor with a
100ppm/C temperature coefficient that will not go
below the calculated minimum due to tolerance and
temperature is 1k.
In Fast-mode designs with 6mA capable output drivers
and a supply voltage maximum of 5.5V, the minimum
Fast-mode pull-up resistor value is calculated to be:
RPUB_min = (0.8 • 5.5 + 60mV) / 6mA = 743.3
For a Fast-mode design with high capacitive bus
loading, a 768, 1%, 100ppm/C resistor would
suffice. When the bus does not have a heavy
capacitive load, a larger value pull-up resistor can be
used thereby reducing overall power consumption.
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CPC5903
INTEGRATED CIRCUITS DIVISION
5 Manufacturing Information
5.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC5903G / CPC5903GS
MSL 1
5.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
5.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC5903G / CPC5903GS
250°C for 30 seconds
5.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an
optical waveguide in many of its optically isolated products, the use of a short drying bake could be necessary if a
wash is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used.
Cleaning methods that employ ultrasonic energy should not be used.
Pb
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CPC5903
INTEGRATED CIRCUITS DIVISION
5.5 Mechanical Dimensions
5.5.1 CPC5903G 8-Pin DIP Package
2.540 ± 0.127
(0.100 ± 0.005)
9.652 ± 0.381
(0.380 ± 0.015)
8-0.800 DIA.
(8-0.031 DIA.)
2.540 ± 0.127
(0.100 ± 0.005)
9.144 ± 0.508
(0.360 ± 0.020)
6.350 ± 0.127
(0.250 ± 0.005)
Pin 1
PCB Hole Pattern
7.620 ± 0.254
(0.300 ± 0.010)
6.350 ± 0.127
(0.250 ± 0.005)
0.457 ± 0.076
(0.018 ± 0.003)
3.302 ± 0.051
(0.130 ± 0.002)
7.620 ± 0.127
(0.300 ± 0.005)
7.239 TYP.
(0.285)
4.064 TYP
(0.160)
7.620 ± 0.127
(0.300 ± 0.005)
0.254 ± 0.0127
(0.010 ± 0.0005)
Dimensions
mm
(inches)
0.813 ± 0.102
(0.032 ± 0.004)
5.5.2 CPC5903GS 8-Pin Surface Mount Package
9.652 ± 0.381
(0.380 ± 0.015)
2.540 ± 0.127
(0.100 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
Pin 1
3.302 ± 0.051
(0.130 ± 0.002)
0.635 ± 0.127
(0.025 ± 0.005)
9.525 ± 0.254
(0.375 ± 0.010)
0.457 ± 0.076
(0.018 ± 0.003)
PCB Land Pattern
2.54
(0.10)
8.90
(0.3503)
1.65
(0.0649)
7.620 ± 0.254
(0.300 ± 0.010)
0.254 ± 0.0127
(0.010 ± 0.0005)
0.65
(0.0255)
4.445 ± 0.127
(0.175 ± 0.005)
Dimensions
mm
(inches)
0.813 ± 0.102
(0.032 ± 0.004)
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CPC5903
INTEGRATED CIRCUITS DIVISION
5.5.3 CPC5903GSTR Tape & Reel Information for Surface Mount Package
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
W=16.00
(0.63)
Bo=10.30
(0.406)
K0 =4.90
(0.193)
Ao=10.30
(0.406)
K1 =4.20
(0.165)
Embossed Carrier
Embossment
P=12.00
(0.472)
User Direction of Feed
Dimensions
mm
(inches)
NOTES:
1. Dimensions carry tolerances of EIA Standard 481-2
2. Tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed
or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes
to its products at any time without notice.
Specification: DS-CPC5903-R02
©Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/18/2012
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