CPC7514 Quad High Voltage Isolated Analog Switch Array INTEGRATED CIRCUITS DIVISION Features Description • • • • • • • The CPC7514 Quad High Voltage (HV) isolated Analog Switch Array builds upon our Line Card Access Switch (LCAS) design and fabrication expertise for telecom and non-telecom applications. This monolithic solid state device provides the switching functionality of four normally open (1-Form-A) relays in one small economical package. • • • • Low, Matched RON Switch Voltage up to 320V 110dB Switch-to-Switch Isolation at 5kHz Flexible Switch Configurations Smart Logic for Power-Up/Hot-Plug State Control 3.3V Operation with Very Low Power Consumption Switch Current Limiting and Thermal Shutdown Protects Against Fault Conditions TTL Logic-Level Inputs Input Latch Clean, Bounce-Free Switching Monolithic IC Reliability Designed to provide flexible single-ended or differential access to high voltage networks, the CPC7514 high voltage array is configured as two sets of matched paired switches for improved differential performance. Additionally, sensitive differential applications will benefit from the matched pairs’ excellent pair-to-pair isolation. The self-biasing switches do not require external high-voltage supplies for proper operation. Applications • • • • • Instrumentation Industrial Controls and Monitoring Automatic Test Equipment (ATE) Battery Monitoring and Charging Telephony • VoIP Gateways • Central Office (CO) and Remote Terminal (RT) • Digital Loop Carrier (DLC) • Optical Terminals (ONT & ONU) • PBX Systems • Optical Network Terminals (ONT) and Optical Network Units (ONU) • Hybrid Fiber Coax (HFC) Independent switch current limiting and switch-pair thermal shutdown features provide enhanced protection for devices connected to high voltage networks up to +320V. Ordering Information Part # Description CPC7514Z 20-Pin SOIC in Tubes (40/Tube) CPC7514ZTR 20-Pin SOIC Tape & Reel (1000/Reel) Figure 1. CPC7514 Block Diagram VDD = 3.3V S1* S1A S1B S2* CHANNEL 1-2 S2A IN1 IN2 LATCH1-2 S2B L A T C H 1-2 Channel 1-2 S 1 Switch S2 Control Logic TSD1-2 S3* S3A CHANNEL 3-4 S3B S4* S4A IN3 IN4 LATCH3-4 S4B L A T C H 3-4 Channel 3-4 S 3 Switch S4 Control Logic TSD3-4 * ±320V DGND Pb DS-CPC7514-R06 e3 www.ixysic.com 1 CPC7514 INTEGRATED CIRCUITS DIVISION 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Switch Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Digital I/O Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Switch Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 VDD Voltage Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Protection Circuitry Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 CHANNEL1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 CHANNEL3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 4 4 5 6 6 7 7 8 8 8 2. Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Under-Voltage Switch Lock-Out Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Data Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 TSD Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Dynamic High Frequency Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Low Frequency Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Thermal Design Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 10 11 11 11 11 11 12 12 13 13 4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 CPC7514Z Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 CPC7514ZTR Tape & Reel Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 14 15 15 15 2 www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION 1. Specifications 1.1 Package Pinout 1.2 Pin Descriptions Pin Name 6,14 7 13 VDD DGND NC S3B 1 20 S2B S4B 2 19 S1B IN4 3 18 IN2 IN3 4 17 IN1 LATCH3-4 5 16 LATCH1-2 VDD 6 15 TSD1-2 18 17 16 DGND 7 14 VDD 15 TSD3-4 8 13 N/C S4A 9 12 S1A S3A 10 11 S2A 12 19 11 20 3 4 5 8 10 1 9 2 R06 www.ixysic.com Description Logic Supply Voltage Ground Not Connected CHANNEL 1-2 IN2 Input - Switch 2 state control IN1 Input - Switch 1 state control LATCH1-2 Input - Latch control for SW1 & SW2 I/O - Thermal shutdown output and All-Off TSD1-2 input control for SW1 & SW2 S1A Switch 1 - side A S1B Switch 1 - side B S2A Switch 2 - side A S2B Switch 2 - side B CHANNEL 3-4 IN4 Input - Switch 4 state control IN3 Input - Switch 3 state control LATCH3-4 Input - Latch control for SW3 & SW4 I/O - Thermal shutdown output and All-Off TSD3-4 input control for SW3 & SW4 S3A Switch 3 - side A S3B Switch 3 - side B S4A Switch 4 - side A S4B Switch 4 - side B 3 CPC7514 INTEGRATED CIRCUITS DIVISION 1.3 Absolute Maximum Ratings Parameter +3.3V power supply (VDD) Logic input voltage Logic input to switch output isolation Switch open-contact isolation (SW1, SW2, SW3, SW4) Operating relative humidity Operating temperature Storage temperature 1.4 General Conditions Minimum Maximum Unit -0.3 -0.3 +7 VDD + 0.3 V V - 320 V - 320 V 5 -40 -40 95 +110 +150 % C C Unless otherwise specified, minimum and maximum values are guaranteed by production testing. Typical values are characteristic of the device and are the result of engineering evaluations. They are provided for informational purposes only and are not guaranteed by production testing. Specifications cover the operating temperature range TA = -40C to +85C. Also, unless otherwise specified, all testing is performed with VDD = 3.3VDC, logic low input voltage is 0VDC and logic high input voltage is 3.3VDC. Absolute maximum electrical ratings are at 25C. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 4 www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION 1.5 Switch Electrical Specifications Parameter Off-State Leakage Current Test Conditions Symbol Minimum Typical Maximum Unit VSW (differential) = SxA to SxB VSW (differential) = SxB to SxA Switch Off. +25C, VSW (differential) = +320V to Gnd +0.1 ISW +85C, VSW (differential) = +330V to Gnd - -40C, VSW (differential) = +310V to Gnd +0.3 +1 A +0.1 ISW(on) = ±10mA, ±40mA On Resistance +25C - 14.5 - - - 31 8 10.5 - RON - 0.1 0.8 Maximum Differential Voltage 1 VON - - 320 Current-Foldback Voltage-Breakpoint 1 V1 60 - - Current-Foldback Voltage-Breakpoint 2 V2 V1 + 0.5 - - 130 200 - 80 - - - - 425 RON +85C -40C On Resistance Matching Per On Resistance test conditions SW1 & SW2 SW3 & SW4 ON-State Voltage 2 Low Frequency Current Limit 1 2 V VSW (on) = ±10V +25C ILIM1 +85C -40C Low Frequency Current Limit 2 2 mA VSW (on) = ±V2 ILIM2 1 - - mA High Frequency Dynamic Current Limit (t <0.5 s) Switches on, Apply ±1 kV 10x1000 s pulse with appropriate protection in place ISW - 1 - A Logic Input to Switch Output Isolation VSW: VSxA = VSxB to Gnd - +0.1 - - +0.3 +1 -40C, VSW = ±310V - +0.1 - Any switch to any other switch f=5kHz 110 - - dB 1500 2100 - V/s +25C, VSW = ±320V ISW +85C, VSW = ±330V Switch to Switch Isolation Transient Immunity 100VP-P Square Wave at 100Hz 1 Choice of high voltage side protector should ensure this rating is not exceeded. 2 See “Figure R06 dV/dt A 1: Switch Low Frequency Response” on page 12. www.ixysic.com 5 CPC7514 INTEGRATED CIRCUITS DIVISION 1.6 Digital I/O Electrical Specifications Parameter Test Conditions Symbol Minimum Typical Maximum Unit Logic High Input voltage rising VIH - 1.5 2.0 V Logic Low Input voltage falling VIL 0.8 1 - V Input Characteristics Input Voltage: (INx, LATCHx, TSDx) VIN Hysteresis 500 mV Input Leakage Current Logic High: INx LATCHx VDD = 3.6V, VIH = 2.4V IIH TSDx - 0.1 1 -10 -19 -100 -10 -16 -50 - 0.1 1 -10 -47 -125 -10 -16 -50 A Logic Low: INx LATCHx VDD =3.6V, VIL = 0.4V IIL TSDx A Output Characteristics Output Voltage: TSDx: Logic High VDD = 3.6V, ITSD = 10A VTSD_off 2.4 VDD - V Logic Low VDD = 3.6V, ITSD = 1mA VTSD_on - 0 0.4 V Symbol Minimum Typical Maximum Unit 1.7 Switch Timing Specifications Parameter Test Conditions Switch turn on delay LATCHx = 0V, ISW_off = 0mA, ton@ISW = 9mA td_on - 0.25 1.0 ms Switch turn off delay LATCHx = 0V, ISW_on = 10mA, toff@ISW = 0.5mA td_off - 0.05 0.5 ms Switch turn on matching As per Switch Turn On Delay, Any switch to any other switch ton - 10 100 s Switch turn off matching As per Switch Turn Off Delay, Any switch to any other switch toff - 2 100 s - 120 160 - 190 240 Switch Capacitance SxA=SxB to Gnd SxA to SxB, VSW (differential)=0V 6 C www.ixysic.com pF R06 CPC7514 INTEGRATED CIRCUITS DIVISION 1.8 VDD Voltage Supply Specifications Parameter Test Conditions Symbol Minimum Typical Maximum Unit - VDD 3 3.3 3.6 V 0.75 1.5 2.3 mA 2.0 4.5 6.0 mA - 2 2.8 1 1.95 - - 50 - mV Symbol Minimum Typical Maximum Unit TTSD_on 110 125 150 C TTSD_off 10 - 25 C Voltage Requirements Voltage operational range Current Specifications VDD Current 3.0 < VDD < 3.6V, All switches = OFF, All logic I/O = Open 3.0 < VDD < 3.6V, All switches = ON, All logic I/O = Open IDD Under Voltage Lockout Specifications Thresholds VDD rising VDD falling UVLO Hysteresis V 1.9 Protection Circuitry Thermal Specifications Parameter Conditions Temperature Shutdown Specifications 1 Shutdown activation temperature Shutdown circuit hysteresis 1 Not production tested - limits are guaranteed by design and Quality Control sampling audits Temperature shutdown flag (TSDx) will be high during normal operation and low during temperature shutdown state. R06 www.ixysic.com 7 CPC7514 INTEGRATED CIRCUITS DIVISION 1.10 Truth Tables 1.10.1 CHANNEL1-2 LATCH1-2 IN2 IN1 0 0 0 0 1 x 0 0 1 1 x x 0 1 0 1 x x 1Z TSD1-2 Z1 0 S2 S1 OFF OFF OFF ON ON OFF ON ON Unchanged Unchanged OFF OFF LATCH3-4 IN4 IN3 x x x x x x x x x x x x x x x x x x TSD3-4 x x x S4 S3 x x x x x x x x x x x x S4 S3 = High Impedance. Because TSD1-2 has an internal pull-up, it should be controlled with an open-collector or open-drain type device. 1.10.2 CHANNEL3-4 LATCH1-2 IN2 IN1 x x x x x x x x x x x x x x x x x x 1Z TSD1-2 x x S2 S1 LATCH3-4 IN4 IN3 x x x x x x x x x x x x 0 0 0 0 1 x 0 0 1 1 x x 0 1 0 1 x x TSD3-4 Z1 0 OFF OFF OFF ON ON OFF ON ON Unchanged Unchanged OFF OFF = High Impedance. Because TSD3-4 has an internal pull-up, it should be controlled with an open-collector or open-drain type device. As can be seen in the two truth tables above, CHANNEL1-2 and CHANNEL3-4 have identical functionality yet are independent. As such, for each state of one channel there are four possible states for the other channel giving the CPC7514 a total of 16 realizable states. 8 www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION 2. Performance Data Insertion Loss= V +20 log M VS + VM 50Ω Open Circuit= V +20 log M VS Insertion Loss Into 50Ω 0 Transfer Gain (dB) -1.0 VS Loss (dB) -1.5 -2.0 -2.5 -3.0 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) 1E+7 1E+8 VS + VM 50Ω Open Circuit Transfer Gain Into 50Ω -20 -40 -60 -80 -100 1E+3 1E+4 1E+5 1E+6 Frequency (Hz) 1E+7 1E+8 Channel 1 Open Cross Talk= V +20dB log M VS VS Channel 2 + VM Open 50Ω Cross Talk Into 50Ω Transfer Gain (dB) 0 -20 -40 -60 -80 -100 1E+4 1E+5 PSD 1E+6 1E+7 Frequency (Hz) 1E+8 + VM Open 50Ω PSD Closed Switch Into 50Ω -20 -20 -20 -40 -60 -80 -100 -120 Noise Power (dBm/Hz) 0 -40 -60 -80 -100 -120 -140 -140 0 R06 PSD Closed Switch Into 50Ω 0 Noise Power (dBm/Hz) Noise Power (dBm/Hz) PSD Closed Switch Into 50Ω 0 200 400 600 Frequency (kHz) 800 1000 -40 -60 -80 -100 -120 -140 0 1 2 3 Frequency (MHz) www.ixysic.com 4 5 0 2 4 6 8 10 12 14 Frequency (MHz) 16 18 20 9 CPC7514 INTEGRATED CIRCUITS DIVISION 3. Functional Description 3.1 Introduction The CPC7514 High Voltage Quad Analog Switch Array has four independent symmetrical switches providing 16 unique operating states. These operational states and the logical behavior of the device are shown in the tables given in “Truth Tables” on page 8. Switch organization consists of two channels each having a pair of switches. Within each channel there is a single LATCH input and a single Temperature Shutdown circuit shared by the switch pair. Other than these two shared circuits the performance of each switch within a channel is independent of the other. As there is no shared circuitry between the channels, the switches of one channel are completely independent of the other channel. Switch utilization under normal operating conditions allows the switches to be used in any combination. In designs where the switches will be required to carry high load currents or operate in higher temperature environments the thermal specifications should be reviewed. Solid-state switch construction of the CPC7514 offers clean, bounce-free switching with simple logic input control to provide access to high voltage interfaces without the impulse noise generated by traditional electromechanical switching techniques. Simple logic input control eliminates the additional driver circuitry required by traditional techniques. The low on-resistance (RON) symmetrical linear switches are configured as matched pairs, SW1/SW2 and SW3/SW4, for improved performance when differential access is required. Their symmetrical construction provides an additional degree of design flexibility allowing either side of the switch to be connected to the high voltage network. Integrated into the CPC7514 switches are active current limiting and thermal shutdown mechanisms to provide protection for the electronics being connected to the high voltage network during a fault condition. High frequency positive and negative transient currents such as lightning are reduced by the current limiting circuitry. Protection from prolonged low frequency power-cross and DC currents, also reduced by the current limiting circuitry, is supplemented by thermal shutdown circuits. 10 To protect against a high voltage fault in excess of the CPC7514’s maximum voltage rating, use of an over-voltage protector is required. The protector must limit the voltage seen at the SxA and SxB terminals to a level below the switches maximum breakdown voltage. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type protector is highly recommended. With proper selection of the protector, telecom applications using the CPC7514 will meet all relevant ITU, LSSGR, TIA/EIA and IEC protection requirements. Operating from a single +3.3V supply the CPC7514 has extremely low power consumption. 3.2 Under-Voltage Switch Lock-Out Circuitry Smart logic in the CPC7514 provides for switch state control during both power up and power loss transitions to prevent undesired connections to high voltage networks. An internal detector evaluates the VDD supply to determine when to de-assert the under-voltage switch lock-out circuitry with a rising VDD, and when to assert the under-voltage switch lock-out circuitry with a falling VDD. Any time unsatisfactory low VDD conditions exist, the lock-out circuit overrides user switch control by blocking the external information at the input pins, and conditioning internal switch commands to the All-Off state. Upon restoration of VDD, the switches will remain off until the LATCHx input is pulled low with proper conditioning of the INx inputs. The rising VDD lock-out release threshold is internally set to ensure all internal logic is properly biased and functional before accepting external switch commands from the inputs to control the switch states. For a falling VDD event, the lock-out threshold is set to assure proper logic and switch behavior up to the moment the switches are forced off and external inputs are suppressed. 3.3 Switch Logic The CPC7514 uses smart logic to monitor the VDD supply. Any time VDD is below an internally set threshold, the smart logic places the control logic into the All-Off state. After VDD recovers the switches may www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION be reconfigured by setting the LATCHx input low. Prior to the assertion of a logic low at the LATCHx pin, the switch control inputs must be properly conditioned. 3.3.1 Data Latch The CPC7514 has two integrated transparent data latches. The latch-enable operation is controlled by logic input levels at the LATCHx pins. Data input to the latch is via the INx input pins while the outputs of the data latch are internal nodes used for state control. When the latch enable control pin is at a logic 0 the data latch is transparent and the input control signals flow directly through the data latch to the state control circuitry. A change in input will be reflected by a change in the switch state. Whenever the latch enable control pin is at logic 1, the data latch is active and the control data is locked. Subsequent changes to the INx input control pins will not result in a change to the control logic or affect the existing switch states. The switches will remain in the state they were in when the LATCHx changes from logic 0 to logic 1, and will not respond to changes in input as long as the LATCHx is at logic 1. However, the TSDx are not affected by the latch function. Since internal thermal shutdown control is not affected by the state of the latch enable input, TSDx will override state control. recommends the use of an open-collector or an open-drain type output to control TSDx. For lower-voltage logic control, this avoids sinking the TSDx pull-up bias current to ground during normal operation when the All-Off state is not required. And for higher logic-voltage control, this prevents over-voltage biasing of the TSDx input. If TSDx is forced to a logic 1 or tied to VDD, the channel just ignores this input, and still enters the thermal shutdown state at high temperature. In other words, the thermal shutdown feature can not be overridden by an external pull-up on the TSDx control. 3.4 Power Supplies Only a +3.3V logic supply and ground are connected to the CPC7514. Switch state control is powered exclusively by the +3.3V supply. As a result, the CPC7514 exhibits extremely low power consumption during active and idle states. 3.5 Protection The CPC7514 provides protection for both the low voltage side circuitry it connects to high voltage networks and itself. Three separate layers of protection are interleaved within the device to protect against high-energy high-frequency transients and high-power, low-frequency fault conditions. 3.5.1 Dynamic High Frequency Current Limit 3.3.2 TSD Pin Description The TSDx pins are bidirectional I/O structures with internal pull-up resistors sourced from VDD. As outputs, these pins indicate the status of the thermal shutdown circuitry for the associated channel. Typically, during normal operation, these pins will be pulled up to VDD, but, under fault conditions that create excess thermal loading, the channel under duress will enter thermal shutdown and a logic low will be output at TSDx. As inputs, the TSDx pins are utilized to place the channel into the All-Off state by simply pulling the input low. This is a convenient way to temporarily place the channel’s switches into the off state without the need to cycle the inputs and LATCH through an off and then an on sequence. High voltage networks are ofttimes located in environments susceptible to lightning events resulting in high-frequency, high-energy transients being coupled onto the high voltage network. Low voltage circuits accessing high voltage networks through the CPC7514 are protected from these events by the dynamic high-frequency current-limit response incorporated into each switch. While in the ON state, the high frequency current is restricted by the CPC7514. For a GR-1089-CORE specified +1000V 10x1000s lightning pulse with a generator source impedance of 10 applied to the high voltage network though a properly clamped external protector, the current seen at the CPC7514 low voltage side interface will be a pulse with a typical magnitude of 1A and a duration less than 0.5s. For applications using logic devices powered from a supply voltage that differs from the CPC7514, (lower or higher than VDD), IXYS Integrated Circuits Division R06 www.ixysic.com 11 CPC7514 INTEGRATED CIRCUITS DIVISION 3.5.2 Low Frequency Current Limit High-power, low-frequency faults are generally the result of power cross (also known as power contact) events. Current through a switch in the ON state during a power-cross fault will be constrained by the low-frequency current-limit response of the switch. As shown in “Figure 1: Switch Low Frequency Response” on page 12 the low-frequency current-limit response is dependent on the differential voltage across the switch. For low levels of fault current the graph shows that the voltage across the active switch increases with increasing fault current. When the magnitude of the fault current into the CPC7514 reaches the Current Limit 1 (ILIM1) threshold, the switch ceases to accept additional current causing the switch response to transition from low impedance to high impedance. This causes the voltage across the switch to increase rapidly. With a fault source of sufficient magnitude, the voltage across the switch will continue to increase. To limit on-chip power dissipation, the switch will decrease the Current Limit when the voltage across the switch reaches the Current-Foldback Voltage-Breakpoint 1 (V1) level. Additional increases in switch voltage will cause the switch to transition to Current Limit 2 (ILIM2) at Current-Foldback Voltage-Breakpoint 2 (V2) further reducing the thermal loading of the switch. Figure 1: Switch Low Frequency Response ISW ILIM1 2/3 RON -VMAX -V2 -V1 -1.5V ILIM2 RON -ILIM2 1.5V V1 V2 VSW VMAX -ILIM1 Thermal management of each channel is necessary to minimize the internal temperature rise inside the package, created by a fault on one channel, from causing a thermal shutdown event of the other channel. 12 It is important to note that the low-frequency current-limit performance is dependent on a voltage clamping device on the low-voltage side sized to ensure that fault voltages do not exceed the specifications of the low-voltage circuits, and capable of redirecting currents up to the maximum level of Current Limit 1. Note that the current-limit circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to a prolonged power-cross fault condition, the current through the active switch will decrease as the device temperature rises. If the device temperature rises sufficiently, then the temperature shutdown mechanism will activate and the channel will enter the All-Off state. 3.5.3 Thermal Shutdown The thermal-shutdown mechanism activates when the channel’s die temperature reaches a minimum of 110°C, placing the channel’s switch pair into the All-Off state regardless of logic input. During thermal shutdown events the TSDx pin will output a logic low with a nominal 0V level. A logic high is output from the TSDx pin during normal operation with a typical output level equal to VDD. If presented with a short-duration transient, such as a lightning event, the thermal-shutdown feature will typically not activate. But in an extended power-cross event, the device temperature will rise, and the thermal shutdown mechanism will activate, forcing the channel’s switches to the All-Off state. At this point the current into the active switch will drop to zero. Once the channel enters thermal shutdown, it will remain in the All-Off state until the temperature of the channel drops below the de-activation level of the thermal-shutdown circuit. This permits the circuit to autonomously return to normal operation. If the fault has not passed, current will again flow up to the value allowed by the low-frequency current-limit of the switches, and heating will resume, reactivating the thermal-shutdown mechanism. This cycle of entering and exiting the thermal-shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external over-voltage protector will activate, shunting the fault current to ground. www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION 3.6 External Protection Elements The CPC7514 requires only over-voltage secondary protection on the high-voltage side of the switch. Additional external protection may be required on the low-voltage side of the switch if the threshold of the high-voltage side protector exceeds the safe operation of the low-voltage side components. Because the fault current seen by the low-voltage side protector is limited by the switch’s active current limit circuitry, the low-voltage side protector need not be as capable as that of the high-voltage side protector. The high-voltage side protector must limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7514. A foldback or crowbar type protector on the high-voltage side is recommended to minimize stresses on the CPC7514. power is the sum of the maximum current through each active switch times the On-Resistance of the switch (ISWx2 X RON). The second equation is used to calculate the maximum ambient temperature that the device can be operated in based on the calculated total power of the previous equation. PTOTAL, the value obtained in the first equation; T, the junction temperature rise of the CPC7514 from ambient; and JA, the thermal impedance of the device package are used to determine the maximum operating ambient temperature. Using the junction temperature rise equation T = TJ - TA; the thermal impedance JA = 65.8C/W; and a maximum junction temperature TJ-MAX = 110C, the equation reduces to: 3.7 Thermal Design Assessment T A – MAX = T J – MAX – P TOTAL JA A successful design utilizing the CPC7514 Quad High Voltage Analog Switch Array is dependent on careful consideration of the application’s environment and the device’s thermal constraints. For matters regarding the electrical design, this is simply a case of following the parameters provided in the preceding tables and for many this will be sufficient. However, those designers wishing to push the operational limits envelope with higher switch current and/or higher ambient operating temperatures will need to consider the thermal performance. To avoid entering thermal shutdown, the value for the maximum junction temperature was set to 110C. Conversely, it is possible to rework the equations to determine the maximum switch current for a maximum ambient current. When using the individual switches of the CPC7514 within their allowable operating region, no restrictions are placed on any other switch. Being a real physical device the CPC7514 has a finite thermal capability that when properly considered will ensure appropriate behavior and performance. Determination of the thermal constraint is easily accomplished using the following power equations: P TOTAL = P V DD + P SW and T P TOTAL = -------- JA Where PVDD is the dissipated power drawn from the VDD supply and PSW is the power dissipated by the active switches. The VDD power can be calculated from the “VDD Voltage Supply Specifications” on page 7 while the power dissipated by the switches is the sum of the concurrent active switches. Total switch R06 www.ixysic.com 13 CPC7514 INTEGRATED CIRCUITS DIVISION 4. Manufacturing Information 4.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC7514Z MSL 1 4.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 4.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC7514Z 260°C for 30 seconds 4.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 14 e3 www.ixysic.com R06 CPC7514 INTEGRATED CIRCUITS DIVISION 4.5 Mechanical Dimensions 4.5.1 CPC7514Z Package Dimensions Recommended PCB Land Pattern 12.757 ± 0.254 (0.502 ± 0.010) 1.27 (0.050) PIN 20 10.312 ± 0.381 (0.406 ± 0.015) 7.493 ± 0.127 (0.295 ± 0.005) 9.40 (0.370) 2.00 (0.079) PIN 1 0.406 ± 0.076 (0.016 ± 0.003) 1.270 TYP (0.050 TYP) 0.60 (0.024) 45º 2.337 ± 0.051 (0.092 ± 0.002) 0.649 ± 0.102 (0.026 ± 0.004) 0.203 ± 0.102 (0.008 ± 0.004) 0.889 ± 0.178 (0.035 ± 0.007) 0.254 / +0.051 / -0.025 (0.010 / +0.002 / -0.001) DIMENSIONS mm (inches) NOTES: 1. Coplanarity = 0.1016 (0.004) max. 2. Leadframe thickness does not include solder plating (1000 microinch maximum). 4.5.2 CPC7514ZTR Tape & Reel Specification 330.2 DIA. (13.00 DIA) Top Cover Tape Thickness 0.102 MAX (0.004 MAX) W=24.00±0.3 (0.94) B0=13.40±0.15 (0.53±0.006) A0=10.75±0.15 (0.42±0.006) K0=3.20±0.15 (0.126±0.006) Embossed Carrier K1=2.60±0.15 (0.10±0.006) P=12.00 (0.47) Dimensions mm (inches) NOTE: Unless otherwise specified, all dimension tolerances per EIA-481 Embossment For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specifications: DS-CPC7514-R06 © Copyright 2013, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 4/5/2013 R06 www.ixysic.com 15