CPC5750

CPC5750
Single-Channel
Voice Band CODEC
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Features
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Description
-law and A-law ITU G.711 Companding Codec
Operates on +3.3V Power
Differential Analog Signal Paths
Programmable Transmit and Receive Gain, +/-12dB
in 0.1dB increments
Transmit Path 60Hz Rejection Filter
Differential amplifier drives +3.2dBm into 600
Stable Gain over temperature
PCM and IOM-2 GCI telecommunication interfaces
Short and Long Frame Syncs Supported
Independent Transmit and Receive Programmable
Time Slots
Accepts PCLK from 512kHz to 8.192MHz
SPI Serial Interface for control in PCM Mode
Programmable Power Down Mode, IDD = 20A
Analog and Digital Loopback Modes for testing
The CPC5750 is a voice-band CODEC with
pin-selectable PCM or IOM-2 (GCI) digital interfaces.
Clock frequencies for the PCM Mode range from
512kHz to 8.192MHz while the GCI interface allows
clocking at 2.048MHz and 4.096MHz. While the GCI
interface utilizes the integrated data link to read and
write the control registers, a four-wire Serial Peripheral
Interface (SPI) bus provides register access while in
PCM Mode.
The CODEC provides the necessary A/D and D/A
functions with pin-selectable -law or A-law
companding. A low-noise internal reference is used to
keep signal gains well controlled over supply and
temperature variations. Programmable gain of ±12dB
for both transmit and receive allow the CPC5750 to
accept differential input signals as large as +8dBm,
and to source +3.2dBm differential signals into 600
while operating from a single 3.3V supply.
Ordering Information
Part
Description
CPC5750U
SSOP-24 Package 50/Tube
CPC5750UTR
SSOP-24 Package 2000/Reel
VDD
D3
D2
D1
D0
CPC5750 Block Diagram
Control
Register
RST
SPI
Interface
SCLK
SDI
SDO
CS
POR
DLB
AIN+
+
AIN-
-
ADC
FIR
Filter
µ-law/A-law
Encoder
VREF
BAND GAP
BUF
PCM/IOM-2
Interface
Logic
0.22µF
VDD
VEE
FS
DTX
DRX
PCLK
SFSEL
BUF
MUTE
AOUT+
AOUT-
+
-
DAC
Noise
Shaper
FIR
Filter
m-law/A-law
Decoder
ALB
DS-CPC5750-Rev F
PRELIMINARY
1
INTEGRATED CIRCUITS DIVISION
1.
CPC5750
PRELIMINARY
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Specifications: General Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Analog Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Digital Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Transmit Path: Analog Inputs (AIN+ and AIN-) to Digital Output (DTX) - AC Characteristics . . . . . . . . . .
1.9 Receive Path: Digital Input (DRX) to Analog Outputs (AOUT+ and AOUT-) - AC Characteristics . . . . . . . .
1.10 Power Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 TX Path Gain: ±1dB Steps Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 TX Path Gain: +0.1dB Steps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 RX Path Gain: ±1dB Steps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 RX Path Gain: +0.1dB Steps Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 PCM Interface DRX Time Slot Assignment Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 PCM Interface DRX Bit Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 PCM Interface DTX Time Slot Assignment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 PCM Interface DTX Bit Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.
3
3
4
4
4
5
6
7
8
9
9
11
12
12
13
13
13
13
14
14
14
14
Digital Transmission Modes: PCM or IOM-2 GCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Digital Transmission Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 PCLK Frequencies and Time Slot Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Hardware Configuration For Transmission Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.
Functional Description - To Do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.
PCM Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.
IOM-2 (GCI) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Monitor Channel Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.
4-Wire SPI (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Data Compression/Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.
Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1
8.2
8.3
8.4
8.5
Rev F
Moisture Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRELIMINARY
36
36
36
36
37
2
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1. Specifications
24 - VDD
23 - VSS
22 - AIN21 - AIN+
20 - AOUT19 - AOUT+
18 - VCC
17 - VEE
16 - VREF
15 - MUTE
14 - D3
13 - D2
PCLK - 1
DRX - 2
DTX - 3
RST - 4
FS - 5
SFSEL - 6
CS - 7
SDO - 8
SCLK - 9
SDIN - 10
D0 - 11
D1 - 12
1.1 Pinout
1.2 Pin Descriptions
Pin Name
Pin #
Pin Type
Description
Power and Ground
VDD
24
Power In
Digital Supply Voltage
VSS
23
Power In
Digital Ground
VCC
18
Power In
Analog Supply Voltage
VEE
17
Power In
Analog Ground
VREF
16
Power Out
Analog Reference Voltage - CREF = 0.22F (From VREF to VEE )
Control Interface
RST
4
Digital Input - PU
CS
7
Digital Input
(Dual Purpose)
D0
D1
D2
D3
11
12
13
14
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
MUTE
15
Digital Input - PU
SCLK
9
Digital Input
(Dual Purpose)
SDI
10
Digital Input
(Dual Purpose)
SDO
8
SFSEL
6
Digital Input/Output
Tri-State
(Dual Purpose)
Digital Input
Active low digital input with internal pull-up (PU). When asserted low, all logic is asynchronously reset.
1) Companding selection during Power-Up or RST. Hold for 40s after Power-Up or RST:
CS = low, Companding = -law; CS = high, Companding = A-law. Can be modified via programming.
2) PCM Mode: SPI bus Chip Select, active low.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
General purpose input/output pin.
Active low digital input with internal pull-up. When asserted low, the analog output amplifier is disabled
and it’s outputs AOUT+ and AOUT- are held at a nominal ½ VCC.
1) PCM Mode: SPI bus clock.
2) GCI Mode: Input, MSB address bit to select sub-frame.
1) Transmission Mode select during Power-Up or Reset. Hold for 40s after Power-Up or RST:
SDI = low, Mode = IOM-2 GCI; SDI = high, Mode = PCM.
2) PCM Mode: SPI bus data input. Connects to the SPI bus master SDO output.
1) PCM Mode: SPI bus data output. Connects to the SPI bus master SDI input.
2) GCI Mode: Input, address bit to select sub-frame used.
GCI Mode: Input LSB address bit to select sub-frame. PCM Mode: Not used.
PCM/IOM-2 Digitized Voice Interface
DRX
2
Digital Input
Receive data for PCM Interface or GCI bus.
DTX
3
Digital Output Tri-State
Transmit data for PCM Interface or GCI bus.
FS
PCLK
5
1
Digital Input
Digital Input
Frame synchronization signal for GCI or PCM Interface bus.
Master clock signal for GCI or PCM Interface bus as well as signal processing.
Analog Interface
AIN+
21
Analog Input
Differential amplifier Non-inverting input.
AIN -
22
Analog Input
Differential amplifier Inverting input.
AOUT+
19
Analog Output
Positive amplifier output, differential 600 driver.
AOUT -
20
Analog Output
Negative amplifier output, differential 600 driver.
Rev F
PRELIMINARY
3
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
1.3 Absolute Maximum Ratings
Unless otherwise noted, Absolute Maximum Ratings are provided over the operational temperature range and all
voltages are referenced to VEE = VSS = 0V.
Parameter
Symbol
Min
Max
Units
- 0.4
3.7
V
DC Supply Voltages
Analog Supply
VCC
Digital Supply
VDD
Input Voltage
Analog Pins
Digital Pins
VIN
- 0.4
VCC + 0.4
VDD + 0.4
V
Output Current
Analog Pins
Digital Pins
Operational Temperature
Storage Temperature
IO
10
mA
TA
- 40
+85
°C
TSTG
- 40
+150
°C
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device.
Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not
implied. Exposure to absolute-maximum rated conditions for extended periods of time may affect device reliability.
1.4 Recommended Operating Conditions
Parameter
Symbol
Min
Typical
Max
Units
3.0
3.3
3.6
V
DC Supply Voltages
Analog Supply
VCC
Digital Supply
VDD
Input Voltage
Analog Pins
Digital Pins
Ambient Temperature
VIN
0
TA
- 40
VCC
VDD
+85
V
°C
1.5 Specifications: General Conditions
Unless otherwise specified:
The characteristics provided in the following tables cover the Operating Ambient Temperature Range -40°C to +85°C;
VCC = VDD = 3.0V to 3.6V, VEE = VSS = 0V.
Additionally, transmission characteristics cover the programmable gain settings; analog input and output
specifications are differential; the test signal and reference signal is 0dBm0 at 1020Hz; and the companding is set to
-law. Signal power given in dBm is referenced to 600 ohms.
NOTE: Characteristics over the transmission gain settings are bounded by the limitations of the companding and the
analog amplifier’s input and output capabilities.
Typical values are for 25°C with nominal supplies and are provided for reference purposes only.
4
PRELIMINARY
Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
1.6 Analog Interface Characteristics
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
Inputs
Input Offset Voltage: AIN+ and AIN-
PD = 0
PD = 1
½ VCC
VIN
V
0
Input Impedance
Differential
Input to Ground (VEE)
Maximum Differential Input Signal
Differential Common Mode Rejection Ratio
Differential Power Supply Rejection Ratio
1
-
RAIN+/-
160
200
240
k
-
RAIN
-
100
-
k
Referenced to
600
-
-
-
+8
dBm
Relative to
-26dBm0,
0 to 3.6kHz
-
60
-
-
dB
-
60
RAIN+/- = Open
0 to 3.6kHz
dB
Outputs
Output Offset Voltage: AOUT+ and AOUT-
PD = 0, MUTE = x
PD = 1
Output drive
½ VCC
VOUT
RL = 500
V
0
mAp
3.2
Referenced to
600
-
-
-
3.2
dBm
-
-
500
600
-

Differential
-
CLD
-
-
250
pF
To GND
-
CL
-
-
50
pF
0 to 3.6kHz
-
60
-
-
dB
Maximum Output Signal
Differential Load Impedance
Load Capacitance
Differential Power Supply Rejection Ratio 1
1
Not tested, guaranteed by design. Power supply rejection is evaluated for sample parts.
Rev F
PRELIMINARY
5
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
1.7 Digital Interface Characteristics
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
Inputs: All logic inputs and all GPIO provisioned as inputs are Schmitt trigger inputs.
Input Voltage
Logic 1 Threshold
-
VIH
-
1.65
2
Logic 0 Threshold
-
VIL
0.8
1.1
-
Hysteresis
-
VHYS
0.3
0.55
0.7
VIN = VSS to VDD
IIN
Input Leakage (Inputs without Pull-Up Resistors and Dx
when provisioned as inputs.)
Pull-Up Resistors: Pins RST & MUTE
V
± 10
A
k
RPU
24
33
42
Outputs
Output Voltage
Logic 1
IOH = -4mA
VOH
VDD-0.3
VDD-0.17
-
Logic 0
IOL = 4mA
VOL
-
0.12
0.3
Leakage: 3-State Off (Hi-Z)
VOZ = VSS to VDD
IOZ
6
PRELIMINARY
± 10
V
A
Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
1.8 Transmit Path: Analog Inputs (AIN+ and AIN-) to Digital Output (DTX) - AC Characteristics
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
0 dBm0, 1020 Hz
-
-0.3
-
0.3
dB
Variation with Frequency (Frequency Response) Relative to 0 dBm0, 1020 Hz
< 60 Hz
< 200 Hz
200 Hz to 300 Hz
300 Hz to 3000 Hz
3000 Hz to 3400 Hz
3400 Hz to 3600 Hz
3600 Hz to 4600 Hz
> 4.6kHz
-0.25
- 0.9
-
-
- 29
0
0.25
0.25
0.25
0.25
0
- 25
dB
Gain
Absolute
Variation with Signal Level (Amplitude Tracking)
Idle Channel Noise
C Message Weighted, -law
P Message Weighted, A-law
Signal to Total Distortion
Relative to 0 dBm0, 1020Hz
+3 dBm0 to -40 dBm0
-40 dBm0 to -50 dBm0
-50 dBm0 to -55 dBm0
dB
Transmit Gain = 0dB
-
-
12
3.2 dBm0
0dBm0 to -30dBm0
- 40 dBm0
- 45 dBm0
30
36
30
25
-
-
-
dBrnC0
dBm0p
dB
Single Frequency Distortion:
Receive any single frequency distortion product.
Any frequency 300 Hz
to 3400 Hz
-46
dB
Intermodulation Distortion
300 Hz to 3400 Hz,
any two frequencies.
-41
dB
315
s
210
130
70
35
70
95
145
s
-75
dB
Envelope Delay Distortion
Absolute
Variation with Frequency
Crosstalk - Receive Path to Transmit Path
Rev F
1600 Hz
Relative to 1600 Hz
500 Hz to 600 Hz
600 Hz to 800 Hz
800 Hz to 1000 Hz
1000 Hz to 1600 Hz
1600 Hz to 2600 Hz
2600 Hz to 2800 Hz
2800 Hz to 3000 Hz
0dBm0,
300 Hz to 3400 Hz,
PRELIMINARY
7
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
1.9 Receive Path: Digital Input (DRX) to Analog Outputs (AOUT+ and AOUT-) - AC Characteristics
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
-0.3
-
0.3
dB
-0.25
- 0.9
-
-
0
0.25
0.25
0.25
0.25
0
- 25
Gain
Absolute
0 dBm0 @1020Hz
Variation with Frequency (Frequency Response) Relative to 0 dBm0, 1020Hz
< 200 Hz
200 Hz to 300 Hz
300 Hz to 3000 Hz
3000 Hz to 3400 Hz
3400 Hz to 3600 Hz
3600 Hz to 4600 Hz
> 4.6kHz
Variation with Signal Level (Amplitude Tracking)
Idle Channel Noise
C Message Weighted, -law
P Message Weighted, A-law
Signal to Distortion
-
Relative to 0 dBm0, 1020Hz
+3 dBm0 to -40 dBm0
-40 dBm0 to -50 dBm0
-50 dBm0 to -55 dBm0
dB
Transmit Gain = 0dB
Alternating positive and
negative PCM zero
codes
Positive zero PCM
code
3.2 dBm0
0dBm0 to -30dBm0
- 40 dBm0
- 45 dBm0
dB
-
-
-
-
-
30
36
30
25
-
12
dBrnC0
dBm0p
-
dB
Single Frequency Distortion:
Receive any single frequency distortion product.
Any frequency 300 Hz
to 3400 Hz
-46
dB
Intermodulation Distortion
300 Hz to 3400 Hz,
any two frequencies.
-41
dB
200
s
90
125
175
s
Envelope Delay Distortion
Absolute
Variation with Frequency
Spurious Out of Band Signals
Crosstalk - Transmit Path to Receive Path
Mute Signal Attenuation
8
1600 Hz
Relative to 1600 Hz
500 Hz to 1000 Hz
1000 Hz to 1600 Hz
1600 Hz to 2600 Hz
2600 Hz to 2800 Hz
2800 Hz to 3000 Hz
-40
-30
0dBm0, 300 Hz to 3400 Hz
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8400 Hz to 50 kHz
dB
0dBm0,
300 Hz to 3400 Hz,
PCM DRX = Positive
zero code
Input 0dBm0, 1020Hz
PRELIMINARY
90
-
-75
dB
-
dB
Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
Parameter
Noise Single Frequency
Conditions
Symbol
Tie DTX to DRX, 0 Hz to
100kHz, VIN = 1Vrms,
VOUT
Minimum
Typical
Maximum
Units
-53
dB
1.10 Power Characteristics
IDC = ICC + IDD
Parameter
Conditions
Symbol
Minimum
Typical
Maximum
Units
Power-On Reset Voltage (Voltage at Which Reset is Active)
VDD Rising
VPOR
-
1.3
2
V
Power-On Reset
Reference Voltage
VREF
V
Power Supply Current
Total Supply Current, Device Shut Down
Total Supply Current, Device Active
A
IDC
-
1
IDC
-
7.5
Conditions
Symbol
Minimum
Typical
Maximum
Units
-
TPOR
-
20
40
TRST
-
20
-
s
PD = 1
PD = 0, No AC
transmission
20
mA
1.11 Power-On Reset
Parameter
Power-On Reset Period
De-Bounce Time
NOTE: With VDD rising, VIH = VDD for VDD < VPOR_MAX.
Rev F
PRELIMINARY
9
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
2. Control Registers
The control registers are used to set up operating characteristics, transmit/receive gains, PCM time slot assignments
and GPIO control. Access to these registers is dependent on the transmission mode set by the logical state of SDI
(pin 10) during a Reset or Power-Up event. With SDI held at a logic high, the device is configured for PCM Mode and
register access is only available via the SPI bus. When SDI is held at a logic low, the device is configured for IOM-2
GCI Mode and register access is only available through the GCI data link.
NOTE: PCLK and FS must be active before a write command is issued to the control registers, otherwise the written
values will not be retained.
Power Up and Reset events set the device’s Power Down bit (PD) to a logic high which disables the input and output
analog amplifiers and if configured for PCM Mode, disables the upstream digital signal and places the DTX output into
a high impedance state. After provisioning the control registers and if necessary, assigning the PCM interface to the
proper time slot, PD can be set low to begin operation. The GCI Mode does not allow changing the time slot of the
digitized voice data.
The table below shows the CPC5750 control register names, the bit names, and the register address. Access to the
registers is only available via read or write commands. The structure of a register command consists of two parts; first
is the command type nibble which is followed immediately by the register address nibble. Write commands will be
followed by the data word to be stored in the addressed register. The first four bits (nibble) of a read command are
1010 (0xA) while the write command’s first four bits (nibble) are 1011 (0xB). Following the command type nibble is the
register address nibble as provided in the table below. As an example, the command to read back the value
provisioned into the PCM Transmit Time Slot register is: 0xA7. Detailed discussions of each register are provided in
the following sections.
Table 1: Control Registers
Register Name
(MSB)
7
Mode Control
Companding
TX Gain: ±1dB Steps
Not Used
TX Gain: ±0.1dB Steps Not Used
RX Gain: ±1dB Steps
Not Used
RX Gain: ±0.1dB Steps Not Used
PCM DRX Time Slot
Not Used
PCM DRX Bit Delay
Not Used
Bits
Address
6
5
4
3
2
1
0
Dec
Hex
Not Used
ALB
DLB
[4:0]
PD
CPB
TXZ
TM
0
1
2
3
4
5
0x0
0x1
0x2
0x3
0x4
0x5
[3:0]
[4:0]
[3:0]
[6:0]
[2:0]
PCM DTX Time Slot
Not Used
[6:0]
PCM DTX Bit Delay
Not Used
0
DIR(3)
0
DIR(2)
Reserved
GPIO Control
(LSB)
0
DIR(1)
0
DIR(0)
0
D(3)
[2:0]
0
D(2)
0
D(1)
0
D(0)
6
0x6
7
0x7
8
9
10
0x8
0x9
0xA
NOTE: All registers are Read / Write and all user defined bits are Read / Write.
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2.1 Mode Control Register
This register allows the programmable control of the Companding, analog and digital loop backs for debug testing,
Power Down mode, and custom control of the PCM interface.
Register
Mode Control
Default
7
6
Companding
Not Used
0
(CS Level at Reset)
5
4
3
2
1
0
Address
ALB
0
DLB
0
PD
1
CPB
0
TXZ
0
TM
0
0x0
-
2.1.1 Companding (bit 7)
This bit determines the data compression method to be used. The value of this bit during Power Up or Reset is
determined by the level on CS (pin 7) when the chip reset goes inactive. During either of these events the logical
level on CS must be maintained for a minimum duration of 40s. For Power Up, the hold time begins with a valid
VDD level and a logic high at RST (pin 4). For an external reset (RST = 0) the hold time begins with a logic high at
RST. Once active, this bit can be modified using the SPI interface (PCM Mode) or the GCI link (IOM-2 GCI Mode).
The bit values to set the compression method are:
Logic '0': -law
Logic '1': A-law
2.1.2 ALB (bit 5)
The Analog Loop Back (ALB) bit is used to test the analog interface of the CPC5750 by connecting the output of
the analog input amplifier to the input of the analog output amplifier. To prevent received digital information from
interfering with the test, the connection between the DAC and the input of the analog output amplifier is opened.
This provides an all-analog test path from the AIN+ and AIN- inputs to the AOUT+ and AOUT- outputs. Additionally
the analog to digital transmit path remains intact, allowing the means to monitor the analog input gain. The bit
values to activate and de-activate the Analog Loop Back are:
Logic '0': Normal Operation (Analog Loop Back disabled)
Logic '1': Analog Loop Back Mode
2.1.3 DLB (bit 4)
The Digital Loop Back (DLB) bit is used to test the digital interfaces, (PCM or GCI) and the DSP sections of the
CPC5750 by separating the transmit path analog input section and ADC from the transmit DSP section and
connecting the digital output of the receive path DSP to the digital input of the transmit path DSP. This provides an
all-digital test path through the receive path’s DAC filters and Noise Shaper and back out through ADC digital
filters. The DLB configuration retains the connection between the receive path’s digital and analog sections
providing the means to monitor the converted receive digital signal at the AOUT+ and AOUT- analog outputs. The
bit values to control the Digital Loop Back function are:
Logic '0': Normal Operation (Digital Loop Back disabled)
Logic '1': Digital Loop Back Mode
2.1.4 PD (bit 3)
The Power-Down (PD) bit is used to put the CPC5750 in a standby mode where it draws very little current.
Logic '0': Normal Operation
Logic '1': Device is Powered Down. The SPI bus interface (PCM Mode) and GCI link (GCI Mode)
are still functional to allow enabling the part. The GCI interface will draw current if clocked
externally. In PCM Mode, DTX is set to high impedance (Hi-Z).
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2.1.5 CPB (bit 2)
The Clocks Per Bit (CPB) selection bit is used to set the number of PCM clock cycles per bit of transmit and
receive data transfer at either 1 clock-per-bit or 2 clocks-per-bit. This programmable option is only used in PCM
Mode as the clock rate is auto-detected in GCI Mode.
Logic '0': 1 Clock cycle Per data Bit
Logic '1': 2 Clock cycles Per data Bit
2.1.6 TXZ (bit 1)
The PCM data Tri-state (TXZ) selection bit is used to set when the PCM transmit output driver, DTX, goes high
impedance.
Logic '0': Tri-State on the first PCLK Rising Edge following the LSB of the time slot.
Logic '1': Tri-State on the PCLK Falling Edge during the LSB of the time slot. (The second falling
edge of PCLK when CPB = 1.)
2.1.7 TM (bit 0)
Reserved: This bit is not user defined and it’s value should not be modified. The default power up and reset value
of this bit is 0 and must not be changed.
2.2 TX Path Gain: ±1dB Steps Register
FIve bits of this register determine the analog input amplifier gain in 1 dB steps as shown in the following table.
Register
TX Path Gain: ±1dB Steps
Default Value
7
6
5
4
3
2
1
0
Address
0
0
0
TXG(4)
0
TXG(3)
0
TXG(2)
0
TXG(1)
0
TXG(0)
0
0x1
-
2.2.1 TXG (bits [4:0])
TXG is a 5-bit, 2's complement number between -12 and 12. This value sets the transmit path gain in 1 dB
increments. Values of TXG larger than +12 set a gain of +12dB. Values of TXG less than -12 set a gain of -12dB.
2.3 TX Path Gain: +0.1dB Steps Register
Four bits of this register determine the analog input amplifier gain in 0.1 dB steps as shown in the following table.
Register
TX Path Gain: +0.1dB Steps
Default Value
7
6
5
4
3
2
1
0
Address
0
0
0
0
TXB(3)
0
TXB(2)
0
TXB(1)
0
TXB(0)
0
0x2
-
2.3.1 TXB (bits [3:0])
TXB is a 4-bit number between 0 and +9. This value increases the transmit path gain in 0.1dB increments. These
bits are used in conjunction with the TXG bits to define a 9-bit gain value from -12dB to +12.9dB in 0.1dB steps.
For example, to set the transmit gain to -0.1dB, the TXG bits are set for -1dB (11111) and the TXB bits are set for
+0.9dB (1001). The nine bit value 111111001(binary) provides for a transmit gain = -1dB + 0.9dB = -0.1dB;
EX2: 111110000 = -1dB; EX3: 001110011 = +7.3dB. Values of TXB are always positive and values greater
than 9 continue to define the gain as +0.9dB.
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2.4 RX Path Gain: ±1dB Steps Register
FIve bits of this register determine the analog output amplifier gain in 1 dB steps as shown in the following table.
Register
RX Path Gain: ±1dB Steps
Default Value
7
6
5
4
3
2
1
0
Address
0
0
0
RXG(4)
0
RXG(3)
0
RXG(2)
0
RXG(1)
0
RXG(0)
0
0x3
-
2.4.1 RXG (bits [4:0])
RXG is a 5-bit, 2's complement number between -12 and 12. This value sets the receive path gain in 1dB
increments. Values of RXG larger than +12 set a gain of +12dB. Values of RXG less than -12 set a gain of -12dB.
2.5 RX Path Gain: +0.1dB Steps Register
Four bits of this register determine the analog output amplifier gain 0.1 dB steps as shown in the following table.
Register
RX Path Gain: +0.1dB Steps
Default Value
7
6
5
4
3
2
1
0
Address
0
0
0
0
RXB(3)
0
RXB(2)
0
RXB(1)
0
RXB(0)
0
0x4
-
2.5.1 RXB (bits [3:0])
RXB is a 4-bit number between 0 and +9. This value increases the receive path gain in 0.1 dB increments. These
bits are used in conjunction with the RXG bits to define a 9-bit gain value from -12 to +12.9dB in 0.1 steps. For
example, to set the receive gain to -3.1dB, the RXG bits are set for -4dB (11100) and the RXB bits are set for
+0.9dB (1001). The nine bit value 111001001(binary) provides for a receive gain = -4dB + 0.9dB = -3.1dB;
EX2: 110110011 = -5dB + 0.3dB = -4.7dB; EX3: 010011000 = +9.8dB. Values of RXB are always positive and
values greater than 9 continue to define the gain as +0.9dB.
2.6 PCM Interface DRX Time Slot Assignment Register
The lower seven bits of this register determine which of the available 8-bit time slots the CPC5750 uses to receive
data when in the PCM Mode.
Register
PCM DRX Time Slot
Default Value
7
6
5
4
3
2
1
0
Address
0
PRC(6)
0
PRC(5)
0
PRC(4)
0
PRC(3)
0
PRC(2)
0
PRC(1)
0
PRC(0)
0
0x5
-
2.7 PCM Interface DRX Bit Delay Register
The lower three bits of this register delay the receiver from reading the selected time slot by 0 to 7 bits.
Register
PCM DRX Bit
Default Value
Rev F
7
6
5
4
3
2
1
0
Address
0
0
0
0
0
PRB(2)
0
PRB1)
0
PRB(0)
0
0x6
-
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2.8 PCM Interface DTX Time Slot Assignment Register
The lower seven bits of this register determine which of the available 8-bit time slots the CPC5750 uses to transmit
data when in the PCM Mode.
Register
PCM DTX Channel
Default Value
7
6
5
4
3
2
1
0
Address
0
PTC(6)
0
PTC(5)
0
PTC(4)
0
PTC(3)
0
PTC(2)
0
PTC(1)
0
PTC(0)
0
0x7
-
2.9 PCM Interface DTX Bit Delay Register
The lower three bits of this register delay the transmit data in the selected time slot by 0 to 7 bits.
Register
PCM DTX Bit
Default Value
7
6
5
4
3
2
1
0
Address
0
0
0
0
0
PTB(2)
0
PTB1)
0
PTB(0)
0
0x8
-
2.10 Reserved Register
The Reserved register is not user defined and it’s value should not be modified. The default power up and reset value
of this register is 0 and must not be changed.
Register
Reserved
7
6
5
4
3
2
1
0
Address
0
0
0
0
0
0
0
0
0x9
2.11 GPIO Control Register
The CPC5750 has four General Purpose I/O pins that can be programmed as inputs or outputs and whose values
can be examined or controlled by the user. This register allows for control and monitoring of external digital nets using
these I/O pins.
Register
GPIO Control
Default Value
7
6
5
4
3
2
1
0
Address
DIR(3)
0
DIR(2)
0
DIR(1)
0
DIR(0)
0
D(3)
0
D(2)
0
D(1)
0
D(0)
0
0xA
-
2.11.1 DIR(x) (bits [3:0])
Setting a DIR(x) bit to 1, configures the corresponding CPC5750 I/O pin as an output. When the DIR(x) bits are
cleared, i.e. DIR(x) = 0, the corresponding I/O pin will be configured as an input. Following a Power Up or Reset
the CPC5750 configures all four I/O pins as inputs thereby eliminating any possibility of an I/O pin back driving
another output.
2.11.2 D(x) (bits [3:0])
When an I/O is configured as an input, then reading the corresponding D(x) bit of this register gives the logical
state of that input pin. Writing to the D(x) bits of inputs performs no function while writing to the D(x) bit of an I/O
configured as an output determines the state of that output pin. Reading this register returns the current value of
the bits. For an I/O pin configured as an output, reading this register returns the last value written to it’s D(x) bit.
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3. Digital Transmission Modes: PCM or IOM-2 GCI
The CPC5750 was designed to be used in communication systems utilizing either the traditional PCM bus method of
digital transmission flow or the newer IOM-2 GCI bus. Both operational modes make use of the 4-wire digital
transmission bus consisting of the data clock (PCLK), an 8kHz Frame Synchronization clock (FS), an upstream
transmit data signal (DTX) and a downstream receive data signal (DRX). Although both modes use this 4-wire bus, the
data structure within the digital transmit and receive streams is dissimilar.
One major difference between the PCM Mode and the GCI Mode of operation is how provisioning, control and status
is implemented. When operating in the PCM Mode a serial (SPI) bus is utilized to perform these functions. In the GCI
Mode these functions are embedded in the transmit and receive data streams, thereby eliminating the need for an
additional bus for command and control.
3.1 Digital Transmission Mode Selection
Configuring the CPC5750 to operate in PCM or GCI Mode is performed during either a Power Up or Reset event
using the level at the SDI input pin to determine the mode. Holding SDI high will cause the CPC5750 to be placed into
the PCM Mode of operation while holding SDI low will result in the GCI Mode.
For PCM applications, the voltage available at SDI during power up may not satisfy the specified logic high threshold
voltage stated in Section 1.7 Digital Interface Characteristics on page 6. To ensure a logic high is recognized at
the SDI input during power up, the input should be biased to VDD. As the VDD supply rises towards the Power On
Reset threshold, the CPC5750 will accept the VDD voltage level at SDI as a logic high.
Because the GCI Mode does not utilize the SPI bus, those applications should tie the SDI input low and the CS input
to the appropriate logic level dependent on the desired companding. The companding method set by CS during
Power Up or Reset can be overridden by provisioning bit 7 of the Mode Control register.
3.2 PCLK Frequencies and Time Slot Selection
The clocking circuits use the Frame Sync (FS) signal from the PCM or IOM-2 bus to automatically determine the
PCLK frequency and divides or multiplies the clock as necessary to generate an on-chip 1.024MHz clock.
The table below shows the allowed PCLK frequencies for both the PCM and GCI Modes and the time slot allocations.
For the PCM Mode there are eight allowed PCLK frequencies while the IOM-2 GCI Mode has only two. When using
the PCM Mode, the maximum number of available time slots is dependent on the number of eight bit channels that
can be transferred within one period of the 8kHz Frame Sync clock. For all systems, the maximum number of time
slots is the PCLK frequency divided by the Frame Sync frequency divided by the number of clock bits (pulses) per
channel. A system that uses one clock bit for each transmission bit, the number of time slots is the PCLK frequency
divided by 8kHz divided by 8 clock pulses which is PCLK / 64kHz. PCM systems using two PCLK pulses per
transmission bit will need to set bit 2 of the Mode Control register to a logic 1. Calculating the number of time slots is
now PCLK frequency / 128kHz. The table below provides a quick reference.
Assignment of the specific time slot to be used when in PCM Mode is done by provisioning the PCM transmit and
receive time slot assignment registers described in Section 2.8 and Section 2.6 beginning on page 13.
Only two PCLK frequencies are allowed for the IOM-2 GCI Mode and the number of available time slots is
independent of the clock frequency. Because the number of time slots in GCI Mode is fixed and the higher allowed
frequency is twice the lower allowed frequency, the CPC5750 will use two PCLK bits per transmission bit when it
detects the higher allowed PCLK frequency. This is shown in the following table.
Available time slots for the IOM-2 GCI Mode is based on the number of available sub-frames. The IOM-2 GCI
definition provides for eight sub-frames within a single frame defined by the time period of the Frame Sync clock.
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Although the IOM-2 specification provides for two digitized voice time slots per sub-frame, the CPC5750 only uses the
B1 time slot. This allows for a total of eight available time slots when operating in the GCI Mode.
Selection of the sub-frame is not a provisioning option. It is done by applying the appropriate logic levels at pins:
SCLK, SDO, and SFSEL. See Section 6 IOM-2 (GCI) Interface beginning on page 23 and Table 4 on page 23
for more details.
Table 2: PCLK Frequencies and Available PCM Time Slots
Frequency
Available PCM Time Slots
CPB = 0
(1 Clock per bit)
512kHz
1.024MHz
1.536MHz
2.048MHz
3.072MHz
4.096MHz
6.144MHz
8.192MHz
Available PCM Time Slots
CPB = 1
(2 Clocks per bit)
GCI Frequency
8
4
No
16
8
No
24
12
No
32
16
Yes: 1 Clock per bit
48
24
No
64
32
Yes: 2 Clocks per bit
96
48
No
128
64
No
3.3 Hardware Configuration For Transmission Mode Selection
To ensure correct initialization of the CPC5750 following a Power Up or Reset event, the appropriate inputs must be
properly conditioned.
PCM Mode: SDI = 1 and CS = x
GCI Mode: SDI = 0 and CS = x;
Also, the sub-frame selection using SCLK, SDO, and SFSEL must be made at this time.
Failure to condition and hold these inputs at the appropriate logic level for the specified duration during Power Up or
Reset will require a Reset to re-initialize the device.
While the input CS may be conditioned to configure the CPC5750 for the desire companding method, this can be
modified via provisioning once the part becomes active.
Special Notes:
1) SDI and CS are not used in normal operation of the GCI Mode, therefore it is recommended that these
unused inputs be fixed to a stable logic level.
2) For the PCM Mode, SFSEL is an unused input and should be fixed to a stable logic level.
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4. Functional Description - To Do
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5. PCM Bus Interface
The PCM bus consists of four signals: PCLK, FS, DTX, and DRX which are used to transmit and receive one byte each
(eight bits) of -law or A-law companded audio data every cycle of the 8kHz Frame Sync (FS) clock. This provides for
a 64k bit per second data rate in each direction. Provided within each frame (cycle of the FS clock) are a number of
8-bit time slots determined by the frequency of PCLK and the value assigned to the CPB bit in the Mode Control
register. The number of available time slots is calculated as the PCLK frequency (variable) divided by the FS
frequency (fixed at 8kHz) divided by the number of PCLK cycles per data byte (variable, 8 or 16 controlled by CPB).
The relationship between the PCLK frequency and CPB to the number of available PCM time slots is shown in
Table 2: PCLK Frequencies and Available PCM Time Slots.
Capable of transmitting (upstream) and receiving (downstream) in separate time slots, the CPC5750 PCM upstream
and downstream data paths can be provisioned independently to any of the available time slots within the frame.
Additionally, the upstream and downstream paths can be provisioned independently for bit delays within the time slot.
While the non-delayed timing mode does not have bit delays, the delayed timing mode does. To provide for bit delays
within the system, the CPC5750 allows the user to provision the time slot starting point to any of the possible bits
within the 125s frame. This requires 10 bits to accommodate the device’s 128 maximum time slots. The lower 3 bits
used to modify the start bit (MSB) position within a time slot is in a separate register from the time slot assignment
register to ease provisioning for applications that require setting only the 8-bit time slot or just the bit delay, allowing
the other register to be ignored.
The CPC5750 PCM bus is a 4-wire full duplex digital transmission medium using two data wires, DTX and DRX, so
data can be transmitted and received simultaneously. The DTX transmit signal used to send data upstream is output
onto a common bus. Since other devices assigned to different time slots transmit their upstream data onto this same
bus, the CPC5750 must tri-state DTX during all non-assigned time slots. Determination of when DTX tri-states after it
outputs 8-bits of data is contingent upon the value set in the Mode Control register’s TXZ bit. For provisioning details
see Section 2.1.6 TXZ (bit 1) and Section 2.1.5 CPB (bit 2) beginning on page 12.
Time slot locations within the transmit and receive data bit streams are defined by the location of the Frame
Synchronization (FS) pulse and the value set in bit delay registers as described in Section 2.9 PCM Interface DTX
Bit Delay Register and Section 2.7 PCM Interface DRX Bit Delay Register beginning on page 13. Historically,
timing of data bit streams was defined by two modes, Non-delayed Timing Mode and Delayed Timing Mode by means
of a Long Frame Sync pulse and a Short Frame Sync pulse to establish a reference point for the first bit of the first
time slot of the frame.
The Non-delayed Timing Mode used the Long Frame Sync as an enable to define the location of the time slot. The
first data bit of the Long Frame Sync time slot was defined as the first concurrent logic high of the PCM clock and the
frame sync pulse. In this configuration there is no requirement for the rising edge of the clock or the sync pulse to
precede the other. Because the Long Frame Sync pulse is an enable, the width of pulse needs to be sufficient to
ensure data transfer of all eight bits.
The Delayed Timing Mode used the Short Frame Sync to establish the beginning of the first time slot within the frame.
This method used the first falling edge of the PCM clock to register the frame synchronization pulse marking the end
of the current frame. With the conclusion of the current frame, the first bit of the next frame begins with the next rising
edge of the PCM clock. Because this method provides an indicator prior to the beginning of the frame it is ideal for use
in systems wishing to delay data transfer.
The CPC5750 uses a timing mode that is compatible with both of these legacy techniques. Interoperability is assured
by the internal timing circuitry and the device’s ability to access the data bit stream at any point within the frame. In the
CPC5750, the first bit of the frame is defined as coincident with the PCLK rising edge preceding the falling PCLK
edge used to detect the active FS pulse.
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Because the first transmitted data bit is in the same bit time as the FS pulse, the DTX driver must be enabled with the
correct data before the FS signal is detected. For this to happen, the CPC5750 must count the PCLK cycles in the first
complete frame to determine the number of 8-bit time slots per frame so it can predict when to drive the DTX bus. If
the FS pulse does not arrive as predicted, then the CPC5750 will re-synchronize, and recount the time slots in the
frame. For this reason the data in the first two received frames after connection to a PCM bus will be ignored and no
data will be transmitted upstream.
Detection of the FS pulse with the PCLK falling edge eliminates the rigid FS pulse width constraints and the required
synchronization of the FS rising edge with the PCLK rising edge. The minimum FS pulse width is the sum of the setup
and hold times while the maximum pulse width must allow for a minimum of one FS low detect by the falling PCLK
edge.
Assuring the first upstream data bit is available with the rising edge of FS and allowing the FS pulse to persist for
multiple PCLK cycles provides compatibility with the legacy Long Frame Sync, Non-delayed Timing Mode when the
time slot and bit delay setting registers are configured for the first bit of the first time slot, (Time Slot 0 {zero} and no bit
delay) of the frame. Additionally, since the CPC5750 is designed to accept small FS pulses and can be provisioned for
the transfer of data delayed by one or more bits it is compatible with the legacy Short Frame Sync Delayed Timing
Mode. As with the legacy data bit stream formats, the Most Significant Bit (MSB) will be the first bit received and the
first bit transmitted in the data byte.
Figure 1: PCM Time Slot 0, Short FS, No Bit Delay (PTC=PRC=0, PTB=PRB=0, CPB=0, TXZ=1)
FS
PCLK
1
FRAME BIT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB
DTX
HI-Z
HI-Z
MSB
Rev F
LSB
LSB
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Figure 2: PCM Time Slot 0, Long FS, No Bit Delay (PTC=PRC=0, PTB=PRB=0, CPB=0, TXZ=1)
FS
PCLK
1
FRAME BIT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB
DTX
LSB
HI-Z
HI-Z
Figure 3: PCM Time Slot 1, Long FS, 2 Bit Delay (PTC=PRC=1, PTB=PRB=2, CPB=0, TXZ=1)
FS
PCLK
1
FRAME BIT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
MSB
LSB
HI-Z
DTX
HI-Z
MSB
20
PRELIMINARY
LSB
Rev F
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Figure 4: PCM Time Slot 0, Short FS, No Bit Delay, 2x PCLK (PTC=PRC=0, PTB=PRB=0, CPB=1, TXZ=1)
FS
PCLK
1
FRAME BIT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
DTX
MSB
LSB
MSB
LSB
HI-Z
HI-Z
Table 3: PCM Interface AC Characteristics
Ambient temperature range -40°C to +85°C; VCC=VDD=3V to 3.6V
Parameter
FS Period
FS Jitter
PCLK Cycle Time
PCLK Duty Cycle
PCLK Jitter
PCLK Rise Time
PCLK Fall Time
DTX Data Access Valid from PCLK Rising
DTX Tri-State from PCLK Rising
DTX Tri-State from PCLK Falling
FS Setup Time to PCLK Falling
FS Hold Time from PCLK Falling
DRX Data Setup Time to PCLK Falling
DRX Data Hold Time from PCLK Falling
Rev F
Test Condition
Symbol
Min
Typ
20% to 80%
20% to 80%
TXZ = 0
TXZ = 1
-
tFP
-
tFJ
-
tPC
PRELIMINARY
Max
Units
125
-
s
-
100
ns
122
40
50
1955
60
%
tPJ
-
-
±2
tPR
-
-
25
tPF
-
-
25
tTXDA
-
-
20
tTRIR
-
-
20
tTRIF
-
-
20
tFSU
25
-
-
tFHD
20
-
-
tRXSU
25
-
-
tRXHD
20
-
-
21
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Figure 5: AC Timing for PCM Time Slot 0, 1 Bit Delay (PTC=PRC=0, PTB=PRB=1, CPB=0)
tFP
FS
tFSU
tFHD
tFSU
tPC
tFHD
PCLK
DTX
D7
(TXZ=1)
D6
D1
D0
tTRIF
tTXDA
DTX
D7
(TXZ=0)
D1
D6
D0
tTRIR
D7
DRX
D1
D6
tRXSU
D0
tRXHD
Figure 6: AC Timing for PCM Time Slot 0, 1 Bit Delay, 2x PCLK (PTC=PRC=0, PTB=PRB=1, CPB=1)
tFP
FS
tFSU
tFSU
tPC
tFHD
tFHD
PC LK
D7
DTX(TXZ=1)
D6
D5
tTXDA
tTRIF
D7
DTX(TXZ=0)
D0
D6
D5
D0
tTRIR
D7
DR X
D6
D5
D0
tRXSU
tRXHD
22
PRELIMINARY
Rev F
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
6. IOM-2 (GCI) Interface
IOM-2 is a superset specification that includes the General Circuit Interface (GCI), the line card portion of the
specification. The CPC5750 implements the GCI part of this bus as specified in the Advanced Micro Devices
document, IOM-2 Interface Reference Guide.
The GCI bus has an 8kHz frame sync pulse that indicates the start of each frame. Each frame consists of 8 sub-frame
locations with 4 bytes per sub-frame. The CPC5750 can be configured to transmit and receive on any of these
sub-frames. The selection of which sub-frame to use is done with the three pins; SCLK, SDO and SFSEL. The SPI
pins SCLK and SDO are utilized since the SPI bus is not used when in the GCI Mode. The logical value of these three
inputs when reset is complete sets the sub-frame assignment. Sub-Frame assignments are shown in logic table
below.
Table 4: GCI Mode Sub-Frame Selection
SCLK
SDO
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
SFSEL
Sub-Frame
L
0
H
1
L
2
H
3
L
4
H
5
L
6
H
7
The 4 bytes within each sub-frame are considered communication channels. The 32 bits of the sub-frame are
designated for specific use by the standard. Each sub-frame can support a pair of codecs, one each for channels B1
& B2. Although the CPC5750 uses the entire sub-frame, only B1 is used.
(32 bits per sub-frame) x (8 sub-frames) x (8kHz frame rate) x (2 clocks per bit) = 4.096MHz clock. There is also a
mode that uses 1 clock per bit for a 2.048MHz clock rate.
Figure 7: GCI Sub-Frame Makeup
125µs
FSYNC
SF0
SF1
SF2
SF3
SF4
SF5
SF6
SF7
Sub-Frame
8
B1
8
B2
8
M
C/I
0
1
2
6
Channel
MR MX
1
1
SC Channel
Time-Multiplexed GCI Frame Structure
Rev F
B1:
Channel slot used to transmit and receive audio data by CPC5750
M:
Channel used to read and write CPC5750 control registers
SC:
Channel used to control CPC5750 register access
PRELIMINARY
23
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Figure 8 and Figure 9 show the timing relationships between the GCI bus signals used to transmit and receive PCM
data and register data when in the GCI Mode. The single-clock or double-clock mode is detected automatically by the
CPC5750 in GCI Mode.
Table 5: GCI Interface AC Timing
Parameter
Test Condition
Symbol
Min
Typ
Max
Units
FS Period
-
tFP
-
125
-
s
FS Jitter
-
tFJ
-
-
±120
PCLK Cycle Time - Single-Clocking Mode
-
tPC
-
488
-
PCLK Cycle Time - Double-Clocking Mode
-
tPC
-
244
-
PCLK Jitter
-
tPJ
-
-
±2
PCLK Rise Time
20% to 80%
tPR
-
-
25
PCLK Fall Time
20% to 80%
tPF
-
-
25
-
tTXDA
-
-
20
TXZ = 0
tTRIR
-
-
20
TXZ = 1
tTRIF
-
-
20
-
tFSU
25
-
-
TX Data Access Valid from PCLK Rising
DTX Tri-State from PCLK Rising
DTX Tri-State from PCLK Falling
FS Setup Time to PCLK Falling
FS Hold Time from PCLK Falling
DRX Data Setup Time to PCLK Falling
-
tFHD
20
-
-
-
tRXSU
25
-
-
DRX Data Hold Time from PCLK Falling
-
tRXHD
20
-
-
ns
Figure 8: GCI Interface AC Timing with 1x PCLK
tPC
tFHD
FS
tFP
PCLK
tFSU
tRXSU
tTRIR
DRX
tRXSU
tTRIF
tRXHD
DTX
tTXDA
24
PRELIMINARY
Rev F
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Figure 9: GCI Interface Timing with 2x PCLK
tPC
tFHD
FS
tFP
PCLK
tRXSU
tFSU
tTRIR
DRX
tRXHD
tTRIF
DTX
tTXDA
tTXDA
6.1 Monitor Channel Operations
The Monitor (M) channel is used for reading and writing the CPC5750's registers. The Monitor channel requires the
use of the MR and MX bits in the SC channel for handshaking.
All Monitor channel transfers are in the following format:
1.
Device Address: 0x91 for normal transfers, 0x90 for the special “Channel Identification Command”
2.
Command: 0x81 for a read, 0x01 for a write, 0x00 for the “Channel Identification Command”
3.
Address: 0x0 - 0xA corresponding to register address in Table 1: Control Registers (Not sent for “Channel
Identification Command”)
4a. Write commands follow the address with up to 11 data bytes
4b. Read commands terminate after the address, and are followed by a write sequence (controlled by the CPC5750)
that transfers data to the host device
4c. The special “Channel Identification Command” is terminated after the command byte is sent
(The CPC5750 responds by controlling a write sequence to the host of two fixed bytes: 0x90, 0xB8)
Before a Monitor channel command can be started by the host device, the MX and MR bits must be inactive (high) for
at least two frames. To initiate a transfer of data by the host device, the MX bit should be set active by the external
controller. This signals the CPC5750 to look for a transmission on the Monitor channel. To confirm that the data was
received, the CPC5750 asserts the MR bit. Once confirmation is complete, the external controller makes the MX
inactive for one frame, then, if it is to continue to transmit, it sets the MX bit active again; otherwise, it ends the
message by leaving the MX bit inactive for another frame.
Rev F
PRELIMINARY
25
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
When writing data, an initial address must be specified. Once the data is written to that address, the CPC5750
automatically increments the address after every register access so that in one transmission multiple consecutive
registers can be written (see Figure 11). The transmission can continue until either an invalid memory location is
reached or the host device sends two frames with MX inactive.
When the host device wants to read a register or registers, it begins by controlling the MX bit, and the CPC5750
controls the MR bit exactly as in a write command except that the second byte sent is the read command code 0x81.
The third byte sent is the register address to be read first. The CPC5750 responds by controlling its MX bit to begin a
write transfer to the host device. This transfer begins with the contents of the register addressed in the read
command, and auto-increments the register address for each byte read (see Figure 10). When the CPC5750 is not
executing a read command from the host, it transmits 0xFF on the monitor byte.
The CPC5750 can also signal an abort by sending two frames with the MR bit inactive. The CPC5750 will signal an
abort if:
•
•
•
•
The host device attempts to read or write from an invalid memory location
The CPC5750 does not recognize the command it received
The data byte received was not held for at least two consecutive frames
A collision occurs on the monitor data bytes while the CPC5750 is transmitting (see Figure 12, Figure 13,
and Figure 15).
If an invalid command is received, the state of the CPC5750 does not change. If the host device attempts to read or
write to an invalid memory address, the previous reads or writes to the memory are still valid. If the abort signal is
detected before a command has been sent, the CPC5750 returns to an idle state and no changes are made.
26
PRELIMINARY
Rev F
Rev F
PRELIMINARY
MR BIT LEVEL
MX BIT LEVEL
Monitor Slot Data
XX
125µs
One frame
time
XX
MR transition allows
transmitter to send next
XX
Device Address
for 2 frames
Read Command
for 2 frames
Register Address
for 2 frames
XX
XX
XX
MX must go high
before receive brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next data
transmitted
Data
Received
XX
XX
Except for second byte,
MR must go high before
transmitter brings MX
high. Receiver may hold
off next byte by holding
MR low if data in both
frames does not match.
For high speed,
transmitter assumes MR
bit will go low next
frame.
Next data
transmitted
0x91 0x91 0x81 0x81 0x01 0x01
High to Low
indicates data
received
High to low indicates
data transmitted
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
MR BIT LEVEL
MX BIT LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
Host Device
Data from 2 frames must match or transfer is aborted
by the receiver holding MR high for 2 frames.
Data
Received
XX
XX
XX
CPC5750
Transmits Address
before requested data
0x91
Data
Received
End of message
2 frames high
0x91
XX
XX
Contents of Mode
Control Register
Next Data
Transmitted
Contents of Mode
Control Register
MX must go high
before receiver
brings MR high
XX
XX
Contents of RX
Contents of RX
Gain +/-1dB
Gain +/-1dB
Register
Register
Next Data
Transmitted
Register Address
autoincrement
XX
Contents of RX
Gain +0.1dB
Register
Register Address
autoincrement
Except for second byte,
MR must go high before
transmitter brings MX
high. Receiver may hold
off next byte by holding
MR low. For high speed,
transmitter assumes MR
bit will go low next frame.
Data
Received
XX
XX
XX
XX
End of Message
2 Frames High
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 10: Example GCI Read from Mode Control and RX Gain ±1dB Registers
27
28
MR LOGIC LEVEL
PRELIMINARY
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
XX
125µs
XX
MR transition allows
transmitter to Send Next
XX
Write Command
for 2 frames
Register Address
for 2 frames
Write Data for
Mode Control
Write Data for
RX Gain +/- 1dB
XX
XX
XX
MX must go high
before receiver brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next data
transmitted
Data
Received
XX
XX
XX
Data
Received
Except for second byte,
MR must go high before
transmitter brings MX
high. Receiver may hold
off next byte by holding
MR low if data in both
frames does not match.
For high speed,
transmitter assumes MR
bit will go low next
frame.
Next data
transmitted
XX
Next data
transmitted
Data
Received
XX
XX
XX
Data
Received
XX
XX
MX high for
second frame
indicates
“End of Message”
0x91 0x91 0x01 0x01 0x01 0x01 BYTE0 BYTE0 BYTE1 BYTE1 XX
Device Address
for 2 frames
High to Low
indicates data
received
High to Low indicates
data transmitted
MX LOGIC LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
Host Device
One Frame
Time
Data from 2 frames must match or transfer is aborted
by the receiver holding MR high for 2 frames
XX
XX
End of Message
2 frames high
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 11: Example GCI Write to Mode Control and RX Gain ±1dB Registers
Rev F
Rev F
Host Device
PRELIMINARY
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
0x91
XX
MR transition allows
transmitter to send text
XX
XX
0x91
Device Address
for 2 frames
High to Low indicates
data received
High to Low indicates
data transmitted
XX
125µs
One Frame
Time
0x01
XX
XX
MX must go high
before receiver brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next Data
Transmitted
0x01
Write Command
for 2 frames
0x10
Data
Received
XX
XX
Except for second byte,
MR must go high before
transmitter brings MX
high. Receive may hold
off next byte by holding
MR low if data in both
frames does not match.
For high speed,
transmitter assumes MR
bit will go low next
frame.
Next Data
Transmitted
0x10
Invalid Address
for 2 frames
XX
XX
XX
XX
XX
Invalid address
causes CPC5750 not
to acknowledge
address transfer.
This aborts transfer.
XX
XX
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 12: Example GCI Write Command Aborted Due to Invalid Address
29
30
PRELIMINARY
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
Host Device
XX
XX
0x91
Device Address
for 2 frames
0x91
MR transition allows
transmitter to Send Next
XX
High to Low
indicates
data received
High to Low indicates
data transmitted
XX
125µs
One Frame
Time
0x81
XX
XX
MX must go high
before receiver brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next data
transmitted
0x01
Command does not
match for 2 frames
XX
Command frame
mismatch causes
CPC5750 not to
acknowledge
command transfer.
This aborts transfer.
XX
XX
XX
XX
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 13: Example GCI Write Command Aborted Due to Frame Mismatch
Rev F
Rev F
PRELIMINARY
XX
XX
High to Low
indicates
data received
MR transition allows
transmitter to Send Next
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
MR LOGIC LEVEL
XX
XX
XX
MX must go high
before receiver brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next data
transmitted
0x90 0x90 0x00 0x00
XX
Special Command
for 2 frames
Channel Identification
Address for 2 frames
125µs
High to Low indicates
data transmitted
MX LOGIC LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
Host Device
One Frame
Time
Data from 2 frames must match or transfer is aborted
by the receiver holding MR high for 2 frames.
XX
Data
Received
XX
XX
Data
Received
XX
XX
CPC5750 responds to
Channel Identification
Command with
2 byte code
Next Data
Transmitted
0x90 0x90 0xB8 0xB8
Except for second byte,
MR must go high before
transmitter brings MX
high. Receiver may hold
off next byte by holding
MR low if data in both
frames does not match.
For high speed,
transmitter assumes MR
LOGIC will go low next
frame.
XX
XX
XX
XX
MX must go high
before receiver brings
MR high.
End of
Message
2 Frames High
Data
Received
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 14: Example GCI Channel Identification Command
31
32
PRELIMINARY
XX
XX
High to Low
indicates data
received
XX
0x91
Device Address
for 2 frames
0x91
High to Low indicates
data transmitted
XX
125µs
MR transition allows
transmitter to Send Next
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data transmitted by CPC5750 via DTX)
CPC5750 Device
MR LOGIC LEVEL
MX LOGIC LEVEL
Monitor Slot Data
(Data received by CPC5750 via DRX)
Host Device
One Frame
Time
0x81
XX
XX
MX must go high
before receiver brings
MR high. Transmitter
may hold off next byte
by keeping MX low.
Next Data
transmitted
0x81
Read Command
for 2 frames
0x01
Data
Received
XX
XX
Except for second byte,
MR must go high before
transmitter brings MX
high. Receiver may hold
off next byte by holding
MR low if data in both
frames does not match.
For high speed,
transmitter assumes
MR LOGIC will go low
next frame.
Next Data
transmitted
0x01
Register Address
for 2 frames
Data from 2 frames must match or transfer is aborted
by the receiver holding MR high for 2 frames.
Data
Received
XX
XX
XX
0x91
CPC5750
transmits address
before requested data
0x91
XX
XX
Data Corrupted
due to DTX
collision
Data Corrupted
due to DTX
collision
MX must go high
before receiver brings
MR high.
Data
Received
End of Message
2 frames high
XX
XX
XX
XX
End of Message
2 frames High
XX
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
CPC5750
Figure 15: Example GCI Read Command Aborted Due to Bus Contention
Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
7. 4-Wire SPI (Serial Peripheral Interface)
A 4-wire, bidirectional serial interface is used for control and status monitoring when the CPC5750 is configured for
the PCM transmission mode. Typical hardware implementation of a SPI bus consists of a single master with one or
more slave devices where the role of the master is generally performed by the system controller. In PCM voice circuit
applications where a configurable CODEC is utilized such as the CPC5750, the CODEC is a slave. Data is passed
between the master and slave(s) by means of four logic signals. They are: SCLK (the serial clock); SDO (the serial
data out); SDI (the serial data in); and CS (the chip select line). Of these four logical signals, three are output by the
SPI bus master. The SPI bus master drives the CPC5750 serial data pins SCLK, SDI and CS. For the SPI bus to
function properly, the bus master’s input and output nodes must be cross connected to the SPI bus slave’s output and
input nets. This means, the master’s SDO output must be connected to the slave’s SDI input and the slave’s SDO
output must be connected to the master’s SDI input. In order to connect multiple slave devices onto the SPI bus, all
slaves must set their SDO output to high impedance (HI-Z) when not actively driving the common SDO net and each
slave must have it’s own dedicated CS connection back to the SPI bus master.
SPI bus commands issued by the system controller to the CPC5750 are eight bits in length (MSB first) and are
constructed by appending the command nibble (4 bits) with the register address nibble. The CPC5750 SPI bus
circuitry recognizes only two commands; they are READ and WRITE. For the system controller to issue a command
via the SPI bus it must drive the three SPI bus slave inputs; SCLK, CS and SDI.
Write commands are the means by which the system controller places data into one the CPC5750 control registers.
Each packet of a single register write sequence contains an 8-bit command byte appended by the 8-bit data byte to
be stored in the register listed in the command byte. The CPC5750 inputs eight bits of SDI data beginning with the
first rising edge of SCLK after CS goes active (low). When the input data byte is 0xB (1011) followed by a legitimate
four bit register address, the command is accepted and the second data byte is written into the appropriate register.
This sequence is illustrated in Figure 16.
Read commands are used by the system controller to validate the values written into the configuration registers and
to query the logical values applied to the GPIO ports configured as inputs. The read command byte sequence is the
same as described above for the write mode. The CPC5750 recognizes and accepts read commands when the input
data byte is 0xA (1010) followed by a legitimate four bit register address. With a valid read command, the CPC5750
will output the eight data bits contained in the register listed in the command byte. This data is output onto the SDO
net beginning with the MSB of the register’s contents on the first falling edge of SCLK after the rising edge of SCLK
used to clock in the LSB of the command byte. In this manner, the first control register bit will be available to the
system controller on the next rising edge of SCLK. Reliable data transfer from the CPC5750 to the system controller
requires CS to remain low while the CPC5750 is outputting data, going high only after satisfying the controller’s input
data setup and hold time requirements to ensure the last output bit is received. This sequence is illustrated in
Figure 16.
Multi-byte writes and reads are supported for single write or read commands. The register address automatically
increments after each data byte for as long as CS is active.
Rev F
PRELIMINARY
33
CPC5750
INTEGRATED CIRCUITS DIVISION
PRELIMINARY
Table 6: SPI Timing
Parameter
Cycle Time
Pulse Width
Pulse Edge Rise Time
Pulse Edge Fall Time
Data Setup Time
Data Hold Time
CS Setup Time, Write
CS Hold Time, Write
Read Access Time
Read Output Disable Time
Condition
Symbol
Min
Max
CL=100pF
CL=100pF
tCYCS
250
-
tHI, tLO
50
-
tR
50
tF
50
tDS
50
-
tDH
30
-
tSS
30
-
tSH
30
-
tACCS
-
30
tOHS
-
30
Units
ns
Figure 16: 4-Wire SPI
Write Cycle*
CS
SCLK
SDIN
D7
1
0
1
1
0
0
0
D6
D5
D4
D3
D2
D1
D0
0
Write Cycle Timing - Detailed
CS
SCLK
tR
tSS
tHI
tF
tDS
SDIN
tCYCS
tSH
tDH
tLO
D7
D6
D5
D4
D3
D2
D1
D0
*PCLK and FS must be present for SPI Bus write commands.
Read Cycle
CS
SCLK
SDIN
SD0
From
CPC5750
Register
1
0
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Read Cycle Timing - Detailed
CS
SCLK
tACCS
SDO
34
tOHS
D7
PRELIMINARY
D0
Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
7.1 Data Compression/Expansion
The differential analog signal on AIN+/- is converted and filtered as 14-bit data internally. This digital data is
compressed to 8 bits as specified by the ITU G.711 standard before being transmitted in 8-bit words via the PCM bus.
8-bit data received via the PCM interface is decompressed as specified by ITU G.711 to 14-bit data before being
converted to a differential analog signal, and output on the AOUT+/- signals.
7.2 Power On Reset (POR)
The power-on-reset circuit will be active when power is first applied to the device. This power up active reset signal will
go inactive after 20s nominally. Additionally, a hardware reset pin (RST) is supplied to force an internal reset. The
hardware reset pin is also de-bounced by the same nominal 20s delay.
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INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
8. Manufacturing Information
8.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
CPC5750U
MSL 1
8.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
8.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
CPC5750U
260°C for 30 seconds
8.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
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Rev F
INTEGRATED CIRCUITS DIVISION
CPC5750
PRELIMINARY
8.5 Mechanical Dimensions
8.5.1 CPC5750U - 24-Pin SSOP Package
PCB Land Pattern
8.560 / 8.738
(0.337 / 0.344)
3.810 / 3.988
(0.150 / 0.157)
0.178 / 0.254
(0.007 / 0.010)
5.40
(0.213)
5.791 / 6.198
(0.228 / 0.244)
1.55
(0.061)
0.406 / 1.270
(0.016 / 0.050)
0.203 / 0.305
(0.008 / 0.012)
0º / 8º
1.499 MAX
(0.059 MAX)
0.635
(0.025)
0.635
(0.025)
1.346 / 1.753
(0.053 / 0.069)
0.40
(0.016)
Dimensions
mm MIN / mm MAX
(inches MIN / inches MAX)
0.102 / 0.254
(0.004 / 0.010)
8.5.2 Tape and Reel Drawing
2.0 ± 0.1
(0.08 ± 0.004)
4.0 ± 0.1
(0.16 ± 0.004)
7.50 ± 0.10
(0.295 ± 0.004)
1.75 ± 0.1
(0.069 ± 0.004)
W=16.00 ± 0.3
(0.630 ± 0.012)
B0=9.05 ± 0.10
(0.356 ± 0.004)
K0=2.10 ± 0.10
(0.083 ± 0.004)
P=8.00 ± 0.1 A0=6.55 ± 0.1
(0.315 ± 0.004) (0.258 ± 0.004)
Dimensions
mm
(inches)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC5750-Rev F
©Copyright 2015, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
6/8/2015
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