ispGAL22V10AV/B/C Data Sheet

ispGAL™22V10AV/B/C Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
ispGAL22V10AV
ispGAL22V10AB
Ordering Part Number
ispGAL22V10AV-23LS
ispGAL22V10AV-23LSN
ispGAL22V10AV-5LS
ispGAL22V10AV-5LSN
ispGAL22V10AV-75LS
ispGAL22V10AV-75LSN
ispGAL22V10AV-5LSI
ispGAL22V10AV-5LSNI
ispGAL22V10AV-75LSI
ispGAL22V10AV-75LSNI
ispGAL22V10AV-28LJ
ispGAL22V10AV-5LJ
ispGAL22V10AV-75LJ
ispGAL22V10AV-5LJI
ispGAL22V10AV-75LJI
ispGAL22V10AB-23LS
ispGAL22V10AB-5LS
ispGAL22V10AB-75LS
ispGAL22V10AB-5LSI
ispGAL22V10AB-75LSI
ispGAL22V10AB-28LJ
ispGAL22V10AB-5LJ
ispGAL22V10AB-75LJ
ispGAL22V10AB-5LJI
ispGAL22V10AB-75LJI
Product Status
Reference PCN
Discontinued
PCN#09-10
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
ispGAL22V10AC
Ordering Part Number
ispGAL22V10AC-23LS
ispGAL22V10AC-5LS
ispGAL22V10AC-75LS
ispGAL22V10AC-5LSI
ispGAL22V10AC-75LSI
ispGAL22V10AC-28LJ
ispGAL22V10AC-5LJ
ispGAL22V10AC-75LJ
ispGAL22V10AC-5LJI
ispGAL22V10AC-75LJI
Product Status
Reference PCN
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
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Fast
est &
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SPLD t
ispGAL22V10AV/B/C
In-System Programmable Low Voltage
´®
E2CMOS PLD Generic Array Logic
December 2008
Data Sheet
Features
Introduction
■ High Performance
The ispGAL22V10A is manufactured using Lattice
Semiconductor’s advanced E2CMOS process, which
combines CMOS with Electrically Erasable (E2) floating
gate technology. With an advanced E2 low-power cell
and full CMOS logic approach, the ispGAL22V10A family offers fast pin-to-pin speeds, while simultaneously
delivering low standby power without requiring any
“turbo bits” or other traditional power management
schemes. The ispGAL22V10A can interface with both
3.3V, 2.5V and 1.8V signal levels.
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• tPD = 2.3ns propagation delay
• fMAX = 455 MHz maximum operating frequency
• tCO = 2ns maximum from clock input to data
output
• tSU = 1.3 ns clock set-up time
■ Low Power
• 1.8V core E2CMOS® technology
• Typical standby power <300µW
(ispGAL22V10AC)
• CMOS design techniques provide low static and
dynamic power
The ispGAL22V10A is functionally compatible with the
ispGAL22LV10, GAL22LV10 and GAL22V10.
■ Space-Saving Packaging
Figure 1. Functional Block Diagram
• Available in 32-pin QFNS (Quad Flat-pack,
No lead, Saw-singulated) package 5mm x 5mm
body size1
8
■ Easy System Integration
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
OLMC
I/O
I
• Operation with 3.3V (ispGAL22V10AV), 2.5V
(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)
supplies
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3 interface
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Lead-free package option
• Programmable output slew rate
• 3.3V PCI compatible
10
I
12
I
I
I
I
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V in-system programmable
(ISP™) using IEEE 1532 compliant interface
I
■ E2 CELL TECHNOLOGY
PROGRAMMABLE
AND-ARRAY
(132X44)
I
■ In-System Programmable
14
16
16
14
12
I
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)
I
■ Applications Include
•
•
•
•
RESET
I/CLK
I
DMA control
State machine control
High speed graphics processing
Software-driven hardware configuration
TDO
TDI
TMS
TCK
10
8
PROGRAMMING
LOGIC
PRESET
■ Boundary Scan USERCODE Register
• Supports electronic signature
1. Use 32-pin QFNS package for all new designs. Refer to PCN
#13A-08 for 32-pin QFN package discontinuance.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
1
isp22v10a_03.0
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
ispGAL Architecture
Output Logic Macrocell (OLMC)
The ispGAL22V10A has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs
have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve
product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen
product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
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The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or
registered mode. This allows each output to be individually configured as either active high or active low.
The ispGAL22V10A has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset
(SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to
zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on
the rising edge of the next clock pulse after this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the
polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a
high or low at the output pin, depending on the pin polarity chosen.
Figure 2. Output Logic Macrocell
AR
D
4 TO 1
MUX
Q
Q
CLK
SP
2 TO 1
MUX
Output Logic Macrocell Configurations
Each of the Macrocells of the ispGAL22V10A has two primary functional modes: registered, and combinatorial I/O.
The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on
the following page.
Registered
In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s Dtype flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive
either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for
each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND
array, with both the true and complement of the feedback available as inputs to the AND array.
2
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin
defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins.
Combinatorial I/O
In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate.
Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true
(active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both
polarities (true and inverted) of the pin are fed back into the AND array.
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Figure 3. Registered Mode
AR
D
AR
Q
D
Q
CLK
Q
CLK
SP
Q
SP
ACTIVE LOW
ACTIVE HIGH
S0 = 0
S1 = 0
S0 = 1
S1 = 0
Figure 4. Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S0 = 1
S1 = 1
S0 = 0
S1 = 1
3
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Figure 5. Logic Diagram/JEDEC Fuse Map – PLCC & (QFN/QFNS) Package Pinout
JEDEC
Fuse #5676
2 (30)
JEDEC
Fuse #0
0
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8
OLMC
S1, S0 = 5808, 5809
SR = 5830
OD = 5831
10
OLMC
S1, S0 = 5810, 5811
SR = 5832
OD = 5833
26 (25)
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3 (31)
27 (26)
12
OLMC
25 (24)
S1, S0 = 5812, 5813
SR = 5834
OD = 5835
4 (32)
14
OLMC
24 (23)
S1, S0 = 5814, 5815
SR = 5836
OD = 5837
5 (1)
16
OLMC
23 (22)
S1, S0 = 5816, 5817
SR = 5838
OD = 5839
6 (2)
16
OLMC
21 (19)
S1, S0 = 5818, 5819
SR = 5840
OD = 5841
7 (3)
14
OLMC
20 (18)
S1, S0 = 5820, 5821
SR = 5842
OD = 5843
9 (6)
12
OLMC
19 (17)
S1, S0 = 5822, 5823
SR = 5844
OD = 5845
10 (7)
10
OLMC
S1, S0 = 5824, 5825
SR = 5846
OD = 5847
18 (16)
11 (8)
8
12 (9)
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
13 (10)
JEDEC Fuse #131
OLMC
S1, S0 = 5826, 5827
SR = 5848
OD = 5849
S1, S0 = Arch Control Bits
SR = Slew Rate Bit
OD = Open Drain Bit
JEDEC Fuse #5807
4
17 (15)
16 (14)
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Electronic Signature
An electronic signature (ES) is provided in every ispGAL22V10A device. It contains 32 bits of reprogrammable
memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. IEEE 1149.1
and IEEE 1532 compliant USERCODE is supported.
Low Power and Power Management
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The ispGAL22V10A family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E2 low power cell and no sense-amplifiers (full CMOS logic approach), the
ispGAL22V10A family offers fast pin-to-pin speeds, while simultaneously delivering low standby power without
requiring any “turbo bits” or other traditional power-management schemes.
I/O Configuration
Each output supports a variety of output standards dependent on the VCCO. Outputs can also be configured for
open drain operation. Each input can be programmed to support a variety of standards, independent of the VCCO
supplied to its I/O. For 28 PLCC package the VCCO and VCC must be the same. The option to set the VCCO independent of VCC is available with the 32 QFN/QFNS package only. The I/O standards supported are:
• LVTTL
• LVCMOS 1.8
• LVCMOS 3.3
• 3.3V PCI Compatible
• LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each ispGAL22V10A device I/O has an individually programmable output slew rate control bit. Each output can be
individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the
fast slew rate can be used to achieve the highest speed.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispGAL22V10A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including rapid prototyping, lower inventory levels, higher quality and the ability to make in-field modifications. All ispGAL22V10A devices provide In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, welldefined interface. All ispGAL22V10A devices are also compliant with the IEEE 1532 standard.
The ispGAL22V10A devices can be programmed across the commercial temperature and voltage range. The PCbased Lattice software facilitates in-system programming of ispGAL22V10A devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
5
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common automated test equipment. This equipment can then be used to program ispGAL22V10A devices during the testing of a
circuit board.
Security Bit
A programmable security bit is provided on the ispGAL22V10A devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.
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Hot Socketing
The ispGAL22V10A devices are well-suited for applications that require hot socketing. Hot socketing a device
requires that the device, during power-up and down, tolerate active signals on the I/Os and inputs without being
damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The
ispGAL22V10A devices provide this capability for input voltages in the range of 0V to 3.0V.
Power-up Reset
Circuitry within the ispGAL22V10A provides a reset signal to all registers during power-up. All internal registers will
have their Q outputs set low after a specified time (tpr, 1µs typical). As a result, the state on the registered output
pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing
diagram for power-up is shown above. Because of the asynchronous nature of system power-up, some conditions
must be met to provide a valid power-up reset of the ispGAL22V10A. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback
path setup times have been met. The clock must also meet the minimum pulse width requirements.
Figure 6. Timing Diagram for Power-up
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
6
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Absolute Maximum Ratings1, 2, 3
ispGAL
22V10AC (1.8V)
ispGAL
22V10AB (2.5V)
ispGAL
22V10AV (3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V
-0.5 to 5.5V
-0.5 to 5.5V
Output Supply Voltage VCCO . . . . . . . . . . . . . . . . . -0.5 to 4.5V
-0.5 to 4.5V
-0.5 to 4.5V
Input or I/O Tristate Voltage Applied . . . . . . . . . . . -0.5 to 5.5V
-0.5 to 5.5V
-0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
-65 to 150°C
-65 to 150°C
Junction Temperature (Tj) with Power Applied . . . . -55 to 150°C
-55 to 150°C
-55 to 150°C
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4
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Undershoot of -2V and overshoot of (VIH (MAX) +2), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.
Recommended Operating Conditions
Symbol
Parameter
VCC
Min
Max
Units
Supply Voltage for 1.8V Devices
1.65
1.95
V
Supply Voltage for 2.5V Devices
2.3
2.7
V
Supply Voltage for 3.3V Devices
3.0
3.6
V
0
90
C
-40
105
C
Min
Max
Units
1,000
—
Cycles
Junction Temperature (Commercial)
Tj
Junction Temperature (Industrial)
Erase Reprogram Specifications
Parameter
Erase/Reprogram Cycle
Note: Valid over commercial temperature range.
Hot Socketing Characteristics1,2,3
Symbol
IDK
Parameter
Condition
Input or I/O Leakage Current
0 ≤ VIN ≤ 3.0V, Tj = 105°C
Min
Typ
Max
Units
—
—
±50
μA
1. Insensitive to sequence of VCC and VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ≤ 3.0V.
2. 0 ≤ VCC ≤ VCC (MAX), 0 ≤ VCCO ≤ VCCO (MAX)
3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
I/O Recommended Operating Conditions
VCCO (V)1
Standard
LVTTL
Min
Max
3.0
3.6
LVCMOS 3.3
3.0
3.6
LVCMOS 2.5
2.3
2.7
LVCMOS 1.8
1.65
1.95
PCI 3.3
3.0
3.6
1. Typical values for VCCO are the average of the Min and Max values.
7
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Units
Input Leakage Current
0 < VIN ≤ 3.6V, Tj = 105°C
—
—
10
µA
2
IIH
Input High Leakage Current
3.6V < VIN ≤ 5.5V, Tj = 105°C
3.0V ≤ VCCO ≤ 3.6V
—
—
20
µA
IOS
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V,
TA = 25°C
—
—
-80
mA
IPU
I/O Weak Pull-up Resistor Current
0 ≤ VIN ≤ 0.7VCCO
20
—
150
µA
IPD
I/O Weak Pull-down Resistor Current VIL (MAX) ≤ VIN ≤ VIH (MAX)
20
—
150
µA
IBHLS
Bus Hold Low Sustaining Current
VIN = VIL (MAX)
20
—
—
µA
IBHHS
Bus Hold High Sustaining Current
VIN = 0.7 VCCO
20
—
—
µA
IBHLO
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VIH (MAX)
—
—
150
µA
—
—
150
µA
VIL (MAX)
—
VIH (MIN)
V
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IIL, IIH
IBHHO
Bus Hold High Overdrive Current
0 ≤ VIN ≤ VIH (MAX)
VBHT
Bus Hold Trip Points
—
C1
I/O Capacitance3
C2
Clock Capacitance3
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
VCCO = 3.3V, 2.5V, 1.8V
—
VCC = 1.8V, VIO = 0 to VIH (MAX)
—
6
8
—
—
—
—
pf
pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5 volt tolerant inputs and I/Os apply to VCCO condition of 3.0V ≤ VCCO ≤ 3.6V.
3. TA = 25°C, frequency = 1.0MHz
Supply Current
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC = 3.3V
—
8
90
mA
VCC = 2.5V
—
8
90
mA
VCC = 1.8V
—
3
80
mA
VCC = 3.3V
—
7
—
mA
VCC = 2.5V
—
7
—
mA
VCC = 1.8V
—
150
—
µA
ispGAL22V10AV/B/C
1, 2
ICC
ICC3
1.
2.
3.
Operating Power Supply Current
Standby Power Supply Current
TA = 25°C, frequency = 15MHz.
ICC varies with specific device configuration and operating frequency.
TA = 25°C
8
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
I/O DC Electrical Characteristics1
Over Recommended Operating Conditions
VIL
Standard
LVTTL
LVCMOS 3.3
Min (V)
Max (V)
Min (V)
Max (V)
-0.3
0.80
2.0
5.5
-0.3
0.80
-0.3
2.0
0.70
5.5
1.70
3.6
VOL
Max (V)
VOH
Min (V)
IOL
(mA)
IOH
(mA)
0.40
VCCO - 0.40
8.0
-4.0
0.20
VCCO - 0.20
0.1
-0.1
0.40
VCCO - 0.40
8.0
-4.0
0.20
VCCO - 0.20
0.1
-0.1
0.40
VCCO - 0.40
8.0
-4.0
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LVCMOS 2.5
VIH
LVCMOS 1.8
-0.3
(ispGAL22V10AV/B)
LVCMOS 1.8
0.63
-0.3
(ispGAL22V10AC)
PCI 3.3
0.35 VCC
-0.3
(ispGAL22V10AV/B)
PCI 3.3
-0.3
(ispGAL22V10AC)
1.17
3.6
0.65 * VCC
1.08
3.6
1.5
0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8)
0.20
VCCO - 0.20
0.1
-0.1
0.40
VCCO - 0.45
2.0
-2.0
0.20
VCCO - 0.20
0.1
-0.1
0.40
VCCO - 0.45
2.0
-2.0
0.20
VCCO - 0.20
5.5
0.1 VCCO
0.9 VCCO
5.5
0.1 VCCO
0.9 VCCO
0.1
-0.1
1.5
-0.5
1.5
-0.5
1. For 28 PLCC package the I/O voltage and core voltage must be the same. The option to set the I/O voltage independent of the core voltage
is available with the 32 QFN/QFNS package only.
3.3V VCCO
IOL
IOH
80
60
40
20
0
0.5
1.0 1.5
50
IOL
IOH
40
30
20
10
0
2.0 2.5 3.0 3.5
50
IOL
IOH
40
30
20
10
0
0.5
1.0
1.5
0.5
1.0
1.5
2.0
VO Output Voltage (V)
1.8V VCCO
60
Typical I/O Output Current (mA)
60
0
0
VO Output Voltage (V)
0
2.5V VCCO
70
Typical I/O Output Current (mA)
Typical I/O Output Current (mA)
100
2.0
VO Output Voltage (V)
9
2.5
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
ispGAL22V10AV/B/C External Switching Characteristics1
Over Recommended Operating Conditions
-23
Param
tPD
tCO
2
Description
-28
-5
-75
Min
Max
Min
Max
Min
Max
Min
—
2.3
—
2.8
—
—
—
1 Output Switching Propagation Delay
Max Units
—
10 Output Switching Propagation Delay
—
2.6
—
3.0
—
5.0
—
7.5
Clock to Output Delay
—
2.0
—
2.5
—
3.5
—
5.0
ns
ns
Clock to Feedback Delay
—
1.9
—
2.2
—
2.5
—
2.5
ns
Setup Time, Input or Feedback before CLK↑
1.3
—
2.0
—
3.5
—
5.0
—
ns
tH
Hold Time, Input or Feedback after CLK↑
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
tCF
tSU
fMAX3
0
—
0
—
0
—
0
—
ns
Maximum Clock Frequency with External Feedback,
[1/ (tSU + tCO)]
303
—
222
—
143
—
100
—
ns
Maximum Clock Frequency with Internal Feedback,
[1/ (tSU + tCF)]
312
—
238
—
166
—
133
—
ns
Maximum Clock Frequency with No Feedback
455
—
357
—
200
—
166
—
ns
tWH3
Clock Pulse Duration, High
1.1
—
1.4
—
2.5
—
3.0
—
ns
tWL3
Clock Pulse Duration, Low
1.1
—
1.4
—
2.5
—
3.0
—
ns
tEN
Input or I/O to Output Enabled
—
3.0
—
3.5
—
6.0
—
7.5
ns
tDIS
Input or I/O to Output Disabled
—
3.0
—
3.5
—
6.0
—
7.5
ns
tAR
Input or I/O to Asynch, Reset of Reg.
—
2.8
—
3.5
—
5.5
—
9.0
ns
tARW
Asysnchronous Reset Pulse Duration
2.8
—
3.5
—
5.5
—
7.0
—
ns
tARR
Asysnchronous Reset to CLK↑ Recovery Time
2.5
—
3.0
—
4.0
—
5.0
—
ns
tSPR
Synchronous Preset to CLK↑ Recovery Time
2.5
—
3.0
—
4.0
—
5.0
—
ns
1. Refer to Switching Test Conditions section.
2. Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3. Refer to fmax Descriptions section. Characterized but not 100% tested.
Note: Maximum clock input rise and fall time between 10% to 90% of Vout = 2ns.
10
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
ispGAL22V10AV/B/C Timing Adders
Over Recommended Operating Conditions
-23
Adder
Type
Description
-28
-5
-75
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
tIOI Input Adjusters
Using LVTTL standard
—
0.6
—
0.6
—
0.6
—
0.6
ns
LVCMOS33_in
Using LVCMOS 3.3
standard
—
0.6
—
0.6
—
0.6
—
0.6
ns
LVCMOS25_in
Using LVCMOS 2.5
standard
—
0.6
—
0.6
—
0.6
—
0.6
ns
LVCMOS18_in
Using LVCMOS 1.8
standard
—
0
—
0
—
0
—
0
ns
PCI_in
Using PCI compatible input
—
0.6
—
0.6
—
0.6
—
0.6
ns
—
0.2
—
0.2
—
0.2
—
0.2
ns
LVCMOS33_out Output configured as 3.3V buffer
—
0.2
—
0.2
—
0.2
—
0.2
ns
LVCMOS25_out Output configured as 2.5V buffer
—
0.1
—
0.1
—
0.1
—
0.1
ns
LVCMOS18_out Output configured as 1.8V buffer
A
D LL
IS
C DE
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N VIC
TI
N ES
U
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LVTTL_in
tIOO Output Adjusters
LVTTL_out
Output configured as TTL buffer
—
0
—
0
—
0
—
0
ns
PCI_out
Output configured as
PCI compatible buffer
—
0.2
—
0.2
—
0.2
—
0.2
ns
Slow Slew
Output configured for slow slew rate
—
1.0
—
1.0
—
1.0
—
1.0
ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
11
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Switching Waveforms
Figure 7. ispGAL22V10AV/B/C Switching Waveforms
Combinatorial Output
INPUT or
I/O FEEDB ACK
Registered Output
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
ts u
tp d
th
CLK
CO MB INA TO RI AL
OUTPUT
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
tc o
REGISTERED
OUTPUT
1 / fm a x
(external fdbk)
fMAX with Feedback
Input or I/O to Output Enable/Disable
INPUT or
I/O FEEDBACK
CLK
tdis
1 / fm ax (int ern al fd bk )
ten
t su
tc f
REGISTERED
FEEDBACK
OUTPUT
Synchronous Preset
INPUT or
I/O FEEDBACK
DRIVING SP
tsu
th
Asynchronous Reset
INPUT or
I/O FEEDBACK
DRIVING AR
tspr
CLK
tarw
CLK
tco
tarr
REGISTERED
OUTPUT
REGISTERED
OUTPUT
tar
Clock Width
tw l
tw h
CLK
1 / fm a x
(w/o fdbk)
12
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
fMAX Descriptions
Figure 8. ispGAL22V10AV/B/C fMAX Descriptions
CL K
CLK
LOGIC
ARRAY
R EG I S T E R
REGISTER
A
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IS
C DE
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N VIC
TI
N ES
U
ED
LOGIC
ARR AY
ts u
t cf
t pd
tc o
fmax with External Feedback 1/(tsu+tco)
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by
subtracting tsu from the period of fmax
w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when
calculating the delay from clocking a
register to a combinatorial output (through
registered feedback), as shown above. For
example, the timing from clock to a
combinatorial output is equal to tcf + tpd.
Note: fmax with external feedback is
calculated from measured tsu and tco.
CLK
LOGIC
ARRAY
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
13
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Switching Test Conditions
Figure 9 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 1.
Figure 9. Output Test Load, LVTTL and LVCMOS Standards
VCCO
R1
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Test
Point
DUT
R2
CL
Table 1. Test Fixture Required Components
Test Condition
I/O Standard
R1
R2
CL1
Input
Timing Ref.2
Output
Timing Ref.
VCCO
1.5V
1.5V
3.0V
LVCMOS 3.3
LVCMOS 2.5
LVCMOS I/O, (L -> H, H -> L)
106Ω 106Ω
35pF
LVCMOS I/O (Z -> H)
106Ω 106Ω
35pF
LVCMOS I/O (Z -> L)
106Ω 106Ω
LVCMOS 1.8
1.2V
VCCO/2
2.3V
(V/B) 0.9V
VCCO/2
(V/B) 1.65V
VCCO/2
(C) VCC
Hi-Z + 0.3
3.0V
(C) VCC/2
35pF
Hi-Z - 0.3
3.0V
LVCMOS I/O (H -> Z)
∞
106Ω
5pF
VOH - 0.3
3.0V
LVCMOS I/O (L -> Z)
106Ω
∞
5pF
VOL + 0.3
3.0V
1. CL includes test fixtures and probe capacitance.
2. Input conditions.
Pin Diagrams
32
26
TDO
11
5
I/O
I/O
Vcco
Vcc
TCK
Top View
21
TDO
20
GNDO
I
I/O
I
I/O
I
I/O
I/O
8
9
I/O
I/O
I
16
TDI
GND
14
I
I
12
19
18
I/O
TMS
Vcco
14
17
16
12 13
I/O
21
I/O
4
I
9
I
I
I/O
I/O
I/O
I
I/O
I
I
25
24
TDI
Top View
TMS
I/O
29 28
1
GNDO
23
I
GND
7
I/O
I
25
I
I
I
I
I/O
I/O
28
5
I
2
Vcc
TCK
I/CLK
I
I
4
I
I/CLK
QFN, QFNS
PLCC
I/O
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Part Number Description
ispGAL 22V10A X – XX X X X
Grade
C = Commercial
I = Industrial
Device Family
Device Number
Supply Voltage
V = 3.3V
B = 2.5V
C = 1.8V
Speed
23 = 2.3ns
28 = 2.8ns
5 = 5.0ns
75 = 7.5ns
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Package
J = PLCC (28 pins)
N = QFN (32 pins)
NN = Lead Free QFN (32 pins)
S = QFNS (32 pins)
SN = Lead Free QFNS (32 pins)
Power
L = Low Power
Ordering Information
Conventional Packaging
Commercial
Part Number
Voltage
tPD
Power
Package
Pin Count
Grade
ispGAL22V10AV-23LS
3.3
2.3ns
Low
QFNS
32
C
ispGAL22V10AV-23LN1
3.3
2.3ns
Low
QFN
32
C
ispGAL22V10AV-5LS
3.3
5.0ns
Low
QFNS
32
C
ispGAL22V10AV-5LN1
3.3
5.0ns
Low
QFN
32
C
ispGAL22V10AV-75LS
3.3
7.5ns
Low
QFNS
32
C
ispGAL22V10AV-75LN1
3.3
7.5ns
Low
QFN
32
C
ispGAL22V10AV-28LJ
3.3
2.8ns
Low
PLCC
28
C
ispGAL22V10AV-5LJ
3.3
5.0ns
Low
PLCC
28
C
ispGAL22V10AV-75LJ
3.3
7.5ns
Low
PLCC
28
C
ispGAL22V10AB-23LS
2.5
2.3ns
Low
QFNS
32
C
ispGAL22V10AB-23LN1
2.5
2.3ns
Low
QFN
32
C
ispGAL22V10AB-5LS
2.5
5.0ns
Low
QFNS
32
C
1
ispGAL22V10AB-5LN
2.5
5.0ns
Low
QFN
32
C
ispGAL22V10AB-75LS
2.5
7.5ns
Low
QFNS
32
C
ispGAL22V10AB-75LN
2.5
7.5ns
Low
QFN
32
C
ispGAL22V10AB-28LJ
2.5
2.8ns
Low
PLCC
28
C
1
ispGAL22V10AB-5LJ
2.5
5.0ns
Low
PLCC
28
C
ispGAL22V10AB-75LJ
2.5
7.5ns
Low
PLCC
28
C
ispGAL22V10AC-23LS
1.8
2.3ns
Low
QFNS
32
C
ispGAL22V10AC-23LN1
1.8
2.3ns
Low
QFN
32
C
ispGAL22V10AC-5LS
1.8
5.0ns
Low
QFNS
32
C
ispGAL22V10AC-5LN1
1.8
5.0ns
Low
QFN
32
C
ispGAL22V10AC-75LS
1.8
7.5ns
Low
QFNS
32
C
ispGAL22V10AC-75LN1
1.8
7.5ns
Low
QFN
32
C
ispGAL22V10AC-28LJ
1.8
2.8ns
Low
PLCC
28
C
ispGAL22V10AC-5LJ
1.8
5.0ns
Low
PLCC
28
C
ispGAL22V10AC-75LJ
1.8
7.5ns
Low
PLCC
28
C
1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08.
15
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Industrial
Part Number
Voltage
tPD
Power
Package
Pin Count
Grade
3.3
5.0ns
Low
QFNS
32
I
1
ispGAL22V10AV-5LNI
3.3
5.0ns
Low
QFN
32
I
ispGAL22V10AV-75LSI
3.3
7.5ns
Low
QFNS
32
I
ispGAL22V10AV-75LNI
3.3
7.5ns
Low
QFN
32
I
ispGAL22V10AV-5LJI
3.3
5.0ns
Low
PLCC
28
I
ispGAL22V10AV-5LSI
1
3.3
7.5ns
Low
PLCC
28
I
2.5
5.0ns
Low
QFNS
32
I
ispGAL22V10AB-5LNI1
2.5
5.0ns
Low
QFN
32
I
ispGAL22V10AB-75LSI
2.5
7.5ns
Low
QFNS
32
I
ispGAL22V10AB-75LNI
2.5
7.5ns
Low
QFN
32
I
ispGAL22V10AB-5LJI
2.5
5.0ns
Low
PLCC
28
I
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
ispGAL22V10AV-75LJI
ispGAL22V10AB-5LSI
1
ispGAL22V10AB-75LJI
2.5
7.5ns
Low
PLCC
28
I
ispGAL22V10AC-5LSI
1.8
5.0ns
Low
QFNS
32
I
ispGAL22V10AC-5LNI1
1.8
5.0ns
Low
QFN
32
I
ispGAL22V10AC-75LSI
1.8
7.5ns
Low
QFNS
32
I
ispGAL22V10AC-75LNI
1.8
7.5ns
Low
QFN
32
I
ispGAL22V10AC-5LJI
1.8
5.0ns
Low
PLCC
28
I
ispGAL22V10AC-75LJI
1.8
7.5ns
Low
PLCC
28
I
Power
Package
Pin Count
Grade
1
1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08.
Lead-Free Packaging
Commercial
Part Number
Voltage
tPD
ispGAL22V10AV-23LSN
3.3
2.3ns
Low
QFNS
32
C
ispGAL22V10AV-23LNN1
3.3
2.3ns
Low
QFN
32
C
ispGAL22V10AV-5LSN
3.3
5.0ns
Low
QFNS
32
C
ispGAL22V10AV-5LNN1
3.3
5.0ns
Low
QFN
32
C
ispGAL22V10AV-75LSN
3.3
7.5ns
Low
QFNS
32
C
ispGAL22V10AV-75LNN1
3.3
7.5ns
Low
QFN
32
C
1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08.
Industrial
Part Number
Voltage
tPD
Power
Package
Pin Count
Grade
3.3
5.0ns
Low
QFNS
32
I
1
ispGAL22V10AV-5LNNI
3.3
5.0ns
Low
QFN
32
I
ispGAL22V10AV-75LSNI
3.3
7.5ns
Low
QFNS
32
I
3.3
7.5ns
Low
QFN
32
I
ispGAL22V10AV-5LSNI
1
ispGAL22V10AV-75LNNI
1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08.
Note: For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For
example, the commercial speed grade -5LJ is also marked with the industrial grade -7LJI. The commercial grade is
always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed
grade is marked as commercial grade only.
16
Lattice Semiconductor
ispGAL22V10AV/B/C Data Sheet
Revision History
Date
Version
—
03.0
Previous Lattice releases.
Added 32-pin QFNS package Ordering Part Number information per PCN #13A-08.
A
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U
ED
—
December 2008
Change Summary
17