ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV March 2007 Application Note AN6059 Introduction The Lattice Semiconductor ispPAC®-POWR1208P1 In-System-Programmable Analog Circuit allows designers to implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208P1 provides the power-supply designer with a rich set of features in a single device. ISP™ (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic functions. All configuration data is stored internally in E2CMOS® nonvolatile memory. Programming a configuration is accomplished through an industry-standard JTAG IEEE 1149.1 interface. PAC-POWR1208P1-EV Evaluation Board The PAC-POWR1208P1-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the ispPAC-POWR1208P1 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP package, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD® programming cable connected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the ispPAC-POWR1208P1 can be easily configured using PAC-Designer® software. Figure 1. PAC-POWR1208P1-EV Evaluation Board © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 an6059_01.1 ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV Lattice Semiconductor A complete schematic for the evaluation board is shown in Figure 2. Figure 2. Schematic VDD VDDINP VDD R1B 470 R1D 470 LED POWER 5 11 VDD 26 CLK VDDINP J9 C3 0.1U J7.5 C1 0.1U C5 4.7U R1E 470 R1F 470 LED OUT5 VDDINP R1G 470 R10 2k LED OUT7 LED OUT6 CLK R9 2k R8 2k R7 2k LED OUT8 12 VDDINP OUT5 OUT6 OUT7 VDDINP OUT8 VDD OUT5 13 OUT6 14 OUT7 15 OUT8 VDD R2 10K J7.1 C4 0.1U R3 2k ispPAC-POWR1208P1 25 POR P5 VMON1 33 VMON2 34 VMON3 35 VMON4 36 VMON5 37 VMON6 VMON1 HVOUT2 VMON2 HVOUT3 VMON3 HVOUT4 VMON9 VMON10 VMON11 VMON12 7 IN2 8 IN3 9 IN4 COMP1 COMP2 COMP3 COMP4 COMP5 COMP6 IN1 COMP8 IN2 CREF IN3 IN4 TDI VDD 30 TCK 24 TMS TDO 31 VDD P1 R4 2k R5 2k R6 2k J8 4 HVOUT1 3 HVOUT2 2 HVOUT3 1 HVOUT4 VMON6 COMP7 6 IN1 VDDINP VMON5 VMON7 40 VMON8 41 VMON9 42 VMON10 43 VMON11 44 VMON12 VMON8 VDD VMON4 38 VMON7 J7.4 POR HVOUT1 32 J7.3 P5 SW1 Reset J7.2 RESET GND 28 S 27 23 COMP1 22 COMP2 21 COMP3 20 COMP4 19 COMP5 18 COMP6 17 COMP7 16 COMP8 39 C2 1U VDD TDO LED R1C 470 VDD CH TDI TDI TDO TDO TMS TMS TCK TCK GND GND P2 10 RESET Programming Interface Lattice Semiconductor’s ispDOWNLOAD® cable can be used to program the ispPAC-POWR1208P1 on the evaluation board. This cable plugs into a PC-compatible’s parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispDOWNLOAD cable terminates in an 8-pin 0.100” pitch header connector which plugs directly into a mating connector provided on the PAC-POWR1208P1-EV evaluation board. Prototype Area A 19x18 grid (0.100” pitch) of uncommitted, plated through holes with annular-ring pads is provided as a user prototyping area. Adjacent to this uncommitted array are two 19-hole rows providing easy connections to both power and ground. This prototyping area allows the user to build small circuits directly on the evaluation board. In the case of larger circuits, the evaluation board can be readily connected into off-board circuitry through P5, into which can be mounted a 20 x 2 header. Power Supply Considerations The ispPAC-POWR1208P1 operates with power supplies ranging from 2.7V to 5.5V, and allows for separate core (VDD) and I/O (VDDINP) voltages. Voltages ranging from 0 to 5.94V may be monitored at any of the 12 VMONx 2 ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV Lattice Semiconductor pins independent of the values of VDD and VDDINP. For device programming, however, VDD must be set between 3.0 and 5.5V. On the evaluation board, VDD and VDDINP are normally connected together with a user-removable jumper (J7.5). This jumper can be removed to allow for independent VDD and VDDINP supplies. Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 3. Power is supplied through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board. The JTAG programming cable is connected to a keyed header (P1) in the lower right corner of the board. A PCB land pattern is provided for the addition of an additional JTAG interface header (P2) to allow for connecting multiple PAC-POWR1208P1-EV evaluation boards into a multi-device programming chain. Access to the ispPAC-POWR1208P1’s I/O pins is available at P5, which is a 2x20 row of pads to which one may attach test probes or a ribbon-cable connector. At this point all of the device’s I/O pins (except those required for the JTAG programming interface) are accessible. Figure 3. I/O and Jumpers J9 J8 VDD J7 VDD OUT[5-8] HVOUT PULL-UP 1 2 3 4 VDD GND VDD HVOUT[1-4] VDDINP VDDINP VDDINP P5 VMON1 VMON3 VMON2 VMON4 VMON5 VMON7 VMON9 VMON11 HVOUT4 HVOUT2 VDD VMON6 VMON8 VMON10 VMON12 HVOUT3 HVOUT1 IN1 IN2 IN4 VDDINP GND OUT5 OUT7 IN3 RESET GND GND OUT6 OUT8 COMP8 COMP6 COMP4 COMP2 POR COMP7 COMP5 COMP3 COMP1 CLK OUT8 ispPACPOWR1208P1 OUT7 OUT6 OUT5 RESET P1 Power TDO JTAG Interface 1 Jumper Options Several jumpers are provided on the evaluation board to make it simple to implement common circuit configurations. These jumpers are: • J7 - positions 1-4 connect pull-up resistors to the high voltage outputs HVOUT1-4, and allow the user to enable the pull-ups on an output-by-output basis. The pull-up voltage is selected by J8. Position 5 (the rightmost position) is used to connect VDDINP to VDD, and should normally be left in place. This jumpers needs to be removed when using separate VDD and VDDINP supplies. • J8 - Selects a pull-up voltage to which the High-Voltage outputs (HVOUT1-4) may be pulled up to, either VDD or VDDINP. 3 ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV Lattice Semiconductor • J9 - Selects whether open-drain digital outputs OUT5-OUT8 are pulled up to VDD (upper position), VDDINP (lower position), or not pulled up at all. These outputs are pulled up through 2KΩ resistors. Controls and Indicators A reset switch is provided on the evaluation board which pulls the RESET input pin low when it is depressed, re-initializing the ispPAC-POWR1208P1. LEDs are also provided as an aid to debugging. One LED shows whether the board has power applied, while another is connected to the JTAG TDO line, and will flash when a download is being performed. Additionally, four LEDs are attached to the ispPAC-POWR1208P1’s OUT5-OUT8 lines. By adding appropriate code to the sequencer program, these LEDs can be made to indicate the internal status of the ispPAC-POWR1208P1, and can be a useful debug aid. PCB Artwork Figure 4. Silk Screen 4 ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV Lattice Semiconductor Figure 5. Top-side Foil Figure 6. Bottom-side Foil 5 ispPAC-POWR1208P1 Evaluation Board PAC-POWR1208P1-EV Lattice Semiconductor Component List Quantity Ref. Designators Description 2 C1, C3 0.1µF capacitor 1 C2 1µF capacitor 1 C4 0.1µF capacitor 1 C5 4.7µF capacitor 1 J7 2 x 5 header strip, dual row, 0.1” spacing 2 J8,J9 1 x 3 header strip, single row, 0.1” spacing 5 LED_A, LED_B, LED_C, LED_D, POWER_LED T-1-3/4 red LED 1 P1 1x8 header strip, single row, 0.1” spacing 1 P3 Red banana jack 1 P4 Black banana jack 1 R1 470 ohm SIP-8 resnet, 7-resistor SIP, bussed type 1 R2 10K resistor 8 R3, R4, R5, R6, R7, R8, R9, R10 2K 5% resistor 1 SW3 Pushbutton switch 1 TDO_LED T1-3/4 green LED 1 U1 ispPAC-POWR1208P1 Ordering Information Description Ordering Part Number ispPACPOWR1208 Precision Evaluation Board PACPOWR1208P1-EV ispPAC Power Manager 1208 Precision Design System PAC-SYSPOWR1208P1 China RoHS Environment-Friendly Use Period (EFUP) Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: [email protected] Internet: www.latticesemi.com Revision History Date Version Change Summary February 2005 01.0 Previous Lattice releases. March 2007 01.1 Added Ordering Information section. 6 10