LatticeECP3 PCI Express Solutions Board


LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
August 2012
Revision: EB43_01.2

LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Introduction
As PCI Express applications have emerged, the LatticeECP3™ FPGA family has become a well-suited solution for
many system designs. The features of the LatticeECP3 PCI Express Solutions Board can assist engineers with
rapid-prototyping and testing their designs. The board is an enhanced form-factor of the PCI Express add-in card
specification. It allows for full x1 form-factor compliance and x4 is available for demonstration purposes with some
non-standard form-factor issues. The flexibility to use the same board to demonstrate both x1 and x4 configurations
is accomplished by simply changing the mounting hardware. The board has several debugging and analyzing features for complete evaluation of the LatticeECP3 device. This guide is intended to be referenced in conjunction with
evaluation design tutorials to demonstrate the LatticeECP3 FPGA.
This user’s guide describes the LatticeECP3 PCI Express Solutions Board featuring the LatticeECP3 LFE3-95EAFN672 FPGA. The stand-alone evaluation board provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces to demonstrate PCI Express capabilities using an
add-on card form-factor. The board is manufactured using standard FR4 dielectric and through-hole vias. The nominal impedance is 50-ohm for single-ended traces and 85-ohm for differential traces.
Important: This document (including the schematics in the appendix) describes LatticeECP3 PCI Express Solutions Boards marked as Rev A. This marking can be seen on the silkscreen of the printed circuit board, under the
Lattice Semiconductor logo.
Figure 1. LatticeECP3 PCI Express Solutions Board
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Features
• PCI Express x1 and x4 edge connector interfaces
• Allows demonstration of PCI Express (x 1and x4) interfaces
– x1 is form-factor compliant and will fit a standard PC-equipped PCI Express motherboard socket
– x4 is non-compliant but will demonstrate x4 functionality by a simple change to the hardware
• Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
• On-board Boot Flash
– Both Serial SPI Flash and Parallel Flash via MachXO™ programming bridge
• Shows interoperation with a high performance DDR2 memory component
• Includes driver based “run-time” device configuration capability via ORCAstra or PCI Express
• Switches, LEDs, displays for demo purposes
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board.
Figure 2. PCI Express Solutions Board Outline Drawing, Top Side
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 3. PCI Express Solutions Board Outline Drawing, Bottom Side
x1 and x4 PCI Express Support
PCI Express x1 and x4 is supported with the same PCB. This add-in PCB is designed to work in both types of
motherboard slots. The PCB complies with the width and length dimensions of the PCI Express Card Electromechanical (CEM) Specification Revision 1.1. The only exclusion of the CEM specification is the component and back
side of the add-in board may interfere with other boards in a fully-populated motherboard.
This board is easily interchanged from x1 to x4 configurations by removing the back-panel bracket and reinstalling
it on the opposite side. This permits plug-in into PCI Express sockets on the motherboard and securing it in the
chassis if desired. The back-panel bracket is shown below.
Figure 4. Back Panel Drawing
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
LatticeECP3 Device
This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP3 devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP3 Family Data Sheet on the Lattice website at www.latticesemi.com.
Note: The connections referenced in this document refer to the LFE3-95EA-FN672 device. Available I/Os and
associated sysI/O™ banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeECP3 PCI Express Solutions Board is ready to power on. The board can be supplied with power from
an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a benchtop supply via
terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host
board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J1 and plug the wall-transformer into an AC wall-outlet.
Power Supplies
(see Appendix A, Figure 21)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a benchtop supply adjusted
to provide a nominal +12V DC.
All input power sources and on-board power supplies are fused with surface-mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses (see Appendix A, Figure 21)
F1
12V Fuse
F2
1.2V Core Fuse
F3
3.3V Fuse
F4
1.8V Fuse
F5
1.2V Analog Supply
Table 2. Board Power Supply Indicators (see Appendix A, Figure 21)
D1
3.3V Source Good Indicator
D2
1.2V VCC Core Source Good Indicator
D3
1.8V Source Good Indicator
D4
1.2V Analog Source Good Indicator
D5
12V Input Good Indicator
External power can be alternatively connected rather than the wall transformer power pack.
Table 3. External Board Supply Input Terminal (see Appendix A, Figure 21)
TB1
Screw terminal for +12V DC
Pin1 (square PCB pad): +12V DC
Pin2: Ground
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
PCI Express Power Interface
Power can be sourced to the board via the PCB edge-fingers (CN1 and CN2). This interface allows the user to provide power from a PCI Express Host board.
Programming/FPGA Configuration
(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
ispVM Download Interface
J4 and J8 are 6-pin JTAG connectors used in conjunction with the ispVM USB download cable to program and control the device. These connectors are available through the back-panel bracket as needed for x1 or x4 PCI Express
configurations. These connectors are used in conjunction with the ispVM programming cable and software to program the configuration memory or FPGA directly.
Table 4. Standard ispVM Programming Cable Configuration
Pin 1
VCC
Pin 2
TDO
Pin 3
TDI
Pin 4
TMS
Pin 5
GND
Pin 6
TCK
After initial board setup, use the following procedure to program the evaluation board. Instructions assume ispVM
software has been installed on a local PC.
Connect the ispDOWNLOAD cable rainbow colored flywires to the connector J4.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 5. ispVM JTAG Connector (see Appendix A, Figure 21)
6
5
4
3
2
1
Note: A dot denotes PIN 1 on the both the
PCB or back-panel bracket.
Pin
Function
Color
1
PWR
Red
2
TDO
Brown
3
TDI
Orange
4
TMS
Purple
5
GND
Black
6
TCK
White
Figure 5. ispVM Programming Cable Connector
Programming the Daisy Chain
This board includes two Lattice Semiconductor programmable (U1=LFE3-95, U12=LCMXO1200) devices that can
be programmed in a daisy chain.
Figure 6. JTAG Chain
TCK
TMS
TDI
TDO
TCK
LatticeECP3
FPGA
(U1)
7
TMS
TDO
TDI
MachXO1200
CPLD
(U13)
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Download Procedures
Requirements:
• PC with ispVM System v.17.7 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.)
JTAG Download
The LatticeECP3 device can be configured easily via its JTAG port. The device is SRAM-based; it must remain
powered on to retain its configuration when programmed in this fashion.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used for the 1x6 connection. J8 is used in
the same manner for x4 configurations.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LatticeECP3 and the MachXO1200 devices should be automatically detected.
Figure 7. ispVM Main Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse
button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
6. To program only the LatticeECP3-95, place the LCMXO1200C device into BYPASS and the LFE3-95 should be
in FAST PROGRAM mode.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 8. ispVM Fast Programming Mode
Figure 9. ispVM Device Information Dialog Box
7. Add Data File.
8. Click the green GO button. This will begin the download process into the device. Upon successful download, the
device will be operational.
Configuration Status Indicators
(see Appendix A, Figure 23)
These LEDs indicate the status of configuration to the FPGA.
• D6 (red) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low.
• D9 (green) is illuminated, this indicates the successful completion of configuration by releasing the open collector
DONE output pin.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
• D10 (green) will flash indicating TDI activity.
• D8 (red) illuminated, this indicates that PROGRAMN is low.
• D7 (red) illuminated, this indicates that GSRN is low.
PROGRAMN & GSRN
(see Appendix A, Figure 23)
• These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3 or SW7) and GSRN
(SW1 or SW6). Depressing the button drives a logic level “0” to the device.
• These push-buttons are accessible from the back panel if the evaluation board is mounted in a PCI Express slot
of a PC.
CFG [2:0]
(see Appendix A, Figure 23)
• The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch.
• JTAG programming is independent of the MODE pins and is always available to the user.
• Pushing in (depressing) the switch is ON and sets the value to 0.
Table 6. CFG Mode Selections
CFG2
CFG1
CFG0
Configuration Mode
SPI Flash
0 (ON)
0 (ON)
0 (ON)
0 (ON)
1 (OFF)
0 (ON)
SPIm
1 (OFF)
0 (ON)
1 (OFF)
Slave Serial
1 (OFF)
1 (OFF)
1 (OFF)
Slave Parallel
X
(don’t care)
X
(don’t care)
X
(don’t care)
ispJTAG™
On-Board Serial SPI Flash Memory
(see Appendix A, Figure 23)
• One Serial SPI (16-pin tssop 64M) Flash memory device (U6) is on-board for non-volatile configuration memory
storage. Either a STMicro M25P64VMF16 or Macronix MX25L6405 device is populated on-board.
• All CFG [2:0] need to be [000] depressed to read the Flash memory at power-up or after toggling the PROGRAMN pin.
• Install jumper across pins 2 and 4 on J2.
Programming Serial SPI Flash Memory
The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to
be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power-up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used with the cable.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LFE3-95 and the LCMXO1200C devices should be automatically detected.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 10. Results of Scanning Board via ispVM
5. Double-click the Operation column for the LFE3-95 and the Device Dialog box shown below will open.
6. In the dialog box, select the SPI Flash Programming mode in the Device Access Options pull-down menu.
This will open the SPI Serial Flash Dialog box.
Figure 11. Device Information Dialog Screen
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 12. SPI Serial Flash Dialog Screen
7. The SPI Serial Flash Device dialog box will open. In this box select SPI Flash Erase, Program, Verify in the
Operation pull-down menu.
8. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu,
SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
Figure 13. Select Device Dialog Box
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 14. Sample SPI Serial Flash Device Dialog Box
9. Click OK in the SPI Flash Device dialog box. Then click OK in the Select Device dialog box. You will then
return to the main configuration screen. If you do not desire to load the LCMXO1200C device, this device
should be placed in Flash Bypass mode by double-clicking the Operation column and selecting the Bypass
operation shown below.
Figure 15. FLASH Bypass for LCMXO1200C Device
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 16. Programming Main Window
10.From the main programming window, select GO in the top toolbar. This will begin the SPI Serial Flash programming.
Figure 17. SPI Serial Flash Programming Status Window
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 18. Successful SPI Serial Flash Programming Session
On-Board Parallel SPI Flash Memory
(see Appendix A, Figure 24)
• A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO CPLD device to act as a programming bridge from the Flash device.
• The CFG [2:0] need to be [111], all up.
• Lattice ispVM programming software can be used to program either the serial SPI Flash or the parallel Flash
devices. Application note AN8077, Parallel Flash Programming and FPGA Configuration, addresses the use of
the parallel Flash implementation. Note: For parallel Flash loading, the board needs the appropriate connections
of J2. J2 requires a jumper be installed between pins 1 and 3.
User-Defined General Purpose Clock Oscillator
(see Appendix A, Figure 27, Y1)
A 100MHz oscillator is included on-board. It is fanned-out to several destinations on the board, as described in
Table 7.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 7. 100MHz Clock Destinations
Clock Destination
PCB Designation
Destination Pin
CPLD
U12
A8
FPGA
U1
P21-PCLKT2_0
FPGA
U1
K3-LLUM0-GDLLT_IN
FPGA
U1
M4-PCLKT7_0
SERDES
(see Appendix A, Figure 25)
SERDES/FPGA Reference Clocks
The 50-ohm terminated SMA connectors are optionally provided to supply reference clocks directly to the
LatticeECP3 device. Please contact the factory for information to populate the PCB with SMA connectors.
Table 8. SMA Inputs for External Clock Source
Connector
SERDES Signal
FPGA Pin
J6
FPGA_SMA_REFCLKP
V20
J7
FPGA_SMA_REFCLKN
W19
SERDES PCI Express Channels
(see Appendix A, Figure 25)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edgefingers (CN1 or CN2) that fit directly into a PCI Express host receptacle. Power can be supplied directly from the
PCI Express host via the edge-finger connections.
Table 9. x1 PCI Express Connections
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSA_HDOUTP_0
AF21
PERp0
A16
PCSA_HDOUTN_0
AF20
PERn0
A17
PCSA_HDINP_0
AD21
PETp0
B14
PCSA_HDINN_0
AD20
PETn0
B15
PCSA_REFCLKP
AC17
PCIe_CLKp
A13
PCSA_REFCLKN
AC18
PCIe_CLKn
A14
PCIE_PERSETN
U20
PERSTN
A11
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
Table 10. x4 PCI Express Connections
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSB_HDOUTP_0
AF13
PERp0
A16
PCSB_HDOUTN_0
AF12
PERn0
A17
PCSB_HDINP_0
AD13
PETp0
B14
PCSB_HDINN_0
AD12
PETn0
B15
PCSB_HDOUTP_1
AF10
PERp1
A21
PCSB_HDOUTN_1
AF11
PERn1
A22
PCSB_HDINP_1
AD10
PETp1
B19
PCSB_HDINN_1
AD11
PETn1
B20
16
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 10. x4 PCI Express Connections (Continued)
CML Pin Name
FPGA Pin
PCIE
PCI Express Edge
PCSB_HDOUTP_2
AF9
PERp2
A25
PCSB_HDOUTN_2
AF8
PERn2
A26
PCSB_HDINP_2
AD9
PETp2
B23
PCSB_HDINN_2
AD8
PETn2
B24
PCSB_HDOUTP_3
AF6
PERp3
A29
PCSB_HDOUTN_3
AF7
PERn3
A30
PCSB_HDINP_3
AD6
PETp3
B27
PCSB_HDINN_3
AD7
PETn3
B28
PCSB_REFCLKP
AC9
PCIe_CLKp
A13
PCSB_REFCLKN
AC10
PCIe_CLKn
A14
PCIE_PERSETN
U20
PERSTN
A11
Description
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block transmit pair
Integrated endpoint block receive pair
Integrated endpoint block differential clock pair
Fundamental PCI Express reset
FPGA Test Pins
(see Appendix A, Figure 27)
General Purpose DIP Switch
(see Appendix A, Figure 27, SW5)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW5) which
is an SPST side actuated DIP switch. The switch is physically located on the secondary side of the PCB along the
back-panel edge. The switches are connected to a logic level 0 when depressed toward the board and a 1 when
away from the board. The designated pins are connected according to Table 11.
Table 11. FPGA Test Pins (See Appendix A, Figure 26)
FPGA BGA
SW5 Switch Position
D9
1
F9
2
G8
3
A6
4
A5
5
E9
6
E8
7
A7
8
Logic 1
PCB
Logic 0
17
1
2
3
4
5
6
7
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 19. 8-position DIP Switch (SW5) on Secondary PCB Side
General Purpose LEDs
(see Appendix A, Figure 27)
LEDs are provided along the back panel edge of the PCB. These LEDs are connected to general-purpose FPGA
I/Os. The LEDs are illuminated by the associated FPGA outputs being driven to a valid LOW level. The use of these
LEDs is defined for PCI Express applications to observe the status of the PCI Express link during operation. The
LEDs must be included in the FPGA design. These status LEDs are available in both x1 or x4 configurations. The
back panel marking reflects PCI Express specific status.
Table 12. LED Definitions
PCI Express x1
PCI Express x4
FPGA Pin#
PCB Designator
FPGA Pin#
PCB Designator
Description
H11
D19
C10
D20
User defined
H10
D21
A9
D22
User defined
F11
D26
A10
D27
User defined
G11
D24
B10
D25
User defined
D10
D11
D10
D12
Data link up active
F10
D13
A8
D14
L0 state active
G9
D15
B8
D16
Polling state inactive
G10
D17
C9
D18
PLL locked
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
General-Purpose Header
(see Appendix A, Figure 27, J5)
A 2x9 header (J5) provides a general-purpose connection to communicate with general purpose FPGA I/Os.
Table 13. General Purpose Header Connections
Header Pin
FPGA Pin
Header Pin
FPGA Pin
1
GND
2
GND
3
C15
4
E15
5
B15
6
E14
7
C14
8
A20
9
D14
10
A19
11
B16
12
C17
13
C16
14
B17
15
F13
16
A18
17
F14
18
A17
17-Segment LED Display
(see Appendix A, Figure 27, D13)
General-purpose FPGA pins are connected to a 17-segment display according to Table 14. These pins can be
driven low to illuminate the display segments.
Table 14. 17-Segment LED Display
Segment
BGA
A
B7
B
F8
C
F7
D
A4
E
A3
F
H8
G
G7
H
C8
K
D8
M
B4
N
C5
P
C6
R
D6
S
C4
T
D5
U
C7
DP
B6
A
H
B
K M N
U
G
P
T S
F
C
R
E
D
DP
Logic Analyzer Probe
(see Appendix A, Figure 27, LA1)
An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to utilize for test points. This connection provides 34 general I/O signals to be observed on a Logic Analyzer probe using
Mictor connections such as the Agilent 5346A.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 15. Logic Analyzer To FPGA Pin Reference
Signal
FPGA Pin
Signal
FPGA Pin
LA1
AA25
LA2
Y24
LA3
W23
LA4
W22
LA5
AA26
LA6
AB26
LA7
W21
LA8
W20
LA9
AD26
LA10
AD25
LA11
AA24
LA12
AA23
LA13
AC26
LA14
AC25
LA15
Y19
LA16
Y20
LA17
AB24
LA18
AC24
LA19
Y22
LA20
AA22
LA21
AE25
LA22
AF24
LA23
AD24
LA24
AE24
LA25
AD23
LA26
AC23
LA27
AB20
LA28
AB21
LA29
AF23
LA30
AE23
LA31
W17
LA32
AB23
LA33
AB22
LA34
Y21
DDR2 Memory Devices
(see Appendix A, Figure 26, U14)
• The LatticeECP3 PCI Express Solutions Board is equipped with a 84-ball BGA DDR2 SDRAM memory device
such as a Micron MT47H16M16BG-3 device.
• The DDR2 memory interfaces include a 16-bit wide device.
• The evaluation board includes termination of address and command signals. It includes all power and external
components needed to demonstrate the memory controller of the LatticeECP3 device.
CPLD Device
(see Appendix A, Figure 24, U12)
The board includes a Lattice Semiconductor LCMXO-1200C CPLD. This device is used in conjunction with the parallel Flash device for loading the configuration memory of the FPGA. It is also used for general-purpose board
management functions. It has several connections to the FPGA and other devices on the PCB. It includes an active
high, push-button (SW4) if needed for a user design.
Generic user-defined interconnections are defined in Table 16.
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LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 16. CPLD TO FPGA Interconnections
CPLD Pin
FPGA Pin
M1
B2
P13
B3
P10
D4
N7
E4
N8
C3
P11
D3
N13
G5
N1
G6
N3
E3
N4
F4
P1
H6
M12
J6
M2
C2
M3
D2
M4
K8
M6
J7
Ordering Information
Description
Ordering Part Number
LatticeECP3 PCI Express Development Kit
(Includes LatticeECP3 PCI Express Solutions
Board)
China RoHS Environment-Friendly
Use Period (EFUP)
LFE3-95EA-PCIE-DKN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail:
[email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
March 2010
01.0
Initial release.
December 2010
01.1
LED definitions table, L0 state changed from active to inactive.
Download Procedures section, changed ispVM requirement from ispVM
v.17.4 (or later) to ispVM v.17.7 (or later).
August 2012
01.2
Updated document with new corporate logo.
Replaced Programming schematic.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
21
22
A
B
C
5
CH0
PCIe-X1
LOOPS
CH1, CH2
CH3
PCIe-X4
PCIE_CLOCK
PCSA
PCSB
PCIE_CLOCK
STATUS LEDs
100MHZ
GENERAL
OSC.
DIP SWITCH
4
LOGIC ANALYZER PROBE
16- GPIO HEADER
SMA CLOCK
4
16-bit DDR2
D
5
JTAG/ISPVM
16-SEGMENT DISPLAY
3
3
2
2
Date:
Size
C
Title
Thursday, May 21, 2009
1
Sheet
1
ECP3 PCIe DevKit Eval Board
Project
Cover Page
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Appendix A. Schematic
Figure 20. Cover Page
A
B
C
D
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
LP2
1
1
1
LP3
1
5016
5
1
5016
1
1
5016
LP5
1
1_2V_A
1_8V
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
TestPoint
1
1
TP12
1
TP10
1
1
TP8
TP6
1
TP4
1
TP2
1
5016
LP4
1
1
5016
LP1
1
1
1
TP11
1
TP9
TP7
TP5
TP3
TP1
VCC_CORE
3_3V
GND Pads
Distributed around the board
8
R1
1_8K-1206SMT
G
1.2V
VCC_CORE
1
2
3
4
5
6
7
GND
VIN
3.3V
R21
10K-0603SMT
SENSE
VOUT
4
C7
F3
Q1
2N2222/SOT23
R3
1_8K-1206SMT
+
+
8
330UF-FKSMT
C3
C6
+
10UF-16V-TANTBSMT
3_3V
R8
1
10K-0603SMT
1_2V_A
LED-SMT1206_GREEN
D4
1.2V
Analog
F4
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
330UF-FKSMT
C8
+
1_8V
R10 0R-0603SMT
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
1.8V
3_3VIN
806R-0603SMT
R18
3_3V
5
6
R7
1
10K-0603SMT
LED-SMT1206_GREEN
D3
1_8V
1.8V
R2
1_8K-1206SMT
10UF-16V-TANTBSMT
1K-0603SMT
R17
12_0V
G
Q3
2N2222/SOT23
R14
2K-0603SMT
PTH12060W
1_8V
1_8_TRIM
R15
100R-0805SMT
GND
R12
OPEN-0805SMT
1
2
U3
R6
1
10K-0603SMT
LED-SMT1206_GREEN
D2
VCC_CORE
12_0V
ILIM
IN
CNTL
GND
OUT
SENSE
EN
SC1592
TAB
U4
Q2
2N2222/SOT23
3
2
G
3
2
3
2
12_0V
3
ILIM
IN
CNTL
GND
OUT
SENSE
EN
1
2
3
4
5
6
7
R5
220R-0603SMT
3.3V
D1
R22
10K-0603SMT
1
2
U2
12_0V
GND
VIN
+
1.2V
Analog
C9
5
2
12_0VIN
VCC_CORE
1
+
F5
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
330UF-FKSMT
C10
+
1_2V_A
J1
330UF-FKSMT
C5
+
C1
Date:
Size
C
Title
GND
+12VDC
+
100UF-FKSMT
12_0V
F1
F1251CT-ND
10A Fast-Blo SMT Socketed Fuse
Thursday, March 26, 2009
1
Sheet
2
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
ECP3 PCIe DevKit Eval Board
Project
Power Generation
C2
12_0V
Terminal Block/ED1202DS
TB1
470UF-FKSMT
+
12_0V
2
1
12_0VIN
POWER INPUT
D33
SCHOTTKY/VISHAY-V12P10
F1228CT-ND
5A Fast-Blo SMT Socketed Fuse
R9
F2
0R-0603SMT
C4
10UF-16V-TANTBSMT
SENSE
6
1.2V
Core
Male Power Jack 2.1mm
22HP037-2.1mm 3
R13
12_1K-0603SMT
PTH12060L
2K-0603SMT
R20
3_3V
R4
VOUT
LED-SMT1206_GREEN
D5
12VIN GOOD
2
12_0V
1_8K-1206SMT
10UF-16V-TANTBSMT
1K-0603SMT
R19
VCCA_TRIM
12_0V
R11
OPEN-0805SMT
1_2V_A
R16
100R-0805SMT
GND
LED-SMT1206_GREEN
SC1592
TAB
U5
G
3_3V
9
12_0V
3
MUP
4
G
POWER RAIL GOOD INDICATORS
MUP
10
INHIBIT#
3
8
TRACK
9
MDWN
ADJUST
4
GND
7
10
INHIBIT#
3
MDWN
ADJUST
4
8
TRACK
12_0V
3_3V
23
3_3V
GND
7
2
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 21. Power Generation
A
B
C
5
C32
VCC_CORE
K11
K12
K13
K14
K15
K16
L10
L11
L12
L15
L16
L17
M11
M16
N10
N17
P10
P17
R11
R16
T10
T11
T12
T15
T16
T17
U11
U12
U13
U14
U15
U16
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCPLL_L
VCCPLL_L
VCCPLL_R
VCCPLL_R
C28
C35
ECP3-672fpBGA
U1J
C49
C50
C51
C52
C33
1_2V_A
V13
V14
W12
W13
W14
W15
Y13
Y14
J11
J16
J18
J9
L18
L9
T18
T9
V11
V16
V18
V9
M10
R10
M17
R17
VCC_PLL
3_3V
C62
C63
C64
C65
C53
C66
10NF-0603SMT
C54
C67
10NF-0603SMT
C34
C68
10NF-0603SMT
C55
+ C29
22UF-16V_TANTBSMT
C79
C82
C80
C84
C85
C86
+ C81
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C83
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C78
MH2
M HOLE2
MH1
M HOLE2
4
C77
VCC_PLL
M HOLE2
MH3
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C61
10NF-0603SMT10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
FB1
BLM41PG600SN1
3_3V
C31
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
100NF-0603SMT
100NF-0603SMT 100NF-0603SMT 100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
C30
VCC_CORE
ECP3-672fpBGA
U1I
22UF-16V_TANTBSMT
ECP3-672fpBGA
U1K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3
3
A2
A25
AA13
AA14
AA18
AA19
AA21
AA6
AA8
AA9
AB19
AB2
AB25
AB8
AC11
AC12
AC13
AC14
AC15
AC16
AC19
AC20
AC21
AC22
AC5
AC6
AC7
AC8
AD22
AD5
AE1
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE26
AE5
AE6
AE7
AE8
AE9
AF2
AF22
AF25
AF5
B1
B14
B18
B22
B26
B5
B9
D11
D16
D20
D7
E2
E25
F21
F6
G12
G15
G23
G4
H18
H9
J12
J15
J19
J2
J25
J8
K10
K17
L13
L14
L23
L4
M12
M13
M14
M15
M18
M20
M7
M9
N11
N12
N13
N14
N15
N16
N2
P11
P12
P13
P14
P15
P16
P25
R12
R13
R14
R15
R20
R7
R9
T13
T14
T19
T23
T4
U17
V12
V15
V19
V2
V25
W11
W16
Y10
Y11
Y12
Y15
Y16
Y17
Y18
Y23
Y4
Y9
C20
C12
C13
3_3V
1_8V
C15
C21
C22
C37
C38
C39
C23
C40
10NF-0603SMT
C41
C46
C47
C57
C58
C59
C60
C73
C74
C70
2
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C72
C24
C17
C43
C25
C76
100NF-0603SMT 10NF-0603SMT
C75
+ C69
+ C44
10NF-0603SMT
100NF-0603SMT 10NF-0603SMT
C42
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C56
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C45
C16
10NF-0603SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C36
C14
C18
Date:
Size
C
Title
C71
C48
C26
22UF-16V_TANTBSMT
Monday, February 23, 2009
1
Sheet
3
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
1
ECP3 PCIe DevKit Eval Board
Project
Power Supplies
+ C27
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
1000PF-0402SMT
C11
10NF-0603SMT 10NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C19
1_2V_A
2
1UF-16V-0805SMT
1UF-16V-0805SMT
4
1UF-16V-0805SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
24
1UF-16V-0805SMT
D
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 22. Power Supplies
1UF-16V-0805SMT
A
B
C
Q4
2N2222/SOT23
D9
220R-0603SMT
G
3
C87
2
R31
10K-0603SMT
DONE
[5] GSRN
C88
3_3V
PROGRAMN
SW1
FPGA GSRN
5
6
3
SW PUSHBUTTON-SPST
SW3
PROGRAMN
SW PUSHBUTTON-SPST
SW7
SW PUSHBUTTON-SPST
SW1 and SW3 on Primary Side
SW6 and SW7 on Secondary Side
GSRN
SW6
SW PUSHBUTTON-SPST
PROGRAMN
& GSRN
Pushbuttons
FPGA_CSSPI0N_DI
SPI0_Q
FLASH_DIS
D8
2Y
1Y
1
2
3
4
5
6
7
8
U6
5
4
2
1
3
1
SN74LVC125A/SO14
2A
2OE_N
1A
1OE_N
U9A
3_3V
M25P64-FLASH
HOLD# CK
VCC
D
DU8
DU1
DU2
DU7
DU6
DU3
DU4
DU5
S#
VSS
Q
W#
OUT2
OUT1
MAX6817
IN2
IN1
U7
16
15
14
13
12
11
10
9
4
6
SPI_CLK
FPGA_SISPI
R32
R33
R34
10K-0603SMT
10K-0603SMT
10K-0603SMT
3_3V
680R-0603SMT
R24
LED-SMT1206_RED
SPI FLASH
CONFIG
Status LEDs
1
D7
Y
PROGRAMN
LED-SMT1206_RED
DONE indicator will light when
configuration is successfully
completed
R39
10K-0603SMT
D
100NF-0603SMT
R26
LED-SMT1206_GREEN
10NF-0603SMT
LED-SMT1206_RED
R44
INITN
C89
11
8
3_3V
4Y
3Y
3_3V
4
CFG1
CFG0
R48
10K-0603SMT
R49
10K-0603SMT
0(ON)
1(OFF)
1(OFF)
X
0(ON)
1(OFF)
0(ON)
1(OFF)
X
ON
CFG2
CFG1
1(OFF)
1(OFF)
0(ON)
0(ON)
CFG0
X
[5]
R27
10K-0603SMT
3_3V
SW2INS38259285
SW DIP-3 CTS 194-3MST
ispJTAG
3
Slave Parallel
Slave Serial
SPIm
SPI Flash
Configuration Mode
R35
10K-0603SMT
R28
10K-0603SMT
FPGA_WRITEN
R29
10K-0603SMT
4
6
OUT Y2
OUT Y1
[5] TCK_BUF
TCK_BUF
TMS_BUF
4
6
OUT Y2
OUT Y1
NC7WZ16-MACO6A/Fairchild TinyLogic
R47
220R-0603SMT
D10
LED-SMT1206_GREEN
This LED
indicates activity
on TDI.
TDI_BUF
NC7WZ16-MAAO6A/Fairchild TinyLogic
JTAG
3_3V
[5] TMS_BUF
FPGA_SISPI
FPGA_D7
SPI0_Q
FPGA_D7
FPGA_D6
FPGA_D5
FPGA_D4
FPGA_D3
FPGA_D2
FPGA_D1
FPGA_D[0..7] [5]
FPGA_D0
FPGA_MCLK
FPGA_WRITEN
FPGA_WRITEN [5]
FPGA_CSSPI1N_DOUT
FPGA_CSSPI0N_DI
FPGA_CSN
FPGA_CSN [5]
FPGA_CS1N
FPGA_CS1N [5]
GSRN
DONE
DONE [5]
FPGA_CCLK
INITN
INITN [5]
PROGRAMN
PROGRAMN [5]
CFG0
CFG1
CFG[0..2] [5]
CFG2
FPGA_D15
FPGA_D14
FPGA_D[8..15] [5]
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
TMS_BUF
TDI_XO
TDI_XO [5]
TCK_BUF
TDI_BUF
FPGA_XRES
R46
10K-0603SMT
K21
K20
C26
B25
J22
J21
D26
D25
D23
C25
E24
D24
C24
H22
G22
C23
B24
A24
H21
J20
B23
A23
E21
F22
F23
E22
E23
G21
G20
D21
D22
E6
E7
E5
F5
R18
U10
V8
H19
H20
H7
FPGA_CCLK
CONFIG
CFG Switches
0(ON)
CFG2
3_3V
ECP3-672fpBGA
13
R45
10K-0603SMT
R43
4_7K-0603SMT
U1G
FPGA_CCLK
FPGA_MCLK
PR16B/BUSY/SISPI/AVDN
PR16A/D7/SPID0
PR14B/D6/SPID1
PR14A/D5
PR13B/D4/SO
PR13A/D3/SI
PR11B/D2
PR11A/D1
PR10B/D0/SPIFASTN
PR8B/MCLK
PR10A/WRITEN/OEN
PR8A/DOUT/CSON/CSSPI1N
PR5B/DI/CSSPI0N/CEN
PR7B/CSN/SN/CONT1N
PR7A/CS1N/HOLD/CONT2N
PR5A
DONE
CCLK
INITN
PROGRAMN
CFG0
CFG1
CFG2
PT145B
PT145A
PT143B
PT143A
PT142B
PT142A
PT140B
PT140A
TMS
TDO
TCK
TDI
XRES
TEMPSENSE
TEMPVSS
VCCIO8
VCCIO8
VCCJ
1
2
J2
HEADER 2X2
3
4
12
9
10
SN74LVC125A/SO14
4A
4OE_N
3A
3OE_N
U9B
FPGA_XRES
FPGA_CCLK
[5] LOADER_CK
[5] SPI_CLK
LOADER_CK
SPI_CLK
3_3V
FPGA_CS1N
R25
D6
680R-0603SMT
R
100NF-0603SMT
R38
10K-0603SMT
Y
GSRN
3_3V
R37
10K-0603SMT
3_3V
R41
OPEN-0603SMT
R36
10K-0603SMT
R42
OPEN-0603SMT
3
3_3V
3_3V
U8
IN A2
IN A1
2
IN A2
2
U10
IN A1
3
1
3
1
1
2
HEADER 2
J3
C90
100NF-0603SMT
4
[5] TDO_XO
SPIFASTN
R30
FPGA_D0
3
EXBV8V472JV
Date:
Size
C
5
1
1
5
+3.3V
TDO
TDI
TMS
GND
TCK
Primary
Component
HEADER 6 Side
J4
Secondary
Component
Side
100NF-0603SMT
C91
3_3V
Thursday, August 09, 2012
1
Sheet
4
ECP3 PCIe DevKit Eval Board
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
FROM ISPVM CABLE
Progamming
Project
J8
1
HEADER 6
6
2
3
4
6
4.7K
LOCAL_TCK
4.7K
4
2
3
4
Title
4.7K
RN1D
LOCAL_TDI
LOCAL_TMS
4.7K
3_3V
10K-0603SMT
2
680R-0603SMT
R23
4_7K-0603SMT
5
VCC
RN1B
INITN indicator will light
if an error occurs during
configuration programming
R50
GND
2
R51
100R-0603SMT
5
FPGA_CSN
R
RN1C
3_3V
100R-0603SMT
6
5
4
1
2
3
4_7K-0603SMT
R40
GND
7
14
VCC
C92
VCC
GND
2
5
VCC
GND
2
FPGA_D[8..15]
100NF-0603SMT
1
RN1A
25
8
INITN
7
DONE
6
PROGRAMN
5
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 23. Programming
A
B
C
5
4
2
Momentary Switch
B3F-1150
3
1
SW4
CPLD RESET
3_3V
R53
0R-0603SMT
3_3V
[4] FPGA_D[8..15]
[8] FPGA_[0:15]
3_3V
[4] SPI_CLK
[4] FPGA_CCLK
[4] CFG[0..2]
R55
2_2K-0603SMT
[4] LOADER_CK
[4] PROGRAMN
[4] FPGA_D[0..7]
R52
OPEN-0603SMT
C101
100NF-0603SMT
FPGA_D[8..15]
[4] TCK_BUF
[4] TDI_XO
[4] TDO_XO
[4] TMS_BUF
[4] GSRN
[4] DONE
4
N14
GSRN
CFG0
CFG1
CFG2
FPGA_0
FPGA_1
FPGA_2
FPGA_3
FPGA_4
FPGA_5
FPGA_6
FPGA_7
FPGA_8
FPGA_9
FPGA_10
FPGA_11
FPGA_12
FPGA_13
FPGA_14
FPGA_15
TMS_BUF
R57
1K-0603SMT
TCK_BUF
TDI_XO
A4
M7
M1
P13
P10
N7
N8
P11
N13
N1
N3
N4
P1
M12
M2
M3
M4
M6
H12
H13
M13
N6
M14
B1
L3
A3
A2
M9
P4
M5
N5
P3
N12
K12
A1
INITN
DONE
J2
G1
A5
P8
M8
J3
K1
E3
B7
P5
H2
FPGA_D0
FPGA_D1
FPGA_D2
FPGA_D3
FPGA_D4
FPGA_D5
FPGA_D6
FPGA_D7
LOADER_CK
PROGRAMN
[4] INITN
C6
C2
K14
P12
L14
M11
G2
E2
FPGA_D15
FPGA_D14
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
4
U12
G12
VCC
H3
VCC
NC
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
SPI_CLK
FPGA_CLK
CFG0
CFG1
CFG2
TCK
TDI
TDO
TMS
SLEEPN
FUNC_RESET
FPGA_RESETN
FPGA_DONE
FPGA_INITN
TSALL
FPGA_DATA_0
FPGA_DATA_1
FPGA_DATA_2
FPGA_DATA_3
FPGA_DATA_4
FPGA_DATA_5
FPGA_DATA_6
FPGA_DATA_7
FPGA_CCLK
FPGA_PROGRAMN
FPGA_D15
FPGA_D14
FPGA_D13
FPGA_D12
FPGA_D11
FPGA_D10
FPGA_D9
FPGA_D8
C7
VCC
C93
A7
VCCAUX
P6
VCC
C94
10NF-0603SMT
C95
100NF-0603SMT
Lattice
FPGA
Loader
LCMXO1200C-CSBGA132
C96
3
C97
100NF-0603SMT
FLASH_DQ_15
FLASH_DQ_14
FLASH_DQ_13
FLASH_DQ_12
FLASH_DQ_11
FLASH_DQ_10
FLASH_DQ_9
FLASH_DQ_8
FLASH_DQ_7
FLASH_DQ_6
FLASH_DQ_5
FLASH_DQ_4
FLASH_DQ_3
FLASH_DQ_2
FLASH_DQ_1
FLASH_DQ_0
CLOCK
FLASH_WE_N
FLASH_WP_N_ACC
FLASH_RESET_N
FLASH_OE_N
FLASH_CEm
FLASH_RD/BY
FLASH_BYTEn
FLASH_CE1_N
FLASH_CE0_N
FLASH_ADDRESS_0
FLASH_ADDRESS_1
FLASH_ADDRESS_2
FLASH_ADDRESS_3
FLASH_ADDRESS_4
FLASH_ADDRESS_5
FLASH_ADDRESS_6
FLASH_ADDRESS_7
FLASH_ADDRESS_8
FLASH_ADDRESS_9
FLASH_ADDRESS_10
FLASH_ADDRESS_11
FLASH_ADDRESS_12
FLASH_ADDRESS_13
FLASH_ADDRESS_14
FLASH_ADDRESS_15
FLASH_ADDRESS_16
FLASH_ADDRESS_17
FLASH_ADDRESS_18
FLASH_ADDRESS_19
FLASH_ADDRESS_20
FLASH_ADDRESS_21
FPGA_CSN
FPGA_CS1N
FPGA_WRITEN
10NF-0603SMT
K3
100NF-0603SMT
N2
3
D2
VCCIO7
3_3V
P7
VCCAUX
GND
D13
FPGA_D[0..7]
C5
VCCIO0
GND
E1
GND
B4
B11
VCCIO1
GND
F1
GND
A10
E12
VCCIO2
GND
J14
GND
C9
L12
VCCIO3
GND
L2
VCCIO5
GND
M10
VCCIO4
GND
L13
VCCIO6
GND
P2
GND
P9
26
N11
D
5
C98
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_CLK
FLASH_WE_N
FLASH_WP_N_ACC
FLASH_RESET_N
FLASH_OE_N
FLASH_CEm
FLASH_RD/BY
FLASH_BYTEn
E14
D12
J12
G14
J13
F14
F13
E13
D3
C4
J1
H1
N9
K13
G13
G3
A8
K2
L1
P14
C1
B2
D1
F2
F3
C3
FLASH_CLK
[9]
FLASH_A[0..21]
FPGA_CSN [4]
FPGA_CS1N [4]
FPGA_WRITEN [4]
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
B6
A6
B3
B5
A9
B9
C10
B10
C11
A11
D14
C8
A14
B8
C14
B12
C13
A13
B13
A12
C12
B14
F12
H14
N10
10NF-0603SMT
2
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
2
H6
H1
C4
D3
D4
C3
B2
E6
D6
C6
A6
B6
D5
C5
A5
B5
A2
C2
D2
B1
A1
C1
D1
E1
U11
VCC
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CEn
OEn
WEn
RD/BY
BYTEn
WPn
RESETn
FLASH_D[0..15]
S29GL064A
GND
GND
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
G4
G6
F5
G5
F4
G3
F3
G2
F2
E5
H5
E4
H4
H3
E3
H2
E2
F1
G1
A4
A3
F6
B3
B4
Date:
Size
C
Title
3_3V
C99
C100
Monday, February 23, 2009
1
Sheet
5
ECP3 PCIe DevKit Eval Board
Project
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
R54
10K-0603SMT
3_3V
FLASH_D[0..15]
10NF-0603SMT
Parallel FPGA Loader
FLASH_D15
FLASH_D14
FLASH_D13
FLASH_D12
FLASH_D11
FLASH_D10
FLASH_D9
FLASH_D8
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_CEm
FLASH_OE_N
FLASH_WE_N
FLASH_RD/BY
FLASH_BYTEn
FLASH_WP_N_ACC
FLASH_RESET_N
100NF-0603SMT
1
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 24. Parallel FPGA Loader
R56
1K-0603SMT
27
A
B
C
[8] PCIE_PERSTN
PCSA_HDOUTP0
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
CN2
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C127
x1_PETp0
x1_PETn0
PCIE_3V3
x1_PERn0
x1_PERp0
X1 PCIe Board Fingers
PCI Express x1 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
C126
100NFX5R-0402SMT
100NFX5R-0402SMT
1
5
AD21
AD20
AD18
AD19
AD17
AD16
AD14
AD15
AF21
AF20
AF18
AF19
AF17
AF16
AF14
AF15
AC17
AC18
AB18
AA16
AA15
AB14
AA17
AB17
AB16
AB15
AD13
AD12
AD10
AD11
AD9
AD8
AD6
AD7
AF13
AF12
AF10
AF11
AF9
AF8
AF6
AF7
AC9
AC10
AB13
AB11
AA11
AB9
AB12
AA12
AB10
AA10
TP14
TESTPOINT
PCSB_VCCOB
PCSB_VCCIB
x1_PRSNTn
x4_PETp0
x4_PETn0
x4_PETp1
x4_PETn1
x4_PETp2
x4_PETn2
x4_PETp3
x4_PETn3
PCSB_HDOUTP0
PCSB_HDOUTN0
PCSB_HDOUTP1
PCSB_HDOUTN1
PCSB_HDOUTP2
PCSB_HDOUTN2
PCSB_HDOUTP3
PCSB_HDOUTN3
x4_PCIE_CLKP
x4_PCIE_CLKN
PCSA_VCCOB
PCSA_VCCIB
x1_PETp0
x1_PETn0
LOOP1_P
LOOP1_N
LOOP2_P
LOOP2_N
LOOP3_P
LOOP3_N
PCSA_HDOUTP0
PCSA_HDOUTN0
LOOP1_P
LOOP1_N
LOOP2_P
LOOP2_N
LOOP3_P
LOOP3_N
x1_PCIE_CLKP
x1_PCIE_CLKN
[8]
PRSNT1#
+12V
+12V
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V
+3.3V
PERST#
GND
REFCLK+
REFCLKGND
PERp0
PERn0
GND
RSVD_A19
GND
PERp1
PERn1
GND
GND
PERp2
PERn2
GND
GND
PERp3
PERn3
GND
RSVD_A32
CN1
4
C113
C119
PCSB_VCCIB
C120
C121
+12V
+12V
RSVD_B3
GND
SMCLK
SMDAT
GND
+3.3V
JTAG1
3.3Vaux
WAKE#
RSVD_B12
GND
PETp0
PETn0
GND
PRSNT3#
GND
PETp1
PETn1
GND
GND
PETp2
PETn2
GND
GND
PETp3
PETn3
GND
RSVD_B30
PRSNT4#
GND
x4_PETp3
x4_PETn3
x4_PETp2
x4_PETn2
x4_PETp1
x4_PETn1
x4_PETp0
x4_PETn0
PCIE_3V3
X4 PCIe Board Fingers
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
1
TP13
TESTPOINT
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C118
PCI Express x4 Edge Finger Conn.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
C112
C107
PCSA_VCCOB
C103
x4_PRSNTn
3
2
100NF-0603SMT
C124
PCSB_HDOUTN3
PCSB_HDOUTP3
PCSB_HDOUTN2
PCSB_HDOUTP2
PCSB_HDOUTN1
PCSB_HDOUTP1
PCSB_HDOUTN0
PCSB_HDOUTP0
10NF-0603SMT
C123
100NF-0603SMT
C116
C109
PCSB_VCCOB
C105
PCSB_VCCIB
10NF-0603SMT
C115
+ C108
+ C104
[8]
100NF-0603SMT
C122
PCSB_VCCOB
100NF-0603SMT
C114
PCSA_VCCOB
FB5
BLM41PG600SN1
1_2V_A
FB3
BLM41PG600SN1
1_2V_A
2
B side = Secondary Component Side(BOTTOM)
A side = PRIMARY Component Side(TOP)
x4_PERp3
x4_PERn3
x4_PERp2
x4_PERn2
x4_PERp1
x4_PERn1
x4_PERp0
x4_PERn0
x4_PCIE_CLKP
x4_PCIE_CLKN
PCIE_PERSTN
PCIE_3V3
12_0V
C111
PCSA_VCCIB
+ C106
+ C102
PCSA_VCCIB
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C110
FB4
BLM41PG600SN1
1_2V_A
FB2
BLM41PG600SN1
1_2V_A
All Nets are 85-ohm differential pairs.
The P and N traces shall be <20mil matched in length
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
x1_PERp0
x1_PERn0
x1_PCIE_CLKP
x1_PCIE_CLKN
PCIE_PERSTN
PCIE_3V3
12_0V
PCSA_HDOUTN0
PCSA_HDINP0
PCSA_HDINN0
PCSA_HDINP1
PCSA_HDINN1
PCSA_HDINP2
PCSA_HDINN2
PCSA_HDINP3
PCSA_HDINN3
PCSA_HDOUTP0
PCSA_HDOUTN0
PCSA_HDOUTP1
PCSA_HDOUTN1
PCSA_HDOUTP2
PCSA_HDOUTN2
PCSA_HDOUTP3
PCSA_HDOUTN3
PCSA_REFCLKP
PCSA_REFCLKN
PCSA_VCCIB0
PCSA_VCCIB1
PCSA_VCCIB2
PCSA_VCCIB3
PCSA_VCCOB0
PCSA_VCCOB1
PCSA_VCCOB2
PCSA_VCCOB3
PCSB_HDINP0
PCSB_HDINN0
PCSB_HDINP1
PCSB_HDINN1
PCSB_HDINP2
PCSB_HDINN2
PCSB_HDINP3
PCSB_HDINN3
PCSB_HDOUTP0
PCSB_HDOUTN0
PCSB_HDOUTP1
PCSB_HDOUTN1
PCSB_HDOUTP2
PCSB_HDOUTN2
PCSB_HDOUTP3
PCSB_HDOUTN3
PCSB_REFCLKP
PCSB_REFCLKN
PCSB_VCCIB0
PCSB_VCCIB1
PCSB_VCCIB2
PCSB_VCCIB3
PCSB_VCCOB0
PCSB_VCCOB1
PCSB_VCCOB2
PCSB_VCCOB3
All Nets are 85-ohm differential pairs.
The P and N traces shall be <20mil matched in length
ECP3-672fpBGA
U1H
3
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
4
1UF-16V-0805SMT
1UF-16V-0805SMT
1UF-16V-0805SMT
1UF-16V-0805SMT
22UF-16V_TANTBSMT
22UF-16V_TANTBSMT
D
5
Date:
Size
C
Title
C132
C134
OPEN-0603SMT
C135
C133
C131
C129
OPEN-0603SMT
Monday, February 23, 2009
1
Sheet
6
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
x4_PCIE_CLKN
x1_PCIE_CLKN
x4_PERn3
x4_PERp3
x4_PERn2
x4_PERp2
x4_PERn1
x4_PERp1
x4_PERn0
x4_PERp0
ECP3 PCIe DevKit Eval Board
Project
SERDES
R59
Place near U1
R58
100NFX5R-0402SMT
100NFX5R-0402SMT
x4_PCIE_CLKP
C130
100NFX5R-0402SMT
100NFX5R-0402SMT
x1_PCIE_CLKP
C128
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
100NFX5R-0402SMT
10NF-0603SMT
C125
10NF-0603SMT
C117
1
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 25. SERDES
A
B
R64
0R-0603SMT
R61
1K-0603SMT
R66
1K-0603SMT
5
3_3V
R60
4_7K-0603SMT
1_8V
+ C166
DDR2_VDDQ
BLM41PG600SN1
FB8
DDR2_VREF
C157
R62
1K_ADJ/SMT3MM
C155
10NF-0603SMT
R63
OPEN-0603SMT
10NF-0603SMT
1_8V
100NF-0603SMT
C
C170
C176
10NF-0603SMT
10NF-0603SMT
C171
C177
100NF-0603SMT
100NF-0603SMT
100NF-0603SMT
+ C152
C167
+ C153
VDDL
C154
8
3
+
LP2998-SO8
VTT
VSENSE
C138
PP2
C144
FB6
BLM41PG600SN1
1_8V
VDDQ
VREF
SD
FB7
BLM41PG600SN1
DDR2_VDDQ
1_8V
5
4
U13
C137
2
6
7
AVIN
PVIN
D
22UF-16V-TANTBSMT
4
4
C139
C141
100NF-0603SMT
1UF-16V-0805SMT
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VREF
VDDL
VSSDL
U14B
C142 +
10UF-16V-TANTBSMT
DDR2_VDD
DDR2-SDRAM-84FBGA
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J2
J1
J7
DDR2_VDD
C140 +
DDR2_VDDQ
PP1
DDR2_VTT
1
2
1UF-16V-0805SMT
C168
22UF-16V-TANTBSMT
1UF-16V-0805SMT
C136
C172
C178
C173
C179
10NF-0603SMT
10NF-0603SMT
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
LDQS
LDQS#/NU
UDQS
UDQS#/NU
LDM
UDM
CK
CK#
CKE
WE#
RAS#
CAS#
ODT
CS#
BA0
BA1
NC_A2
NC_E2
NC_R8
RFU_L1
RFU_R3
RFU_R7
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
F7
E8
B7
A8
F3
B3
J8
K8
K2
K3
K7
L7
K9
L8
L2
L3
A2
E2
R8
L1
R3
R7
DDR2_DQ15
DDR2_DQ14
DDR2_DQ13
DDR2_DQ12
DDR2_DQ11
DDR2_DQ10
DDR2_DQ9
DDR2_DQ8
DDR2_DQ7
DDR2_DQ6
DDR2_DQ5
DDR2_DQ4
DDR2_DQ3
DDR2_DQ2
DDR2_DQ1
DDR2_DQ0
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_DQS0
DDR2_DQS0#
DDR2_DQS1
DDR2_DQS1#
DDR2_DM0
DDR2_DM1
DDR2_K
DDR2_K#
DDR2_CE0#
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_ODT0
DDR2_CS0#
DDR2_BA0
DDR2_BA1
DDR2_44
DDR2_43
DDR2_42
DDR2_41
DDR2_40
DDR2_39
DDR2_38
DDR2_37
DDR2_36
DDR2_35
DDR2_34
DDR2_33
DDR2_32
DDR2_31
DDR2_30
DDR2_29
DDR2_28
DDR2_27
DDR2_26
DDR2_25
DDR2_24
DDR2_23
DDR2_22
DDR2_21
DDR2_20
DDR2_19
DDR2_18
DDR2_17
DDR2_16
DDR2_15
DDR2_14
DDR2_13
DDR2_12
DDR2_11
DDR2_10
DDR2_9
DDR2_8
DDR2_7
DDR2_6
DDR2_5
DDR2_4
DDR2_3
DDR2_2
DDR2_1
DDR2_0
DDR2_K#
R223
50R-0402SMT
DDR2_[0:44]
[8]
3
DDR2_VTT
R224
50R-0402SMT
DDR2_VTT
C220
10NF-0402SMT
PLACE CLOSE TO U14
DDR2_K
ALL Memory controller
buses, clocks, and control
traces must be 50 Ohm
Transmission lines
DDR2-SDRAM-84FBGA
U14A
3
VTT
C143
GND
1
22UF-16V-TANTBSMT
100NF-0603SMT
1
2
DDR2_CS0#
DDR2_ODT0
DDR2_CE0#
2
A3
B3
C3
D3
E3
F3
G3
H3
J3
2
C151
A3
B3
C3
D3
E3
F3
G3
H3
J3
100NF-0603SMT
H2
J2
CTS-RT2402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
R1=50 Ohm
SP2
R1
R1
A1
B1
C1
D1
E1
F1
G1
H1
J1
RP1
A1
B1
C1
D1
E1
F1
G1
H1
J1
C146
R1=50 Ohm
R1
R1
A1
B1
C1
D1
E1
F1
G1
H1
J1
Date:
Size
C
Title
RP2
A1
B1
C1
D1
E1
F1
G1
H1
J1
C147
1
C148
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
C165
C162
Thursday, March 26, 2009
1
Sheet
7
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
ECP3 PCIe DevKit Eval Board
Project
DDR2 Memory
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_BA1
DDR2_BA0
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C160
C161
100NF-0603SMT
100NF-0603SMT
10NF-0603SMT
10NF-0603SMT
C145
SP4
SP3
MEMORY DEVICE
Pin
U1 Pin
X1
Termination
at end of line
X1
needs to be matched length
for all traces
X2
CTS-R2402B7
A3
B3
C3
D3
E3
F3
G3
H3
J3
SP1
1
3_3V
C169
100NF-0603SMT
C150
10NF-0603SMT
C159
47UF-10V-TANTBSMT
10NF-0603SMT
10NF-0603SMT
100NF-0603SMT
1
F2
F2
F2
F2
1UF-16V-0805SMT
100NF-0603SMT
100NF-0603SMT
C174
C180
C163
G2
G2
G2
G2
C149
10NF-0603SMT
C158
E2
E2
E2
E2
1UF-16V-0805SMT
10NF-0603SMT
10NF-0603SMT
C175
C181
D2
D2
10NF-0603SMT
100NF-0603SMT
C164
D2
D2
1
A2
A2
100UF-FKSMT
100NF-0603SMT
100NF-0603SMT
C2
J2
J2
J2
C2
C2
1
A2
H2
H2
H2
B2
B2
B2
B2
28
A2
DDR2_A[0:12]
C2
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 26. DDR2 Memory
C156
A
B
C
5
PT74A
PT74B
PT76A
PT76B
PT77A
PT77B
PT79A
PT79B
PT80A
PT80B
PT82A
PT82B
PT83A
PT83B
PT85A
PT85B
PT86A
PT86B
PT88A
PT88B
PT89A
PT89B
PT91A
PT91B
PT101A
PT101B
PT103A
PT103B
PT104A
PT104B
PT106A
PT106B
PT107A
PT107B
PT109A
PT109B
PT128A
PT128B
PT130A
PT130B
PT131A
PT131B
PT133A
PT133B
PT134A
PT134B
PT136A/VREF1_1
PT136B/VREF2_1
VCCIO1
VCCIO1
VCCIO1
VCCIO1
ECP3-672fpBGA
U1B
ECP3-672fpBGA
C15
B15
C14
D14
B16
C16
F13
F14
A17
A18
B17
C17
A19
A20
E14
E15
A21
B20
G14
F15
C20
B19
D15
E16
E17
F18
G16
F16
C19
D19
H16
H17
C18
D18
F17
G17
E19
E20
E18
D17
B21
A22
F19
F20
C22
C21
G18
G19
H14
H15
J14
J17
TP_0
TP_1
TP_2
TP_3
TP_4
TP_5
TP_6
TP_7
TP_8
TP_9
TP_10
TP_11
TP_12
TP_13
TP_14
TP_15
GSRN
3_3V
3_3V
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SWITCH8
SWITCH7
SWITCH6
SWITCH5
SWITCH4
SWITCH3
SWITCH2
SWITCH1
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
[9]
TP_[0:15]
[6]
LED[0:15]
[9]
[9]
SWITCH[1:8]
SEG[0:16]
[9]
ECP3-672fpBGA
J23
H23
G26
F26
F24
G24
H26
H25
K23
K22
F25
E26
L21
L22
H24
G25
L20
M21
K24
J24
M23
M24
L24
K25
M22
N21
J26
K26
N23
N22
K19
L19
P23
R22
L25
L26
P21
P22
M25
M26
T21
R21
K18
M19
N18
N19
N20
4
R69
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LA30
LA31
LA32
LA33
LA34
3_3V
R70
3_3V
3_3V
OSC_IN_3
R75
0R-0603SMT
N24
N25
U20
U19
P24
R24
R23
T22
N26
P26
T20
U21
R25
R26
U24
V24
T25
T24
V21
V22
T26
U26
U23
U22
U25
V26
V20
W19
W26
W25
Y26
Y25
V23
W24
V17
W18
AA25
Y24
W23
W22
AA26
AB26
W21
W20
AD26
AD25
AA24
AA23
AC26
AC25
Y19
Y20
AB24
AC24
Y22
AA22
AE25
AF24
AD24
AE24
AD23
AC23
AB20
AB21
AF23
AE23
W17
AB23
AB22
Y21
AA20
P18
P19
R19
U18
P20
R67
0R-0603SMT
PR44A
PR44B
PR46A/PCLKT3_0
PR46B/PCLKC3_0
PR47A
PR47B
PR49A
PR49B
PR50A
PR50B
PR52A/VREF1_3
PR52B/VREF2_3
PR53A
PR53B
PR55A
PR55B
PR56A
PR56B
PR58A
PR58B
PR59A
PR59B
PR61A
PR61B
PR61E_A/RLM1_GPLLT_FB_A
PR61E_B/RLM1_GPLLT_FB_B
PR61E_C/RLM1_GPLLT_IN_A
PR61E_D/RLM1_GPLLT_IN_B
PR70E_A/RLM2_GPLLT_FB_A
PR70E_B/RLM2_GPLLT_FB_B
PR70E_C/RLM2_GPLLT_IN_A
PR70E_D/RLM2_GPLLT_IN_B
PR79E_A/RLM3_GPLLT_FB_A
PR79E_B/RLM3_GPLLT_FB_B
PR79E_C/RLM3_GPLLT_IN_A
PR79E_D/RLM3_GPLLT_IN_B
PR80A
PR80B
PR82A
PR82B
PR83A
PR83B
PR85A
PR85B
PR86A
PR86B
PR88A
PR88B
PR89A
PR89B
PR91A
PR91B
PR92A
PR92B
PR94A
PR94B
PR95A
PR95B
PR97A
PR97B
PB137A
PB137B
PB139A
PB139B
PB140A
PB140B
PB142A
PB143A
PB143B
PB145A
PB145B
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VTT3
U1D
ECP3-672fpBGA
PR19A
PR19B
PR20A
PR20B
PR22A
PR22B
PR23A
PR23B
PR25A
PR25B
PR25E_A
PR25E_B
PR25E_C
PR25E_D
PR26A
PR26B
PR28A
PR28B
PR29A
PR29B
PR31A
PR31B
PR32A
PR32B
PR34A/VREF1_2
PR34B/VREF2_2
PR35A
PR35B
PR37A/RUM0_GDLLT_IN_A
PR37B/RUM0_GDLLT_IN_B
PR38A/RUM0_GDLLT_FB_A
PR38B/RUM0_GDLLT_FB_B
PR40A
PR40B
PR41A
PR41B
PR43A/PCLKT2_0
PR43B/PCLKC2_0
PR43E_A/RUM2_GPLLT_FB_A
PR43E_B/RUM2_GPLLT_FB_B
PR43E_C/RUM2_GPLL_IN_A
PR43E_D/RUM2_GPLLT_IN_B
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VTT2
4_7K-0603SMT
U1C
R71
4_7K-0603SMT
U1E
LA[1:34]
[9]
[9]
[9]
3_3V
R227
1_6R-0603SMT
C223
+
VTT6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
PL44A/LDQ49
PL44B/LDQ49
PL46A/PCLKT6_0/LDQ49
PL46B/PCLKC6_0/LDQ49
PL47A/LDQ49
PL47B/LDQ49
PL49A/LDQS49
PL49B/LDQS49#
PL50A/LDQ49
PL50B/LDQ49
PL52A/VREF1_6/LDQ49
PL52B/VREF_2_6/LDQ49
PL53A/LDQ58
PL53B/LDQ58
PL55A/LDQ58
PL55B/LDQ58
PL56A/LDQ58
PL56B/LDQ58
PL58A/LDQS58
PL58B/LDQS58#
PL59A/LDQ58
PL59B/LDQ58
PL61A/LDQ58
PL61B/LDQ58
PL61E_A/LLM1_GPLLT_FB_A
PL61E_B/LLM1_GPLLT_FB_B
PL61E_C/LLM1_GPLLT_IN_A
PL61E_D/LLM1_GPLLT_IN_B
PL62A/LDQ67
PL62B/LDQ67
PL64A/LDQ67
PL64B/LDQ67
PL65A/LDQ67
PL65B/LDQ67
PL70E_A/LLM2_GPLLT_FB_A
PL70E_B/LLM2_GPLLT_FB_B
PL70E_C/LLM2_GPLLT_IN_A
PL70E_D/LLM2_GPLLT_IN_B
PL79E_A/LLM3_GPLLT_FB_A
PL79E_B/LLM3_GPLLT_FB_B
PL79E_C/LLM3_GPLLT_IN_A
PL79E_D/LLM3_GPLLT_IN_A
PL80A/LDQ85
PL80B/LDQ85
PL82A/LDS85
PL82B/LDQ85
PL83A/LDQ85
PL83B/LDQ85
PL85A/LDQS85
PL85B/LDQS85#
PL86A/LDQ85
PL86B/LDQ85
PL88A/LDQ85
PL88B/LDQ85
PL89A/LDQ94
PL89B/LDQ94
PL91A/LDQ94
PL91B/LDQ94
PL92A/LDQ94
PL92B/LDQ94
PL94A/LDQS94
PL94B/LDQS94#
PL95A/LDQ94
PL95B/LDQ94
PL97A/LDQ94
PL97B/LDQ94
PB2A
PB2B
PB4A
PB4B
PB5A
PB5B
PB8A
PB8B
PB10A
PB11A
PB11B
PB13A
PB13B
ECP3-672fpBGA
x1_PRSNTn [6]
x4_PRSNTn [6]
PCIE_PERSTN [6]
FPGA_SMA_REFCLKP
FPGA_SMA_REFCLKN
4_7K-0603SMT
D
B6
C7
D5
C4
D6
C6
C5
B4
D8
C8
G7
H8
A3
A4
F7
F8
B7
A7
E8
E9
A5
A6
G8
F9
D9
D10
F10
E10
A8
B8
G10
G9
C9
C10
H10
H11
A9
B10
F11
G11
A10
A11
D12
C11
B11
B12
E11
E12
A12
B13
C12
C13
A13
A14
F12
G13
A15
A16
E13
D13
H12
H13
J10
J13
C222
PT2A
PT2B
PT4A
PT4B
PT5A
PT5B
PT7A
PT7B
PT8A
PT8B
PT10A
PT10B
PT11A
PT11B
PT13A
PT13B
PT14A
PT14B
PT16A
PT16B
PT17A
PT17B
PT19A
PT19B
PT38A
PT38B
PT40A
PT40B
PT41A
PT41B
PT43A
PT43B
PT44A
PT44B
PT46A
PT46B
PT56A
PT56B
PT58A
PT58B
PT59A
PT59B
PT61A
PT61B
PT62A
PT62B
PT64A
PT64B
PT65A
PT65B
PT67A
PT67B
PT68A
PT68B
PT70A
PT70B
PT71A
PT71B
PT73A
PT73B
VCCIO0
VCCIO0
VCCIO0
VCCIO0
100NF-0603SMT
U1A
3
P7
P8
P9
R8
U9
P1
P2
N5
N6
R1
R2
N3
P3
T2
U3
P5
P6
P4
R3
R5
R6
T1
U1
T3
R4
V1
U2
T7
T8
W1
W2
U4
V5
Y3
W3
T5
T6
V3
V4
W4
W5
U6
U5
Y1
Y2
U7
U8
AA1
AA2
V6
V7
AB1
AC1
W7
W6
AC2
AC3
Y5
AA5
AA3
AA4
AB5
AB6
AB3
AB4
Y6
Y7
AD1
AD2
W8
W9
AD4
AE3
AA7
AB7
AD3
AC4
AE2
AF3
Y8
AE4
AF4
V10
W10
C224
2
1
NC
DDR2_VTT
Q
Q_N
R72
1_8V
DDR2_DQ15
DDR2_DQ14
DDR2_DQ13
DDR2_DQ12
DDR2_DQ11
DDR2_DQ10
DDR2_DQ9
DDR2_DQ8
DDR2_DQ7
DDR2_DQ6
DDR2_DQ5
DDR2_DQ4
DDR2_DQ3
DDR2_DQ2
DDR2_DQ1
DDR2_DQ0
DDR2_A0
DDR2_A1
DDR2_A2
DDR2_A3
DDR2_A4
DDR2_A5
DDR2_A6
DDR2_A7
DDR2_A8
DDR2_A9
DDR2_A10
DDR2_A11
DDR2_A12
DDR2_DQS0
DDR2_DQS0#
DDR2_DQS1
DDR2_DQS1#
DDR2_DM0
DDR2_DM1
DDR2_K
DDR2_K#
DDR2_CE0#
DDR2_WE#
DDR2_RAS#
DDR2_CAS#
DDR2_ODT0
DDR2_CS0#
DDR2_BA0
DDR2_BA1
1K_ADJ/SMT3MM
DDR2_OSC_CLKN
5
R228
50R-0402SMT
DDR2_OSC_CLKP
4
Y2
CRYSTEK-133MHZ
DDR2_VTT
DIS#
1_8V
DDR2_DQ6
DDR2_DQ4
DDR2_DQ7
DDR2_DQ3
DDR2_DQ5
DDR2_DQ2
DDR2_DQS0
DDR2_DQS0#
DDR2_DQ0
DDR2_DQ1
DDR2_DM0
DDR2_DQ11
DDR2_DQ10
DDR2_DQ8
DDR2_DQ9
DDR2_DQ12
DDR2_DQ13
DDR2_DQS1
DDR2_DQS1#
DDR2_DQ15
DDR2_DQ14
DDR2_DM1
DDR2_OSC_CLKP
DDR2_OSC_CLKN
DDR2_K
DDR2_K#
DDR2_CS0#
DDR2_A10
DDR2_WE#
DDR2_CAS#
DDR2_A11
DDR2_A12
DDR2_A0
DDR2_A1
VREF1_6
DDR2_ODT0
DDR2_A5
DDR2_A4
DDR2_BA0
DDR2_BA1
DDR2_CE0#
DDR2_RAS#
DDR2_A8
DDR2_A9
DDR2_A6
DDR2_A7
DDR2_A3
DDR2_A2
R222
50R-0603SMT
3
10UF-16V-TANTBSMT
R68
1K-0603SMT
R74
1K-0603SMT
4
6
VCC
GND
29
3
2
DDR2_[0:44]
2
C225
10NF-0402SMT
PLACE CLOSE TO U1
50R-0402SMT
R229
VREF1_6
DDR2_44
DDR2_43
DDR2_42
DDR2_41
DDR2_40
DDR2_39
DDR2_38
DDR2_37
DDR2_36
DDR2_35
DDR2_34
DDR2_33
DDR2_32
DDR2_31
DDR2_30
DDR2_29
DDR2_28
DDR2_27
DDR2_26
DDR2_25
DDR2_24
DDR2_23
DDR2_22
DDR2_21
DDR2_20
DDR2_19
DDR2_18
DDR2_17
DDR2_16
DDR2_15
DDR2_14
DDR2_13
DDR2_12
DDR2_11
DDR2_10
DDR2_9
DDR2_8
DDR2_7
DDR2_6
DDR2_5
DDR2_4
DDR2_3
DDR2_2
DDR2_1
DDR2_0
C182
10NF-0603SMT
5
[7]
Date:
Size
C
Title
ECP3-672fpBGA
B2
B3
D4
E4
C3
D3
G5
G6
E3
F4
H6
J6
C2
D2
K8
J7
F2
F3
K7
K6
G2
G3
H5
J5
H4
H3
L8
L7
K2
K1
J4
J3
D1
C1
K4
K5
E1
F1
L5
L6
H2
G1
K3
L3
H1
J1
M5
M6
L2
L1
M4
N4
M1
N1
M3
M2
K9
M8
N8
N9
N7
Monday, April 06, 2009
[5]
OSC_IN_[1:3]
FPGA_[0:15]
[9]
1
Sheet
8
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
R73
0R-0603SMT
3_3V
OSC_IN_1
OSC_IN_2
OSC_IN_3
FPGA_0
FPGA_1
FPGA_2
FPGA_3
FPGA_4
FPGA_5
FPGA_6
FPGA_7
FPGA_8
FPGA_9
FPGA_10
FPGA_11
FPGA_12
FPGA_13
FPGA_14
FPGA_15
ECP3 PCIe DevKit Eval Board
Project
FPGA
PL8A
PL8B
PL10A
PL10B
PL11A
PL11B
PL13A
PL13B
PL14A
PL14B
PL16A
PL16B
PL17A
PL17B
PL19A
PL19B
PL20A
PL20B
PL22A
PL22B
PL23A
PL23B
PL25A
PL25B
PL25E_A/LUM2_GPLLT_FB_A
PL25E_B/LUM2_GPLLT_FB_B
PL25E_C/LUM2_GPLLT_IN_A
PL25E_D/LUM2_GPLLT_IN_B
PL26A
PL26B
PL28A
PL28B
PL29A
PL29B
PL31A
PL31B
PL32A
PL32B
PL34A/VREF1_7
PL34B/VREF2_7
PL35A
PL35B
PL37A/LUM0_GDLLT_IN_A
PL37B/LUM0_GDLLT_IN_B
PL38A/LUM0_GDLLT_FB_A
PL38B/LUM0_GDLLT_FB_B
PL40A
PL40B
PL41A
PL41B
PL43A/PCLKT7_0
PL43B/PCLKC7_0
PL43E_A/LUM0_GPLLT_FB_A
PL43E_B/LUM0_GPLLT_FB_B
PL43E_C/LUM0_GPLLT_IN_A
PL43E_D/LUM0_GPLLT_IN_B
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VTT7
U1F
1
These pins are connected
to the XO CPLD.
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 27. FPGA Test
100NF-0603SMT
A
B
C
D
1
2
3
4
3
4
GND
N/C
CY2304-1
REF
FBK
CLKA1 VDD
CLKA2 CLKB2
GND CLKB1
U15
Y1
OUT
Vcc
8
7
6
5
2
1
CTS-CB3LV-3C-100.00MHZ
OSC_IN_1
3_3V
2
4
6
8
10
12
14
16
18
5
[8] FPGA_SMA_REFCLKN
3_3V
1
3
5
7
9
11
13
15
17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
R77
51R-0603SMT
R80
OPEN-0603SMT
R78
51R-0603SMT
C186
SMA
1
J6
LA2
LA4
LA6
LA8
LA10
LA12
LA14
LA16
LA18
LA20
LA22
LA24
LA26
LA28
LA30
LA32
LA34
2
3
4
5
TP_0
TP_1
TP_2
TP_3
TP_4
TP_5
TP_6
TP_7
TP_8
TP_9
TP_10
TP_11
TP_12
TP_13
TP_14
TP_15
TP_[0:15]
[8]
100NF-0603SMT
C187
SMA
1
J7
2
3
4
5
[8]
4
OSC_IN_[1:3]
C185
10NF-0603SMT
Connected to SMA inputs
100NF-0603SMT
HEADER 9X2
J5
2-5767004-2
5V SCL
GND SDA
CLK1 CLK
7
8
9
10
11
12
13
14
15
16
17
18
20
19
21
22
24
23
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R79
OPEN-0603SMT
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
PLACE CLOSE TO U1
LA1
LA3
LA5
LA7
LA9
LA11
LA13
LA15
LA17
LA19
LA21
LA23
LA25
LA27
LA29
LA31
LA33
LA1
LA[1:34]
C184
100NF-0603SMT
OSC_IN_3
OSC_IN_2
3_3V
LOGIC ANALYZER PROBE
[8] FPGA_SMA_REFCLKP
[5] FLASH_CLK
100NF-0603SMT
C183
FLASH_CLK
3_3V
100MHZ GENERAL PURPOSE CLOCKS
4
[8]
3_3V
SEG12
5
15 RN3E
5
6
7
8
13 RN4E
16 RN4F
1 RN4G
2 RN4H
2
3
1
6 RN4B
4
8
4 RN3H
5 RN4A
8 RN4C
7
3 RN3G
9 RN4D
6
17 RN3F
SEG7
SEG8
SEG9
SEG10
SEG11
9 RN2H
8 4_7K
EXB2HV472JV
SWITCH1
SEG0
SEG1
SEG2
SEG3
SEG4
BGA
B7
F8
F7
A4
A3
H8
G7
C8
D8
B4
C5
C6
D6
C4
D5
C7
B6
3
16-SEGMENT DISPLAY
9
10
11
12
13
[8]
10 RN2G
7 4_7K
EXB2HV472JV
SWITCH2
SEG[0:16]
6 4_7K
11 RN2F
EXB2HV472JV
SWITCH3
D24
LED-SMT1206_BLUE
D19
LED-SMT1206_RED
LED6
X1_POLL
LED10
X1_USR3
LED14
X1_USR0
2
8 470R
9 RN5H
EXB2HV471JV
7 470R
10 RN5G
EXB2HV471JV
PLL_LK_PU
USR1_PU
11 RN5F
6 470R
EXB2HV471JV
5 470R
12 RN5E
EXB2HV471JV
4 470R
13 RN5D
EXB2HV471JV
3 470R
14 RN5C
EXB2HV471JV
2 470R
15 RN5B
EXB2HV471JV
1 470R
16 RN5A
EXB2HV471JV
3_3V
LED12
X4_USR0
D25
LED-SMT1206_BLUE
LED8
X4_USR3
D20
LED-SMT1206_RED
LED4
X4_L0
X1_L0
X4_PLL_LK
X1_PLL_LK
X4_USR2
X1_USR2
Date:
Size
C
Title
[8]
X4_USR1
X1_USR1
D27
LED-SMT1206_BLUE
D22
LED-SMT1206_RED
Monday, February 23, 2009
1
Sheet
9
of
9
Rev
1.0
1605 Valley Center Parkway
Bethlehem, PA 18017
BGA
D10
F10
E10
A8
B8
G10
G9
C9
C10
H10
H11
A9
B10
F11
G11
A10
LED USER 1
USR1_PU
LED USER 2
USR2_PU
LED-SMT1206_YELLOW
D18
ECP3 PCIe DevKit Eval Board
Project
D14
LED-SMT1206_GREEN
1
PLL LOCK STATUS
PLL_LK_PU
L0
L0_PU
FPGA TEST
LED
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LED[0:15]
LED15
LED13
D26
LED-SMT1206_BLUE
LED11
LED9
D21
LED-SMT1206_RED
LED7
LED5
D17
LED-SMT1206_YELLOW
LED3
LED1
D13
LED-SMT1206_GREEN
LEDs
X4_POLL
D16
LED-SMT1206_YELLOW
LED2
LED0
USR2_PU
L0_PU
USR0_PU
POLL_PU
USR3_PU
DL_UP_PU
LED USER 0
USR0_PU
LED USER 3
USR3_PU
POLLING STATUS
5 4_7K
12 RN2E
EXB2HV472JV
SWITCH4
D15
LED-SMT1206_YELLOW
POLL_PU
4 4_7K
13 RN2D
EXB2HV472JV
SWITCH5
X1_DL_UP
14 RN2C
3 4_7K
EXB2HV472JV
SWITCH6
D12
LED-SMT1206_GREEN
2 4_7K
15 RN2B
EXB2HV472JV
DL UP
SWITCH7
D11
LED-SMT1206_GREEN
DL_UP_PU
16 RN2A
1 4_7K
EXB2HV472JV
3_3V
2
SWITCH8
SEG6
EXB2HV151JV
SEG5
14 150R
15
16
9
10
11
12
13
SEG14
SEG15
4
7 RN3B
14 RN3A
12 RN3D
SEG16
[8]
SEG13
BGA
D9
F9
G8
A6
A5
E9
E8
A7
SWITCH[1:8]
R76
150R-0603SMT
1
16
EXB2HV151JV
15
2
150R
RN3C
11
3
14
10
LTP-587HR/16-SEGMENT
SEGMENT
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
18
D23
3
DIP SWITCH
SWITCH8
SWITCH7
SWITCH6
SWITCH5
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH
1
2
3
4
5
6
7
8
SW DIP-8/SM
SW5
DP
U
T
S
R
P
N
M
K
H
G
F
E
D
C
B
30
A
5
A
B
C
D
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Figure 28. VSS/Decoupling
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Appendix B. Bill of Materials
Table 17. Bill of Materials
Item
Quantity
1
1
CN1
Reference
PCI Express x4 Edge Finger Conn.
Part
Manufacturer
2
1
CN2
PCI Express x1 Edge Finger Conn.
3
1
C1
470UF-FKSMT
Panasonic
EEV-FK1V471Q
CAP 470UF 35V
ELECT FK SMD
4
2
C2, C140
100UF-FKSMT
Panasonic
EEEFK1V101XP
CAP 100UF 35V
ELECT FK SMD
5
5
C3, C4, C7, C9, C142
10UF-16V-TANTBSMT
AVX
TAJB106K016R
CAP 10UF 16V
TANT B-SIZE
6
4
C5, C6, C8, C10
330UF-FKSMT
Panasonic
EEEFK1C331P
CAP 330UF 16V
ELECT FK SMD
7
30
C11, C12, C13, C14, C15, C16, C17, 1000PF-0402SMT
C18, C36, C37, C38, C39, C40, C56,
C57, C58, C59, C60, C61, C62, C63,
C64, C65, C66, C67, C68, C83, C84,
C85, C86
Panasonic
ECJ-0EB1E102K
CAP 1000PF 25V
CERAMIC X7R
0402
8
54
C19, C20, C21, C22, C23, C24, C25, 10NF-0603SMT
C41, C43, C47, C49, C50, C51, C52,
C53, C54, C55, C70, C73, C76, C79,
C80, C88, C94, C96, C98, C100,
C111, C113, C115, C117, C119,
C121, C123, C125, C146, C148,
C149, C150, C155, C156, C161,
C162, C163, C164, C169, C170,
C172, C174, C176, C178, C180,
C182, C185
Kemet
C0603C103K5RACTU
CAP .01UF 50V
CERAMIC X7R
0603
9
14
C26, C34, C48, C71, C77, C103,
C105, C107, C109, C137, C141,
C144, C154, C167
1UF-16V-0805SMT
Panasonic
ECJ-2FB1C105K
CAP 1UF 16V
CERAMIC 0805
X5R
10
12
C27, C29, C44, C69, C81, C102,
C104, C106, C108, C152, C153,
C166
22UF-16V_TANTBSMT
Kemet
T491B226M016AT
CAPACITOR TANT
22UF 16V 20%
SMD
11
54
C28, C30, C31, C32, C33, C35, C42, 100NF-0603SMT
C45, C46, C72, C74, C75, C78, C82,
C87, C89, C90, C91, C92, C93, C95,
C97, C99, C101, C110, C112, C114,
C116, C118, C120, C122, C124,
C136, C139, C143, C145, C147,
C151, C157, C158, C159, C160,
C165, C168, C171, C173, C175,
C177, C179, C181, C183, C184,
C186, C187
Panasonic
ECJ-1VF1C104Z
CAP .1UF 16V
CERAMIC Y5V
0603
12
10
C126, C127, C128, C129, C130,
C131, C132, C133, C134, C135
100NFX5R-0402SMT
Kemet
C0402C104K8PACTU
CAP .10UF 10V
CERAMIC X5R
0402
13
1
C138
47UF-10V-TANTBSMT
Kemet
T491B476M010AT
CAPACITOR TANT
47UF 10V 20%
SMD
14
11
D1, D2, D3, D4, D5, D9, D10, D11,
D12, D13, D14
LED-SMT1206_GREEN
Panasonic
LNJ316C83RA
LED GREEN (UP)
W/LENS 1206
15
7
D6, D7, D8, D19, D20, D21, D22
LED-SMT1206_RED
Panasonic
LNJ211R82RA
LED RED (UP)
W/LENS 1206
16
4
D15, D16, D17, D18
LED-SMT1206_YELLOW
Panasonic
LNJ411K84RA
LED YELLOW (UP)
W/LENS 1206
17
1
D23
LTP-587HR/16-SEGMENT Lite-On
LTP-587HR
16-segment array
18
4
D24, D25, D26, D27
LED-SMT1206_BLUE
Panasonic
LNJ916C8BRA
LED BLUE (UP)
W/LENS 1206
19
8
FB1, FB2, FB3, FB4, FB5, FB6, FB7, BLM41PG600SN1
FB8
Murata
BLM41PG600SN1L
FERRITE CHIP 60
OHM 6000MA 1806
20
5
F1, F2, F3, F4, F5
F1228CT-ND
Littlefuse
0154005.DR
FUSEBLOCK WITH
5A FUSE SMD
21
1
J1
22HP037-2.1mm
Condor
22HP037-2.1mm
power input
22
1
J2
HEADER 2X2
Samtec
TSW-102-07-T-D
2x2-0.25 Header
23
1
J3
HEADER 2
Samtec
TSW-102-07-T-S
2x1-0.25 Header
24
2
J4, J8
HEADER 6
Samtec
TSM-106-01-T-SH
6x1-0.25 HeaderSMT
25
1
J5
HEADER 9X2
Samtec
TSW-109-07-T-D
9x2-0.25 Header
31
Part Number
Description
PCB Edge finger
PCB Edge finger
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 17. Bill of Materials (Continued)
Item
Quantity
26
2
J6, J7
Reference
SMA
Part
Molex
Manufacturer
73391-0060
Part Number
CONN JACK SMA
STR 50 OHM PCB
Description
27
1
LA1
2_5767004-2
Amp
2_5767004-2
CONN RECEPT
38POS .025 VERT
SMD
28
5
LP1, LP2, LP3, LP4, LP5
5016
Keystone Electronics
5016
TEST POINT PC
COMPACT SMT
29
3
MH1, MH2, MH3
M HOLE2
30
2
PP1, PP2
PROBEPOINT
31
4
Q1, Q2, Q3, Q4
2N2222/SOT23
Diodes Inc.
MMBT2222A-7-F
TRANS NPN 40V
350MW SMD SOT23
32
1
RN1
EXBV8V472JV
Panasonic
EXBV8V472JV
RES ARRAY 4.7K
OHM 5% 4 RES
SMD
33
1
RN2
EXB2HV472JV
Panasonic
EXB2HV472JV
RES ARRAY 4.7K
OHM 5% 8 RES
SMD
34
2
RN3, RN4
EXB2HV151JV
Panasonic
EXB2HV151JV
RES ARRAY 150
OHM 5% 8 RES
SMD
35
1
RN5
EXB2HV471JV
Panasonic
EXB2HV471JV
RES ARRAY 470
OHM 5% 8 RES
SMD
36
2
RP1, RP2
CTS-R2402B7
CTS Corporation Resistor/
Electrocomponents
CTS-R2402B7TR7
RES NET DDR
SDRAM 50 OHM
3X9 BGA
37
4
R1, R2, R3, R4
1_8K-1206SMT
Panasonic
ERJ-8GEYJ182V
RES 1.8K OHM
1/4W 5% 1206 SMD
38
1
R76
150R-0603SMT
Panasonic
ERA-3YEB151V
RES 150 OHM
1/16W .1% 0603
SMD
39
23
R6, R7, R8, R21, R22, R27, R28,
R29, R30, R31, R32
10K-0603SMT
Panasonic
ERJ-3GEYJ103V
RES 10K OHM
1/10W 5% 0603
SMD
Panasonic
ERJ-3GEY0R00V
RES ZERO OHM
1/10W 5% 0603
SMD
R33, R34, R35, R36, R37, R38, R39,
R45, R46, R48, R49, R54
40
7
R9, R10, R53, R64, R67, R73, R75
0R-0603SMT
41
2
R11, R12
OPEN-0805SMT
42
1
R13
12_1K-0603SMT
Susumu Co Ltd.
RG1608P-1212-B-T5
RES 12.1K OHM
1/10W .1% 0603
SMD
43
2
R14, R20
2K-0603SMT
Panasonic
ERJ-3EKF2001V
RES 2.00K OHM
1/10W 1% 0603
SMD
44
2
R15, R16
100R-0805SMT
Panasonic
ERJ-6GEYJ101V
RES 100 OHM
1/8W 5% 0805 SMD
45
8
R17, R19, R56, R57, R61, R66, R68, 1K-0603SMT
R74
Panasonic
ERJ-3EKF1001V
RES 1.00K OHM
1/16W 1% 0603
SMD
46
1
R18
806R-0603SMT
Panasonic
ERJ-3EKF8060V
RES 806 OHM
1/10W 1% 0603
SMD
47
3
R23, R24, R25
680R-0603SMT
Panasonic
ERJ-3GEYJ681V
RES 680 OHM
1/10W 5% 0603
SMD
48
3
R5, R26, R47
220R-0603SMT
Panasonic
ERJ-3GEYJ221V
RES 220 OHM
1/10W 5% 0603
SMD
49
7
R40, R43, R44, R60, R69, R70, R71 4_7K-0603SMT
Panasonic
ERJ-3GEYJ472V
RES 4.7K OHM
1/10W 5% 0603
SMD
50
8
R41, R42, R52, R58, R59, R63, R79, OPEN-0603SMT
R80
51
2
R50, R51
Panasonic
ERA-3YEB101V
RES 100 OHM
1/16W .1% 0603
SMD
100R-0603SMT
32
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 17. Bill of Materials (Continued)
Item
Quantity
52
1
R55
Reference
2_2K-0603SMT
Part
Panasonic
Manufacturer
ERJ-3GEYJ222V
Part Number
RES 2.2K OHM
1/10W 5% 0603
SMD
Description
53
2
R62, R72
1K_ADJ/SMT3MM
Murata
PVG3A102C01R00
POT 1K 3MM
CERM SQ S/T SMD
54
0
R65(deleted)
0R-2010SMT
Vishay/Dale
CRCW20100000Z0EF
RES 0.0 OHM1/2W
5% 2010 SMD
55
2
R77, R78
51R-0603SMT
Panasonic
ERJ-3GEYJ510V
RES 51 OHM
1/10W 5% 0603
SMD
56
4
SP1, SP2, SP3, SP4
TEST POINT
57
4
SW1, SW3, SW6, SW7
SW PUSHBUTTON-SPST C&K Components
EP11FPD1SAPE
SPST- Momentary
RA/SMT
58
1
SW2
SW DIP-3 CTS 194-3MST CTS Corporation Resistor/Electrocomponents
194-3MST
SWITCH SIDE
ACTUATED GOLD
3 SEC
59
1
SW4
B3F-1150
Omron
B3F-1150
SWITCH TACT
6MM 100GF
H=7.3MM
60
1
SW5
SW DIP-8/SM
C&K Components
BPA08SB
8-POSITION DIP
PACK
61
1
TB1
Terminal Block/ED1202DS On-Shore Tech.
ED120/2DS
TERMINAL BLOCK
5.08MM VERT
2POS
62
14
TP1, TP2, TP3, TP4, TP5, TP6, TP7, TESTPOINT
TP8, TP9, TP10
63
1
U1
ECP3-672fpBGA
LATTICE SUPPLIED
64
1
U2
PTH12060L
Texas Instruments
PTH12060LAH
MODULE PIP
12VIN 10A ADJ 10TH
65
1
U3
PTH12060W
Texas Instruments
PTH12060WAH
MODULE PIP
12VIN 10A ADJ 10TH
66
2
U4, U5
SC1592
Semtech
SC1592IMTRT
IC LDO ADJ REG
3A TO-263-7
67
1
U6
M25P64-FLASH
STMicro
M25P64-VMF6P
IC SRL FLASH
64MBIT 3V 16-SOP
Wide(300MIL)
68
1
U7
MAX6817
Maxim
MAX6817-EUT+T
±15kV ESD-Protected, Dual, CMOS
Switch Debouncers
69
2
U8,U10
NC7WZ16-MAAO6A/Fairchild TinyLogic
Fairchild
NC7WZ16P6X
IC BUFFER UHS
DUAL SC70-6
70
1
U9
SN74LVC125A/SO14
Texas Instruments
SN74LVC125AD
IC QUAD BUS BUFFER GATE 14-SOIC
71
1
U11
S29GL064A
Spansion
S29GL064N90BF1040 48fBGA FLASHVBN048
72
1
U12
LCMXO1200CCSBGA132
LATTICE SUPPLIED
73
1
U13
LP2998-SO8
National Semi
LP2998MA/NOPB
IC DDR TERMINATION REG 8SOIC
74
1
U14
DDR2-SDRAM-84FBGA
Micron
MT47H16M16BG-37E
16-Bit DDR2
75
1
U15
CY2304-1
Cypress Semiconductor
CY2304SXC-1
zero delay buffer
76
1
Y1
CTS-CB3LV-3C100.00MHZ
CTS-Frequency Controls
CB3LV-3l-100M0000-T OSC CLOCK
100.000 MHZ 3.3V
SMD
77
1
Bracket
78
2
Screw
4-40 x .250
79
2
Flat washer
4-40
80
2
Lock washer
4-40
81
2
C222, C224
100NF-0603SMT
Panasonic
ECJ-1VF1C104Z
CAP .1UF 16V
CERAMIC Y5V
0603
82
1
C223
10UF-16V-TANTBSMT
AVX
TAJB106K016R
CAP 10UF 16V
TANT B-SIZE
TP11, TP12, TP13, TP14
33
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
Table 17. Bill of Materials (Continued)
Item
Quantity
83
1
R227
Reference
1_6R-0603SMT
Part
Panasonic
Manufacturer
ERJ-3GEYJ1R6V
84
4
R223, R224, R228, R229
50R-0402SMT
Vishay
FC0402E50R0BTBST1 RES 50 OHM
50MW .1% 0402
SMD
85
1
Y2
CRYSTEK_133MHZ
Crystek
CCLD-033-50-133.000 OSC LVDS 133.0
MHZ 3.3V
7mmx5mm SMD
86
2
C220, C225
10NF-0402SMT
Panasonic
ECJ0EB1E103K
CAP .01UF 25V
CERAMIC X7R
0402
87
1
R222
50R-0603SMT
Vishay
FC0603E50R0BTBT1
RES 50 OHM
125MW .1% 0603
SMD
88
1
D33
SCHOTTKY/VISHAYV12P Vishay
10
V12P10-E3/87A
TO277 SCHOTTKY
DIODE
34
Part Number
Description
RESISTOR 1.6
OHM 1/10W 5%
0603