ispLSI® 1016 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line ispLSI 1016 Ordering Part Number ispLSI 1016-60LJ ispLSI 1016-80LJ ispLSI 1016-90LJ ispLSI 1016-110LJ ispLSI 1016-60LJI ispLSI 1016-60LT44 ispLSI 1016-80LT44 ispLSI 1016-90LT44 ispLSI 1016-60LT44I ispLSI 1016-60LH/883 5962-9476201MXC Product Status Discontinued Reference PCN PCN#13-10 PCN#05A-10 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: http://www.latticesemi.com ispLSI 1016 ® In-System Programmable High Density PLD Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Security Cell Prevents Unauthorized Copying B7 D Q A1 B6 A D LL IS C DE O N VIC TI N ES U ED Output Routing Pool A0 Output Routing Pool Features E2CMOS® • HIGH PERFORMANCE TECHNOLOGY — fmax = 110 MHz Maximum Operating Frequency — fmax = 60 MHz for Industrial and Military/883 Devices — tpd = 10 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested A2 A3 Array B5 D Q D Q GLB B4 B3 A4 D Q B2 A5 B1 A6 A7 • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging Logic Global Routing Pool (GRP) B0 CLK Description • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity The ispLSI 1016 is a High-Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1016 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 1016_10 1 January 2002 Specifications ispLSI 1016 Functional Block Diagram Figure 1. ispLSI 1016 Functional Block Diagram Generic Logic Blocks (GLBs) A D LL IS C DE O N VIC TI N ES U ED IN 3 MODE/IN 2 I/O 31 I/O 30 I/O 29 B7 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 B5 A2 A3 I/O 28 B4 Global Routing Pool (GRP) B3 A4 B2 A5 I/O 27 lnput Bus Output Routing Pool (ORP) I/O 8 B6 A1 Input Bus I/O 4 I/O 5 I/O 6 I/O 7 A0 Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 B1 A6 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 B0 A7 SDI/IN 0 SDO/IN 1 Clock Distribution Network Megablock CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1 ispEN Y0 Y1/RESET* SCLK/Y2 *Note: Y1 and RESET are multiplexed on the same pin 0139B(1a)-isp.eps The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1016 device are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The ispLSI 1016 device contains two of these Megablocks. 2 Specifications ispLSI 1016 Absolute Maximum Ratings 1 Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C A D LL IS C DE O N VIC TI N ES U ED Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL VCC PARAMETER MAX. UNITS Commercial TA = 0°C to +70°C 4.75 5.25 Industrial TA = -40°C to +85°C 4.5 5.5 Military/883 TC = -55°C to +125°C 4.5 5.5 Input Low Voltage 0 0.8 V Input High Voltage 2.0 Vcc + 1 V Supply Voltage VIL VIH MIN. V Table 2- 0005Aisp w/mil.eps o Capacitance (TA=25 C, f=1.0 MHz) SYMBOL C1 C2 1 MAXIMUM PARAMETER Dedicated Input Capacitance UNITS TEST CONDITIONS Commercial/Industrial 8 pf VCC=5.0V, VIN=2.0V Military 10 pf VCC=5.0V, VIN=2.0V 10 pf VCC=5.0V, VI/O, VY=2.0V I/O and Clock Capacitance 1. Guaranteed but not 100% tested. Table 2- 0006 Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS 20 — Years 10000 — Cycles Data Retention Erase/Reprogram Cycles Table 2- 0008B 3 Specifications ispLSI 1016 Switching Test Conditions Input Pulse Levels Figure 2. Test Load GND to 3.0V Input Rise and Fall Time ≤ 3ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load + 5V R1 Device Output See figure 2 A D LL IS C DE O N VIC TI N ES U ED 3-state levels are measured 0.5V from steady-state active level. Test Point Output Load Conditions (see figure 2) Test Condition B C *CL includes Test Fixture and Probe Capacitance. R1 R2 CL 470Ω 390Ω 35pF Active High ∞ 390Ω 35pF Active Low 470Ω 390Ω 35pF Active High to Z at VOH - 0.5V ∞ 390Ω 5pF Active Low to Z 470Ω 390Ω 5pF A CL * R2 Table 2- 0003 at VOL + 0.5V Table 2- 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER VOL VOH IIL IIH IIL-isp IIL-PU IOS1 Output Low Voltage IOL =8 mA Output High Voltage IOH =-4 mA ICC2,4 MIN. TYP.3 MAX. UNITS – – 0.4 V 2.4 – – V Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -10 μA Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC – – 10 μA isp Input Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) – – -150 μA I/O Active Pull-Up Current 0V ≤ VIN ≤ VIL – – -150 μA Output Short Circuit Current VCC = 5V, VOUT = 0.5V – – -200 mA Operating Power Supply Current VIL = 0.5V, VIH = 3.0V Commercial – 100 150 mA fTOGGLE = 1 MHz – 100 170 mA Industrial/Military 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. Table 2-0007A-16 w/mil 4 Specifications ispLSI 1016 External Timing Parameters Over Recommended Operating Conditions 5 2 PARAMETER TEST # COND. -90 UNITS MIN. MAX. MIN. MAX. A 1 Data Propagation Delay, 4PT bypass, ORP bypass — 10 — 12 ns A 2 Data Propagation Delay, Worst Case Path — 14.5 — 17 ns Feedback3 A 3 Clock Frequency with Internal 111 — 90.9 — MHz — 4 Clock Frequency with External Feedback (tsu2 1+ tco1) 70.1 — 58.8 — MHz — 5 Clock Frequency, Max Toggle4 125 — 125 — MHz — 6 GLB Reg. Setup Time before Clock, 4PT bypass 4.5 — 6 — ns A 7 GLB Reg. Clock to Output Delay, ORP bypass — 7 — 8 ns — 8 GLB Reg. Hold Time after Clock, 4 PT bypass 0 — 0 — ns — 9 GLB Reg. Setup Time before Clock 7.5 — 9 — ns — 10 GLB Reg. Clock to Output Delay — 8.5 — 10 ns — 11 GLB Reg. Hold Time after Clock 0 — 0 — ns — 14 — 15 ns — 13 Ext. Reset Pulse Duration 10 — 10 — ns B 14 Input to Output Enable — 15 — 15 ns C 15 Input to Output Disable A D LL IS C DE O N VIC TI N ES U ED tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 -110 DESCRIPTION1 1. 2. 3. 4. 5. A 12 Ext. Reset Pin to Output Delay — 15 — 15 ns — 16 Ext. Sync. Clock Pulse Duration, High 4 — 4 — ns — 17 Ext. Sync. Clock Pulse Duration, Low 4 — 4 — ns — 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2) 2 — 2 — ns 5.5 — 6.5 — ns — 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2) Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section. 5 Table 2-0030-16/110,90C Specifications ispLSI 1016 External Timing Parameters Over Recommended Operating Conditions 5 2 PARAMETER TEST # COND. -60 UNITS MIN. MAX. MIN. MAX. A 1 Data Propagation Delay, 4PT bypass, ORP bypass – 15 – 20 A 2 Data Propagation Delay, Worst Case Path – 20 – 25 ns A 3 Clock Frequency with Internal Feedback3 80 – 60 – MHz – 4 Clock Frequency with External Feedback (tsu2 1+ tco1) 50 – 38 – MHz Toggle4 ns – 5 Clock Frequency, Max 100 – 83 – MHz – 6 GLB Reg. Setup Time before Clock, 4PT bypass 7 – 9 – ns A 7 GLB Reg. Clock to Output Delay, ORP bypass – 10 – 13 ns – 8 GLB Reg. Hold Time after Clock, 4 PT bypass 0 – 0 – ns – 9 GLB Reg. Setup Time before Clock 10 – 13 – ns – 10 GLB Reg. Clock to Output Delay – 12 – 16 ns – 11 GLB Reg. Hold Time after Clock 0 – 0 – ns A 12 Ext. Reset Pin to Output Delay – 17 – 22.5 ns A D LL IS C DE O N VIC TI N ES U ED tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 -80 DESCRIPTION1 – 13 Ext. Reset Pulse Duration 10 – 13 – ns B 14 Input to Output Enable – 18 – 24 ns C 15 Input to Output Disable – 18 – 24 ns – 16 Ext. Sync. Clock Pulse Duration, High 5 – 6 – ns – 17 Ext. Sync. Clock Pulse Duration, Low 5 – 6 – ns – 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2) 2 – 2.5 – ns – 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2) 6.5 – 8.5 – ns Table 2-0030-16/80,60C 1. 2. 3. 4. 5. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section. 6 Specifications ispLSI 1016 Internal Timing Parameters1 PARAMETER -110 DESCRIPTION 20 I/O Register Bypass 21 I/O Latch Delay 22 I/O Register Setup Time before Clock -90 MIN. MAX. MIN. MAX. UNITS – 1.0 ns 1.7 – 2.0 ns – 4.5 – ns – 0.8 – 4.1 A D LL IS C DE O N VIC TI N ES U ED Inputs tiobp tiolat tiosu tioh tioco tior tdin 2 # GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp 1.8 – 2.0 – ns I/O Register Clock to Out Delay – 1.7 – 2.0 ns 25 I/O Register Reset to Out Delay – 2.1 – 2.5 ns 26 Dedicated Input Delay – 1.7 – 2.0 ns 27 GRP Delay, 1 GLB Load – 0.6 – 0.7 ns 28 GRP Delay, 4 GLB Loads – 0.8 – 1.0 ns 29 GRP Delay, 8 GLB Loads – 1.5 – 1.8 ns 30 GRP Delay, 12 GLB Loads – 2.1 – 2.6 ns 31 GRP Delay, 16 GLB Loads – 2.8 – 3.4 ns 33 4 Product Term Bypass Path Delay – 5.3 – 6.5 ns 34 1 Product Term/XOR Path Delay – 6.1 – 7.0 ns 35 20 Product Term/XOR Path Delay – 6.6 – 8.0 ns 36 XOR Adjacent Path Delay3 – 8.2 – 9.5 ns 37 GLB Register Bypass Delay – 0.5 – 0.5 ns 38 GLB Register Setup Time before Clock 0.3 – 1.0 – ns 39 GLB Register Hold Time after Clock 2.9 – 3.5 – ns 40 GLB Register Clock to Output Delay – 1.6 – 1.5 ns 41 GLB Register Reset to Output Delay – 2.1 – 2.5 ns 42 GLB Product Term Reset to Register Delay – 8.2 – 10.0 ns 43 GLB Product Term Output Enable to I/O Cell Delay 44 GLB Product Term Clock Delay 45 46 23 I/O Register Hold Time after Clock 24 – 9.0 – 9.0 ns 2.8 6.2 3.5 7.5 ns ORP Delay – 2.0 – 2.5 ns ORP Bypass Delay – 0.4 – 0.5 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros. 7 Specifications ispLSI 1016 Internal Timing Parameters1 PARAMETER -110 DESCRIPTION -90 UNITS MIN. MAX. MIN. MAX. 47 Output Buffer Delay – 2.1 – 2.5 ns 48 I/O Cell OE to Output Enabled – 3.3 – 4.0 ns 49 I/O Cell OE to Output Disabled – 3.3 – 4.0 ns A D LL IS C DE O N VIC TI N ES U ED Outputs tob toen todis 2 # Clocks tgy0 tgy1/2 tgcp tioy1/2 tiocp 50 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.9 2.9 3.5 3.5 ns 51 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.1 3.8 2.5 4.5 ns 52 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 4.2 1.0 5.0 ns 53 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 2.1 3.8 2.5 4.5 ns 54 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 4.2 1.0 5.0 ns – 7.9 – 7.5 ns Global Reset tgr 55 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 8 Specifications ispLSI 1016 Internal Timing Parameters1 PARAMETER -80 DESCRIPTION 20 I/O Register Bypass 21 I/O Latch Delay 22 I/O Register Setup Time before Clock -60 MIN. MAX. MIN. MAX. – 2.0 – 5.5 UNITS – 2.7 ns 3.0 – 4.0 ns – 7.3 – ns A D LL IS C DE O N VIC TI N ES U ED Inputs tiobp tiolat tiosu tioh tioco tior tdin 2 # GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp 1.0 – 1.3 – ns I/O Register Clock to Out Delay – 3.0 – 4.0 ns 25 I/O Register Reset to Out Delay – 2.5 – 3.3 ns 26 Dedicated Input Delay – 4.0 – 5.3 ns 27 GRP Delay, 1 GLB Load – 1.5 – 2.0 ns 28 GRP Delay, 4 GLB Loads – 2.0 – 2.7 ns 29 GRP Delay, 8 GLB Loads – 3.0 – 4.0 ns 30 GRP Delay, 12 GLB Loads – 3.8 – 5.0 ns 31 GRP Delay, 16 GLB Loads – 4.5 – 6.0 ns 33 4 Product Term Bypass Path Delay – 6.5 – 8.6 ns 34 1 Product Term/XOR Path Delay – 7.0 – 9.3 ns 35 20 Product Term/XOR Path Delay – 8.0 – 10.6 ns 36 XOR Adjacent Path Delay3 – 9.5 – 12.7 ns 37 GLB Register Bypass Delay – 1.0 – 1.3 ns 38 GLB Register Setup Time before Clock 1.0 – 1.3 – ns 39 GLB Register Hold Time after Clock 4.5 – 6.0 – ns 40 GLB Register Clock to Output Delay – 2.0 – 2.7 ns 41 GLB Register Reset to Output Delay – 2.5 – 3.3 ns 42 GLB Product Term Reset to Register Delay – 10.0 – 13.3 ns 43 GLB Product Term Output Enable to I/O Cell Delay 44 GLB Product Term Clock Delay 45 23 I/O Register Hold Time after Clock 24 46 – 9.0 – 12.0 ns 3.5 7.5 4.6 9.9 ns ORP Delay – 2.5 – 3.3 ns ORP Bypass Delay – 0.5 – 0.7 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros. 9 Specifications ispLSI 1016 Internal Timing Parameters1 PARAMETER -80 DESCRIPTION -60 UNITS MIN. MAX. MIN. MAX. 47 Output Buffer Delay – 3.0 – 4.0 ns 48 I/O Cell OE to Output Enabled – 5.0 – 6.7 ns 49 I/O Cell OE to Output Disabled – 5.0 – 6.7 ns A D LL IS C DE O N VIC TI N ES U ED Outputs tob toen todis 2 # Clocks tgy0 tgy1/2 tgcp tioy1/2 tiocp 50 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 4.5 4.5 6.0 6.0 ns 51 Clock Delay, Y1 or Y2 to Global GLB Clock Line 3.5 5.5 4.6 7.3 ns 52 Clock Delay, Clock GLB to Global GLB Clock Line 1.0 5.0 1.3 6.6 ns 53 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 3.5 5.5 4.6 7.3 ns 54 Clock Delay, Clock GLB to I/O Cell Global Clock Line 1.0 5.0 1.3 6.6 ns – 9.0 – 12.0 ns Global Reset tgr 55 Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 10 Specifications ispLSI 1016 ispLSI 1016 Timing Model I/O Cell GRP GLB ORP I/O Cell Feedback Ded. In 4 PT Bypass GLB Reg Bypass ORP Bypass #20 #28 #33 #37 #46 Input D Register Q RST #21 - 25 GRP Loading Delay #27, 29, 30, 31, 32 20 PT XOR Delays GLB Reg Delay ORP Delay GRP 4 #34, 35, 36 D Q #45 #47 I/O Pin (Output) #48, 49 A D LL IS C DE O N VIC TI N ES U ED I/O Pin (Input) #26 I/O Reg Bypass #55 #55 Reset Clock Distribution Y1,2 RST #51, 52, 53, 54 #38, 39, 40, 41 Control RE PTs OE #42, 43, CK 44 #50 Y0 Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 5.5 ns = (1.0 + 1.0 + 8.0) + (1.0) - (1.0 + 1.0 + 3.5) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 3.0 ns = (1.0 + 1.0 + 7.5) + (3.5) - (1.0 + 1.0 + 8.0) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 16.0 ns = (1.0+ 1.0 +7.5) + (1.5) + (2.5 + 2.5) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 5.0 ns = (1.0 + 1.0 + 8.0) + (1.0) - (3.5 + 1.5 + 1.0) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 3.5 ns = (3.5 + 1.5 + 5.0) + (3.5) - (1.0 + 1.0 + 8.0) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 16.5 ns = (3.5 + 1.5 + 5.0) + (1.5) + (2.5 + 2.5) 1. Calculations are based upon timing specifications for the ispLSI 1016-90. 11 Specifications ispLSI 1016 Maximum GRP Delay vs GLB Loads ispLSI 1016-60 5 ispLSI 1016-80 4 ispLSI 1016-90/-110 3 A D LL IS C DE O N VIC TI N ES U ED GRP Delay (ns) 6 2 1 0 4 8 GLB Loads 12 16 0126A-80-16-isp.eps Power Consumption Power consumption in the ispLSI 1016 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Fig- ure 3 shows the relationship between power and operating speed. Figure 3. Typical Device Power Consumption vs fmax ICC (mA) 150 ispLSI 1016 100 50 0 10 20 30 40 50 60 70 80 90 100 110 fmax (MHz) Notes: Configuration of Four 16-bit Counters Typical Current at 5V, 25ßC ICC can be estimated for the ispLSI 1016 using the following equation: ICC = 31 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.009) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 12 Specifications ispLSI 1016 Pin Description NAME PLCC TQFP JLCC PIN NUMBERS PIN NUMBERS PIN NUMBERS 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10 9, 13, 19, 23, 31, 35, 41, 1, 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 15, 19, 25, 29, 37, 41, 3, 7, 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, Input/Output Pins - These are the general purpose I/O 22, pins used by the logic array. 28, 32, 40, 44, 6, 10 I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 15, 19, 25, 29, 37, 41, 3, 7, IN 3 2 40 2 Dedicated input pins to the device. ispEN 13 7 13 SDI/IN 0 1 14 8 14 MODE/IN 2 1 36 30 36 SDO/IN 1 1 24 18 24 SCLK/Y2 1 33 27 33 Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Y0 11 5 11 Y1/RESET 35 29 35 GND VCC 1, 23 12, 34 17, 39 6, 28 1, 23 12, 34 A D LL IS C DE O N VIC TI N ES U ED 16, 20, 26, 30, 38, 42, 4, 8, DESCRIPTION Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. This pin performs two functions: – Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. – Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Ground (GND) VCC Table 2 - 0002C-16-isp 1. Pins have dual function capability. 13 Specifications ispLSI 1016 Pin Configuration I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 IN 3 I/O 24 I/O 26 I/O 25 I/O 27 ispLSI 1016 44-Pin PLCC Pinout Diagram 6 5 4 3 2 1 44 43 42 41 40 7 39 I/O 18 I/O 29 8 38 I/O 17 I/O 30 9 37 I/O 16 A D LL IS C DE O N VIC TI N ES U ED I/O 28 I/O 31 Y0 VCC 10 11 36 IN 2/MODE1 12 ispLSI 1016 35 34 ispEN 1SDI/IN 0 13 Top View 33 Y1/RESET VCC Y2/SCLK1 14 32 I/O 15 I/O 0 I/O 1 I/O 2 15 16 17 31 30 29 I/O 14 I/O 13 I/O 12 I/O 9 I/O 10 I/O 11 I/O 8 GND 1 SDO/IN 1 I/O 7 I/O 6 I/O 4 I/O 5 I/O 3 18 19 20 21 22 23 24 25 26 27 28 1. Pins have dual function capability. 0123A-isp1016 I/O 21 I/O 20 I/O 19 I/O 22 GND I/O 23 IN 3 I/O 24 I/O 26 I/O 25 I/O 27 ispLSI 1016 44-Pin TQFP Pinout Diagram 44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 1 2 3 4 5 33 I/O 18 32 31 I/O 17 I/O 16 30 IN2/MODE1 29 28 27 Y1/RESET VCC Y2/SCLK1 8 26 I/O 15 9 10 11 25 24 23 I/O 14 I/O 13 I/O 12 ispLSI 1016 6 Top View 7 I/O 9 I/O 10 I/O 11 I/O 8 GND 1 SDO/IN 1 I/O 7 I/O 6 I/O 4 I/O 5 I/O 3 12 13 14 15 16 17 18 19 20 21 22 1. Pins have dual function capability. 0851-16/TQFP 14 Specifications ispLSI 1016 Pin Configuration I/O 28 I/O 29 I/O 21 I/O 20 I/O 19 I/O 22 I/O 24 I/O 23 I/O 26 I/O 25 6 5 4 3 2 1 44 43 42 41 40 IN 3 GND I/O 27 ispLSI 1016 44-Pin JLCC Pinout Diagram 7 39 8 38 37 36 9 I/O 31 10 I/O 16 A D LL IS C DE O N VIC TI N ES U ED I/O 30 I/O 18 I/O 17 Y0 VCC ispEN 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 11 12 13 ispLSI 1016/883 Top View 35 34 33 32 31 14 15 16 17 IN 2/MODE1 Y1/RESET VCC Y2/SCLK1 I/O 15 30 I/O 14 I/O 13 29 I/O 12 1. Pins have dual function capability. 15 I/O 9 I/O 10 I/O 11 I/O 8 1 SDO/IN 1 I/O 7 GND I/O 6 I/O 4 I/O 5 I/O 3 18 19 20 21 22 23 24 25 26 27 28 0123-16-isp/JLCC Specifications ispLSI 1016 Part Number Description ispLSI 1016 —XXX X XXX X Device Family ispLSI Grade Blank = Commercial I = Industrial /883 = 883 Military Process Device Number Speed 110 = 110 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax A D LL IS C DE O N VIC TI N ES U ED Package J = PLCC T44 = TQFP H = JLCC Power L = Low 0212-80B-isp1016 Ordering Information COMMERCIAL Family fmax (MHz) tpd (ns) Ordering Number Package 110 10 ispLSI 1016-110LJ 44-Pin PLCC 90 12 ispLSI 1016-90LJ 44-Pin PLCC 90 12 ispLSI 1016-90LT44 44-Pin TQFP 80 15 ispLSI 1016-80LJ 44-Pin PLCC 80 15 ispLSI 1016-80LT44 44-Pin TQFP 60 20 ispLSI 1016-60LJ 44-Pin PLCC 60 20 ispLSI 1016-60LT44 44-Pin TQFP ispLSI INDUSTRIAL Family fmax (MHz) tpd (ns) Ordering Number Package 60 20 ispLSI 1016-60LJI 44-Pin PLCC 60 20 ispLSI 1016-60LT44I 44-Pin TQFP ispLSI MILITARY/883 Family fmax (MHz) tpd (ns) Ordering Number SMD # Package ispLSI 60 20 ispLSI 1016-60LH/883 5962-9476201MXC 44-Pin JLCC Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. 16 Table 2-0041-16-isp1016