Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z GAL22LV10ZD Low Voltage, Zero Power E2CMOS PLD Features Functional Block Diagram • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — Interfaces with Standard 5V TTL Devices — 50µA Typical Standby Current (100µA Max.) — 40mA Typical Active Current (55mA Max.) — Input Transition Detection on GAL22LV10Z — Dedicated Power-down Pin on GAL22LV10ZD RESET I/CLK 8 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q I 10 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 71.4MHz — UltraMOS® Advanced CMOS Technology I 12 • COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices PROGRAMMABLE AND-ARRAY (132X44) I/DPP* I • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention I I I • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs 14 16 16 14 I • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability 12 I • APPLICATIONS INCLUDE: — Battery Powered Systems — DMA Control — State Machine Control 10 I 8 • ELECTRONIC SIGNATURE FOR IDENTIFICATION I PRESET *GAL22LV10ZD Only Description Pin Configuration The GAL22LV10Z and GAL22LV10ZD, at 15ns maximum propagation delay time and 100µA standby current, combine 3.3V CMOS process technology with Electrically Erasable (E2) floating gate technology to provide the best PLD solution to support today's new 3.3V systems. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. 4 The generic 22V10 architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22LV10Z uses Input Transition Detection (ITD) to put the device into standby mode and is fully function/fuse map/ parametric compatible with standard bipolar and CMOS 22V10 devices. The GAL22LV10ZD utilizes a Dedicated Power-down Pin (DPP) to put the device into standby mode. I/DPP Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor is able to deliver 100% field programmability and functionality of all GAL® products. In addition,100 erase/rewrite cycles and data retention in excess of 20 years are specified. I 2 I/O/Q 28 I/O/Q Vcc I/CLK NC I I PLCC 26 5 25 7 GAL22LV10Z GAL22LV10ZD 23 9 Top View 21 I I I/O/Q NC I I/O/Q I/O/Q NC I I/O/Q I/O/Q 11 I/O/Q I I/O/Q 16 NC GND 14 I I 12 19 18 I/O/Q Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 22lv10zd_02 1 July 1997 Specifications GAL22LV10Z GAL22LV10ZD GAL22LV10Z: Commercial Grade Specifications Tpd (ns) Tsu1 (ns) Tco (ns) Icc (mA) Isb (µA) 15 10 10 55 100 GAL22LV10Z-15QJ 28-Lead PLCC 25 15 15 55 10 0 GAL22LV10Z-25QJ 28-Lead PLCC Ordering # Package GAL22LV10ZD: Commercial Grade Specifications Tpd (ns) Tsu1 (ns) Tco (ns) Icc (mA) Isb (µA) 15 10 10 55 100 GAL22LV10ZD-15QJ 28-Lead PLCC 25 15 15 55 10 0 GAL22LV10ZD-25QJ 28-Lead PLCC Ordering # Package Part Number Description XXXXXXXX _ XX Device Name GAL22LV10Z (Zero Power ITD) GAL22LV10ZD (Zero Power DPP) X X X Grade Blank = Commercial Package J = PLCC Speed (ns) Active Power Q = Quarter Power 2 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z and GAL22LV10ZD Ordering Information Specifications GAL22LV10Z GAL22LV10ZD The GAL22LV10Z and GAL22LV10ZD have a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The GAL22LV10Z and GAL22LV10ZD have a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. A R D 4 TO 1 MUX Q CLK Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Output Logic Macrocell (OLMC) Q SP 2 TO 1 MUX GAL22LV10Z AND GAL22LV10ZD OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations NOTE: In registered mode, the feedback is from the Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. Each of the Macrocells of the GAL22LV10Z and GAL22LV10ZD have two primary functional I/O modes: registered, and combinatorial. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. 3 Specifications GAL22LV10Z GAL22LV10ZD AR AR Q D CLK Q D Q CLK SP Q SP ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 0 S0 = 1 S1 = 0 Combinatorial Mode ACTIVE LOW ACTIVE HIGH S0 = 0 S1 = 1 S0 = 1 S1 = 1 4 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Registered Mode Specifications GAL22LV10Z GAL22LV10ZD PLCC Package 2 0 4 8 12 16 20 24 28 32 36 40 ASYNCHRONOUS RESET (TO ALL REGISTERS) 0000 0044 . . . 0396 8 S0 5808 S1 5809 0440 . . . . 0880 10 OLMC S0 5810 S1 5811 3 0924 . . . . . 1452 12 OLMC 27 26 25 S0 5812 S1 5813 4 1496 . . . . . . 2112 * OLMC 14 OLMC 24 S0 5814 S1 5815 5 2156 . . . . . . . 2860 16 OLMC 23 S0 5816 S1 5817 6 2904 . . . . . . . 3608 16 OLMC 21 S0 5818 S1 5819 7 3652 . . . . . . 4268 14 OLMC 20 S0 5820 S1 5821 9 4312 . . . . . 4840 12 OLMC 19 S0 5822 S1 5823 10 4884 . . . . 5324 10 OLMC S0 5824 S1 5825 11 5368 . . . 5720 8 OLMC S0 5826 S1 5827 12 SYNCHRONOUS PRESET (TO ALL REGISTERS) 5764 13 5828, 5829 ... Electronic Signature ... 5890, 5891 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B L S B * Note: Input not available on GAL22LV10ZD 5 18 17 16 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z and GAL22LV10ZD Logic Diagram/JEDEC Fuse Map Specifications GAL22LV10Z GAL22LV10ZD Recommended Operating Conditions Supply voltage VCC .................................... -0.5 to +5.6V Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V Input voltage applied ................................. -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +5.6V Storage Temperature ................................. -65 to 150°C Ambient Temperature with Power Applied ......................................... -55 to 125°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IOS1 MIN. TYP.2 MAX. UNITS Input Low Voltage Vss – 0.5 — 0.8 V Input High Voltage 2.0 — 5.25 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX.) — — -10 µA Input or I/O High Leakage Current (VCC − 0.2)V ≤ VIN ≤ VCC — — 10 µA VCC ≤ VIN ≤ 5.25V — — 1 mA IOL = MAX. Vin = VIL or VIH — — 0.5 V IOL = 0.5 mA Vin = VIL or VIH — — 0.2 V IOH = MAX. Vin = VIL or VIH 2.4 — — V IOH = -0.5 mA Vin = VIL or VIH Vcc-0.45 — — V IOH = -100 µA Vin = VIL or VIH Vcc-0.2 — — V Low Level Output Current — — 8 mA High Level Output Current — — -8 mA -30 — -130 mA Output Low Voltage Output High Voltage Output Short Circuit Current COMMERCIAL ISB Stand-by Power VCC = 3.3V VIL = GND VIH = Vcc Outputs Open Z -15/-25 ZD -15/-25 — 50 100 µA VIL = GND VIH = 3.0V ftoggle = 5 MHz Outputs Open Z -15/-25 ZD -15/-25 — 40 55 mA Supply Current ICC Operating Power Supply Current VOUT = 0.5V TA = 25°C 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and TA = 25 °C 6 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Absolute Maximum Ratings(1) Specifications GAL22LV10Z SpecificationsGAL22LV10ZD GAL22LV10Z Over Recommended Operating Conditions PARAM tpd tco tcf2 tsu1 tsu2 th fmax3 twh twl ten tdis tar tarw tarr tspr tas tsa4 TEST COND.1 COM COM -15 -25 DESCRIPTION MIN. MAX. MIN. MAX. UNITS A Input or I/O to Combinatorial Output 3 15 3 25 ns A Clock to Output Delay 2 10 2 15 ns — Clock to Feedback Delay — 10 — 10 ns — Setup Time, Input or Fdbk before Clk↑ 10 — 15 — ns — Setup Time, SP before Clk↑ 14 — 20 — ns — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 50 — 33.3 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 50 — 40 — MHz A Maximum Clock Frequency with No Feedback 71.4 — 50 — MHz — Clock Pulse Duration, High 6 — 10 — ns — Clock Pulse Duration, Low 6 — 10 — ns B Input or I/O to Output Enabled 3 15 3 25 ns C Input or I/O to Output Disabled 3 15 3 25 ns A Input or I/O to Asynch. Reset of Reg. 3 20 3 25 ns — Asynch. Reset Pulse Duration 15 — 25 — ns — Asynch. Reset to Clk↑ Recovery Time 10 — 25 — ns — Synch. Preset to Clk↑ Recovery Time 10 — 15 — ns A Last Active Input to Standby 100 250 100 250 ns A Standby to Active Output — 15 — 20 ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. 4) Add tsa to tpd, tsu, tar, ten and tdis when the device is transitioning from standby state to active state. Standby Power Timing Waveforms Icc POWER Isb t as t sa t pd, ten, tdis INPUT or I/O FEEDBACK t su CLK t co OUTPUT 7 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm AC Switching Characteristics Specifications GAL22LV10Z Specifications GAL22LV10ZD GAL22LV10ZD Over Recommended Operating Conditions PARAM tpd tco tcf2 tsu1 tsu2 th fmax3 twh twl ten tdis tar tarw tarr tspr TEST COND.1 COM COM -15 -25 DESCRIPTION MIN. MAX. MIN. MAX. UNITS A Input or I/O to Combinatorial Output 3 15 3 25 ns A Clock to Output Delay 2 10 2 15 ns — Clock to Feedback Delay — 10 — 10 ns — Setup Time, Input or Fdbk before Clk↑ 10 — 15 — ns — Setup Time, SP before Clk↑ 14 — 20 — ns — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — ns A Maximum Clock Frequency with External Feedback, 1/(tsu + tco) 50 — 33.3 — MHz A Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) 50 — 40 — MHz A Maximum Clock Frequency with No Feedback 71.4 — 50 — MHz — Clock Pulse Duration, High 6 — 10 — ns — Clock Pulse Duration, Low 6 — 10 — ns B Input or I/O to Output Enabled 3 15 3 25 ns C Input or I/O to Output Disabled 3 15 3 25 ns A Input or I/O to Asynch. Reset of Reg. 3 20 3 25 ns — Asynch. Reset Pulse Duration 15 — 25 — ns — Asynch. Reset to Clk↑ Recovery Time 10 — 25 — ns — Synch. Preset to Clk↑ Recovery Time 10 — 15 — ns 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. 8 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm AC Switching Characteristics Specifications GAL22LV10Z Specifications GAL22LV10ZD GAL22LV10ZD Over Recommended Operating Conditions PARAMETER twhd twld TEST COND1. COM COM -15 -25 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — DPP Pulse Duration High 40 — 40 — ns — DPP Pulse Duration Low 30 — 40 — ns — Valid Input before DPP High 0 — 0 — ns — Valid Clock Before DPP High 0 — 0 — ns — Input Don't Care after DPP High — 15 — 25 ns — Clock Don't Care after DPP High — 15 — 25 ns — Input Don't Care before DPP Low — 0 — 0 ns — Clock Don't Care before DPP Low — 0 — 0 ns — DPP Low to Valid Input or I/O 20 — 25 — ns — DPP Low to Valid Clock 30 — 35 — ns A DPP Low to Valid Output 5 35 5 45 ns ACTIVE TO STANDBY tivdh tcvdh tdhix tdhcx STANDBY TO ACTIVE tixdl tcxdl tdliv tdlcv tdlov 1) Refer to Switching Test Conditions section. Dedicated Power-Down Pin Timing Waveforms DPP tivdh tdhix tixdl tdliv tdhcx tcxdl tdlcv INPUT or I/O FEEDBACK tcvdh CLK tco tpd, ten, tdis OUTPUT 9 tdlov Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Dedicated Power-Down Pin (DPP) Specifications Specifications GAL22LV10Z GAL22LV10ZD INPUT or I/O FEEDBACK INPUT or I/O FEEDBACK VALID INPUT VALID INPUT ts u th t pd CLK COMBINATORIAL OUTPUT tc o REGISTERED OUTPUT Combinatorial Output 1 / fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK t dis t en CLK OUTPUT 1 / fm ax (int ern al fd bk ) t su tc f REGISTERED FEEDBACK Input or I/O to Output Enable/Disable fmax with Feedback tw l tw h CLK 1 / fm a x INPUT or I/O FEEDBACK DRIVING SP (w/o fdbk) Clock Width INPUT or I/O FEEDB ACK DRIVI NG AR tsu th tspr CLK tco tarw REGISTERED OUTPUT CLK tarr Synchronous Preset R E G I S T ER E D OUTPUT tar Asynchronous Reset Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CI Input Capacitance 8 pF VCC = 3.3V, VI = 0V CI/O I/O Capacitance 8 pF VCC = 3.3V, VI/O = 0V 10 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Switching Waveforms Specifications GAL22LV10Z GAL22LV10ZD CLK CLK LOGIC ARRAY REGISTER LOGIC ARRAY REGISTER tsu tco fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. t cf t pd CLK LOGIC ARRAY fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels +3.3V GND to 3.0V 2ns 10% – 90% 1.5V 1.5V Output Load R1 See Figure All 3-state levels are measured at (Voh - 0.5) V and (Vol + 0.5) V. FROM OUTPUT (O/Q) UNDER TEST TEST POINT Output Load Conditions (see figure) R1 R2 CL 270Ω 220Ω 35pF 270Ω 220Ω 35pF Active Low 270Ω 220Ω 35pF Active High 270Ω 220Ω 5pF Active Low 270Ω 220Ω 5pF Test Condition A B C Active High R2 C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 11 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm fmax Descriptions Specifications GAL22LV10Z GAL22LV10ZD Output Register Preload An electronic signature (ES) is provided in every GAL22LV10Z and GAL22LV10ZD device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Electronic Signature When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The electronic signature is an additional feature not present in other manufacturers’ 22V10 devices. To use the extra feature of the userprogrammable electronic signature it is necessary to choose a Lattice Semiconductor 22LV10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically a GAL22LV10 and a GAL22LV10-UES (UES = User Electronic Signature). This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. GAL22LV10Z and GAL22LV10ZD devices include circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. The JEDEC map for the GAL22LV10Z and GAL22LV10ZD contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, GAL22LV10Z and GAL22LV10ZD devices can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer. Input Buffers GAL22LV10Z and GAL22LV10ZD devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. Security Cell Input Transition Detection (ITD) A security cell is provided in every GAL22LV10Z and GAL22LV10ZD device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. The GAL22LV10Z relies on its internal input transition detection circuitry to put the device into power down mode. If there is no input transition for the specified period of time, the device will go into the power down state. Transition detection on any input or I/O will put the device back into the active state. Any input pulse widths greater than 5ns at an input transition voltage level of 1.5V will be detected as an input transition. The device will not detect input pulse widths less than 1ns measured at an input transition voltage level of 1.5V as an input transition. Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Dedicated Power-Down Pin The GAL22LV10ZD uses pin 5 as the dedicated power-down signal to put the device into the standby state. DPP is an active high signal. A logic high driven onto this signal puts the device into the standby state. Input pin 5 cannot be used as a logic function input on this device. 12 Specifications GAL22LV10Z GAL22LV10ZD Vcc (min.) Vcc t su t wl CLK t pr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" Circuitry within the GAL22LV10Z and GAL22LV10ZD provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 10µs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid powerup reset of the device. First, the VCC rise must be monotonic. Second, the clock input must be at a static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN PIN Feedback Vcc Vcc Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm Power-Up Reset Tri-State Control Vcc Vcc ESD Protection Circuit Data Output PIN ESD Protection Circuit PIN Feedback (To Input Buffer) Typical Input Typical Output 13 Specifications GAL22LV10Z GAL22LV10ZD Normalized Tpd vs Vcc Normalized Tco vs Vcc 1.2 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 RISE 1.1 FALL 1 0.9 0.8 3.00 3.60 PT L->H 1 0.9 0.8 3.15 3.30 3.45 3.60 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp PT H->L PT L->H 1.2 1 0.8 0.6 1.6 RISE 1.4 Normalized Tsu 1.4 Normalized Tco 1.6 FALL 1.2 1 0.8 0.6 25 50 75 100 125 -55 -25 Temperature (deg. C) 0 25 50 75 100 Delta Tpd vs # of Outputs Switching PT L->H 1.2 1 0.8 0.6 -55 125 -25 0 0 -0.2 -0.4 RISE -0.6 FALL -0.8 -0.2 -0.4 RISE -0.6 FALL -0.8 1 2 3 4 5 6 7 8 9 10 1 Number of Outputs Switching 2 3 4 5 6 7 8 9 10 Number of Outputs Switching Delta Tpd vs Output Loading Delta Tco vs Output Loading 14 14 12 12 10 10 8 6 4 RISE 2 0 -2 FALL 8 6 4 RISE 2 0 FALL -2 -4 -4 0 50 100 150 200 250 300 0 50 100 150 200 250 Output Loading (pF) Output Loading (pF) 14 25 50 75 100 Temperature (deg. C) Delta Tco vs # of Outputs Switching 0 Delta Tpd (ns) PT H->L 1.4 Temperature (deg. C) Delta Tco (ns) 0 Delta Tco (ns) -25 Delta Tpd (ns) -55 PT H->L 1.1 Supply Voltage (V) 1.6 Normalized Tpd 1.2 Normalized Tsu PT H->L Normalized Tco Normalized Tpd 1.2 Normalized Tsu vs Vcc 300 125 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z/ZD: Typical AC and DC Characteristic Diagrams Specifications GAL22LV10Z GAL22LV10ZD Vol vs Iol Voh vs Ioh Voh vs Ioh 3 0.8 3.00 2.5 2.97 0.4 2 Voh (V) Voh (V) Vol (V) 0.6 1.5 1 2.94 2.91 0.2 2.88 0.5 0 0 0.00 10.00 20.00 30.00 10.00 20.00 30.00 40.00 Iol (mA) Ioh (mA) Normalized Icc vs Vcc Normalized Icc vs Temp 0.00 1 0.9 0.8 3.15 3.3 3.45 3.6 1.1 1 0.9 4.00 1.8 1.4 1.0 0.6 -55 -25 0 25 50 75 100 Supply Voltage (V) Temperature (deg. C) Delta Icc vs Vin (1 input) Input Clamp (Vik) 4 3.00 2.2 0.8 3 2.00 Normalized Icc vs Freq. Normalized Icc 1.1 1.00 Ioh (mA) 1.2 Normalized Icc 1.2 Normalized Icc 2.85 0.00 40.00 125 0 20 40 60 80 100 Frequency (MHz) Normalized Icc vs Freq. (ITD) 0 2 1 Normalized Icc Iik (mA) Delta Icc (mA) 1 40 3 80 120 160 0 0 0.5 1 1.5 2 Vin (V) 2.5 3 3.5 200 -1.20 0.8 0.6 0.4 0.2 0 -1.00 -0.80 -0.60 -0.40 Vik (V) 15 -0.20 0.00 1 10 100 1000 Frequency (KHz) 10000 Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z/ZD: Typical AC and DC Characteristic Diagrams Notes Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm 16