R1LV0408D Series 4M SRAM (512-kword × 8-bit) REJ03C0310-0100 Rev.1.00 May.24.2007 Description The R1LV0408D is a 4-Mbit static RAM organized 512-kword × 8-bit, fabricated by Renesas’s highperformance 0.15µm CMOS and TFT technologies. R1LV0408D Series has realized higher density, higher performance and low power consumption. The R1LV0408D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32pin TSOP II and 32-pin STSOP. Features • Single 3 V supply: 2.7 V to 3.6 V • Access time: 55/70 ns (max) • Power dissipation: Standby: 3 µW (typ) • Equal access and cycle times • Common data input and output. Three state output • Directly TTL compatible. All inputs and outputs • Battery backup operation. Rev.1.00, May.24.2007, page 1 of 12 R1LV0408D Series Ordering Information %: Type No. Access time R1LV0408DSP-5S% 55 ns R1LV0408DSP-7L% 70 ns R1LV0408DSB-5S% 55 ns R1LV0408DSB-7L% 70 ns R1LV0408DSA-5S% 55 ns R1LV0408DSA-7L% 70 ns Temperature version; see table below. % Temperature Range R 0 to +70°C I −40 to +85°C Rev.1.00, May.24.2007, page 2 of 12 Package 525-mil 32-pin plastic SOP (32P2M-A) 400-mil 32-pin plastic TSOP II (32P3Y-H) 8mm × 13.4mm STSOP (32P3K-B) R1LV0408D Series Pin Arrangement 32-pin SOP 32-pin TSOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin STSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 A11 A9 A8 A13 WE# A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 (Top view) Pin Description Pin name Function A0 to A18 Address input I/O0 to I/O7 Data input/output CS# (CS) Chip select OE# (OE) Output enable WE# (WE) Write enable VCC Power supply VSS Ground Rev.1.00, May.24.2007, page 3 of 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 R1LV0408D Series Block Diagram LSB MSB V CC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 V SS Row Decoder I/O0 • • • • • Memory Matrix 2,048 × 2,048 • • Column I/O Input Data Control • • Column Decoder I/O7 LSB A0 A1 A2 A3 A4 A5 A17 A18 MSB •• CS# WE# Timing Pulse Generator Read/Write Control OE# Rev.1.00, May.24.2007, page 4 of 12 R1LV0408D Series Operation Table WE# CS# OE# Mode VCC current I/O0 to I/O7 Ref. cycle × H × Not selected ISB, ISB1 High-Z H L H Output disable ICC High-Z H L L Read ICC Dout Read cycle L L H Write ICC Din Write cycle (1) L L L Write ICC Din Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value VCC −0.5 to +4.6 Terminal voltage on any pin relative to VSS VT −0.5* to VCC + 0.5* Power dissipation PT 0.7 Power supply voltage relative to VSS Operating temperature 1 Topr Unit V 2 V W °C R ver. 0 to +70 I ver. −40 to +85 −65 to +150 Storage temperature range Tstg Storage temperature range under bias Tbias °C °C R ver. 0 to +70 I ver. −40 to +85 Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +4.6 V. DC Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Ambient temperature range R ver. Symbol Min Typ Max Unit VCC 2.7 3.0 3.6 V VSS 0 0 0 V VIH 2.2 VCC + 0.3 V VIL −0.3* 0.6 V Ta 0 +70 °C −40 +85 I ver. Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, May.24.2007, page 5 of 12 1 R1LV0408D Series DC Characteristics Parameter Symbol Min Typ Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS# = VIH or OE# = VIH or WE# = VIL or VI/O = VSS to VCC Operating current ICC 10 mA CS# = VIL, Others = VIH/ VIL, II/O = 0 mA Average operating current ICC1 25 mA Min. cycle, duty = 100%, CS# = VIL, Others = VIH/VIL II/O = 0 mA ICC2 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS# ≤ 0.2 V, VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V ISB 0.1*1 0.3 mA CS# = VIH to +85°C ISB1 10 µA Vin ≥ 0 V, CS# ≥ VCC − 0.2 V to +70°C ISB1 8 µA Average values to +40°C ISB1 3 µA to +25°C ISB1 1* 2.5 µA to +85°C ISB1 20 µA to +70°C ISB1 16 µA to +40°C ISB1 10 µA ISB1 1* 10 µA VOL 0.4 V IOL = 2.1 mA VOL2 0.2 V IOL = 100 µA VOH 2.4 V IOH = −1.0 mA VOH2 VCC − 0.2 V IOH = −0.1 mA Standby current Standby −5S% current −7L% to +25°C Output low voltage Output high voltage Note: Max Unit 1 1 Test conditions 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.1.00, May.24.2007, page 6 of 12 Test conditions Note R1LV0408D Series AC Characteristics (Ta = 0 to +70°C / −40 to +85°C, VCC = 2.7 V to 3.6 V) Test Conditions • • • • Input pulse levels: VIL = 0.4 V, VIH = 2.4 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: 1 TTL Gate + CL (50 pF) (R1LV0408D-5S%) 1 TTL Gate + CL (100 pF) (R1LV0408D-7L%) (Including scope and jig) Note: Temperature range depends on R/I-version. Please see table on page 2. Read Cycle R1LV0408D -5S% Parameter -7L% Symbol Min Max Min Max Unit Read cycle time tRC 55 70 ns Address access time tAA 55 70 ns Chip select access time tCO 55 70 ns Output enable to output valid tOE 30 35 ns Chip select to output in low-Z tLZ 10 10 ns 2 Output enable to output in low-Z tOLZ 5 5 ns 2 Chip deselect to output in high-Z tHZ 0 20 0 25 ns 1, 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2 Output hold from address change tOH 10 10 ns Rev.1.00, May.24.2007, page 7 of 12 Notes R1LV0408D Series Write Cycle R1LV0408D -5S% Parameter -7L% Symbol Min Max Min Max Unit Notes Write cycle time tWC 55 70 ns Chip selection to end of write tCW 50 60 ns 4 5 Address setup time tAS 0 0 ns Address valid to end of write tAW 50 60 ns Write pulse width tWP 40 50 ns 3, 12 Write recovery time tWR 0 0 ns 6 Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2, 7 Data to write time overlap tDW 25 30 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2, 7 Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to the end of write. 5. tAS is measured from the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max Rev.1.00, May.24.2007, page 8 of 12 R1LV0408D Series Timing Waveform Read Timing Waveform (WE# = VIH) tRC Address Valid address tAA tCO CS# tLZ tHZ tOE tOLZ OE# tOHZ Dout High impedance Valid data tOH Rev.1.00, May.24.2007, page 9 of 12 R1LV0408D Series Write Timing Waveform (1) (OE# Clock) tWC Address Valid address tAW tWR OE# tCW CS# *8 tWP tAS WE# tOHZ Dout High impedance tDW Din Rev.1.00, May.24.2007, page 10 of 12 Valid data tDH R1LV0408D Series Write Timing Waveform (2) (OE# Low Fixed) tWC Address Valid address tCW tWR CS# *8 tAW tWP WE# tOH tAS tOW tWHZ *9 Dout High impedance tDW tDH *11 Din Rev.1.00, May.24.2007, page 11 of 12 Valid data *10 R1LV0408D Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C / −40 to +85°C) Parameter −5S% −7L% VDR 2 V ICCDR 10 µA VCC = 3.0 V, Vin ≥ 0 V to +70°C ICCDR 8 µA CS# ≥ VCC − 0.2 V to +40°C ICCDR 3 µA Average values to +25°C ICCDR 1* 2.5 µA to +85°C ICCDR 20 µA to +70°C ICCDR 16 µA to +40°C ICCDR 10 µA ICCDR 1* 10 µA tCDR 0 ns tR 5 ms to +25°C Chip deselect to data retention time Operation recovery time Note: Test conditions to +85°C VCC for data retention Data retention current Symbol Min Typ Max Unit 1 1 CS# ≥ VCC − 0.2 V, Vin ≥ 0 V See retention waveform 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. Low VCC Data Retention Timing Waveform (CS# Controlled) tCDR Data retention mode VCC 2.7 V 2.2 V VDR CS# 0V Rev.1.00, May.24.2007, page 12 of 12 CS# ≥ VCC – 0.2 V tR Revision History Rev. Date 0.01 1.00 Dec. 25, 2006 May. 24, 2007 R1LV0408D Series Data Sheet Contents of Modification Description Page Initial issue 6 DC Characteristics ISB1 (-5S%) (to +25°C) max: 3 µA to 2.5 µA Low VCC Data Retention Characteristics 12 ICCDR (-5S%) (to +25°C) max: 3 µA to 2.5 µA Deletion of note 2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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