Teccor® brand Thyristors AN1009 Miscellaneous Design Tips and Facts Introduction dv/dt Definitions This application note presents design tips and facts on the following topics: The rate-of-rise of voltage (dv/dt) of an exponential waveform is 63% of peak voltage (excluding any overshoots) divided by the time at 63% minus 10% peak voltage. (Figure AN1009.2) • Relationship of IAV, IRMS, and IPK • dv/dt Definitions Exponential dv/dt = 0.63 • [VPK] = (t2 − t1) • Examples of gate terminations Resistor Capacitor circuit t = RC = (t2 − t1) • Curves for Average Current at Various Conduction Angles Resistor Capacitor circuit 4 • RC = (t3 − t2) • Double-exponential Impulse Waveform • Failure Modes of Thyristor (Peak Value) 100% Percent of Voltage • Characteristics Formulas for Phase Control Circuits Relationship of IAV, IRMS, and IPK Since a single rectifier or SCR passes current in one direction only, it conducts for only half of each cycle of an AC sinewave. The average current (IAV) then becomes half of the value determined for full-cycle conduction, and the RMS current (IRMS) is equal to the square root of half the mean-square value for full-cycle conduction or half the peak current (IPK). In terms of half-cycle sinewave conduction (as in a single-phase half-wave circuit), the relationships of the rectifier currents can be shown as follows: 63% Numerical dv/dt 10% 0% t0 Figure AN1009.2 IPK = π • IAV = 3.14 • IAV Time t2 t1 t3 Exponential dv/dt Waveform The rate-of-rise of voltage (dv/dt) of a linear waveform is 80% of peak voltage (excluding any overshoots) divided by the time at 90% minus 10% peak voltage. (Figure AN1009.3) IAV = (1/π) IPK = 0.32 • IPK IPK = 2 • IRMS IRMS = 0.5 • IPK Linear dv/dt = 0.8 = [VPK] = (t2 − t1) IAV = (2/π) IRMS = 0.64 • IRMS Linear dv/dt = [0.9 • VPK −0.1 • VPK] = (t2 − t1) IRMS = (π/2) IAV = 1.57 • IAV When two identically rated SCRs are connected inverse parallel for full-wave operation, as shown in Figure AN1009.1, they can handle 1.41 times the RMS current rating of either single SCR. Therefore, the RMS value of two half sinewave current pulses in one cycle is √2 times the RMS value of one such pulse per cycle. Percent of Voltage 90% 10% 0% t0 t1 Figure AN1009.3 Figure AN1009.1 Time t2 Linear dv/dt Waveform SCR Anti-parallel Circuit Miscellaneous Design Tips and Facts 455 ©2013 Littelfuse, Inc Specifications are subject to change without notice. Revised: 09/23/13 Teccor® brand Thyristors AN1009 Curves for Average Current at Various Conduction Angles Examples of Gate Terminations SCR maximum average current curves for various conduction angles can be established using the factors for maximum average current at conduction angle of: Primary Purpose (1) Increase dv/dt capability (2) Keep gate clamped to ensure VDRM capability (3) Lower tq time 30º = 0.40 x Avg 180º 60º = 0.56 x Avg 180º Related Effect – Raises the device latching and holding current 90º = 0.70 x Avg 180º 120º = 0.84 x Avg 180º Primary Purpose The reason for different ratings is that the average current for conduction angles less than 180º is derated because of the higher RMS current connected with high peak currents. (1) Increase dv/dt capability (2) Remove high frequency noise Related Effects (1) (2) (3) (4) (5) Increases delay time Increases turn-on interval Lowers gate signal rise time Lowers di/dt capability Increases tq time Note that maximum allowable case temperature (TC) remains the same for each conduction angle curve but is established from average current rating at 180º conduction as given in the data sheet for any particular device type. The maximum TC curve is then derated down to the maximum junction (TJ). The curves illustrated in Figure AN1009.4 are derated to 125 ºC since the maximum TJ for the non-sensitive SCR series is 125 ºC. Primary Purpose (1) Decrease DC gate sensitivity (2) Decrease tq time Related Effects 125 Maximum Allowable Case Temperature (TC) – °C (1) Negative gate current increases holding current and causes gate area to drop out of conduction (2) In pulse gating gate signal tail may cause device to drop out of conduction Current: Halfwave Sinusoidal Load: Resistive or Inductive Conduction Angle: As Given Below Case Temperature: Measured as Shown on Dimensional Drawings 120 115 110 Primary Purpose – Select frequency 105 Related Effects – Unless circuit is “damped,” positive and negative gate current may inhibit conduction or bring about sporadic anode current 5.1 6 7.2 8 0° 4 18 2 60 ° 80 0° 12 90 ° 85 0 10.8 12.8 10 12 14 16 Average On-state Current [IT(AV)] – Amps Related Effects – Isolates the gate if high impedance signal source is used without sustained diode current in the negative cycle Figure AN1009.4 Primary Purpose – Decrease threshold sensitivity Typical Curves for Average On-state Current at Various Conduction Angles versus TC for a SXX20L SCR. Double-Exponential Impulse Waveform Related Effects A double-exponential impulse waveform or waveshape of current or voltage is designated by a combination of two numbers (tr/td or tr x td µs). The first number is an exponential rise time (tr) or wave front and the second number is an exponential decay time (td) or wave tail. The rise time (tr) is the maximum rise time permitted. The decay time (td) is the minimum time permitted. Both the tr and the td are in the same units of time, typically microseconds, designated at the end of the waveform description as defined by ANSI/IEEE C62.1-1989. (1) Affects gate signal rise time and di/dt rating (2) Isolates the gate Primary Purpose – Isolate gate circuit DC component Related Effects – In narrow gate pulses and low impedance sources, Igt followed by reverse gate signals which may inhibit conduction Miscellaneous Design Tips and Facts 90 ° (1) Supply reverse bias in off period (2) Protect gate and gate supply for reverse transients (3) Lower tq time 95 30 ° Primary Purpose Zener optional Conduction Angle 100 456 ©2013 Littelfuse, Inc Specifications are subject to change without notice. Revised: 09/23/13 Teccor® brand Thyristors AN1009 The rise time (tr) of a current waveform is 1.25 times the time for the current to increase from 10% to 90% of peak value. See Figure AN1009.5. Catastrophic Failures A catastrophic failure can occur whenever the Thyristor is operated beyond its published ratings. The most common failure mode is an electrical short between the main terminals, although a Triac can fail in a half-wave condition. It is possible, but not probable, that the resulting shortcircuit current could melt the internal parts of the device which could result in an open circuit. tr = Rise Time = 1.25 • [tc - ta] tr = 1.25 • [t(0.9 IPK) - t(0.1 IPK)] = T1 - T0 The rise time (tr) of a voltage waveform is 1.67 times the time for the voltage to increase from 30% to 90% of peak value. (Figure AN1009.5) Failure Causes tr = Rise Time = 1.67 • [tc - tb] Most Thyristor failures occur due to exceeding the maximum operating ratings of the device. Overvoltage or overcurrent operations are the most probable cause for failure. Overvoltage failures may be due to excessive voltage transients or may also occur if inadequate cooling allows the operating temperature to rise above the maximum allowable junction temperature. Overcurrent failures are generally caused by improper fusing or circuit protection, surge current from load initiation, load abuse, or load failure. Another common cause of device failure is incorrect handling procedures used in the manufacturing process. Mechanical damage in the form of excessive mounting torque and/or force applied to the terminals or leads can transmit stresses to the internal Thyristor chip and cause cracks in the chip which may not show up until the device is thermally cycled. tr = 1.67 • [t(0.9 VPK) - t(0.3 VPK)] = T1 - T0 The decay time (td) of a waveform is the time from virtual zero (10% of peak for current or 30% of peak for voltage) to the time at which one-half (50%) of the peak value is reached on the wave tail. (Figure AN1009.5) Current Waveform td = Decay Time = [t(0.5 IPK) - t(0.1 IPK)] = T2 - T0 Voltage Waveform td = Decay Time = [t(0.5 VPK) - t(0.3 VPK)] = T2 - T0 t Decay = e - 1.44 T2 Percent of Current or Voltage Virtual Start of Wavefront (Peak Value) 100% 90% Prevention of Failures Careful selection of the correct device for the application’s operating parameters and environment will go a long way toward extending the operating life of the Thyristor. Good design practice should also limit the maximum current through the main terminals to 75% of the device rating. Correct mounting and forming of the leads also help ensure against infant mortality and latent failures. The two best ways to ensure long life of a Thyristor is by proper heat sink methods and correct voltage rating selection for worst case conditions. Overheating, overvoltage, and surge currents are the main killers of semiconductors. 50% 30% 10% 0% T0 ta tb tc T1 T2 Time Figure AN1009.5 Double-exponential Impulse Waveform Failure Modes of Thyristor Most Common Thyristor Failure Mode Thyristor failures may be broadly classified as either degrading or catastrophic. A degrading type of failure is defined as a change in some characteristic which may or may not cause a catastrophic failure, but could show up as a latent failure. Catastrophic failure is when a device exhibits a sudden change in characteristic that renders it inoperable. To minimize degrading and catastrophic failures, devices must be operated within maximum ratings at all times. When a Thyristor is electrically or physically abused and fails either by degradation or a catastrophic means, it will short (full-wave or half-wave) as its normal failure mode. Rarely does it fail open circuit. The circuit designer should add line breaks, fuses, over-temperature interrupters or whatever is necessary to protect the end user and property if a shorted or partially shorted Thyristor offers a safety hazard. Degradation Failures A significant change of on-state, gate, or switching characteristics is quite rare. The most vulnerable characteristic is blocking voltage. This type of degradation increases with rising operating voltage and temperature levels. Miscellaneous Design Tips and Facts 457 ©2013 Littelfuse, Inc Specifications are subject to change without notice. Revised: 09/23/13 Teccor® brand Thyristors AN1009 Characteristics Formulas for Phase Control Circuits Max Thyristor Voltage Circuit Name PRV SCR Max. Load Voltage Ed =Avg. Ea=RMS Load Ed = Half-wave Resistive Load 1.4 ERMS EP Ea = Full-wave Bridge 1.4 ERMS EP Ed = Full-wave AC Switch Resistive Load 1.4 ERMS EP Ea = Max. Average Thyristor or Rectifier Current Load Voltage with Delayed Firing Avg. Amps Ep E d= π Ep 2 (1+ cos α) 1 Ea= (π - α+ sin2α ) 2 2 π Ed = π 1.4 2π Ep 2E p Ep Ep Ea= Ep 2 π (1+ cos α ) Ep 1 (π - α+ sin2α ) 2 2π Conduction Period Ep 180° πR Ep 180° πR Ep 180° πR NOTE: Angle alpha (α) is in radians. EP ERMS R 0 Load α Half-wave Resistive Load - Waveform Half-wave Resistive Load - Schematic L EP 0 Load E R α Full-wave Bridge - Schematic Full-wave Bridge - Waveform EP ERMS 0 R Load α Full-wave AC Switch Resistive Load - Waveform Full-wave AC Switch Resistive Load - Schematic Miscellaneous Design Tips and Facts 458 ©2013 Littelfuse, Inc Specifications are subject to change without notice. Revised: 09/23/13