New Product R2A20158NP 8-bit 8ch D/A Converter with Buffer Amplifiers for I2C BUS (Corresponds to Fast mode) R03DS0015EJ0100 Rev.1.00 2011.09.05 Description The R2A20158NP is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A converters with output buffer operational amplifiers. It is the electrical characteristic improvement version of the M62393. The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a microcomputer with minimum wiring. This IC corresponds to Fast mode of I2C BUS standard. The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0mA or more, and it operates in the whole voltage range from Vcc to ground. Maximum 8 ICs can be connected to a bus by using 3-chip select pins, so that it is possible to handle up to 64 channels analog data. Features Guarantee Differential nonlinearity error : +/-0.7LSB, Nonlinearity error : +/-1.0LSB Digital data transfer format: I2C BUS serial data method (corresponds to Fast mode: 400kHz) Output buffer operational amplifier It operates in the whole range from Vcc to ground. High output current drive capacity: 1mA over The very small size (4mmX4mm) QFN-20 package is added to the lineup. Application Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. Blurring correction control or various control of the interchangeable lens of digital camera Block Diagram CS0 CS1 CS2 18 17 VDD 16 15 Ao1 Ao2 Ao3 Ao4 13 12 11 10 VrefU2 9 Vcc 14 I2C BUS TRANCEIVER -+ -+ -+ 20 8 -+ Channel decoder Chip select 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R 8-bit upper segment R-2R +- +- +- +- 8 1 19 6 SCL SDA RESET VrefL R03DS0015EJ0100 Rev.1.00 2010.09.05 2 Ao5 3 4 5 7 8 Ao6 Ao7 Ao8 VrefU1 GND Page 1 of 8 New Product R2A20158NP Pin Arrangement Ao7 4 Ao8 5 16 CS2 18 CS0 17 CS1 13 Ao4 12 Ao3 11 Ao2 Ao1 10 3 14 Vcc VrefU2 9 Ao6 GND 8 2 VrefU1 7 Ao5 15 VDD VrefL 6 1 R2A20158NP SDA 19 RESET 20 SCL R2A20158NP (Top view) Outline: PWQN0020KB-A [NP] Pin Description Pin No. Pin Name Function 1 SDA 19 RESET 20 SCL 10 Ao1 11 Ao2 12 Ao3 13 Ao4 2 Ao5 3 Ao6 4 Ao7 5 Ao8 14 Vcc Analog power supply terminal 15 VDD Digital power supply terminal 8 GND Analog and digital common GND 6 VrefL D/A converter low level reference voltage input terminal 7 VrefU1 D/A converter high level reference voltage input terminal 1 (for ch5 to ch8) 9 VrefU2 D/A converter high level reference voltage input terminal 2 (for ch1 to ch4) 16 CS2 Chip select data input terminal 2 *1 17 CS1 Chip select data input terminal 1 *1 18 CS0 Chip select data input terminal 0 *1 Serial data input terminal Reset signal input terminal. A low state of RESET clear the all 8-bit latches. Serial clock input terminal 8-bit resolution D/A converter output terminal (After power on, analog output of every channel is set in DAC data “00h”) *1 : This IC can be accessed only when the slave address (A0 to A2) coincides with the chip select input (CS0 to CS2). R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 2 of 8 New Product R2A20158NP (Ta = 25 deg unless otherwise noted) Absolute Maximum Ratings Item Symbol Conditions Ratings Unit V Analog Supply voltage Vcc -0.3 to +6.5 Digital Supply voltage VDD -0.3 to < 6.5 V VrefU1, VrefU2 -0.3 to < 6.5 V VIN D -0.3 to VDD+0.3 6.5 V Upper reference voltage of D/A *1 Digital input voltage Buffer amplifier output current IAO Continuous -2.0 to +2.0 mA Power dissipation Pd Ta= +85deg 290 mW Thermal derating factor K theta Ta> +25deg 7.25 mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg *1 VDD VrefU1, VrefU2 Electrical Characteristics « Digital Part » (Vcc,VDD,VrefU1,V1refU2 = +5V +/-10%, Vcc VrefU1,VrefU2, GND=VrefL=0V, Ta=-30 to +85deg Item Symbol Supply voltage Supply current Input leak current Output low voltage (SDA) Input low voltage Input high voltage VDD IDD IILK VOL VIL VIH « Analog Part » Test conditions CLK = 500kHz operation, IAO =0 µA VIN = 0 to Vcc IOL = 3 mA unless otherwise noted) Limits Typ 5.0 - Min 2.7 -10 0.8VDD Max 5.5 1.0 10 0.4 0.2VDD - Unit V mA µA V V V (Vcc,VDD,VrefU1,V1refU2 = +5V +/-10%, Vcc VrefU1,VrefU2, GND=VrefL=0V, Ta=-30 to +85deg unless otherwise noted) Item Symbol Test conditions Limits Unit Min Typ Max 2.7 - 5.5 V Supply Voltage Vcc Supply current Icc CLK=500kHz operation, IAO = 0µA - 0.4 1.2 mA D-A converter high level reference voltage input current IrefU1, 2 VtefU = 5V, VrefL = 0V, Data condition: at maximum current for each terminal - 0.6 1.2 mA D-A converter high level reference voltage range *2 VrefU1, VrefU2 0.7Vcc - Vcc V D-A converter low level reference voltage range *2 VrefL GND - 0.3Vcc V Buffer amplifier output voltage range IAO = +/- 100 µA 0.1 - Vcc-0.1 V VAO IAO = +/- 500 µA 0.2 - Vcc-0.2 V Buffer amplifier output current range IAO Upper side saturation voltage = 0.3V, Lower side saturation voltage = 0.2V -1.0 - 1.0 mA Differential nonlinearity error SDL -0.7 - 0.7 LSB Nonlinearity error SL -1.0 - 1.0 LSB Zero code error SZERO -2.0 - 2.0 LSB Full scale error SFULL -2.0 - 2.0 LSB Output capacitative load Co - - 0.1 µF Buffer amplifier output impedance Rp - 5.0 - ohm VrefU1,VrefU2 = 4.79V, VrefL = 0.95V, Vcc = 5.5V (15mV/LSB), Without load (IAO = 0µA) *2 : The output does not necessary be the value with the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). VDD VrefU1, VrefU2 R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 3 of 8 New Product R2A20158NP I2C BUS Line Characteristics Item Symbol SCL clock frequency Free time: the bus must be free before a new transmission can start Hold time START condition after this period, the first clock pulse is generated Low period of the clock High period of the clock Set-up time for START condition. Only relevant for a repeated START condition. Data Hold time Data Set-up time Rise time of SDA and SCL signals FAST MODE Unit fSCL Min. 0 Max. 100 Min. 0 Max. 400 tBUF 4.7 - 1.3 - µs tHD:STA 4.0 - 0.6 - µs tLOW tHIGH 4.7 4.0 - 1.3 0.6 - µs µs tSU:STA 4.7 - 0.6 - µs tHD:DAT tSU:DAT tR 0 250 - 3.45 1000 0 100 - 0.9 300 µs ns ns tF - 300 - 300 ns tSU:STO Cb 4.0 - 400 0.6 - 400 µs pF Fall time of SDA and SCL signals Set-up time for STOP condition Capacitive load of bus line STANDARD MODE kHz All of above value are corresponds to VIHmin and VILmax. Timing Chart tR, tF tBUF VIH SDA VIL tHD:STA tSU:DAT tHD:DAT tsu:STA tSU:ST0 VIH SCL VIL tLOW Start R03DS0015EJ0100 Rev.1.00 2010.09.05 tHIGH Start Stop Start Page 4 of 8 New Product R2A20158NP I2C BUS Format STA Slave address W A Sub address A DAC data A STP Note: STA: start condition, A: acknowledge bit, W: write (SDA=Low), STP: stop condition Slave address First MSB 1 0 Sub address First MSB Last LSB 0 1 A2 (Slave address) A1 A0 X X Chip select data Last LSB X X S3 S2 S1 S0 Channel select data Don’t care DAC data First MSB D7 Last LSB D6 D5 D4 D3 D2 D1 D0 Chip select data Channel select data A2 A1 A0 CS2 CS1 CS0 S3 S2 S1 S0 Channel selection 0 0 0 L L L 0 0 1 L L H 0 1 0 L H L : : : : : : 1 1 1 H H H 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Don’t care ch1 selection ch2 selection ch3 selection ch4 selection ch5 selection ch6 selection ch7 selection ch8 selection Don’t care : : : : 1 1 1 1 (L=Low, H=High) Note: This IC can be accessed only when the lower 3 bits data of slave address (A0 to A2) coincide with the input data of CS0 to CS2. : Don’t care DAC data D7 D6 D5 D4 D3 D2 D1 D0 DAC output 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 (VrefU – VrefL) / 256 x 1 + VrefL (VrefU – VrefL) / 256 x 2 + VrefL (VrefU – VrefL) / 256 x 3 + VrefL (VrefU – VrefL) / 256 x 4 + VrefL : : : : : : : : : 1 1 1 1 1 1 1 0 (VrefU – VrefL) / 256 x 255 + VrefL 1 1 1 1 1 1 1 1 VrefU R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 5 of 8 New Product R2A20158NP Data Timing Chart SCL and SDA (Model) < Start condition to slave address bit > SDA 1 2 3 4 5 6 7 W A 2 3 4 5 6 7 8 A SCL D/A output Start condition < Sub address bit > SDA 1 SCL D/A output < DAC data bit to stop condition > SDA 1 2 3 4 5 6 7 8 A SCL D/A output Stop condition Start condition With SCL at High, SDA line goes from High to Low Stop condition With SCL at High, SDA line goes from Low to High ( Under normal circumstance, SDA is changed when SCL is Low ) Acknowledge bit The receiving IC has to pull down SDA line whenever receive slave data. ( The transmitting IC releases the SDA line just then transmit 8-bit data. ) R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 6 of 8 New Product R2A20158NP Digital Data Format STA Slave address Sub address 2 A W A DAC data 2 Sub address 1 A A Sub address n DAC data 1 A DAC data n A A STP After the Start condition, the transmitting IC accesses the slave IC by Slave address, and transmits the data to each channel by two bites (Sub address and DAC data). Precaution For use If ripple or spike is input to D/A converter upper reference voltage terminal (VrefU1,2), accuracy of D/A converter is down, So, when use this device, please connect capacitor among Vcc to GND for stable D/A conversion. This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when connect capacitor ( 0.1 µF Max ) among output to GND for every noise elimination. Application Example + + 10µF + 15 14 VDD Vcc 10µF 7 VrefU1 Ao1 10 10µF + 9 VrefU2 Ao2 11 10µF Ao3 12 Chip select data R2A20158NP 18 CS0 17 CS1 16 CS2 RESET signal 19 RESET Ao4 13 Analog output terminals Ao5 2 Ao6 3 Ao7 4 MCU 1 SDA 20 SCL Ao8 5 GND VrefL 8 6 + 10µF R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 7 of 8 New Product R2A20158NP Package Dimensions PWQN0020KB-A [NP] Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20158NP QFN-20 PWQN0020KB-A NP Embossed Taping/2,500 pcs. R03DS0015EJ0100 Rev.1.00 2010.09.05 Page 8 of 8 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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