DS1481 www.maxim-ic.com 2 O1/BSY1 3 es i ENI 14 I/O 13 ENO 12 I1 O2/BSY2 4 11 I2 D/CLK 5 10 NC RES 6 9 NC NC 7 8 GND 14-PIN SO (150 MIL) PIN DESCRIPTION VCC ENI D/CLK RES O1/BSY1 O2/BSY2 GND I1 I2 I/O ENO NC - Supply Enable In Data/Clock Reset Output 1/Busy 1 Output 2/Busy 2 Ground Input 1 Input 2 1-Wire Enable Out No connection ec om m en de d 1 D Vcc rN Provides a synchronous interface to Dallas Semiconductor 1-Wire devices Compatible with low power parallel ports (can be used with microcontrollers) Can be cascaded with other DS1481s Allows print spooler and other processes to run during 1-Wire I/O Provides high speed communication with overdrive capable devices Space saving 14-pin (150 mil), SO package Recommended for short 1-Wire networks less than 3 inches. Longer 1-Wire lengths can be achieved with the DS2480B. fo PIN CONFIGURATION ew FEATURES gn 1-Wire Bus Master with Overdrive DESCRIPTION ot R The DS1481 is a dedicated 1-Wire® timing generator. The device is normally used in conjunction with a parallel port controller to provide the necessary interface to the host processor. Busy signals allow the host processor to perform other tasks while 1-Wire “time-slots” are completed. The DS1481 also saves the state of D/CLK and RES, allowing print spoolers to operate without affecting 1-Wire communication. N DS1481 based devices can be cascaded. The first device’s O1/BSY1 and O2/BSY2 connect to the PC printer port’s BUSY and SELECT OUT signals (pins 11 and 13 respectively). The next DS1481 connects its O1/BSY1 and O2/BSY2 to the first device’s I1 and I2 respectively. ENO of the first device connects to ENI of the second device. More DS1481s can be stacked in a similar manner. The last device’s I1 and I2 connect to BUSY and SELECT of the attached printer. 1-Wire is a registered trademark of Dallas Semiconductor. 1 of 10 061907 DS1481 The DS1481’s 3V operation insures compatibility with most low power parallel ports (i.e., portable computers). DEVICE OPERATION RES logic low logic low (see Figure 7) Read 0, Read 1, Write 1 logic high logic high (see Figure 4) Write 0 logic low logic high (see Figure 5) 1-Wire Reset logic high logic low (see Figure 6) ew Toggle Speed es i D/CLK D TIME SLOT gn 1-Wire communication is executed in “time slots”. The DS1481 generates either a read/write bit “time slot” or a reset on the I/O pin. The operation performed is determined by the states of the D/CLK and RES pins as follows: fo rN After D/CLK and RES have been set, the time slot begins when ENI is driven to its active state. A falling edge on ENI causes the DS1481 to save the state of D/CLK and RES. If the time slot is a 1-Wire reset the DS1481 will issue a busy signal by driving O1/BSY1 low and O2/BSY2 high. After 2μs O2/BSY2 is driven low. Both outputs will remain low until the communication on the I/O line is finished. A busy signal for a bit time slot differs from the reset busy signal only in that both O1/BSY1 and O2/BSY2 are driven low immediately. de d While the busy signal is asserted, the host processor is free to perform other tasks (including running the print spooler). When the time slot is complete, the DS1481 restores both O1/BSY1 and O2/BSY2 to the states of I1 and I2 (see Figure 1). om m en When the host detects that one or both of the busy signals has returned high, it must query the result of the time slot. This is accomplished by driving D/CLK low. If the result of the time slot was low (Read 0, Write 0 or presence detect) the DS1481 drives both O1/BSY1 and O2/BSY2 low (this state is held until ENI returns high). Otherwise it propagates the states of I1 and I2. After the host reads the result of the time slot it must drive ENI to its inactive state (high). The DS1481 will then set O1/BSY1 and O2/BSY2 to the states of I1 and 1-WIRE TIMING GENERATION ec For all time slots, the DS1481 samples the I/O pin at tSO (see Figure 4). The DS1481 waits a minimun of 60μs from the start of the time slot and de-asserts O1/BSY1 and O2/BSY2. R When a reset is requested, the DS1481 drives the I/O pin low for at least 480μs and then releases it. During a normal reset the I/O pin immediately begins to return high. N ot If a 1-Wire device is present on the I/O line it pulls I/O low after time T (15μs ≤ T ≤ 60μs) from the previous rising edge. The 1-Wire device(s) holds the I/O line low for 4T and then releases it, allowing the I/O line to return high. This is the presence detect pulse. The I/O line must remain high (in its idle state) for at least 3T before the 1-Wire device(s) is ready for further communication. To ensure this idle high time is satisfied, the DS1481 does not release O1/BSY1 and O2/BSY2 for at least 960μs (measured from the 1st falling edge on the I/O pin). 2 of 10 DS1481 gn If after 480μs of low time the I/O line did not return high, either the I/O line has been shorted to ground or there is at least one 1-Wire device connected to the I/O line which is issuing an alarm interrupt (see Figure 6). In this case the DS1481 waits for I/O to return high for an additional 3840μs (64 * 60). If time expires the I/O line is assumed to be shorted and the DS1481 releases O1/BSY1 and O2/BSY2. If the I/O line returns high, the DS1481 continues to monitor the presence detect portion of the reset (as described above) as for the non-interrupt case. Note that the 3T idle high time is still required after the presence detect ends. OVERDRIVE ew D es i The DS1481 also supports overdrive communication with overdrive capable 1-Wire devices. When the DS1481 powers up it is in normal mode (i.e., OD = 0, Figure 1). To toggle to overdrive mode the host sets D/CLK and RES low and drives ENI low. The DS1481 toggles the OD bit to a logic high and returns the states of I1 and I2 on O1/BSY1 and O2/BSY2. Overdrive mode is cleared in the same way. When overdrive is turned off (OD = 0). O1/BSY1 and O2/BSY2 are driven low to report the state of the OD bit. When OD = 1, communication with the 1-Wire device is exactly as described in the operation section above. The actual 1-Wire timing for both modes of operation is described in Figures 4, 5, and 6. rN Note that when toggling the OD bit there is no change on the I/O line. PRINTER COEXISTENCE d fo In order to coexist with parallel port printers, the DS1481 utilizes two input pins (I1 and I2) and two output pins (O1/BSY1 and O2/BSY2). When ENI is low these pins are used for transmitting data received on the I/O pin or for issuing an unmistakable busy signal. When ENI is inactive (high) O1/BSY1 and O2/BSY2 propagate the states of I1 and I2. de If a printer is attached to a DS1481, I1 is connected to the printers BUSY signal (low only if printer is on line and busy), and I2 is connected to SELECT OUT (driven low if printer is off line), see Figure 2. om m en If the attached printer is “powered up” and on line, the DS1481 uses SELECT OUT for communication regardless of the state of the printer’s BUSY signal. If the printer is off line its BUSY signal is inactive (high) and this line is used by the DS1481 for host communication. If the attached printer is powered off, both SELECT OUT and BUSY will be low. This prevents meaningful communication with the DS1481 because it is unable to de-assert its busy signal (O1/BSY1 and O2/BSY2 low) or return a high sample of the I/O pin. R ec To solve this problem, the DS1481 uses the busy signal issued during a reset to detect the presence of another DS1481 based device attached behind it on the parallel port. If this busy signal is not detected by the DS1481, it assumes that it is the last DS1481 based device on the port. N ot If the DS1481 determines that it is the last device on the port it ignores the states of its I1 and I2 pins while ENI is low. It also leaves the ENO pin high to prevent sending line feed signals to the printer. This gives the last device the ability to control O1/BSY1 and O2/BSY2 without affecting stackability. 3 of 10 DS1481 EPP/ECP TRANSPARENT MODE When the DS1481 first powers up it is in a transparent mode in which the three signal lines (auto line feed, busy and select) that pass through the part are directly connected by transmission gates. This allows bi-directional printers (or other parallel port peripherals) to communicate in either the EPP or ECP mode of the PC parallel port. The DS1481 pin sets connected are as follows: gn ENO I1 I2 es i ENI O1/BSY1 O2/BSY2 ew D 1-Wire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the ENI pin remains high for at least 10ms the part will enter its normal mode of operation. Note that any other 1-Wire time slot command issued during the sequence resets the sequence. The steps needed to return to transparent mode are as described above with the exception that no additional wait is required at the end of the four overdrive toggles to enter transparent mode. rN While in transparent mode if the DS1481 detects that the ENO pin has been held low for more than 10ms it turns off the transmission gate connecting ENI and ENO. This guarantees the host will have the ability to take the DS1481 out of transparent mode and perform 1-Wire I/O operations. d fo Figure 1. DS1481 FUNCTIONAL BLOCK DIAGRAM 50K ENO en de ENI 50K 50K D/CLK D om m LAST PART DETECTION RES Q ec CLK Q 1-WIRE BUS MASTER I/O 50K R D CLK Q Q OD 50K O1/BSY1 ot I1 N O2/BSY2 50K I2 4 of 10 DS1481 Figure 2. CONNECTION TO PC TYPE PARALLEL PORTS +5 ENI O1/BSY1 O2/BSY2 D/CLK RES NC DS9100 P14 P11 P13 gn Auto Feed Busy Select Data 1 Data 2 P14 P11 P13 P2 P3 I/O ENO I1 I2 NC NC GND P18 TO HOST es i VCC ew D TO PRINTER OR ANOTHER PARALLEL PORT RESIDENT DEVICE Figure 3. CONNECTION TO MICROCONTROLLERS ENI O1/BSY1 O2/BSY2 D/CLK RES NC de P1.2 P1.3 DS9100 fo P1.0 P1.1 I/O ENO I1 I2 NC NC GND d VCC rN +5 DS80C320 om m en The logic states of D/CLK and RES determine the type of 1-Wire function to be executed. These signals are transferred into the DS1481 by activating ENI. This also activates the busy signals. N ot R ec In Figures 4 through 6 below, during time slots or reset presence sequences the busy lines are active. Once the busy state is over the computer queries the result of the time slot or reset presence sequence by generating a falling edge on D/CLK. The result is found on the busy lines until ENI is de-activated. 5 of 10 DS1481 Figure 4. TIMING DIAGRAM: HOST INTERFACE ENI RES VALID VALID gn D/CLK es i O1/BSY1 O2/BSY2 D tBLB ew READ 0 (I/O) READ 1 (I/O) rN WRITE 1 (I/O) tSIO fo tSIO = 8 μs (STANDARD SPEED), tBLB = 60 μs (MINIMUM) tSIO = 2 μs (OVERDRIVE SPEED), tBLB = 6 μs (MINIMUM) (OD = 0) (OD = 1) d READ O, READ 1, WRITE 1 BIT TIME SLOTS de Figure 5. TIMING DIAGRAM: HOST INTERFACE RES VALID VALID O1/BSY1 tBLB tBLB = 60 μs (MINIMUM) tBLB = 6 μs (MINIMUM) (OD = 0) (OD = 1) WRITE 0 TIME SLOT N ot R WRITE 0 (I/O) ec O2/BSY2 om m D/CLK en ENI 6 of 10 DS1481 Figure 6. TIMING DIAGRAM: HOST INTERFACE ENI VALID tBLR O1/BSY1 Note 1 Note 1 RESET (I/O) tBLR = 960 μs (MINIMUM) tBLR = 96 μs (MIMIMUM) Note 1: 0 only if presence pulse. (OD = 0) (OD = 1) rN 1-WIRE RESET fo Figure 7. TIMING DIAGRAM: HOST INTERFACE de VALID VALID en RES d ENI om m O1/BSY1 O2/BSY2 ew D O2/BSY2 D/CLK gn RES VALID es i D/CLK N ot R ec TOGGLE OVERDRIVE MODE 7 of 10 DS1481 TYPE O1/BSY1 O O2/BSY2 O D/CLK I RES I DC supply voltage. Chip enable, driven low to begin 1-Wire I/O. Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I1 after time slot has finished. O1/BSY1 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I1 when ENI goes back high (see Figure 1). Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I2 after time slot has finished. O2/BSY2 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I2 when ENI goes back high (see Figure 1). Data/Clock pin. Used to specify type of time slot before communication begins. After the time slot has been completed this pin is driven low in order to solicit the result of the time slot. Set low (before ENI is driven low) to specify that a reset pulse should be generated on the I/O pin. System ground. Can be connected to the O1/BSY1 of another DS1481. May also be connected to parallel port printer’s BUSY signal. Internally pulled high via a weak resistor. Can be connected to the O2/BSY2 of another DS1481. Can also be connected to a parallel port printer SELECT OUT signal. Internally pulled high via a weak resistor. Set to ENI if not the last part on port. Open-drain output with weak internal pullup resistor. 1-Wire I/O line. Bidirectional line with open-drain output. I ENO O I/O I/O rN fo d de I2 en I N ot R ec I1 om m GND ew D I DESCRIPTION es i PIN VCC ENI gn DETAILED PIN DESCRIPTION 8 of 10 DS1481 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -1.0V to +7.0V 0°C to +70°C -55°C to +125°C See IPC/JEDEC JSTD-020A es i gn * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0ºC to 40ºC) MIN 2.4 -0.3 2.7 TYP MAX VCC + 0.3 +0.8 5.5 UNITS V V V 5.0 NOTES 1 1 1 D SYMBOL VIH VIL VCC ew PARAMETER Logic 1 Logic 0 Supply MAX +1 +1 0.4 d 50 50 50 50 50 50 de en ZI1 ZI2 ZENI ZENO ZDC ZR ICC II/O TYP fo SYMBOL MIN IIL -1 ILO -1 500 40 N ot R ec om m PARAMETER Input Leakage Output Leakage VOL @ ISINK = -2mA I1 Pullup Resistance I2 Pullup Resistance ENI Pullup Resistance ENO Pullup Resistance D/CLK Pullup Resistance RES Pullup Resistance Active Current Available I/O Current rN DC ELECTRICAL CHARACTERISTICS (0ºC to 40ºC; 2.7 ≤ VCC ≤ 5.5) 9 of 10 UNITS μA μA V kΩ kΩ kΩ kΩ kΩ kΩ μA mA NOTES 5 2 6 DS1481 AC ELECTRICAL CHARACTERISTICS: HOST INTERFACE SYMBOL MIN tSIO TYP MAX UNITS NOTES μs 8 OD = 0 1 40 40 200 tBLB 60 6 tBLR 960 96 ew rN N ot R ec om m en de d NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open and I1, I2 high. 3. Minimum time required for 1-wire bit time slot. 4. Minimum time required for 1-wire reset time slot. 5. Only pins without pullups. 6. Overdrive mode only. μs 3 μs 4 D 200 μs μs μs ns ns es i tREC tDE tRE tCL tCOV 10 of 10 gn 2 OD = 1 fo PARAMETER Sample Time (For Bit Time Slot, OD = 0) (For Bit Time Slot, OD = 1) Recovery Time Data to Enable Hold Reset to Enable Hold Clock Low Time Clock Low to O1, O2 Valid BSY1, BSY2 Low Time (For Bit Time Slot, OD = 0) (OD = 1) BSY1, BSY2 Low Time (For Reset Time Slot, OD = 0) (OD = 1)