19-2105; Rev 2; 7/06 +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier Features The MAX3271 transimpedance amplifier provides a compact low-power solution for 2.5Gbps communications. It features 495nA input-referred noise, 2GHz bandwidth, and 2mA AC input overload. The MAX3271 is a compact 30mil x 50mil die and requires no external compensation capacitor. It operates from a single +3.3V supply and consumes 83mW. A space-saving filter connection is provided for positive bias to the photodiode through a 750Ω resistor to VCC. These features allow easy assembly into a TO-46 or TO-56 header with a photodiode. The MAX3271 has a typical optical dynamic range of -21dBm to +3dBm in a shortwave configuration or -24dBm to 0dBm in a longwave configuration. The MAX3271 and MAX3272* provide a two-chip solution for Gigabit Ethernet and Fibre Channel receiver applications. ♦ Single +3.3V Power Supply ♦ 83mW Power Consumption ♦ 495nA Input-Referred-Noise ♦ 2GHz Bandwidth ♦ 2mA AC Input Overload ♦ 30mil x 50mil Die Size Applications Ordering Information Gigabit Ethernet Optical Receivers TEMP RANGE PIN-PACKAGE MAX3271E/D -40°C to +85°C Dice** MAX3271E/W -40°C to +85°C Wafer** PART Fibre Channel Optical Receivers System Interconnects **Dice/wafers are designed to operate from -40°C to +85°C, but 2.5Gbps Optical Receivers are tested and guaranteed only at TA = +25°C. SONET/SDH Receivers Typical Application Circuit +3.3V 0.1µF VCC LIMITING AMPLIFIER 750Ω CFILTER 470pF 0.1µF FILTER OUT+ PHOTODIODE IN TIA OUT+ 0.1µF 100Ω OUT- GND MAX3271 OUT- MAX3272 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3271 General Description MAX3271 +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (VCC) ................................-0.5V to +6.0V Input Current (IN) ..................................................-4mA to +4mA FILTER Current ................................…………..-12mA to +12mA Voltage at OUT+, OUT- ..................(VCC - 1.5V) to (VCC + 0.5V) Operating Junction Temperature Range (TJ) ............……………-55°C to +150°C Storage Ambient Temperature Range (Tstg) ....-55°C to +150°C Die Attach Temperature ..................................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, source capacitance = 0.85pF, TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS Input Bias Voltage Power-Supply Current MIN TYP MAX 0.66 0.83 1.1 V 25 35 mA 3.4 ICC UNITS 40µAP-P input, differential out 2.1 2.8 (Note 3) 1.5 2 Output Impedance Single-ended 42 50 58 Ω Maximum Differential Output Swing Input = 1mAP-P 185 300 430 mVP-P Transimpedance Small-Signal Bandwidth BW AC Input Overload DC Input Overload Input-Referred Noise IN Input-Referred Noise Density (Note 3) 2.0 (Note 3) 1.0 (Note 4) 11 -3dB, input ≤ 20µA DC 0.95 ≤ linearity ≤ 1.05 (Note 3) Power-Supply Noise Rejection PSNR mA 495 Transimpedance Linear Range DJ mAP-P (Note 3) Low-Frequency Cutoff Deterministic Jitter Ω 750 Filter Resistor (Notes 3, 5) 655 nARMS pA/√Hz 50 kHz 40 µAP-P 10µAP-P input 18 40 20µAP-P ≤ input ≤ 2mAP-P 12 30 ∆VCC = 100mVP-P, f < 2MHz (Note 6) kΩ GHz 36 psP-P dB Note 1: Production test at room ambient temperature only. Die parameters are guaranteed by design and characterization at -40°C and +85°C. Note 2: Source capacitance represents the total capacitance at the IN pad during characterization of the noise and bandwidth parameters. Note 3: Guaranteed by design and characterization. Note 4: Input-referred noise density is IN/√BW. No external filters are used for the noise measurements. Note 5: Deterministic jitter is measured with a K28.5 pattern (0011 1110 1011 0000 0101). Note 6: Power-supply noise rejection PSNR = -20log(∆VOUT/∆VCC), where ∆VOUT is the differential output voltage and ∆VCC is the noise on VCC. 2 _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier 550 CIN = 0.85pF 500 65 CIN = 0.5pF 450 55 50 40 35 30 25 20 15 10 5 350 0 40 -25 0 25 50 75 100 10M 1G 0.01 10G 0.1 1 JUNCTION TEMPERATURE (°C) FREQUENCY (Hz) INPUT AMPLITUDE (mAP-P) SMALL-SIGNAL TRANSIMPEDANCE vs. TEMPERATURE BANDWIDTH vs. TEMPERATURE EYE DIAGRAM (INPUT = 20µAP-P) 2500 68 66 65 64 63 2200 2100 1600 60 1500 50 75 100 CIN = 1.5pF 1800 1700 25 9.5mV/div 1900 61 0 CIN = 1.0pF 2000 62 -25 CIN = 0.5pF 2300 BANDWIDTH (MHz) 67 2400 INPUT: 213 -1 PRBS -50 -25 0 25 50 75 57ps/div 100 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) EYE DIAGRAM (INPUT = 2mAP-P) MAX3271 toc07 200 150 OUPUT VOLTAGE (mVp-p) 53mV/div DC TRANSFER FUNCTION (VFILT = 0V) MAX3271 toc08 69 10 MAX3271 toc06 MAX3271 toc04 70 -50 100M MAX3271 toc05 -50 TRANSIMPEDANCE (dBΩ) 60 45 400 K28.5 DATA STREAM re = 6dB 45 DETERMINISTIC JITTER (psP-P) 600 50 MAX3271 toc02 CIN IS SOURCE CAPACITANCE PRESENTED TO DIE, INCLUDING PACKAGE PARASITIC, PIN DIODE, AND PARASITIC INTERCONNECT CAPACITANCE TRANSIMPEDANCE (dBΩ) 650 70 MAX3271 toc01 INPUT-REFERRED NOISE (nARMS) 750 700 DETERMINISTIC JITTER vs. INPUT AMPLITUDE FREQUENCY RESPONSE MAX3271 toc03 INPUT-REFERRED NOISE vs. TEMPERATURE 100 50 0 -50 -100 -150 INPUT: 213 -1 PRBS -200 57ps/div -200 -150 -100 -50 0 50 100 150 200 INPUT CURRENT (µA) _______________________________________________________________________________________ 3 MAX3271 Typical Operating Characteristics (VCC = +3.3V, CIN = 0.85pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +3.3V, CIN = 0.85pF, TA = +25°C, unless otherwise noted.) OUTPUT AMPLITUDE vs. TEMPERATURE (INPUT = 1mAP-P) DIFFERENTIAL OUTPUT REFLECTION COEFFICIENT -5 350 AMPLITUDE (mVP-P) -10 -15 -20 -25 MAX3271 toc10 400 MAX3271 toc09 0 S22 (dB) MAX3271 +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier 300 250 200 150 100 -30 50 -35 0 0 500 1000 1500 2000 2500 3000 -50 FREQUENCY (MHz) -25 0 25 50 75 100 JUNCTION TEMPERATURE (°C) Pin Description 4 BOND PAD NAME FUNCTION 1 FILTER 2 N.C. 3 IN 4, 5 VCC Power Supply. Both pads must be connected to supply. Bond pad 4 supplies power to the transimpedance stage. Bond pad 5 supplies power to the remaining circuitry. 6, 9 GND Ground. Both pads must be connected to ground. Bond pad 9 is ground for the transimpedance stage. Bond pad 6 is ground for the remaining circuitry. 7 OUT+ Noninverted Data Output. Current flowing into IN causes VOUT+ to increase. 8 OUT- Inverted Data Output. Current flowing into IN causes VOUT- to decrease. Provides bias voltage for the photodiode through a 750Ω resistor to VCC. When grounded, this pin disables the DC-cancellation amplifier to allow a DC path from IN to OUT+ and OUT- for testing. No Connection. Leave unconnected. TIA Input _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier The MAX3271 is a transimpedance amplifier designed for 2.5Gbps fiber optic applications. A functional diagram of the MAX3271 is shown in Figure 1. The MAX3271 is comprised of a transimpedance amplifier stage, a voltage amplifier stage, an output buffer, and a direct current feedback cancellation circuit. Transimpedance Amplifier Stage The signal current at the input flows into the summing node of a high-gain amplifier. Shunt feedback through the resistor RF converts this current to a voltage. In parallel with the feedback are two back-to-back Schottky diodes that clamp the output signal for large input currents as shown in Figure 2. Voltage Amplifier Stage Output Buffer The output buffer provides a reverse-terminated voltage output. The buffer is designed to drive a 100Ω differential load between OUT+ and OUT-. The output current is divided between internal 50Ω resistors and the external load resistor. In the Typical Applications Circuit, this creates a voltage-divider with gain of 1/2 for a 100Ω differential load. The MAX3271 can also be terminated with higher output impedances, which increases gain and output voltage swing but lowers bandwidth. For optimum supply-noise rejection, the MAX3271 should be terminated with a differential load. If a singleended output is required, the unused output should be similarly terminated. The MAX3271 will not drive a DCcoupled 50Ω grounded load. The voltage amplifier stage provides gain and converts the single-ended input to differential outputs. MAX3271 RF TRANSIMPEDANCE AMPLIFIER VOLTAGE AMPLIFIER OUTPUT BUFFER 50Ω OUT+ OUT- IN 50Ω LOWPASS FILTER VCC VCC GND DISABLE 750Ω DC CANCELLATION CIRCUIT FILTER Figure 1. Functional Diagram _______________________________________________________________________________________ 5 MAX3271 Detailed Description DC Cancellation Circuit The direct current (DC) cancellation circuit uses lowfrequency feedback to remove the DC component of the input signal. This feature centers the input signal within the transimpedance amplifier’s linear range, thereby reducing pulse-width distortion caused by large input signals (Figure 3). The DC cancellation circuit is internally compensated and therefore does not require external capacitors. This circuit minimizes pulse-width distortion for data sequences that exhibit a 50% mark density. A mark density significantly different from 50% will cause the MAX3271 to generate pulse-width distortion. DC cancellation current is drawn from the input and creates noise. For low-level signals with little or no DC component, this is not a problem. Amplifier noise will increase slightly for signals with significant DC component. Applications Information Optical Power Relations Many of the MAX3271 specifications relate to the input signal amplitude. When working with fiber optic receivers, the input is sometimes expressed in terms of average optical power and extinction ratio. Figure 4 shows relations that are helpful for converting optical power to input signal when designing with the MAX3271. Optical power relations are shown in Table 1; the definitions are true if the average duty cycle of the input data is 50%. Optical Sensitivity Calculation The input-referred RMS noise current (I N ) of the MAX3271 generally determines the receiver sensitivity. To obtain a system bit error rate (BER) of 1E-12, the SNR ratio must always exceed 14.1. The input sensitivity, expressed in average power, can be estimated as: ⎛ 14.1 IN (re + 1) ⎞ Sensitivity = 10log ⎜ 1000⎟ dBm ⎝ 2ρ(re − 1) ⎠ where ρ is the photodiode responsivity in A/W. AMPLITUDE Input Optical Overload The overload is the largest input that the MAX3271 accepts while meeting specifications. The optical overload can be estimated in terms of average power with the following equation: TIME OUTPUT (SMALL SIGNALS) OUTPUT (LARGE SIGNALS) ⎛ 2mA ⎞ Overload = 10 log ⎜ 1000⎟ dBm ⎝ 2ρ ⎠ Figure 2. MAX3271 Limited Output P1 AMPLITUDE INPUT FROM PHOTODIODE TIME INPUT AFTER DC CANCELLATION OPTICAL POWER MAX3271 +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier PAVG P0 TIME Figure 3. DC Cancellation Effect on Input 6 Figure 4. Optical Power Relations _______________________________________________________________________________________ +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier PARAMETER SYMBOL TOP VIEW OF TO-46 HEADER RELATION Average Power PAVG Extinction Ratio re re = P1/P0 Optical Power of a 1 P1 P1 = 2PAVG (re) / (re + 1) PAVG = (P0 + P1) / 2 P0 P0 = 2PAVG / (re + 1) PIN PIN = P1 - P0 = 2PAVG (re - 1) / (re + 1) CFILT CVCC OUT- Signal Amplitude IN FILT OUT+ Optical Linear Range The MAX3271 has high gain, which limits the output when the input signal exceeds 40µAP-P. The MAX3271 operates in a linear range for inputs not exceeding: ⎛ 40µA(re + 1) ⎞ Linear Range = 10log ⎜ 1000⎟ dBm ⎝ 2ρ(re − 1) ⎠ Layout Considerations Noise performance and bandwidth will be adversely affected by capacitance at the IN pin. Minimize capacitance on this pin and select a low-capacitance photodiode. Assembling the MAX3271 in die form using chip and wire technology provides the best possible performance. Figure 5 shows a suggested layout for a TO header. Photodiode Filter Supply voltage noise at the cathode of the photodiode produces a current I = CPD ∆V/∆t, which reduces the receiver sensitivity (C PD is the photodiode capacitance.) The filter resistor of the MAX3271, combined with an external capacitor, can be used to reduce this noise (see the Typical Application Circuit). Current generated by supply noise voltage is divided between CFILTER and CPD. The input noise current due to supply VCC PHOTODIODE GND Optical Power of a 0 MAX3271 Table 1. Optical Power Relations MAX3271 PHOTODIODE IS MOUNTED ON CFILT. CASE IS GROUND. Figure 5. Suggested Layout for TO-56 Header noise is (assuming the filter capacitor is much larger than the photodiode capacitance): INOISE = (VNOISE)(CPD) / (RFILTER)(CFILTER) If the amount of tolerable noise is known, the filter capacitor can be easily selected: CFILTER = (VNOISE)(CPD) / (RFILTER)(INOISE) For example, with maximum noise voltage = 100mVP-P, CPD = 0.85pF, RFILTER = 750Ω, and INOISE selected to be 250nA (1/2 of the MAX3271’s input noise): CFILTER = (100mV)(0.85pF) / (750Ω)(250nA) = 450pF Wire Bonding For high-current density and reliable operation, the MAX3271 uses gold metalization. Connections to the die should be made with gold wire only, using ballbonding techniques. Wedge bonding is not recommended. Die thickness is typically 15mils (0.375mm). _______________________________________________________________________________________ 7 MAX3271 +3.3V, 2.5Gbps Low-Power Transimpedance Amplifier Chip Topography V CC (PAD 5) GND (PAD 6) OUT+ (PAD 7) V CC (PAD 4) IN (PAD 3) 0.030" (0.76mm) N.C. (PAD 2) OUT(PAD 8) FILTER (PAD 1) GND (PAD 9) 0.050" (1.27mm) Pad Coordinates PAD# COORDINATES (MILS) 1 2 3 4 5 6 7 8 47, 47 47, 197 47, 346 44, 507 222, 505 374, 505 1006, 505 1006, 89 9 226, 47 Coordinates are for the center of the pad. Coordinate 0, 0 is the lower left corner of the passivation opening for pad 1. Chip Information TRANSISTOR COUNT: 340 SUBSTRATE: ELECTRICALLY ISOLATED PROCESS: SiGe BIPOLAR Revision History Rev 0; 7/01: Original data sheet release. Rev 1; 11/05: Page 7: Updated Figure 5. Rev 2; 7/06: Page 1: Removed future status from MAX3272 in Typical Application Circuit. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.