19-3496; Rev 2; 11/06 10Gbps Clock and Data Recovery with Equalizer Features The MAX3992 is a 10Gbps clock and data recovery (CDR) with equalizer IC for XFP optical transmitters. The MAX3992 and the MAX3991 (CDR with limiting amplifier) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps. ♦ Multirate Operation from 9.95Gbps to 11.1Gbps The MAX3992 recovers the data for up to 12 inches of FR-4 and one connector without the need for a standalone equalizer. The phase-locked loop is optimized for jitter tolerance in SONET, Ethernet, and Fibre-Channel applications. Low jitter generation of 4mUIRMS leaves adequate margin for meeting SONET jitter requirements at the optical output. An AC-based power detector asserts the loss-of-signal (LOS) output when the input signal is removed. An external reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate, is used to aid in frequency acquisition. A loss-of-lock (LOL) indicator is provided to indicate the lock status of the receiver PLL. The MAX3992 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 356mW from a single +3.3V supply and operates over a 0°C to +85°C temperature range. ♦ LOS Indicator ♦ Span Up to 300mm (12in) FR4 with One Connector ♦ Low-Output Jitter Generation: 4mUIRMS ♦ Low-Output Deterministic Jitter: 4.6psP-P ♦ XFI-Compliant Input Interface ♦ LOL Indicator ♦ Power Dissipation: 356mW Ordering Information PART TEMP RANGE 0°C to +85°C 24 QFN T2444-4 MAX3992UTG+* 0°C to +85°C 24 QFN T2444-4 *Future product—contact factory for availability. +Denotes lead-free package. Pin Configuration FCTL1 REFCLK- REFCLK+ LOS LOL 24 23 22 21 20 19 VCC 1 18 VCC GND 2 17 GND SDI- 3 16 SDO- MAX3992 SDI+ 4 GND 5 14 GND VCC 6 13 VCC 8 9 10 11 12 FCTL2 POL VCC CFIL 15 SDO+ SCLKO- 7 SCLKO+ Typical Application Circuit appears at end of data sheet. TOP VIEW VTH 10.3Gbps/11.1Gbps Ethernet XFP Transceivers 10.5Gbps Fibre-Channel XFP Transceivers 10Gbps DWDM Transceivers 10Gbps XFP Copper Modules High-Speed Backplane Interconnects PKG CODE MAX3992UTG Applications 9.95Gbps to 11.1Gbps Optical XFP Modules SONET OC-192/SDH STM-64 XFP Transceivers PINPACKAGE 4mm x 4mm QFN* *THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3992 General Description MAX3992 10Gbps Clock and Data Recovery with Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +4.0V Input Voltage Levels (SDI+, SDI-, REFCLK+, REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V) CML Output Voltage (SDO+, SDO-, SCLKO+, SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V) Voltage at (CFIL, LOL, VTH, POL, LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 24-Pin QFN (derate 20.8mW/°C above +85°C) .........1355mW Junction Temperature Range .............................-40°C to+150°C Storage Temperature Range.............…………..-55°C to +150°C Lead Temperature (soldering, 10s) ..……………………..+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL Supply Current CONDITIONS MIN ICC TYP MAX UNITS 108 145 mA DATA INPUT SPECIFICATION (SDI±) Single-Ended Input Resistance RSE 42 50 58 Ω Differential Input Resistance RD 84 100 116 Ω ±5 % Single-Ended Input Resistance Matching 0.1GHz to 5.5GHz (Note 1) 15 5.5GHz to 12GHz (Note 1) 6 SCD11 0.1GHz to 15GHz 17 dB SCC11 0.1GHz to 15GHz 7 dB Differential-Input Return Loss SDD11 Differential to Common-Mode Conversion Common-Mode Input Return Loss dB REFERENCE CLOCK SPECIFICATION (REFCLK±) Single-Ended Input Resisitance 84 100 116 Ω Differential Input Resistance 168 200 232 Ω 575 650 725 mVP-P CML OUTPUT SPECIFICATION (SDO±) SDO± Differential Output Swing (Note 2) SDO± Output Common-Mode Voltage RL = 50Ω to VCC VCC 0.16 SCLKO± Differential Output 380 Single-Ended Output Resistance Differential Output Resistance RO SDD22 50 58 Ω 84 100 116 Ω ±5 % 0.1GHz to 5.5GHz (Note 1) 13 5.5GHz to 12GHz (Note 1) 8 Rise/Fall Time (20% to 80%) (Note 2) Power-Down Assert Time (Note 3) 2 mVP-P 42 Single-Ended Output Resistance Matching Differential-Output Return Loss V 18 23 _______________________________________________________________________________________ dB 30 ps 50 µs 10Gbps Clock and Data Recovery with Equalizer MAX3992 ELECTRICAL CHARACTERISTICS (continued) (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 120kHz < f ≤ 8MHz (Notes 2, 4) 0.05 0.25 f ≤ 120kHz (Note 5) 0.03 UNITS JITTER SPECIFICATION Jitter Peaking JP Jitter Transfer Bandwidth JBW (Notes 2, 4) Sinusoidal Jitter Tolerance (Notes 2, 4, 7) Jitter Generation (Notes 2, 4, 8) Serial-Data Output Deterministic Jitter DJ 5.6 f = 400kHz 2.8 >2.8 (Note 6) f = 4MHz 0.4 0.55 f = 80MHz 0.4 0.45 PRBS 27 - 1 (Note 2) 8.0 dB MHz UIP-P 4 5.5 mUIRMS 4.6 13 psP-P PLL ACQUISITION/LOCK SPECIFICATION Acquisition Time Figures 1, 2 (Note 2) 200 µs LOL Assert Time Figure 1 (Note 2) 90 µs Maximum Frequency Pullin Time (Note 9) 2 ms Frequency Difference at which LOL Is Asserted ∆f/fREFCLK ∆f = |fVCO / N - fREFCLK|, N = 16 or 64 651 ppm Frequency Difference at which LOL Is Deasserted ∆f/fREFCLK ∆f = |fVCO / N - fREFCLK|, N = 16 or 64 500 ppm LOSS-OF-SIGNAL (LOS) SPECIFICATION VTH Control Voltage Range VTH 150 500 mV LOS Gain Factor VTH/ VLOS_ASSERT 10 V/V Minimum LOS Assert Voltage VLOS_ASSERT 15 mV Maximum LOS Assert Voltage VLOS_ASSERT 50 mV LOS Gain-Factor Accuracy (Notes 2, 10) -1.5 LOS Hysteresis (Notes 2, 11) 3.5 LOS Gain-Factor Stability (Note 2) Overtemperature and supply -10 +10 % LOS Assert Time Figure 2 (Note 2) 3 90 µs LOS Deassert Time Figure 2 (Note 2) 90 µs +5 µA VTH Input Current -5 3.7 +1.5 dB 3.9 dB LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2) Input High Voltage VIH Input Low Voltage VIL 2.0 Input Current -30 Output High Voltage VOH Sourcing 30µA Output Low Voltage VOL Sinking 1mA V 0.8 V +30 µA VCC 0.5 V 0.4 V _______________________________________________________________________________________ 3 MAX3992 10Gbps Clock and Data Recovery with Equalizer ELECTRICAL CHARACTERISTICS (continued) (See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Note 1: Measured with 100mVP-P differential amplitude. Note 2: Guaranteed by design and characterization. Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0, to the time when the supply current drops to less than 40% of the nominal value. Note 4: Measured with PRBS = 231 - 1. Note 5: Larger CFILT can be used to reduce jitter peaking at ≤ 120kHz. A larger CFILT will increase acquisition time. CFILT should not exceed 200nF. Note 6: Measurement limited by test equipment. Note 7: Jitter tolerance is for BER ≤ 10-12, measured with additional 0.1VI deterministic jitter through 15 inches of FR4. (See Typical Operating Characteristics 1.) Note 8: Measured with 50kHz to 80MHz SONET filter. Note 9: Applies on power-up or after standby. Note 10: Over process, temperature and supply. Note 11: Hysteresis is defined as 20Log(VLOS-DEASSERT/VLOS-ASSERT). Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.) PARAMETER Supply Voltage SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 3.0 3.6 V Ambient Temperature TA 0 +85 °C Input Data Rate Rb Differential Input Voltage to Transmission Line VD 0 to 12 inches FR-4 Output Load Resistance RL RL is AC-coupled (See Table 2) 400 Gbps 1000 mVP-P Ω 50 REFCLK± Differential Input Voltage Swing 300 1600 mVP-P REFCLK Duty Cycle 30 70 % REFCLK Frequency Rb / 16 fREFCLK GHz Rb / 64 REFCLK Accuracy Relative to Rb / 16 or Rb / 64 -100 +100 REFCLK Rise/Fall Times (20% to 80%) FREFCLK = Rb / 64 1200 fREFCLK = Rb / 16 300 REFCLK Random Jitter Noise bandwidth < 100MHz 10 ppm ps psRMS Table 2. Serial Data Rate and Reference Clock Frequency DATA RATE (Rb) (Gbps) /16 REFERENCE CLOCK FREQUENCY (MHz) OC-192 SONET – SDH64 9.95328 622.08 155.52 OC-192 SONET over FEC 10.664 666.5 166.625 APPLICATION /64 REFERENCE CLOCK FREQUENCY (MHz) ITU G.709 10.709 669.3125 167.328125 10Gbps Ethernet, IEEE 802.3ae 10.3125 644.53125 161.1328125 10Gbps Ethernet over ITU G.709 11.09573 693.483125 173.3707813 10Gbps Fibre Channel 10.51875 657.421875 Note: The part should be in standby mode when data rates are being switched. 164.355469 4 _______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Equalizer MAX3992 ∆f/fREFCLK 651ppm 500ppm LOL ASSERT TIME ACQUISITION TIME LOL *ASSERT AND ACQUISITION TIME ARE DEFINED WITH A VALID REFERENCE CLOCK APPLIED. Figure 1. TX LOL Assert and PLL Acquisition Time DATA INPUT POWER LOS ASSERT TIME LOS DEASSERT TIME LOS ACQUISITION TIME LOL Figure 2. LOS Assert/Deassert Time _______________________________________________________________________________________ 5 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) RECOVERED REFERENCE SIGNAL PRBS 231-1 15in FR-4 16 PRBS 231-1 500 14 50 -50 JITTER GENERATION (mUIRMS) DIFFERENTIAL SIGNAL AMPLITUDE (100mV/div) 12 10 8 6 4 2 -500 0 0 0.35 0.65 1 NORMALIZED BIT TIME (UI) 0 1 NORMALIZED BIT TIME (UI) POWER-SUPPLY INDUCED OUTPUT JITTER vs. RIPPLE FREQUENCY SINUSOIDAL JITTER TOLERANCE 12in FR-4 231-1 PRBS DATA JITTER TOLERANCE (U|P-P) 0.05 0.04 0.03 0.02 40 3 0 1 XFI TELECOM MASK 50 -3 -6 -9 -12 -15 0.1 0.01 -18 0 -21 0.01 1k 10k 100k 1M 10M 1k 10k FREQUENCY (Hz) 100k 1M 10M 10k 10 MAX3992 toc08 130 100k 5 0 XFI MASK -5 SDD11 (dB) 120 110 100 -10 -15 -20 -25 -30 90 -35 80 -40 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 1M FREQUENCY (Hz) DIFFERENTIAL S11 SDD11 MAX3992 toc07 140 SUPPLY CURRENT (mA) 1k 100M FREQUENCY (Hz) MAX3992 SUPPLY CURRENT vs. TEMPERATURE 6 30 JITTER TRANSFER TOLERANCE EXCEEDS MODULATION CAPABILITIES OF TEST EQUIPMENT 10 20 MAX3992 toc06 0.06 10 NOISE AMPLITUDE (mVRMS) JITTER TRANSFER (dB) 100 MAX3992 toc04 0.07 0 MAX3992 toc05 DIFFERENTIAL SIGNAL AMPLITUDE (mV) JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE AMPLITUDE (BW < 100kHz) MAX3992 toc02 MAX3992 toc01 MAX3992 toc03 MAX3992 INPUT (15in FR-4) JITTER GENERATION (psP-P/mVP-P) MAX3992 10Gbps Clock and Data Recovery with Equalizer 10M 100M 1G 10G 100G FREQUENCY (Hz) _______________________________________________________________________________________ 10M 100M 10Gbps Clock and Data Recovery with Equalizer DIFFERENTIAL TO COMMON MODE S11 SCD11 COMMON MODE S11 SCC11 XFI MASK -5 MAX3992 toc10 0 MAX3992 toc09 0 XFI MASK -10 -20 -15 SCD11 (dB) SCC11 (dB) -10 -20 -25 -30 -40 -30 -50 -35 -60 -40 10M 100M 1G 10G 100G 10M 100M 1G 10G 100G FREQUENCY (Hz) FREQUENCY (Hz) Pin Description PIN NAME FUNCTION 1, 6, 11, 13, 18 VCC 2, 5, 14, 17 GND +3.3V Power Supply Supply Ground 3 SDI- Negative Serial Input, CML 4 SDI+ Positive Serial Input, CML 7 SCLKO+ Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). 8 SCLKO- Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). 9 FCTL2 10 POL Data Polarity Control Input, TTL. Connect to VCC or leave open to maintain the same polarity as the input. Connect to GND to invert the polarity of the data. 12 CFIL Loop-Filter Capacitor Connection. Connect a 0.047µF capacitor between CFIL and VCC. 15 SDO+ Positive Serial Data Output, CML 16 SDO- Negative Serial Data Output, CML 19 LOL Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock. 20 LOS Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal is removed. 21 REFCLK+ Function Control Input 2, TTL. See Table 3 for more information. Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description section for more information. See Table 2. _______________________________________________________________________________________ 7 MAX3992 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 10Gbps Clock and Data Recovery with Equalizer MAX3992 Pin Description (continued) PIN NAME FUNCTION 22 REFCLK- Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK± have a 200Ω differential impedance. See the Detailed Description section for more information. See Table 2. 23 FCTL1 24 VTH EP Exposed Pad Function Control Input 1, TTL. See Table 3 for more information. LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS power detector can be disabled if VTH is connected to VCC, which forces LOS low. Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical performance. The MAX3992 uses exposed-pad variation T2444-4 in the package outline drawing. See the exposed-pad package. Functional Diagram VTH LOS MAX3992 SDI+ SDI- DFF EQUALIZER CML D CML Q SDO+ SDO- PLL PHASE/ FREQUENCY DETECTOR REFCLK+ REFCLK- SCLKO+ SCLKO- LOL DETECTOR 200Ω CML VCO FUNCTIONAL CONTROL FCTL1 CFIL LOL FCTL2 POL Figure 3. Functional Diagram Detailed Description The MAX3992 clock and data recovery with equalizer recovers data from the XFI interface. It consists of an equalizer with LOS power detector and a data retimer with LOL indicator. An optional recovered clock may also be enabled for performance testing. Equalizer The SDI inputs of the MAX3992 accept serial NRZ data from XFI standard interfaces. When signals from 400mVP-P to 1000mVP-P are applied to a transmission line from 0 to 12 inches of FR-4, the equalizer restores them for recovery by the CDR. The equalizer removes 8 most of the deterministic jitter caused by frequency dependent skin effect and dielectric losses, as well as connector loss. PLL Retimer The integrated PLL recovers a synchronous clock that is used to retime the input data. Connect a 0.047µF capacitor between CFIL and VCC to provide PLL dampening. The external reference connected to REFCLK aids in frequency acquisition. Because the reference clock is only used for frequency acquisition, an extremely low jitter generation can be achieved from a low-quality reference clock. The reference clock should be within ±100ppm of the bit rate divided by 16 or 64. _______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Equalizer Loss-of-Signal Monitor The LOS output indicates a loss of input data. Set VTH >500mV. When the input signal is removed (<50mV), LOS will be asserted high. Reference Clock Input The REFCLK inputs are internally terminated and selfbiased to allow AC-coupling. The input impedance is 100Ω single-ended (200Ω differential). The REFCLK inputs of the MAX3991 and MAX3992 should be connected close together in parallel. The impedance looking into the parallel combination is 100Ω differential. This allows both the MAX3991 and MAX3992 to easily interface with one reference clock without using additional components. See Figure 4. Design Procedure Modes of Operation The MAX3992 has a standby mode and jitter test mode in addition to its normal operating mode. Standby is used to conserve power. In the standby mode, the power consumption of the MAX3992 falls below 40% of the normal-operation power consumption. The jitter test mode enables the SCLK outputs to clock a BERT when testing jitter generation, jitter transfer, and jitter tolerance. The FCTL1 and FCTL2 TTL inputs are used to select the mode of operation as shown in Table 3. Serial Data Rate and Reference Clock Frequency Input Configuration The SDI± inputs of the MAX3992 are current-mode logic (CML) compatible. The inputs have internal 50Ω terminations for minimum external components. See Figure 5 for the input structure. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. Output Configuration The MAX3992 uses CML for its high-speed digital outputs (SDO± and SCLKO±). The configuration of the output circuit includes internal 50Ω back terminations to VCC. See Figure 6 for the output structure. CML outputs may be terminated by 50Ω to VCC, or by 100Ω differential impedance. The relation of the output polarity to input can be reversed using the POL pin. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML. 50W MAX3991 50W REFERENCE CLOCK 200Ω REFERENCE CLOCK MAX3992 200Ω 200Ω 50W 50W TRANSMITTER-ONLY TERMINATION MAX3992 200Ω TRANSCEIVER TERMINATION Figure 4. Reference Clock Termination _______________________________________________________________________________________ 9 MAX3992 Loss-of-Lock Monitor The LOL output indicates that the frequency difference between the recovered clock and the reference clock is excessive. LOL may assert due to excessive jitter at the data input, incorrect frequency, or loss of input data. The LOL detector monitors the frequency difference between the recovered clock and the reference clock. The LOL output is asserted high when the frequency difference exceeds 650ppm. MAX3992 10Gbps Clock and Data Recovery with Equalizer Applications Information VCC Exposed Pad (EP) Package 50Ω The exposed pad, 24-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3992 and must be soldered to the circuit board for proper thermal and electrical performance. 50Ω SDI+ SDI- Layout Considerations For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3992 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals. Figure 5. CML Input Model VCC (SDI+) - (SDI-) 50Ω 50Ω SDO+ (SDO+) - (SDO-) POL = VCC SDO(SDO+) - (SDO-) POL = GND Figure 7. Polarity (POL) Function GND Figure 6. CML Output Model 10 Table 3. Functional Control FCTL1 FCTL2 DESCRIPTION 0 0 Normal operation, serial clock output disabled. 1 0 Standby power-down mode. 0 1 Normal operation, serial clock output disabled. 1 1 Serial clock output enabled for jitter testing. ______________________________________________________________________________________ 10Gbps Clock and Data Recovery with Equalizer VCC 0.047µF TOSA VCC CFIL GND SDI+ SDO+ SDI- MAX3975 DRIVER MAX3992 SDO- REFCLK+ REFCLK- FCTL VTH POL LOL LOS GND 2 30-PIN CONNECTOR DS1862* CONTROLLER 2 2-WIRE INTERFACE N.C. FCTL VTH POL LOL LOS REFCLK+ SDI+ REFCLK- ROSA MAX3991 SDI- SDO+ SDO- CFIL VCC GND XFI REFERENCE 0.047µF VCC 50Ω TRANSMISSION LINE *FUTURE PRODUCT. ______________________________________________________________________________________ 11 MAX3992 Typical Application Circuit MAX3992 10Gbps Clock and Data Recovery with Equalizer Chip Information TRANSISTOR COUNT: 10,300 PROCESS: SiGe bipolar SUBSTRATE: SOI Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maximic.com/packages.) (QFN 4mm x 4mm x 0.8mm, package code: T2444-4) Revision History Rev 0; 11/04: Initial data sheet release. Rev 1; 11/05: Changed Jitter Peaking max to typ (page 3); added new Note 5 (page 4); updated Typical Application Circuit (page 11). Rev 2: 11/06: Changed Jitter Tolerance min from 2.2UIP-P to 2.8UIP-P; changed Jitter Generation max from 6.9mUIRMS, to 5.5mUIRMS (page 3). Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.