CY24242 Laser Printer System Frequency Synthesizer Features Table 1. Pin Selectable Frequency[1] • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Reduces measured EMI by as much as 10 dB • Four skew-controlled copies of CPU output • Four skew-controlled copies of SDRAM output • One copy of 14.31818-MHz Reference output • One copy of 48-MHz USB clock (not spread) • Selectable SSFTG modulation width FS1 FS0 CPU(0:3), SDRAM(0:3) USBCLK 0 0 133.3 MHz 48 MHz 0 1 100 MHz 48 MHz 1 0 66.6 MHz 48 MHz 1 1 50 MHz 48 MHz Table 2. Spread Characteristics. SSON# SS%1 SS%0 CPU(0:3), SDRAM(0:3) 0 0 0 –0.5% 0 0 1 –1.0% 0 1 0 –2.5% VDDC: ............................................... 3.3V±10% or 2.5V±5% 0 1 1 –3.75% VDDS: ............................................... 3.3V±10% or 2.5V±5% 1 0 0 0 (off)\ VDDU: ............................................... 3.3V±10% or 2.5V±5% 1 0 1 0 (off) CPU Clock Cycle to Cycle Jitter: ................................ 250 ps 1 1 0 0 (off) USBCLK Long term Jitter: ....................................... ± 500 ps 1 1 1 0 (off) • Available in 28-pin SSOP (209 mil) Key Specifications Supply Voltage: VDDCORE: ........................................................... 3.3V±10% CPU0:3 Clock Skew: .................................................. 250 ps CPU, SDRAM Output on Resistance: ............................. 15Ω Logic inputs have 250K-ohm pull-up resistors Block Diagram X1 X2 Pin Configuration [2, 3] REF XTAL OSC VDDCORE REF GND X1 X2 SDRAM3 SDRAM2 VDDS SDRAM1 SDRAM0 GND VDDCORE *SDEN *SS%0 PLL Ref Freq SSON# SS%1 SS%0 CPU0:3 SDRAM0:3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 USBCLKEN GND USBCLK VDDU CPU0 CPU1 VDDC CPU2 CPU3 GND SS%1* SSON#^ FS1* FS0* PLL 1 FS0 FS1 SDEN USBCLKEN PLL 2 USBCLK Notes: 1. All clock output loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 2. Signals marked with [*] have internal pull-up resistors 3. Signal marked with[^] has internal pull-down resistors. Cypress Semiconductor Corporation Document #: 38-07268 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY24242 Pin Definitions Pin No. Pin Type CPU0:3 24, 23, 21, 20 O CPU Clock Outputs: These four outputs run at a frequency set by FS0:1. The width of the Spread Spectrum Modulation is enabled by pin SSON#, and selected by pins SS%0:1. SDRAM0:3 10, 9, 7, 6 O SDRAM Outputs: These four SDRAM clock outputs run synchronously to the CPU clock. Modulation and frequency follow the CPU outputs. FS0:1 15, 16 I Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1. SS%0:1 14, 18 I Modulation Width Selection Inputs: These inputs select the width of the Spread Spectrum feature when it is enabled by SSON#. USBCLK 26 O USB Output: Timing signal running at 48.0080 MHz when a 14.31818-MHz frequency is provided as the reference. (167 ppm accuracy to 48 MHz, the output is equal to the reference times 57/17.) SSON# 17 I CPU Spread Spectrum Enable Input: When this pin is pulled LOW, outputs CPU0:3 and SDRAM0:3 will have the Spread Spectrum Feature enabled. USBCLKEN 28 I USB Disable Input: When this pin is pulled LOW, output USBCLK will be disabled to a LOW state. REF 2 O Reference Output: This output will be equal in frequency to the reference signal provided at X1/X2. SDEN 13 I SDRAM Bank Disable Input: When this pin is pulled LOW, outputs SDRAM0:3 will be disabled to a LOW state. X1 4 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. 1, 12 P Power Connection: Core Power supply. Connect to 3.3V supply. VDDU 25 P Power Connection: Power supply for the USB output. Connect to 3.3V or 2.5V supply. VDDC 22 P Power Connection: Power supply for the CPU outputs. Connect to 3.3V or 2.5V supply. VDDS 8 P Power Connection: Power supply for the SDRAM outputs. Connect to 3.3V or 2.5V supply. GND 3,11, 19, 27 G Ground Connections: Connect all ground pins to the common system ground plane. Pin Name VDDCORE Document #: 38-07268 Rev. *B Pin Description Page 2 of 10 CY24242 Spread Spectrum Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ±0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the SMBus data stream. EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) -SS% Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (+.0.5%) MIN. (–0.5%) Figure 2. Typical Modulation Profile Document #: 38-07268 Rev. *B Page 3 of 10 CY24242 Absolute Maximum Ratings[4] rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature –55 to +125 °C TB Ambient Temperature under Bias 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V ± 10% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDDQ3 Supply Current (3.3V) CPUCLK = 100 MHz Outputs Loaded[4] 400 mA IDDQ2 Supply Current (2.5V) CPUCLK = 100 MHz Outputs Loaded[4] 400 mA V Logic Inputs[5] VIL Input Low Voltage GND-3 0.8 2.0 VIH Input High Voltage VDD +.3 V IIL Input Low Current[6] –25 µA IIH Input High Current[6] 10 µA Crystal Oscillator VTH X1 Input Threshold Voltage[1] 1.5 V CLOAD Load Capacitance, Imposed on External Crystal[7] 14 pF CIN,X1 X1 Input Capacitance[8] 28 pF Pin X2 unconnected Pin Capacitance/Inductance CIN Input Pin Capacitance COUT LIN Except X1 and X2 5 pF Output Pin Capacitance 6 pF Input Pin Inductance 7 nH Notes: 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. CY24242 logic inputs have internal pull-up resistors. 6. X1 input threshold voltage (typical) is VDDQ/2. 7. The CY24242 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Document #: 38-07268 Rev. *B Page 4 of 10 CY24242 AC Electrical Characteristics TA = 0°C to +70°C, VDD = VDDQ3 = 3.3V±10%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, VDDC = 3.3V) CPU = 66 MHz Parameter Description Test Condition/Comments Min. CPU = 100 MHz Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 15 – 15.5 10 – 10.5 ns tH High Time Duration of clock cycle above 2.4V 5.2 – – 3.0 – – ns tL Low Time Duration of clock cycle below 0.4V 5 – – 2.8 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.4 – 3.2 0.4 – 3.2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.4 – 3.2 0.4 – 3.2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. – – 250 – – 250 ps tSK Output Skew Measured on rising edge at 1.5V – – 250 – – 250 ps fST Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short start) cycles exist prior to frequency stabilization. – – 3 – – 3 ms Zo AC Output Impedance – 20 – – 20 – Ω Average value during switching transition. Used for determining series termination value. SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, VDDC = 3.3V) CPU = 66 MHz Parameter Description Test Condition/Comments Min. CPU = 100 MHz Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 15 – 15.5 10 – 10.5 ns tH High Time Duration of clock cycle above 2.4V 5.2 – – 3.0 – – ns tL Low Time Duration of clock cycle below 0.4V 5 – – 2.8 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.4 – 3.2 0.4 – 3.2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.4 – 3.2 0.4 – 3.2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. – – 250 – – 250 ps tSK Output Skew Measured on rising edge at 1.5V 100 300 100 350 ps tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on rising edge at 1.5V. – – 350 – – 350 ps fST Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cycles from Power-up (cold exist prior to frequency stabilization. start) – – 3 – – 3 ms Zo AC Output Impedance – 20 – – 20 – Ω Document #: 38-07268 Rev. *B Average value during switching transition. Used for determining series termination value. Page 5 of 10 CY24242 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66/100MHz Parameter Description Test Condition/Comments Min. Typ. Frequency equal to the reference provided at pins X1, X2 Max. Unit f Frequency, Actual tR Output Rise Edge Rate 0.5 – 2 V/ns tF Output Fall Edge Rate 0.5 – 2 V/ns tD Duty Cycle 45 – 55 % fST Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short cycles start) exist prior to frequency stabilization. – – 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. – 40 – Ω Measured on rising and falling edge at 1.5V 14.318 MHz USBCLK Clock Output (Lump Capacitance Test Load = 20 pF, VDDC =3.3V) CPU = 66/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit 0.5 – 2 V/ns tR Output Rise Edge Rate tF Output Fall Edge Rate 0.5 – 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 – 55 % tJL Jitter, Long term Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. – – 500 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. – – 400 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. – – 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. – 40 – Ω Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature –55 to +125 °C TB Ambient Temperature under Bias 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV Document #: 38-07268 Rev. *B Page 6 of 10 CY24242 AC Electrical Characteristics TA = 0°C to +70°C, VDD = VDDQ3 = 2.5V ± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF, VDDC = 2.5V) CPU = 66 MHz Parameter Description Test Condition/Comments Min. CPU = 100 MHz Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 15 – 15.5 10 – 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 – – 3.0 – – ns tL Low Time Duration of clock cycle below 0.4V 5 – – 2.8 – – ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 0.4 – 3.2 0.4 – 3.2 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 0.4 – 3.2 0.4 – 3.2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 – 55 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. – – 250 – – 250 ps tSK Output Skew Measured on rising edge at 1.25V – – 250 – – 250 ps fST Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short start) cycles exist prior to frequency stabilization. – – 3 – – 3 ms Zo AC Output Impedance – 20 – – 20 – Ω Average value during switching transition. Used for determining series termination value. SDRAM Clock Outputs, SDRAM0:3 (Lump Capacitance Test Load = 30 pF, VDDC = 2.5V) CPU = 66 MHz Parameter Description Test Condition/Comments Min. CPU = 100 MHz Typ. Max. Min. Typ. Max. Unit tP Period Measured on rising edge at 1.25V 15 – 15.5 10 – tH High Time Duration of clock cycle above 2.0V 5.2 – – 3.0 – ns tL Low Time Duration of clock cycle below 0.4V 5 – – 2.8 – ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 0.4 – 3.2 0.4 – 3.2 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 0.4 – 3.2 0.4 – 3.2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 – 55 45 – 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. – – 250 – – 250 ps tSK Output Skew Measured on rising edge at 1.25V – 250 300 – 250 350 ps fST Frequency Stabilization Assumes full supply voltage reached within 1 ms from power-up. Short cycles from Power-up (cold exist prior to frequency stabilization. start) – – 3 – – 3 ms Zo AC Output Impedance – 20 – – 20 – Ω Document #: 38-07268 Rev. *B Average value during switching transition. Used for determining series termination value. 10.5 ns Page 7 of 10 CY24242 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) CPU = 66/100 MHz Parameter Description Test Condition/Comments Min. Frequency equal to the reference provided at pins X1, X2 Typ. Max. Unit f Frequency, Actual tR Output Rise Edge Rate Measured from 0.4V to 2.0 0.5 – 2 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 0.5 – 2 V/ns tD Duty Cycle 45 – 55 % fST Frequency Stabilization Assumes full supply voltage reached from Power-up (cold within 1 ms from power-up. Short cycles start) exist prior to frequency stabilization. – – 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. – 40 – Ω Measured on rising and falling edge at 1.25V 14.318 MHz USBCLK Clock Output (Lump Capacitance Test Load = 20 pF, VDDC =2.5V) CPU = 66/100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. Unit tR Output Rise Edge Rate Measured from 0.4V to 2.0 0.5 – 2 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 0.5 – 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 – 55 % tJL Jitter, Long term Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. – – 500 tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. – – 400 fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. – – 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. – 40 – Ω Ordering Information Ordering Code Package Type Temperature Grade Standard CY24242PVC 28-pin SSOP (300 mils) C (Commercial 0 - 70°) CY24242PVCT 28-pin SSOP (300 mils) - Tape and Reel C (Commercial 0 - 70°) CY24242OXC 28-pin SSOP (300 mils) C (Commercial 0 - 70°) CY24242OXCT 28-pin SSOP (300 mils) - Tape and Reel C (Commercial 0 - 70°) Lead-free Document #: 38-07268 Rev. *B Page 8 of 10 CY24242 Package Diagrams 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07268 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24242 Document History Page Document Title: CY24242 Laser Printer Frequency Synthesizer Document Number: 38-07268 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110533 10/08/01 SZV Change from Spec number: 38-01133 to 38-07268 *A 122866 12/20/02 RBI Added power-up requirements to maximum ratings information. *B 310556 See ECN RGL Added Lead-free devices Document #: 38-07268 Rev. *B Page 10 of 10