A Maxim Integrated Products Brand 78M6613 Printed Circuit Board Layout Guidelines APPLICATION NOTE AN_6613_050 October 2010 Introduction The highly integrated 78M6613 SOC minimizes the external component count and reduces the complexity of the printed circuit board layout design. However, some design issues require consideration for optimum measurement accuracy and reliability. This application note discusses these topics: • Printed Circuit Board Stackup • Crystal Oscillator Components • LINE Voltage Resistor Network • Shunt Current Sensor • Dual Outlet 2-Shunt Current Sensor Topology • V3P3 Decoupling Capacitors • In-Circuit Emulator Connector • System Communication Interface This application note covers the layout for Teridian chips. It specifically does not discuss creepage and clearance. Refer to the discussion of creepage and clearance in UL 60950-1. Printed Circuit Board Stackup The 78M6613 can achieve excellent measurement accuracy using a 2-layer printed circuit board stackup. If the component density becomes too high resulting in insufficient plane flooding surface area, a 4-layer stackup must be employed. The plane flooding surface area is insufficient when the critical components presented in this application note are not properly shielded and isolated from external noise or each other. Additionally, there must be multiple redundant connection paths across the board’s surface area to present low impedance paths for the various power and ground connections. For 2-layer printed circuit boards, begin by assigning the layer where the 78M6613 resides as the V3P3 layer. Assign the opposite layer as the Ground layer. The following discussion regarding the respective critical components uses the 78M6613 Evaluation Board as an example. The board has a 2-layer plane assignment. Refer to the schematics in Appendix A. 78M6613 Figure 1: V3P3 Layer Rev. 1.0 Figure 2: GND Layer © 2010 Teridian Semiconductor Corporation 1 78M6613 Printed Circuit Board Layout Guidelines AN_6613_050 Crystal Oscillator Components The 32.768 kHz crystal and its two 27 pF capacitors are placed on the GND layer. This allows the crystal and the two capacitors to be surrounded with a ground shield. Place the XIN and XOUT vias as close as possible to the 78M6613 pins. Shield the XIN and XOUT signal vias with copper plane on the V3P3 layer. Figure 3: Crystal Y1 and Capacitors C20/C21 V3P3 Plane V3P3 Plane Figure 4: V3P3 Plane Surrounds Crystal Traces 2 Rev 1.0 AN_6613_050 78M6613 Printed Circuit Board Layout Guidelines LINE Voltage Resistor Network Place the LINE voltage resistor network and its associated filter components on the V3P3 layer. Provide adequate high voltage isolation clearance around the 1 MΩ resistors. The 1000 pF and 0.1 µF anti-aliasing capacitors are placed next to the 78M6613’s ADC inputs pins sensing the Line voltage (in this case A0 and A2). Place the 1000 pF capacitor closest to the 78M6613. Provide a V3P3 plane in the GND layer under the voltage resistor network components. Excluding the 1 MΩ resistors, include the 750 Ω resistor, anti-aliasing capacitors and the A0 and A2 pins over this V3P3 plane. Surround these components with V3P3 copper on the V3P3 layer. Interconnect the top and bottom V3P3 planes with multiple vias to provide a low impedance shield. Figure 5: LINE Voltage Resistor Network R16 and R15 are the 1 MΩ resistors and C18 and C28 are the anti-aliasing filter components. V3P3 Plane Vias GND Plane V3P3 Plane V3P3 Plane Vias Figure 6: V3P3 Plane Sectioned Out of GND Layer Rev. 1.0 3 78M6613 Printed Circuit Board Layout Guidelines AN_6613_050 V3P3 Plane V3P3 Plane Vias V3P3 Plane Vias Figure 7: V3P3 Plane Shunt Current Sensor Place the shunt resistor and its associated filter components on the V3P3 layer. Provide adequate high-voltage isolation clearance around the shunt resistor. The 1000 pF and 0.1 µF anti-aliasing capacitors are placed next to the 78M6613’s current sensing input (A1 and A3) pins. Place the 1000 pF capacitor closest to the 78M6613. Provide a V3P3 plane in the GND layer under the shunt filter components. Excluding the shunt resistor, include the 750 Ω resistor, anti-aliasing capacitors and the A1 and A3 pins over this V3P3 plane. Surround these components with V3P3 copper on the V3P3 layer. Interconnect the top and bottom V3P3 planes with multiple vias to provide a low impedance shield. Figure 8: Shunt Current Sensor R10 is the shunt resistor and C15 and C27 are the anti-aliasing filter components. 4 Rev 1.0 AN_6613_050 78M6613 Printed Circuit Board Layout Guidelines Dual Outlet 2-Shunt Current Sensor Topology The 78M6613 supports two current sensors for dual outlet energy measurement applications. The same recommendations regarding isolation clearance, anti-aliasing filter component placement and V3P3 and GND plane shielding presented above apply to a dual-shunt printed circuit board layout. However, placement of the two shunts is a very critical printed circuit board layout consideration. The two shunts must be located adjacent and equidistant from their common NEUTRAL connection. The sheet resistance of the copper trace is not “insignificant” relative to the low-ohms value of the current sensing shunt. Any extra trace length or unequal trace length from the NEUTRAL connection to each of the two shunts will produce measurement errors. The following printed circuit board image (from a different evaluation board) shows two shunts in close proximity to their common NEUTRAL connector. Minimum and Equal-Distant Trace Lengths Common NEUTRAL Connector Figure 9: Dual Shunt Topology R15 and R20 are the two current sensing shunt resistors. The NEUTRAL connector hole is in the middle of the two surface mount pads for R15 and R20. V3P3 Decoupling Capacitors Place the 1000 pF and 0.1 µF capacitors next to the 78M6613’s V3P3A pin. Add a 22 µF bulk capacitor in the vicinity of the V3P3D pin. Use multiple vias to connect the V3P3 plane sectioned out of the GND layer to bridge across the V3P3 layer. For example, the A0, A1, A2, A3 signals create islands in the V3P3 layer. The lower layer V3P3 plane reconnects the top side V3P3 plane for a solid reference plane. V3P3 Plane Vias Figure 10: V3P3 Via Connections Rev. 1.0 5 78M6613 Printed Circuit Board Layout Guidelines AN_6613_050 In-Circuit Emulator Connector Minimize the trace lengths of the ICE signals. This minimizes EMI susceptibility reducing the need for additional suppression components. Place the ICE_EN pull-down resistor close to the 78M6613. Place its companion 1000 pF capacitor at the ICE connector. Systems Communication Interface Any systems communication interface (UART, SPI, I2C) between the 78M6613 and external circuitry must be isolated to accommodate the -3.3V disparity in their GND pins (or, in the event of a LINE reversal). Depending on various requirements, a minimum clearance barrier must exist under the isolating components. A gap of 3 mm is the minimum requirement. Verify the isolating component’s maximum barrier voltage meets your system requirements. 6 Rev 1.0 AN_6613_050 78M6613 Printed Circuit Board Layout Guidelines Appendix A – 78M6613 Evaluation Board Schematics . Components V3P3 TP10 TP SIP100P1 C3 1000pF 0603 VR1 MAX8881 SOT23-6 MAX8881EUT33+T-ND 1 +3.3V VIN FB 6 PCK GND VOUT TP11 TP SIP100P1 6 5 4 I2CRXD GND GND C7 0.1uF 0603 I2CCLOCK at shunt pads 6 5 4 R11 750 0603 1 C27 1000pF 0603 C15 0.1uF 0603 R12 750 0603 TP1 Wh SIP100P2 5 9 A2 A1 A3 A0 VREF NC1 2 RST 30 GND 6 7 8 C20 27pF 0603 RESET CKTEST TMUXOUT XIN 4 1 Y1 32.768KHz CM200S 535-9166-1-ND XOUT GND C21 27pF 0603 XIN TEST XOUT U5 78M6613-32 QFN32 GNDD GNDA RST MAX810S/SOT23 I2C_5V I2C_DAT I2C_CLK I2C_GND 1 I2CCKHDB AN 6 5 4 VCC COL EMT CAT 3 AN UARTTX UARTRX 15 13 CKT TMUX UARTTX UARTRX U8 PS9122 SOIC6 NEC R22 68 0603 1 V3P3 J10 ICE SIP100P6 CKT TMUX V3P3 ICEEN 3 AN CAT R13 470 0603 VCC COL EMT 6 5 4 TP3 DIO17 SIP100P2 2 1 TP4 1 2 3 4 5 6 7 DIO8 DIO15 DIO16 DIO17 DIO19 1 2 3 4 5 6 RXTX TCLK ERST LED1 DIO17 SIP100P2 MS 604-WP1503GD LED, Grn 6 5 4 VCC COL EMT CAT DIO7 14 29 J2 I2C SIP100P4 R6 330 0603 3 C14 0.1uF 0603 V3P3 1 2 3 4 C8 4.7uF 1206P 1 AN CAT V3P3 12 10 11 24 E_RXTX E_TCLK E_RST ICE_E VCC COL EMT U4 PS9122 SOIC6 NEC GND R19 330 0603 23 31 VCC GND 3 TX RX External 1.1K pullups on CLK and DATA 10KHz to 100KHz clock R4 330 0603 3 CAT R9 174 0603 22 25 26 27 28 18 19 20 17 21 DIO4 DIO5 DIO6 DIO7 DIO8 DIO14 DIO15 DIO16 DIO17 DIO19 U9 V3P3 3 32 16 C28 1000pF 0603 C18 0.1uF 0603 V3P3A V3P3D 3 1 2 4 IB LINEV 1 INPUT R23 750 0603 1 I2CTXLOB R8 10K 0603 C30 1000pF 0603 C25 0.1uF 0603 C6 NC 0603 1 AN VCC COL EMT USBGND USB5P U3 PS9122 SOIC6 NEC R7 174 0603 V3P3 V3P3 TP8 TP SIP100P1 1 Sensor connection at shunt pads C10 NC 0603 PULSE OUTPUT C29 1000pF 0603 C16 0.1uF 0603 J1 5VEXT RAPC712A MS 502-RAPC712 R1 NC 0603 C9 NC 0603 C26 0.1uF 0603 GND TP2 TP SIP100P1 V3P3 R10 0.004 1% 2.5W 2512P MS 66-ULR25R004FLFTR 1 2 3 C5 0.1uF 0603 1 U2 PS9122 SOIC6 NEC 1 2 CURRENT Sensor connection INPUT C12 1000pF 0603 GND 2 U1 PS9122 SOIC6 NEC V3P3 C13 C11 + 10uF 25V 1812 0.1uF 478-1762-1-ND 0603 GND GND VIN GND VGND Isolated DC/DC R5 2K 0603 R15 R16 J6 1M 0.1% 1M 0.1% CON4 1206W 1206W STERM MS 660-RN732BTTD1004B25 MS 534-8191 LINEE 1 Black 2 R18 3 750 0.1% 4 VOLTAGE 0603 J8 CON4 STERM MS 534-8191 4 GND NEUTRAL White 1 2 3 4 5 C2 4.7uF 1206P GND VB NUETI J4 CON4 STERM MS 534-8191 V5P0 C1 0.1uF 0603 GND 5 SHDN R3 2K 0603 J13 CON4 STERM MS 534-8191 1 2 3 4 C4 0.1uF 0603 GND Isolated Interface VR2 VBT1-5V VBT1 102-1397-2-ND R27 R26 1M 0.1% 1M 0.1% 1206W 1206W MS 660-RN732BTTD1004B25 VOLTAGE INPUT B J3 CON4 STERM MS 534-8191 1 2 3 4 High Voltage GND 1 1 2 3 4 System Components 2 1 1 J14 CON4 STERM MS 534-8191 1 2 3 4 Optional Measurement 3 4 R24 750 0603 J11 CON4 STERM MS 534-8191 78M6613 NC4 NC3 NC2 NC1 R25 0.004 1% 2.5W 2512P MS 66-ULR25R004FLFTR TP9 TP SIP100P1 8 7 6 3 1 GND 1 2 3 4 CURRENT INPUT B 2 J12 CON4 STERM MS 534-8191 1 2 3 4 C24 1000pF 0603 GND CON7 SIP100P7 LCD seg driv ers when ICEE low ICE inputs become GND GND MT3 MT2 MT1 MT4 MTGPS.PRT MS 561-PS500A MTGPS.PRT MS 561-PS500A MTGPS.PRT MS 561-PS500A LOGO1 LOGO2 1 MTGPS.PRT MS 561-PS500A 1 Warning MAXIM Figure 11: 78M6613 Evaluation Board Electrical Schematic (1 of 2) . R2 0 0603 USB5P USB5P UTX URX 1 2 3 4 J5 DEBUG SIP100P4 1.5M A/B White Cable Mouser 571-1487588-2 V2 V1 VIA VOA VOB VIB G2 ND1 1 2 3 4 GND U7 ADUM3201 ADUM3201 ADUM3201ARZ-ND CKT TMUX CKT TMUX 1 2 3 4 V3P3 J15 CON2 SIP100P2 USBRX USBTX 32 8 31 6 7 3 22 21 10 11 9 RXD TXD VCCIO VCC RTS CTS DTR DSR DCD RI USBDM USBDP CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 U6 FTQFN32 FT232QFN32 MS 895-FT232RQ J9 RTM SIP100P4 USBGND RESETB NC1 NC2 NC3 NC4 NC5 NC6 OSCI OSCO TEST GND3 GND2 GND1 AGND 8 7 6 5 UARTTX UARTRX R21 0 0603 1 2 V3P3 UARTTX UARTRX 2 30 3V3OUT 1 19 15 14 18 5 12 13 25 29 23 USB5V USBDM USBDP C22 4.7uF 1206P 1 2 3 4 5 6 J7 USB-B USBB MS 154-2442-E 27 28 16 26 20 17 4 24 R17 10K 0603 C19 0.1uF 0603 GND C23 0.1uF 0603 USBGND GND High Voltage Isolated Interface Figure 12: 78M6613 Evaluation Board Electrical Schematic (2 of 2) Rev. 1.0 7 Revision History Revision Date Description 1.0 10/29/2010 First publication. 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