ARMADA 16x Hardware Manual

Marvell® ARMADA 16x
Applications Processor Family
Hardware Manual
Doc. No. MV-S301545-00 Rev. A
May 2013
Marvell. Moving Forward Faster
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ARMADA 16x Applications Processor Family
Hardware Manual
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Doc. No. MV-S301545-00 Rev. A
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Table of Contents
1
Revision History .......................................................................................................................... 13
1
Introduction.................................................................................................................................. 19
1.1
Product Summary.............................................................................................................................19
1.2
Document Purpose...........................................................................................................................22
1.3
Number Representation ...................................................................................................................23
1.4
Naming Conventions ........................................................................................................................23
1.5
Applicable Documents......................................................................................................................23
2
Product Overview ........................................................................................................................ 25
3
Pin and Ball Map Views............................................................................................................... 27
4
5
6
7
3.1
ARMADA 168 (88AP168) Applications Processor 15mm x 15mm TFBGA Ball Map.......................27
3.2
ARMADA 166 (88AP166) Applications Processor 15mm x 15mm TFBGA Ball Map.......................28
3.3
ARMADA 162 (88AP162) Applications Processor 15mm x 15mm TFBGA Ball Map.......................29
Package Information ................................................................................................................... 31
4.1
Introduction.......................................................................................................................................31
4.2
Package Marking..............................................................................................................................32
4.3
Packaging Materials .........................................................................................................................32
4.4
ARMADA 16x Applications Processor Family 15mm x 15mm TFBGA Packaging...........................33
Maximum Ratings and Operation Conditions........................................................................... 35
5.1
Absolute Maximum Ratings..............................................................................................................35
5.2
Operating Conditions........................................................................................................................36
Electrical Specifications ............................................................................................................. 39
6.1
DC Voltage and Current Characteristics ..........................................................................................39
6.2
Oscillator Electrical Specifications....................................................................................................43
6.2.1
26.000 MHz Oscillator Specifications .................................................................................43
AC Electrical Characteristics ..................................................................................................... 47
7.1
DDR SDRAM Timing Diagrams and Specifications .........................................................................47
7.1.1
Measurement Conditions ...................................................................................................48
7.1.2
DDR SDRAM Timing Diagrams and Specifications ...........................................................48
7.1.3
DDR SDRAM Skew Timings ..............................................................................................52
7.2
Static Memory Controller Timing Diagrams and Specifications........................................................61
7.2.1
Address Cycle ....................................................................................................................61
7.2.2
Read Access Data Phases.................................................................................................62
7.2.3
Write Access Data Phases .................................................................................................66
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7.3
NAND Timing Diagrams and Specifications .....................................................................................72
7.3.1
NAND Flash Program Timing .............................................................................................72
7.3.2
NAND Flash Erase Timing .................................................................................................72
7.3.3
Small Block NAND Flash Read Timing ..............................................................................73
7.3.4
Large Block NAND Flash Read Timing ..............................................................................73
7.3.5
NAND Flash Status Read Timing .......................................................................................74
7.3.6
NAND Flash ID Read Timing .............................................................................................74
7.3.7
NAND Flash Reset Timing .................................................................................................75
7.3.7.1 NAND Flash Timing Parameters.................................................................................75
7.4
SD Host Controller (SDH) Timing Diagrams and Specifications ......................................................77
7.5
LCD Controller Timing Diagrams and Specifications .......................................................................78
7.5.1
LCD Smart Panel Timing and Specifications .....................................................................78
7.5.2
LCD Dumb Panel Timing and Specifications .....................................................................81
7.6
Quick Capture Camera Interface (CCIC) Timing Diagrams and Specifications ...............................84
7.6.1
CCIC Parallel Interface Timing Requirements ...................................................................84
7.7
SSP Timing Diagrams and Specifications ........................................................................................84
7.7.1
SSP Slave Mode Timing ....................................................................................................86
7.8
TWSI Timing Diagrams and Specifications ......................................................................................87
7.8.1
TWSI Test Circuit ...............................................................................................................89
7.9
AC ’97 Timing Diagrams and Specifications ....................................................................................90
7.10
JTAG Interface Timing Diagrams and Specifications .......................................................................90
7.10.1 JTAG Interface Timing Diagrams .......................................................................................91
7.10.2 JTAG Interface AC Timing Table .......................................................................................91
7.10.3 JTAG Interface Test Circuit ................................................................................................92
7.11
USB 2.0 Timing Diagrams and Specifications..................................................................................93
7.11.1 USB Interface Driver Waveforms .......................................................................................93
7.11.2 Differential Interface Electrical Characteristics ...................................................................94
7.11.2.1 USB Driver and Receiver Characteristics ...................................................................94
7.12
PCI Express Specifications ..............................................................................................................96
7.12.1 PCIE Differential TX Output Electrical Characteristics .......................................................96
7.12.2 PCIE Differential RX Input Electrical Characteristics..........................................................97
7.13
Ethernet MAC (MII) Timing Diagrams and Specifications ................................................................98
7.14
Powerup/Down Sequences ............................................................................................................100
7.14.1 Power Up Timings ............................................................................................................100
7.14.1.1 Host Side PMIC USB Signals ...................................................................................100
7.14.2 Powerdown Timings .........................................................................................................103
Design Guidelines and Checklist .............................................................................................105
8.1
DDR Interface General Routing Guidelines....................................................................................105
8.1.1
General Rules: .................................................................................................................105
8.1.1.1 Data and QS Signals ................................................................................................105
8.1.1.2 Address/Command Signals ......................................................................................106
8.1.1.3 Clock Signals ............................................................................................................106
8.1.2
DDR Interface Detailed Routing Guidelines .....................................................................106
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CONFIDENTIAL
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8.2
EPD Controller Design Guidelines .................................................................................................106
8.2.1
Introduction.......................................................................................................................107
8.2.2
Panel Power Up Sequence ..............................................................................................107
8.2.3
Display Common Power Signal ........................................................................................108
8.2.3.1 Vcom Setting by DPOT (Digital Potentiometer) ........................................................108
8.2.4
Source Driver Interface ....................................................................................................109
8.2.5
Gate Driver Interface ........................................................................................................111
8.2.6
Start Pulse Control ...........................................................................................................112
8.3
Schematic Checklist .......................................................................................................................113
Copyright © 2013 Marvell
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CONFIDENTIAL
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List of Figures
1
1
Introduction...................................................................................................................................... 19
2
Product Overview ............................................................................................................................ 25
Figure 1:
3
4
5
6
Pin and Ball Map Views................................................................................................................... 27
Figure 2:
ARMADA 168 (88AP168) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top View.....28
Figure 3:
ARMADA 166 (88AP166) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top View.....29
Figure 4:
ARMADA 162 (88AP162) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top View.....30
Package Information ....................................................................................................................... 31
Figure 5:
Sample Package Marking .................................................................................................................32
Figure 6:
ARMADA 16x Applications Processor Family 15mm x 15mm TFBGA Package Information...........33
Maximum Ratings and Operation Conditions ............................................................................... 35
Electrical Specifications ................................................................................................................. 39
Figure 7:
7
ARMADA 16x Applications Processor Family Block Diagram ..........................................................26
Recommended GND Shielding to xtal_in and xtal_out.....................................................................44
AC Electrical Characteristics.......................................................................................................... 47
Figure 8:
Differential Clock...............................................................................................................................48
Figure 9:
SDRAM Timing Diagrams 1..............................................................................................................49
Figure 10:
SDRAM Timing Diagrams 2..............................................................................................................49
Figure 11:
SDRAM Timing Diagrams 3..............................................................................................................50
Figure 12:
SDRAM Timing Diagrams 4..............................................................................................................50
Figure 13:
Basic Write Timing Parameters ........................................................................................................51
Figure 14:
DDR3 SDRAM Timing Diagrams ......................................................................................................52
Figure 15:
DQ to DQS Write Skew ....................................................................................................................53
Figure 16:
CLK to Address/Command Write Skew ............................................................................................53
Figure 17:
DQS to CLK Write Skew ...................................................................................................................53
Figure 18:
DQ to DQS Read Skew ....................................................................................................................54
Figure 19:
Reference Load ................................................................................................................................60
Figure 20:
A/D Address Phase ..........................................................................................................................61
Figure 21:
AA/D Address Phase ........................................................................................................................62
Figure 22:
Asynchronous Read With RDY Signal..............................................................................................63
Figure 23:
Asynchronous Read Without RDY Signal.........................................................................................64
Figure 24:
Synchronous Read With RDY Signal ...............................................................................................65
Figure 25:
Synchronous Read Without RDY Signal ..........................................................................................66
Figure 26:
Asynchronous Write With RDY Signal ..............................................................................................67
Figure 27:
Asynchronous Write Data Phase Without RDY Signal .....................................................................68
Figure 28:
Synchronous Write With RDY Signal................................................................................................69
Figure 29:
Synchronous Write Data Phase Without RDY Signal .......................................................................70
Copyright © 2013 Marvell
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ARMADA 16x Applications Processor Family
Hardware Manual
Figure 30:
8
NAND Flash Program Timing Diagram.............................................................................................72
Figure 31:
NAND Flash Erase Timing Diagram .................................................................................................73
Figure 32:
NAND Flash Small Block Read Timing Diagram ..............................................................................73
Figure 33:
NAND Flash Large Block Read Timing Diagram ..............................................................................74
Figure 34:
NAND Flash Status Read Timing Diagram.......................................................................................74
Figure 35:
NAND Flash ID Read Timing Diagram .............................................................................................75
Figure 36:
NAND Flash Reset Timing Diagram .................................................................................................75
Figure 37:
MultiMedia Card Timing Diagrams....................................................................................................77
Figure 38:
Smart Panel Interface 8-bit 8080-Series Parallel Mode Read Interface Protocol .............................79
Figure 39:
Smart Panel Interface 8-bit 8080-Series Parallel Mode Write Interface Protocol .............................79
Figure 40:
Smart Panel Interface 8-bit 6800-Series Parallel Mode Read Interface Protocol .............................80
Figure 41:
Smart Panel Interface 8-bit 6800-Series Parallel Mode Write Interface Protocol .............................80
Figure 42:
SPI Write/Read Protocol ...................................................................................................................81
Figure 43:
Dumb LCD Panel Horizontal Timing .................................................................................................82
Figure 44:
Dumb LCD Panel Vertical Timing .....................................................................................................82
Figure 45:
Parallel Timing Diagram ...................................................................................................................84
Figure 46:
SSP Master Mode Timing Diagram ..................................................................................................85
Figure 47:
SSP Slave Mode Timing Definitions .................................................................................................86
Figure 48:
TWSI Output Delay AC Timing Diagram...........................................................................................87
Figure 49:
TWSI Output Delay AC Timing Diagram...........................................................................................87
Figure 50:
TWSI Test Circuit..............................................................................................................................89
Figure 51:
AC ’97 CODEC Timing Diagram.......................................................................................................90
Figure 52:
JTAG Interface Output Delay AC Timing Diagram ...........................................................................91
Figure 53:
JTAG Interface Input AC Timing Diagram ........................................................................................91
Figure 54:
JTAG Interface Test Circuit ..............................................................................................................92
Figure 55:
Low/Full Speed Data Signal Rise and Fall Time ..............................................................................93
Figure 56:
High Speed TX Eye Diagram Pattern Template ...............................................................................93
Figure 57:
High Speed RX Eye Diagram Pattern Template...............................................................................94
Figure 58:
MII Tx Mode Interface Timing Diagrams...........................................................................................98
Figure 59:
MII Rx Model Interface Timing Diagrams..........................................................................................99
Figure 60:
MII Management Interface Timing Diagrams....................................................................................99
Figure 61:
Power-Up Reset Timing..................................................................................................................102
Figure 62:
Powerdown Timing .........................................................................................................................104
Design Guidelines and Checklist ................................................................................................. 105
Figure 63:
Panel Power Sequence ..................................................................................................................108
Figure 64:
DPOT Programming Sequence ......................................................................................................109
Figure 65:
Source Driver Connections .............................................................................................................110
Figure 66:
Source Driver Timing ......................................................................................................................111
Figure 67:
Gate Driver Connections ................................................................................................................112
Figure 68:
Gate Driver Output Enable Timing..................................................................................................112
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ARMADA 16x Applications Processor Family
Hardware Manual
List of Tables
1
Introduction....................................................................................................................................... 19
Table 1:
ARMADA 16x Applications Processor Family Feature Breakdown ..................................................20
Table 2:
ARMADA 16x Applications Processor Family Hardware Features2.................................................20
Table 3:
Supplemental Documentation...........................................................................................................23
2
Product Overview ............................................................................................................................. 25
3
Pin and Ball Map Views.................................................................................................................... 27
4
Package Information ........................................................................................................................ 31
5
6
7
Table 4:
Package Materials ............................................................................................................................32
Table 5:
TFBGA Package Dimensions ...........................................................................................................34
Maximum Ratings and Operation Conditions ................................................................................ 35
Table 6:
Absolute Maximum Ratings ..............................................................................................................35
Table 7:
Voltage, Temperature, and Frequency Electrical Specifications ......................................................36
Electrical Specifications .................................................................................................................. 39
Table 8:
LPDDR1/LPDDR2 Input, Output and I/O pins AC/DC Operating Conditions ...................................39
Table 9:
DDR3 Input, Output, and I/O Pins AC/DC Operating Conditions......................................................40
Table 10:
MFP Input, Output, and I/O Pins DC Operating Conditions..............................................................41
Table 11:
Typical 26.000 MHz Crystal Requirements.......................................................................................44
Table 12:
Typical External 26.000 MHz Oscillator Requirements.....................................................................44
AC Electrical Characteristics...........................................................................................................47
Table 13:
Standard Input, Output, and I/O-Pin AC Operating Conditions ........................................................48
Table 14:
Clock Parameters .............................................................................................................................48
Table 15:
DDR Timing Specifications ...............................................................................................................54
Table 16:
DDR Timing Specifications for 533 MHz (VDD_M = 1.8V) ...............................................................55
Table 17:
DDR Timing Specifications for 400 MHz (VDD_M = 1.8V) ...............................................................56
Table 18:
DDR Timing Specifications for 200 MHz (VDD_M = 1.8V) ...............................................................58
Table 19:
DDR3 Timing Specifications for 533 Mhz (VDDQ=1.5V)..................................................................59
Table 20:
DDR3 Setup/Hold Derating table ......................................................................................................60
Table 21:
Static Memory Controller Interface Timing Specifications ................................................................70
Table 22:
NAND Flash Interface Program Timing Specifications .....................................................................76
Table 23:
MultiMedia Card Timing Specifications.............................................................................................77
Table 24:
SD/SDIO Timing Specifications ........................................................................................................78
Table 25:
LCD Smart Panel Controller Timing .................................................................................................81
Table 26:
LCD Dumb Panel Timing1 ................................................................................................................82
Table 27:
CCIC Parallel Timing ........................................................................................................................84
Table 28:
SSP Master Mode Timing Specifications..........................................................................................85
Table 29:
SSP Slave Mode Timing Specifications............................................................................................86
Table 30:
TWSI Master AC Timing Table (Standard Mode 100 kHz) ...............................................................87
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Table 31:
TWSI Master AC Timing Table (Fast Mode 400 kHz).......................................................................88
Table 32:
TWSI Master AC Timing Table(high speed 3.4 MHz).......................................................................89
Table 33:
AC ’97 CODEC Timing Specifications ..............................................................................................90
Table 34:
JTAG Interface 10 MHz AC Timing1 ................................................................................................91
Table 35:
USB Low Speed Driver and Receiver Characteristics1 ....................................................................94
Table 36:
USB Full Speed Driver and Receiver Characteristics1.....................................................................95
Table 37:
USB High Speed Driver and Receiver Characteristics1 ...................................................................96
Table 38:
PCI Express TX Output Electrical Specifications..............................................................................97
Table 39:
PCI Express RX Input Electrical Specifications ................................................................................97
Table 40:
MII Tx Mode Interface Timing Specifications ....................................................................................98
Table 41:
MII Rx Mode Interface Timing Specifications ...................................................................................99
Table 42:
MII Management Interface Timing Specifications .............................................................................99
Table 43:
Terminology ....................................................................................................................................100
Table 44:
Power-Up Timing Specifications .....................................................................................................102
Table 45:
PowerdownTiming Specifications ...................................................................................................104
Design Guidelines and Checklist ..................................................................................................105
Table 46:
Source Driver Signals .....................................................................................................................109
Table 47:
Output Gate Driver Signals .............................................................................................................111
Table 48:
ARMADA 16x Applications Processor Family Schematic Checklist ...............................................113
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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May 2013 PUBLIC RELEASE
Revision History
Revision 4.1, Release - / (August 13, 2010)
Revision History
Public Release, Revision A / (May 2013)
PCB Design Guidelines

Changed entry in Table 46 of Section 8.3 Schematic Checklist. VREF was listed as VDDQ
+/-1% but has been corrected to read VDDQ/2 +/-1%.
Public Release, Release - / (November 2010)
Electrical Specs

Added Table 9 for DDR3 AC/DC info
Pin and Ball Map Views



Added nDDR_RESET, ODT1, SDCKE1, nSDCS1 and SEC_CS_EN to Armada 166/E and
Armada 162 ball maps.
Added Armada 166E (88AP166E) application processor name to the Armada 166 ball map
Removed Armada 160 pin map.
Schematic Review Checklist




Added not for PXTAL_IN and PXTAL_OUT capacitors
Updated SEC_CS_EN recommendations
Added nDDR_RESET, nSDCS1, ODT1 and SDCKE1
Added additional note to nDQS<1:0> recommendation
Revision 4.1, Release - / (August 13, 2010)
Introduction


Updated ARMADA 16x Applications Processor Family Feature Breakdown table to change
Maximum Marvell® Sheeva™ PJ1 Core Speed for ARMADA 168 to 1.066 GHz.
Updated ARMADA 16x Applications Processor Family Hardware Features table to remove
support for booting from UART.
Pin and Ball Map Views

Updated 88AP168 ball map to change V14 into an RFU.
Package Information




Updated ARMADA 16x Application Processor Family 15mm x 15mm TFBGA Package
Information figure and changed Note 2 BGA Solder ball pad from 0.37mm SMD to 0.4mm SMD.
Removed “Dimensions in Inches” columns from Package Dimensions tables.
Maximum Ratings and Operation Conditions
Changed minimum ramp rate on VDD_CORE to 10 mV/µs
Electrical Specifications


Updated DDR DC characteristics table and changed the specs.
Changed the Vhys numbers.
NAND Timing Diagrams and Specifications

Updated numbers in NAND Flash Interface Program Timing Specs Table\
SD Host Controller (SDH) Timing Diagrams and Specifications
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 13
Marvell® ARMADA 16x Applications Processor Family Hardware Manual


Updated MultiMedia Card Timing Diagrams figure and removed rise and fall time parameters.
Updated numbers in the specification tables.
LCD Controller Timing Diagrams and Specifications


Updated LCD Smart Panel Controller Timing Table
Updated LCD Dumb Panel Timing Table and added parameters.
Quick Capture Camera Interface (CCIC) Timing Diagrams and Specs

Changed timing numbers in CCIC Parallel Timing register and reduced the maximum PCLK
frequency to 78 MHz.
SSP Timing Diagrams and Specifications

Changed timing numbers in SSP Master Mode Timing Specifications and SSP Slave Mode
Timing Specifications Tables.
JTAG Interface Timing Diagrams and Specifications

Updated JTAG signal names
USB 2.0 Timing Diagrams and Specifications

Updated USB High Speed Driver and Receiver Characteristics Table
PCI Express Specifications






Updated section to add reference to PCI Express Base Specification Revision 1.1
Added a typical value for CTX.
Changed RLRX_DIFF from 15 to 10 dB
Removed CTX row from the PCI Express RX Input Electrical Specifications Table
Ethernet MAC (MII) Timing Diagrams and Specifications
Updated MII Management Interface Timing Specifications Table to switch Tva and Tvb symbol
locations.
Revision 4.0, Release B / (July 23, 2010)









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
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


Updated Table 1 with ARMADA 160 SKU information
Minor editorial updates to Table 2
Added ARMADA 160 block diagram
Updated solder ball info for Table 4
Removed individual unit chapters and created AC timing chapter that includes AC timing for
each interface.
Added new chapter for Design Guidelines and schematic checklists and updated routing
guideline section.
Added ARMADA 160 pin map to Pin and Ball map chapter
Updated Package Material section.
Added ARMADA 160 package information to the Package Information chapter
Removed Power Consumption section
Updated LCD AC timing section and moved to AC chapter.
Moved EPD design guidelines to Design guidelines section
Updated DDR AC timing section and moved to AC chapter
Updated the NAND AC timing section and moved to AC chapter
Updated Static Memory Controller AC timing section and moved to AC chapter
Added USB AC timing information to the AC chapter
Updated SSP AC timing information and moved to AC chapter
Added TWSI AC timing information to AC chapter
Doc. No. MV-S301545-00 Rev. A
Page 14
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Revision History
Revision 4.0, Release A / (June 16, 2010)







Moved AC97 AC timing information to AC chapter
Updated Quick Capture Camera Interface (CCIC) AC timing information and moved to AC
chapter
Updated SD Host AC timing information and moved to AC chapter
Updated JTAG AC timing information and moved to AC chapter
Added the USB AC timing information to the AC chapter.
Added PCIE AC timing information to the AC chapter
Updated Powerdown Timing information
Revision 4.0, Release A / (June 16, 2010)
Chapter 6 Maximum Ratings and Operating Conditions

Table 7 updated (Rev. 4.0 Rel. - did not capture this updated table in the correct file)
Revision 4.0, Release - / (June 14, 2010)
Chapter 4 Packaging

Added Product Marking diagram

Updated Package Material table
Chapter 5 Pin Listing and Signal Definition

Chapter removed as it is duplicate of that in Software manual
Chapter 6 Maximum Ratings and Operating Conditions

Updated the VDD_CORE voltage settings in Table 7

Updated the thermal data in Table 7
Chapter 7 Electrical Specifications

Updated the notes at the beginning of Table 14 MFP Input, Output, and I/O Pins DC Operating
Conditions

Added Input DC Operating Condition notes at the beginning of Table 14 MFP Input, Output, and
I/O Pins DC Operating Conditions
Chapter 13 EPD

Chapter added
Chapter 35 PCB Routing Guidelines

Chapter updated
Revision 3.0, Release B / (February 18, 2010)
Chapter 2 Overview

Updated block diagram to reflect addition of EPD component
Chapter 3 Ball Map

Updated ball maps for Figure 4 (PXA166) and Figure 5 (PXA162)
Chapter 5 Pin Listing and Signal Definition

Minor updates to Table 8 and Table 9 PXA166 TFBGA Pin List with Alternate Functions
Chapter 33 Temperature Sensor: Removed
Chapter 35 Power and Reset Specifications

Updated Power-up Reset Timing figure (Figure 61) and Power-up Timing Spec table (Table 38)
Revision 3.0, Release A / (November 11, 2009)
Chapter 5 Pin Listing and Signal Definition

Minor updates to all Alternate Function tables (matches Alternate Function Spreadsheet)
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 15
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Chapter 35 Power and Reset Specifications

Minor changes from 3.0 Rev -
Revision 3.0, Release - / (November 5, 2009)
Chapter 5 Pin Listing and Signal Definition

Minor updates to all Alternate Function tables
Chapter 35 Power and Reset Specifications

Minor change to Figure 62 and Table 39
Revision 2.9, Release - (October 8, 2009)
Chapter 1 Introduction

Added “Special Note” that not all devices have external hardware connection.
Chapter 2 Product Overview (both manuals):

Replaced PXA16x block diagram (Figure 1).
Chapter 5 Pin Listing and Signal Definition

Added RT_SEN to signal list (was present on ballmap in previous revs but not in signal list).
Chapter 6 2-D Graphics Controller

Added note to refer to Vivante GC300 Controller documentation available on extranet.
Chapter 8 Electrical Specifications:

Added undershoot/overshoot information to Table 13, Input DC Operating Conditions (Vcc =
1.8V Typical) heading and Input DC Operating Conditions (Vcc = 3.0V and 3.3V Typical)
heading (This information was mistakenly added to Table 14 in previous hardware manual
revision and in Revs L, M of the Spec Update)

Removed Notes 1,2 and 5 from Table 13.

Added Figure 8 Recommended GND shielding to xtal_in and xtal_out.
Chapter 9 Internal Memory Controller

Added note that the IMC has no external hardware connection.
Chapter 11 Real-Time Clock

Added note that the RTC has no external hardware connection.
Chapter 18 USB OTG

Removed code from chapter and pasted into corresponding chapter in PXA16x SW Manual.
Chapter 19 Fast Ethernet MAC

Added Fig. 44 Ethernet/MAC/PHY Connection.
Chapter 32 GPIO Controller

Added link to alternate function spreadsheets in Chapter 5.
Chapter 35 Power and Reset Timings:

Replaced Figure 58 Timing Diagram with an updated version
Revision 2.86, Release - / (August 19, 2009)
Chapter 15 DDR Controller:

Replaced Chapter 15 DDR from Release 2.85 with correct one for 2.86.
Revision 2.85, Release B
Chapter 2 Overview:

Replaced PXA128/PXA16x Application Processor Family block diagram with updated diagram
Chapter 5 Pins and Signals:
Doc. No. MV-S301545-00 Rev. A
Page 16
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Revision History
Revision 2.85, Release B / (August 10, 2009)


Changed entry for SSPSYCLK to ASYSCLK and updated definition in Table 4
Updated Table 4 entry for AVDD5_USB
NOTE: The following items were NOT present in Interim Release 2.85 but are present in 2.85b.

Removed EXT_WAKEUP from Table 5. The pin exists but there isn’t an alternate function for
EXT_WAKEUP that does anything.

Renamed the IPOD_ signals into CCIC_ to get away from IPOD

Made all PMW references PWM0 – 3 instead of 1-4 in the description field

Moved USBHPEN from USB Host to USB OTG and changed description.

Changed USBVBUS description

Moved PWR_I2C signals from Power and Reset signals to the TWSI section

Moved A_ISET from the Power and Reset signals to the USB OTG section.

Updated PXA168 alternate Functions

Added PXA166 alternate functions table

Added PXA162 alternate functions table

Added PXA128 alternate functions table – The other one was for a previous PXA128 package
Revision 2.85, Release B / (August 10, 2009)
Chapter 2 Overview:

Replaced PXA128/PXA16x Application Processor Family block diagram with updated diagram
Chapter 5 Pins and Signals:

Changed entry for SSPSYCLK to ASYSCLK and updated definition in Table 4

Updated Table 4 entry for AVDD5_USB
NOTE: The following items were NOT present in Interim Release 2.85 but are present in 2.85b.

Removed EXT_WAKEUP from Table 5. The pin exists but there isn’t an alternate function for
EXT_WAKEUP that does anything.

Renamed the IPOD_ signals into CCIC_ to get away from IPOD

Made all PMW references PWM0 – 3 instead of
1-4 in the description field

Moved USBHPEN from USB Host to USB OTG and changed description.

Changed USBVBUS description

Moved PWR_I2C signals from Power and Reset signals to the TWSI section

Moved A_ISET from the Power and Reset signals to the USB OTG section.

Updated PXA168 alternate Functions

Added PXA166 alternate functions table

Added PXA162 alternate functions table

Added PXA128 alternate functions table – The other one was for a previous PXA128 package.
Revision 2.85, Release A / (July 31, 2009)
Overall: updated variables, cross-references, general editing
Chapter 1 Introduction:

Updated tables with part numbers

Removed mDOC support, DDR3; added LVDDR2

Added NOTE at end of chapter to refer to Spec Update for content revisions between
documentation releases
Chapter 3 Pin and Ballmap Views (Hardware Manual):

Updated PXA168 ballmap for A0 silicon

Added PXA166 ballmap for A0

Added PXA162 ballmap for A0
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 17
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Chapter 5 Pins and Signals:

Removed EXT_WAKEUP from Table 5. The pin exists but there isn’t an alternate function for
EXT_WAKEUP that does anything.

Renamed the IPOD_ signals into CCIC_ to get away from IPOD

Made all PMW references PWM0 – 3 instead of
1-4 in the description field

Moved USBHPEN from USB Host to USB OTG and changed description.

Changed USBVBUS description

Moved PWR_I2C signals from Power and Reset signals to the TWSI section

Moved A_ISET from the Power and Reset signals to the USB OTG section.

Updated PXA168 alternate Functions

Added PXA166 alternate functions table

Added PXA162 alternate functions table

Added PXA128 alternate functions table – The other one was for a previous PXA128 package.

Updated Alternate Function Table for PXA168 15mm x 15mm TFBGA Pin List for the entry for
Alt Func 0/EXT_WAKEUP (changed to “Not Valid”)
Chapter 7 Maximum Ratings and Operating Conditions

Changed Max value of Vcccore_1 (AVDD Core Voltage) from 1.1 to 1.154 V
Chapter 16 NAND Flash Controller:

Changed description for Table 21, entry tdh
Chapter 17 Static Memory Controller

Updated bullet under Section 17.1 on Asynchronous/Synchronous Read/Write speeds from 52
MHz to 62.4 MHz
Chapter 33 Temperature Sensor

Added this new chapter (also available as an Application Note (MV-S301707-00)
Chapter 36 PCB Guidelines (Hardware Manual)

Added routing guidelines for DDR interface (Note: this section is NOT in the DDR chapter as
suggested by the Spec Update)

Doc. No. MV-S301545-00 Rev. A
Page 18
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Introduction
Product Summary
1
Introduction
Here’s how to correlate the various Public Release versions of Marvell® ARMADA 16x
Applications Processor Family documentation:
Note
Rev. - : signifies initial version of any release.
Rev. A: first revision of any release.
Rev. B: second revision of any release.
Rev. B1: first minor revision of Rev. B, usually to correct documentation errors not
attributed to engineering changes.
This chapter describes:





Section 1.1, Product Summary
Section 1.2, Document Purpose
Section 1.3, Number Representation
Section 1.4, Naming Conventions
Section 1.5, Applicable Documents
The Marvell® ARMADA 16x Applications Processor Family (also referred to as the ARMADA 16x
Applications Processor Family) is a high-performance and highly integrated family of devices
optimized for digital picture frames, personal media players, and other personal consumer devices.
Featuring an advanced 1 GHz processor ARM v5TE-compatible core with an integrated 2-D
graphics engine, the ARMADA 16x Applications Processor Family offers performance headroom
and flexibility for today and future applications. The common software base provides a scalable
platform to cover a breadth of product offerings.
Multiple complete turn-key hardware/software reference designs are available for digital picture
frame, personal navigation, and portable media applications for rapid development and quick time to
market. The digital picture frame platform is based on the optimized chipset of the ARMADA 16x
Applications Processor Family, Marvell Power Management IC, and Marvell Wi-Fi component. Ideal
for digital picture frame applications, the ARMADA 16x Applications Processor Family-based
platform delivers fast response time for sophisticated user interfaces, image processing, and
multimedia applications. Software supports multiple A/V standards and photo-editing capabilities for
pan, zoom, and media effects. The ARMADA 16x Applications Processor Family is designed for high
performance and low power, delivering extended battery life for personal consumer devices.
1.1
Product Summary
The ARMADA 16x Applications Processor Family comprises several products. These products
support a variety of options for packaging, speed, on-chip cache and peripheral support. Table 1
shows a breakdown of the ARMADA 16x Applications Processor Family and the options available.
Refer to Table 2 for the basic features of the ARMADA 16x Applications Processor Family.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 19
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 1:
ARMADA 16x Applications Processor Family Feature Breakdown
ARMADA 162
ARMADA 166
ARMADA 166E
ARMADA 168
Package
BGA-320
BGA-320
BGA-320
BGA-320
Max CPU Speed
400 MHz
800 MHz
800 MHz
1.066 GHz
Yes
Yes
Yes
Yes
LP-DDR1-200
DDR2-400
DDR3-400
LP-DDR1-200
DDR2-800
DDR3-800
LP-DDR1-200
DDR2-800
DDR3-800
LP-DDR1-200
DDR2-1066
DDR3-1066
L1, L2 Caches
32/32/64 KB
32/32/128 KB
32/32/128 KB
32/32/128 KB
LCD Max Res,
Color
XGA 24bpp
WUXGA 24bpp
WUXGA 24bpp
WUXGA 24bpp
2D and Qdeo™
ICR
Yes
Yes
Yes
Yes
WMMX2
Memory
(x16 DRAM)
USB2.0 HS + PHY*
1 OTG, 1 host
1 OTG, 1 host
1 OTG, 1 host
1 OTG, 1 host
xD Picture Card
Yes
Yes
Yes
Yes
CompactFlash+
Yes
Yes
Yes
Yes
FE MAC
-
Yes
Yes
Yes
PCIe2.0 x1 Lane
-
-
-
Yes
ElectroPhoretic
Display (EPD)
-
-
Yes
-
Table 2:
ARMADA 16x Applications Processor Family Hardware Features2
F ea t u r e G r o u p
F e at u r e
Marvell® Sheeva™ Core
and Internal Memory
Marvell® Sheeva™
MULTIMEDIA
D e s c r i p t io n
Embedded CPU
ARM* v5TE instruction set compliant
Technology
L1 Instruction and Data Cache
32 KB I$ + 32 KB D$
L2 Cache
128 KB
Internal Boot ROM
Support boot from 8-bit NAND, 16-bit NAND,
MMC, SD, OneNAND, SLC, MLC NAND,
SSP SPI, and XIP
Multimedia acceleration with WMMX
•
Decode H.264 up to WVGA and
MPEG-4 up to 720p
•
•
•
•
Scaling
Color Space Conversion
Overlaying
Rotation
Hardware 2D graphics
Doc. No. MV-S301545-00 Rev. A
Page 20
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Introduction
Product Summary
Table 2:
ARMADA 16x Applications Processor Family Hardware Features2
F ea t u r e G r o u p
F e at u r e
D e s c r i p t io n
2D Graphics
Bit blt
Qdeo™ Intelligent Color Remapping
•
•
Qdeo™ ICR enhances color to make
vivid images without hue shifts or
clipping
Part of the award-winning Qdeo suite of
video processing
CCIR-656 Camera Interface
•
•
Up to WUXGA (1920x1200)
16-, 18- or 241-bpp color depth
DDR Memory Controller
•
•
•
2 Chip Selects
16-bit DDR2/DDR3 at up to 533 MHz
LP-DDR1
Static Memory Controller
•
•
•
2 Chip Selects
AA/D and A/D Muxed Mode support
Support for VLIO or Companion Chips
NAND Memory Controller
•
•
•
2 Chip Selects
SLC and MLC NAND
x8 and x161 small block and large block
Compact Flash Controller
•
•
2 Chip Selects
Compliant with CompactFlash (CF+)
Spec 4.1
xD Card Controller
•
•
1 Chip Select
Compliant with xD-Picture Card
Specification Version 1.20
MultiMediaCard/SD/SDIO Card and
MS/MSPRO Controller
•
•
Up to 4 MMC/SD/SDIO Controllers
1 Memory Stick Pro Controller w/ support
for 1 Card and support serial interface
and 4-bit parallel interface
LCD Controller
DMA
EXTERNAL MEMORY
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
DMA Controller Interface
Doc. No. MV-S301545-00 Rev. A
Page 21
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 2:
ARMADA 16x Applications Processor Family Hardware Features2
F ea t u r e G r o u p
F e at u r e
D e s c r i p t io n
PERIPHERALS
USB 2.0 Host Controller
1 High-Speed USB2.0 Host with integrated
transceiver
USB 2.0 OTG Controller
1 High-Speed USB2.0 OTG with integrated
transceiver and boot support
Fast Ethernet Interface
•
•
•
MII interface support 10/100 Ethernet
Operation
MDC/MDIO interface for external PHY
control
•
•
Up to 52 MHz with Master and Slave
modes for frame sync and bit clock
I2S support
Up to 5 general purpose SSPs
Universal Asynchronous Serial Port
Controller
•
•
3 UART Controllers
Up to 3.6 Mbps data rate
Two Wire Serial Bus Interface (TWSI)1
•
•
Interfaces to TWSI* peripherals
Up to 3.4 Mbps with 7-bit addressing
Power Two Wire Serial Bus Interface
(PWR_TWSI)1
•
•
Interfaces to TWSI* peripherals
Up to 400 kbps with 7-bit addressing
JTAG Controller
JTAG support for debugging and testing
Program Flash
Pulse Width Modulator (PWM) Controller
4 PWM Controllers
HW Timers
•
AC ‘97 Interface
Supports the Audio CODEC’97 Component
Specification, Revision 2.3
One-Wire Interface
Serial bus operation to receive/transmit
1-Wire bus data
Keypad Controller
•
•
General Purpose Input/Output (GPIO)
Controller
Up to 123 Multi-Function Pins with alternate
GPIO functionality
Synchronous Serial Port Controller
•
Provides three 32-bit General Purpose
Timers
Provides one 16-bit Watchdog timer
Support for up to 8x8 Matrix Keys
Support for up to 8 Direct Keys
1. Two-Wire Serial Interface (formerly referred to as I2C)
2. Not all features may be present in all SKUs - contact your Marvell sales rep.
1.2
Document Purpose
This document constitutes the hardware specifications for the ARMADA 16x Applications Processor
Family, including electrical, mechanical, and thermal information, functional overview, mechanical
data, package signal locations, targeted electrical specifications, functional bus waveforms, and
board design considerations. For software specifications including register programming
information, refer to the Marvell® ARMADA 16x Application Processor Family Software Manual
(MV-S301544-00).
SPECIAL NOTE: Not all of the devices listed in this hardware manual have external hardware
connections. Refer to the software manual (MV-S301544-00) for more information.
Doc. No. MV-S301545-00 Rev. A
Page 22
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Introduction
Number Representation
1.3
Number Representation
All numbers in this document are decimal (base 10) unless designated otherwise. Hexadecimal
numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is
represented as 0x6B in hexadecimal and 0b110_1011 in binary.
1.4
Naming Conventions
All signal and register-bit names appear in uppercase. Active low items are prefixed with a
lowercase “n”.
Pins within a signal name are enclosed in angle brackets:
EXTERNAL_ADDRESS<31:0>
nCS<1>
Bits within a register bit field are enclosed in square brackets:
REGISTER_BITFIELD[3:0]
REGISTER_BIT[0]
Single-bit items have either of two states:
Clear — the item contains the value 0b0
Set — the item contains the value 0b1


1.5
Applicable Documents
Table 3 lists supplemental information sources for the ARMADA 16x Applications Processor Family.
Contact a Marvell representative for the latest document revisions and ordering instructions.
Table 3:
Supplemental ARMADA 16x Applications Processor Family
Documentation, Releases, and Availability
D o c um e n t Ti tle
Av a i la b le
ARMADA 16x Applications Processor Family Hardware Manual (MV-S301545-00)
Public Release Available
Now
ARMADA 16x Applications Processor Family Software Manual (MV-S301544-00)
Public Release Available
Now
ARMADA16x Applications Processor Family Alternate Function Spreadsheet
Now
ARMADA 16x Applications Processor Family Boot ROM Reference Manual
Public Release Available
Now
ARMADA 16x Applications Processor Family PMIC Application Note
Now
USB 2.0 PHY Calibration/ Compliance Guidelines for ARMADA 16x Applications
Processor Family (MV-S301722-00)
Now
ARMADA 16x Applications Processor Family JTAG Application Note
(MV-S301720-00)
Now
ARMADA 16x Applications Processor Family Board Design and Layout Guidelines
(MV-S301721-00)
Now
ARMADA 16x Applications Processor Family Temperature Sensor App Note
(MV-S301707-00)
Now
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 23
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 3:
Supplemental ARMADA 16x Applications Processor Family
Documentation, Releases, and Availability (Continued)
D o c um e n t Ti tle
ARMADA16x Applications Processor Family Spec Update(s)
Av a i la b le
Spec Updates
are released
periodically
Check the Marvell website for the latest versions of available documents
Note
Doc. No. MV-S301545-00 Rev. A
Page 24
Refer to the Marvell® ARMADA 16x Applications Processor Family Specification
Update (MV-S501140-00) for corrections and updates to content between
documentation releases. The specification update is revised on a periodic basis.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Product Overview
2
Product Overview
The ARMADA 16x Applications Processor Family application is an integrated system-on-a-chip
microprocessor targets mid- to high-end picture frame, personal navigation devices, and
smart-monitor applications, among others. It incorporates the Marvell® Sheeva™ Embedded CPU
Technology microarchitecture with sophisticated power management to provide optimum MIPS/mW
performance across its wide range of operating frequencies. The ARMADA 16x Applications
Processor Family complies with the ARM* Architecture V5TE instruction set (excluding floating point
instructions) and follows the ARM* programmers model. The ARMADA 16x Applications Processor
Family multimedia coprocessor provides enhanced Intel® WMMX 2 instructions to accelerate audio
and video processing. The ARMADA 16x Applications Processor Family is available in a discrete
package configuration.
The ARMADA 16x Applications Processor Family memory architecture provides greater flexibility
and higher performance than that of previous products. The ARMADA 16x Applications Processor
Family provides the configuration support for two dedicated memory interfaces to support
high-speed DDR SDRAM, VLIO devices, and NAND Flash devices. This flexibility enables high
performance “store and download” as well as “execute-in-place” system architectures. The
ARMADA 16x Applications Processor Family memory architecture features a memory switch that
allows multiple simultaneous memory transactions between different sources and targets. For
example, the ARMADA 16x Applications Processor Family architecture allows memory traffic
between the core and DDR SDRAM to move in parallel with DMA-generated traffic between the
camera interface and the LCD Controller.
Figure 1 illustrates the ARMADA 16x Applications Processor Family. The diagram shows a
multi-port memory switch and system bus architecture with the core attached, along with an LCD
Controller and hardware accelerators for graphics and color remapping. The key features of all of
the sub-blocks are described in this section, with more detail provided in the respective chapters.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 25
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Figure 1: ARMADA 16x Applications Processor Family Block Diagram
J
T
A
G
Main PMU
Temp
Sensor
Application
Subsystem
PMU
Boot
ROM
Marvell
Sheeva™
Core
L1$
L2 $
DDR
Controller
Addr Decoder
SQU
BIU
RTC Timer
Keypad
Controller
UART 1
UART 2
TWSI1
UART 3
PWR_TWSI
mcb1
mcb2
SD3
SD4
mcb3
AXI Fabric
SD1
DMA
SD2
SDH1
SDH2
CI
OneWire
AC97
3x Timers
WDT
AXI
Decoder
APB
Bus
AXI 1
XD
General and
Configuration
Registers
Bridge/
DMA
APB2AXI
APB2 Bus
SSP1
SSP2
SSP3
SSP4
SSP5
SMC
NFC
USB 2.0
OTG
ICU
CF
AHB
AXI-AHB
Bridge
USB 2.0
Host
MS Pro
GC300
FE
CMU
AXI 2
LCD
Doc. No. MV-S301545-00 Rev. A
Page 26
PCIE
EPD
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Pin and Ball Map Views
ARMADA 168 (88AP168) Applications Processor 15mm x 15mm TFBGA Ball Map
3
Pin and Ball Map Views
In the following pin and ball map figures, the lowercase letter “n”, which normally indicates negation,
appears as uppercase “N”. “RFU” means “Reserved For Future Use”. NC means “No Connect”. Do
not connect these pins.



3.1
Section 3.1, ARMADA 168 (88AP168) Applications Processor 15mm x 15mm TFBGA Ball Map
Section 3.2, ARMADA 166 (88AP166) Applications Processor 15mm x 15mm TFBGA Ball Map
Section 3.3, ARMADA 162 (88AP162) Applications Processor 15mm x 15mm TFBGA Ball Map
ARMADA 168 (88AP168) Applications Processor
15mm x 15mm TFBGA Ball Map
Figure 2 shows the ball map for the 320-ball 15mm x 15mm TFBGA ARMADA 168 (88AP168)
Applications Processor package.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. Page 27
Marvell® ARMADA 100 Applications Processor Family Hardware Manual
Figure 2: ARMADA 168 (88AP168) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top
View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
MFP_92 MFP_88 MFP_86 MFP_84 MFP_80 MFP_76 MFP_72 MFP_68 MFP_64 MFP_63 MFP_59 MFP_35 MFP_31 MFP_29 MFP_22 MFP_19 MFP_17 MFP_16
A
B
MFP_93 MFP_90 MFP_87 MFP_85 MFP_81 MFP_77 MFP_73 MFP_69 MFP_65 MFP_62 MFP_58 MFP_33 MFP_30 MFP_28 MFP_21 MFP_18 MFP_15 MFP_14
B
C
MFP_97 MFP_95 MFP_91
D
MFP_10
E
MFP_10 MFP_10
F
MFP_10 MFP_10 MFP_10 MFP_10 VDD_IO
G
MFP_11 MFP_10 MFP_10 MFP_10 VD D _
H
MFP_11 MFP_11 MFP_11 MFP_11 VD D _
J
MFP_11 MFP_11 MFP_11 MFP_11 VDD_IO
K
MFP_11 MFP_12 MFP_12 MFP_12 VDD_IO
L
RESET_ PWR_S PWR_S
M
PRI_TM PRI_TC PRI_TD PRI_TR VDD_C
1
4
6
0
4
8
9
IN_N
S
N
VREF
P
DQM0
R
DQS0_
T
VD D _
I O2
MFP_82
VSS
VD D _
I O2
2
5
9
3
7
0
CL
K
MFP_99 MFP_96
3
0
8
7
2
1
6
5
1
DA
O
2
PRI_TDI
ST_N
JTAG_S EXT_WA CALPA
VDD_IO
4
MFP_79 MFP_75
I O2
VSS
MFP_57 MFP_34 MFP_27 MFP_24 MFP_20
C OR E
C OR E
3
3
VD D _
C OR E
ORE
VD D _
C OR E
MFP_67 MFP_60
VD D _
C OR E
MFP_36 MFP_26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SEC_C
VSS
VSS
VSS
VSS
D
S_EN
MDQ0
MDQ1
MDQ2
VSS
MDQ12
VDD_M
MDQ3
VDD_M
MDQ10
MDQ13
DQS0
VSS
MDQ4
VSS
MDQ11
MDQ14 VDD_M
U
MDQ5
MDQ6
VDD_M
MDQ9
VDD_M
V
MDQ7
MDM1
MDQ8
DQS1_N
DQS1
1
2
3
4
5
VSS
VSS
VD D _
C OR E
SDCKE nSDCS
0
MDQ15
0
VSS
VSS
SDCKE1 nSDCS1
VDD_M SDBA2
SDBA1
MA0
VSS
VSS
VSS
VSS
VD D _
VDD_IO
0
VDD_IO
VSS
4
KEUP
3.2
VD D _
VSS
MFP_13 MFP_12
MFP_98 MFP_94 MFP_89 MFP_83 MFP_78 MFP_74 MFP_71 MFP_66 MFP_61 MFP_56 MFP_32 MFP_25 MFP_23 MFP_11 MFP_10 MFP_9
EL
N
MFP_70
0
VSS
VD D _
C OR E
VD D _
C OR E
VDD_IO
1
VDD_IO
1
VD D _
C OR E
VD D _
C OR E
VSS
VSS
MA13
VSS
MA3
MA9
MA12
MA14
C OR E
VSS
SDBA0 VDD_M
VSS
MA8
VDD_M
VSS
ODT
nSDWE
MA1
MA4
MA7
MA11
ODT1
MA2
MA5
MA6
MA10
10
11
12
13
SDCLK SDCLK nSDRA nSDCA
0
0_N
S
S
6
7
8
9
C
MFP_8
D
MFP_7
MFP_6
MFP_5
MFP_4
E
MFP_3
MFP_2
MFP_1
MFP_0
F
MFP_55 MFP_54 MFP_53 MFP_52
G
MFP_51 MFP_50 MFP_49 MFP_48
H
MFP_44 MFP_45 MFP_46 MFP_47
J
MFP_40 MFP_41 MFP_42 MFP_43
K
MFP_37 MFP_38 USBID
L
MFP_39
AVDD_
OTG
VSS
RFU_
R15
AVDDT_
PCIE
VSS
AVDD_ USBH_ USBH_
UHC
VSS
P
N
USBOT USBOT
G_P
G_N
AVDD_ USBVB AVDD5_
OSC
US
RT_SEN A_ISET
VSS
USB
PXTAL_
IN
VD D _
PXTAL_
C OR E
OUT
PCIETX AVDD_ PCIERX PCIECL
P
nDDR_ PCIETX
RESET
N
14
15
PCIE
VSS
16
P
KKP
PCIERX PCIECL
N
KKN
17
18
M
N
P
R
T
U
V
ARMADA 166 (88AP166) Applications Processor
15mm x 15mm TFBGA Ball Map
Figure 3 shows the ball map for the 320-ball 15mm x 15mm TFBGA ARMADA 166 (88AP166)
Applications Processor package.
Doc. No. MV-S301545-00 Rev. Page 28
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Pin and Ball Map Views
ARMADA 162 (88AP162) Applications Processor 15mm x 15mm TFBGA Ball Map
Figure 3: ARMADA 166 (88AP166) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top
View
A
MFP_92 MFP_88 MFP_86 MFP_84 MFP_80 MFP_76 MFP_72 MFP_68 MFP_64 MFP_63 MFP_59 MFP_35 MFP_31 MFP_29 MFP_22 MFP_19 MFP_17 MFP_16
A
B
MFP_93 MFP_90 MFP_87 MFP_85 MFP_81 MFP_77 MFP_73 MFP_69 MFP_65 MFP_62 MFP_58 MFP_33 MFP_30 MFP_28 MFP_21 MFP_18 MFP_15 MFP_14
B
C
MFP_97 MFP_95 MFP_91
D
MFP_10
E
MFP_10 MFP_10
F
MFP_10 MFP_10 MFP_10 MFP_10 VDD_IO
G
MFP_11 MFP_10 MFP_10 MFP_10 VD D _
H
MFP_11 MFP_11 MFP_11 MFP_11 VD D _
J
MFP_11 MFP_11 MFP_11 MFP_11 VDD_IO
K
MFP_11 MFP_12 MFP_12 MFP_12 VDD_IO
L
RESET_ PWR_S PWR_S
M
PRI_TM PRI_TC PRI_TD PRI_TR
ST_N
CORE
N
VREF
JTAG_S EXT_WA CALPA
SEC_C
P
DQM0
R
DQS0_
T
U
V
3.3
1
4
6
0
4
8
9
IN_N
S
VD D _
IO2
MFP_82
VSS
VD D _
I O2
VD D _
I O2
VSS
MFP_57 MFP_34 MFP_27 MFP_24 MFP_20
VSS
MFP_13 MFP_12
MFP_98 MFP_94 MFP_89 MFP_83 MFP_78 MFP_74 MFP_71 MFP_66 MFP_61 MFP_56 MFP_32 MFP_25 MFP_23 MFP_11 MFP_10 MFP_9
2
5
9
MFP_99 MFP_96
3
8
3
2
7
6
0
CL
K
1
DA
O
0
7
1
5
2
PRI_TDI
VDD_IO
4
MFP_79 MFP_75
C OR E
C OR E
3
3
VD D _
C OR E
VDD_
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MDQ1
MDQ2
VSS
MDQ12
VDD_M
MDQ3
VDD_M
MDQ10
MDQ13
DQS0
VSS
MDQ4
VSS
MDQ11
MDQ14 VDD_M
MDQ5
MDQ6
VDD_M
MDQ9
VDD_M
DQS1
1
2
3
4
5
VSS
VSS
VSS
VSS
VD D _
C OR E
SDCKE nSDCS
0
MDQ15
SDCLK SDCLK
0
VSS
VSS
SDCKE1 nSDCS1
VDD_M SDBA2
SDBA1
MA0
VSS
VSS
VD D _
VSS
VSS
VSS
S
6
7
8
9
VD D _
C OR E
VD D _
C OR E
MFP_3
MFP_2
MFP_1
MFP_0
F
MFP_55 MFP_54 MFP_53 MFP_52
G
MFP_51 MFP_50 MFP_49 MFP_48
H
MFP_44 MFP_45 MFP_46 MFP_47
J
MFP_40 MFP_41 MFP_42 MFP_43
K
MFP_37 MFP_38 USBID
L
MFP_39
AVDD_
OTG
UHC
VSS
MA14
VSS
VSS
VSS
VSS
ODT1
VSS
MA2
MA5
MA6
MA10
10
11
12
13
RESET
14
P
N
USBOT USBOT
G_P
G_N
AVDD_ USBVB AVDD5_
MA12
nDDR_
VSS
AVDD_ USBH_ USBH_
MA9
MA11
S
1
E
MA3
MA7
0_N
VDD_IO
MFP_4
VSS
MA4
0
1
D
MFP_5
VSS
VDD_M
MA1
VDD_IO
MFP_8
MFP_6
MA13
MA8
nSDCA
VD D _
C OR E
C
MFP_7
VSS
C OR E
VSS
nSDWE
VD D _
C OR E
VSS
SDBA0 VDD_M
ODT
0
0
VSS
nSDRA
VDD_IO
VDD_IO
VSS
MDQ0
DQS1_N
MFP_36 MFP_26
VSS
S_EN
MDQ8
VD D _
C OR E
VSS
D
MDM1
MFP_67 MFP_60
VSS
KEUP
MDQ7
VD D _
C OR E
VSS
4
EL
N
MFP_70
OSC
US
RT_SEN A_ISET
USB
PXTAL_
IN
M
N
P
R
VD D _
PXTAL_
C OR E
OUT
VSS
VSS
VSS
U
VSS
VSS
VSS
VSS
V
15
16
17
18
T
ARMADA 162 (88AP162) Applications Processor
15mm x 15mm TFBGA Ball Map
Figure 4 shows the ball map for the 320-ball 15mm x 15mm TFBGA ARMADA 162 (88AP162)
Applications Processor package.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. Page 29
Marvell® ARMADA 100 Applications Processor Family Hardware Manual
Figure 4: ARMADA 162 (88AP162) Applications Processor 15mm x 15mmTF-BGA Ball Map - Top
View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
MFP_92 MFP_88 MFP_86 MFP_84 MFP_80 MFP_76 MFP_72 MFP_68 MFP_64 MFP_63 MFP_59 MFP_35 MFP_31 MFP_29 MFP_22 MFP_19 MFP_17 MFP_16
A
B
MFP_93 MFP_90 MFP_87 MFP_85 MFP_81 MFP_77 MFP_73 MFP_69 MFP_65 MFP_62 MFP_58 MFP_33 MFP_30 MFP_28 MFP_21 MFP_18 MFP_15 MFP_14
B
C
MFP_97 MFP_95 MFP_91
D
MFP_10
E
MFP_10 MFP_10
F
MFP_10 MFP_10 MFP_10 MFP_10 VDD_IO
G
MFP_11 MFP_10 MFP_10 MFP_10 VD D _
H
MFP_11 MFP_11 MFP_11 MFP_11 VD D _
J
MFP_11 MFP_11 MFP_11 MFP_11 VDD_IO
K
MFP_11 MFP_12 MFP_12 MFP_12 VDD_IO
L
RESET_ PWR_S PWR_S
M
PRI_TM PRI_TC PRI_TD PRI_TR VDD_C
1
4
6
0
4
8
9
IN_N
S
N
VREF
P
DQM0
R
DQS0_
T
VD D _
I O2
MFP_82
VSS
VD D _
I O2
2
5
9
3
7
0
CL
K
MFP_99 MFP_96
3
0
8
7
2
1
6
5
1
DA
O
2
PRI_TDI
ST_N
JTAG_S EXT_WA CALPA
VDD_IO
4
MFP_79 MFP_75
I O2
VSS
MFP_57 MFP_34 MFP_27 MFP_24 MFP_20
C OR E
C OR E
3
3
VD D _
C OR E
ORE
C OR E
MFP_67 MFP_60
VD D _
C OR E
MFP_36 MFP_26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SEC_C
VSS
VSS
VSS
VSS
S_EN
MDQ0
MDQ1
MDQ2
VSS
MDQ12
VDD_M
MDQ3
VDD_M
MDQ10
MDQ13
DQS0
VSS
MDQ4
VSS
MDQ11
MDQ14 VDD_M
U
MDQ5
MDQ6
VDD_M
MDQ9
VDD_M
V
MDQ7
MDM1
MDQ8
DQS1_N
DQS1
1
2
3
4
5
VSS
VSS
VD D _
C OR E
SDCKE nSDCS
0
MDQ15
0
VSS
VSS
SDCKE1 nSDCS1
VDD_M SDBA2
SDBA1
MA0
VSS
VSS
VSS
VSS
VD D _
VDD_IO
0
VDD_IO
VSS
D
Doc. No. MV-S301545-00 Rev. -
VD D _
VSS
4
KEUP
Page 30
VD D _
VSS
MFP_13 MFP_12
MFP_98 MFP_94 MFP_89 MFP_83 MFP_78 MFP_74 MFP_71 MFP_66 MFP_61 MFP_56 MFP_32 MFP_25 MFP_23 MFP_11 MFP_10 MFP_9
EL
N
MFP_70
0
VSS
VD D _
C OR E
VD D _
C OR E
VDD_IO
1
VDD_IO
1
VD D _
C OR E
VD D _
C OR E
VSS
MFP_5
MFP_4
E
MFP_3
MFP_2
MFP_1
MFP_0
F
MFP_55 MFP_54 MFP_53 MFP_52
G
MFP_51 MFP_50 MFP_49 MFP_48
H
MFP_44 MFP_45 MFP_46 MFP_47
J
MFP_40 MFP_41 MFP_42 MFP_43
K
MFP_37 MFP_38 USBID
L
MFP_39
AVDD_
OTG
MA13
VSS
VSS
MA3
MA9
MA12
MA14
VSS
UHC
VSS
OSC
U
VSS
VSS
VSS
VSS
V
15
16
17
18
MA4
MA7
MA11
ODT1
VSS
MA2
MA5
MA6
MA10
10
11
12
13
14
R
VSS
MA1
9
IN
VSS
nSDWE
8
PXTAL_
P
VSS
ODT
7
USB
OUT
VSS
6
US
N
PXTAL_
VSS
RESET
G_N
VD D _
VSS
nDDR_
G_P
M
C OR E
VDD_M
S
N
USBOT USBOT
RT_SEN A_ISET
MA8
S
P
AVDD_ USBVB AVDD5_
VSS
0_N
VSS
AVDD_ USBH_ USBH_
SDBA0 VDD_M
0
D
MFP_6
VSS
SDCLK SDCLK nSDRA nSDCA
MFP_8
MFP_7
VSS
C OR E
C
T
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Package Information
Introduction
4
Package Information
This chapter describes the following:




4.1
Section 4.1, Introduction
Section 4.2, Package Marking
Section 4.3, Packaging Materials
Section 4.4, ARMADA 16x Applications Processor Family 15mm x 15mm TFBGA Packaging
Introduction
This chapter provides the package marking and mechanical specifications for the ARMADA 16x
Applications Processor Family.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 31
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
4.2
Package Marking
Figure 5 shows an example of the package marking for the ARMADA 16x Applications Processor
Family. The Booking Part Number for this specific example is 88AP166EB0-BJD2C008
Figure 5: Sample Package Marking
Package Code:
BJD for TFBGA
TLA for TQFP
Marvell Logo
Environment Code:
2 for Green
8 8 A P 1 - B J D 2
Product Line
Assembly Date Code
L O T #
Y Y WW
Country of Origin
T W
Assembly Lot #
B 0 P
E S
C 0 0 8
8 8 A P 1 6 6 E
Pin 1
Die Revision
ES Mark, for ES only
Temperature and Speed:
Commercial Temp
800 MHz,
Product: (booking P/N prefix)
Aspen-EPD, Auto boot
Assembly Plant Code:
P for SPIL
E for ASE-K
NOTE: The individual text boxes illustrated above are only used to demonstrate the relative location for the marking.
4.3
Packaging Materials
Table 4 shows the solder ball material list.
Table 4:
Package Materials
S o l d e r B a ll s ( S A C 3 0 5 )
Solder balls: 96.5 Sn/3.0 Ag/0.5 Cu
NOTE: Pb-free parts, lead has not been added intentionally, but lead may persist as an impurity below
1000 ppm
Doc. No. MV-S301545-00 Rev. A
Page 32
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Package Information
ARMADA 16x Applications Processor Family 15mm x 15mm TFBGA Packaging
4.4
ARMADA 16x Applications Processor Family 15mm
x 15mm TFBGA Packaging
Figure 6 shows the 320-ball TFBGA packaging for the ARMADA 16x Applications Processor Family.
Table 5 provides TFBGA package dimensions.
.
Figure 6: ARMADA 16x Applications Processor Family 15mm x 15mm TFBGA
Package Information
Top View
-A-
D
PIN # 1
aaa
-B-
CAVITY
C
A1
E
C
A2
bbb
A
//
-C-
SOLDER BALL
ddd
aaa
C
SEATING PLANE
DETAIL: “A”
eee
fff
“A”
C
C
A
B
D1
E1
b
e
DETAIL: “B”
“B”
Bottom View
1. Solder Ball size: 0.45mm
2. BGA solder ball pad: 0.4mm SMD
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 33
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 5:
Symbol
TFBGA Package Dimensions
D im e n s i on s i n m m
Min
N om
D i m e n s io n s i n in c h ( s e e N o t e )
Max
Min
Nom
Max
A
---
---
1.40
---
---
0.055
A1
0.30
0.35
0.40
0.012
0.014
0.016
A2
0.84
0.89
0.94
0.033
0.035
0.037
c
0.32
0.36
0.40
0.013
0.014
0.016
D
14.90
15.00
15.10
0.587
0.591
0.594
E
14.90
15.00
15.10
0.587
0.591
0.594
D1
---
13.60
---
---
0.535
---
E1
---
13.60
---
---
0.535
---
e
---
0.80
---
---
0.031
---
b
0.40
0.45
0.50
0.016
0.018
0.020
aaa
0.15
0.006
bbb
0.10
0.004
ddd
0.12
0.005
eee
0.15
0.006
fff
0.08
0.003
MD/WE
18/18
18/18
NOTE: If the PCB is designed with English units on outer rows, solder balls may not align with PCB
pads due to rounding error from converting from mm to inches. Once solder ball and PCB pad
positional tolerances are factored, there is a risk of SMT failure due to outer balls not aligning
with PCB pads.
Doc. No. MV-S301545-00 Rev. A
Page 34
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Maximum Ratings and Operation Conditions
Absolute Maximum Ratings
5
Maximum Ratings and Operation
Conditions
This chapter discusses:


5.1
Section 5.1, Absolute Maximum Ratings
Section 5.2, Operating Conditions
Absolute Maximum Ratings
The absolute maximum ratings (shown in Table 6) define limitations for electrical and thermal
stresses. These limits prevent permanent damage to the ARMADA 16x Applications Processor
Family.
Note
Table 6:
Absolute maximum ratings are not operating ranges. Operation at absolute maximum
ratings is not guaranteed.
Absolute Maximum Ratings
Sy m b o l
D e s c r ip t i o n
Min
Max
U ni ts
TS
Storage temperature
–40
125
°C
Voltage applied to IO peripherals
VDD_IO0, VDD_IO1, VDD_IO2, VDD_IO3, VDD_IO4
VSS–0.3
VSS+4.0
AVDD_UHC (AVDD_USB03P3) and AVDD_OTG
(AVDD_USB13P3)
VSS–0.3
VSS+3.6
V
VCC_MV
Voltage applied to DDR supply pins
(VDD_M)
VSS–0.5
VSS+2.3
V
VCC_LV
Voltage applied to VDD_Core supply pins
VSS-0.3
VSS+1.155
V
VIP_X
Voltage applied to analog blocks
(XTAL_IN, XTAL_OUT, AVDD_OSC)
VSS–0.3
VSS+1.9
V
VESD
Maximum ESD stress voltage, three stresses
maximum:
• Any pin to any supply pin, either polarity, or
• Any pin to all non-supply pins together,
either polarity
HBM1
—
2000
V
CDM2
—
500
V
—
5
mA
VCC_HV
IEOS
Maximum DC input current (electrical overstress) for any
non-supply pin
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
V
Doc. No. MV-S301545-00 Rev. A
Page 35
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 6:
Sy m b o l
Absolute Maximum Ratings (Continued)
D e s c r ip t i o n
Min
Max
U ni ts
NOTE:
1. HBM = human body model
2. CDM = charge device model
5.2
Operating Conditions
This section discusses operating voltage, frequency, and temperature specifications for the
ARMADA 16x Applications Processor Family.
Refer to the “Clocks Controller and Power Management Unit” chapter of the Marvell®ARMADA 16x
Applications Processor Family Software Manual for supported frequencies and clock-register
settings as listed in Table 7.
Table 7:
Sy m b o l
Voltage, Temperature, and Frequency Electrical Specifications
D e s c r i p t io n
Min
Typical
Max
Units
N ot e s
O pe r at in g Tem pe r at u r e
Tj
Junction Temperature
-25
—
+85
°C
1
Tj
Junction Temperature
-40
—
+105
°C
1
Case Temperature
—
—
See Notes 2 and 3
°C
4, 5, 6, 8
Thermal parameter characterization
junction to top center of package
0.2
—
7.20
°C /
watt
—
Tcase
jt
AV D D _O S C Vol ta g e
Vccosc_1
Voltage applied on VDD_OSC
Tsysramp
Ramp Rate
1.70
1.80
1.90
V
—
—
—
25.00
mV/s
—
AVD D C O R E Vo l ta g e a t F r e q u e n c y R a n g e s ( A 0 Ste p p in g )
Max
10
Vcccore_1
Voltage applied for modes 0 and 1
0.9
1.00
1.155
V
12, 13,
20
Vcccore_2
Voltage applied for modes 2, 2.3, 3 and
3.1
1.05
1.10
1.155
V
14, 15,
16, 17,
20, 21
Tpwrramp
Ramp Rate
1.0
—
AVD D C O R E Vo l ta g e a t F r e q u e n c y R a n g e s ( B 0 Ste p p in g )
25.00
Max
11
mV/s
Max
10
Vcccore_1
Voltage applied for modes 0 and 1
0.90
0.945
1.000
1.155
V
12, 13,
22
Vcccore_2
Voltage applied for modes 2, 2.3, 3 and
3.1
0.97
1.000
1.030
1.155
V
14, 15,
16, 17,
22
Doc. No. MV-S301545-00 Rev. A
Page 36
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Maximum Ratings and Operation Conditions
Operating Conditions
Table 7:
Voltage, Temperature, and Frequency Electrical Specifications (Continued)
Sy m b o l
D e s c r i p t io n
Min
Vcccore_3
Voltage applied for modes 4 and 4.1
Tpwrramp
Ramp Rate
Typical
Max
Units
1.086
1.120
1.155
1.155
V
1.0
—
25.00
25.00
mV/s
N ot e s
18, 19,
21
V D D _ M Vo lta g e
Vcc_m_1
Voltage applied on VDD_M
Tsysramp
Ramp Rate
1.425
1.5
1.575
V
—
1.70
1.80
1.90
V
—
—
—
25.00
mV/s
—
V D D _ IO {0 ,1 , 2 ,3 , 4 } Vol ta g e
Vcciox_1
Voltage applied when using 1.8v devices
1.70
1.80
1.98
V
—
Vcciox_3
Voltage applied when using 3.3v devices
2.97
3.30
3.63
V
—
Tsysramp
Ramp Rate
—
—
25.00
mV/s
—
V D D _U S B Vol ta g e
Vccusb_0
Voltage applied on AVDD_OTG
3.00
3.30
3.6
V
—
Vccusb_1
Voltage applied on AVDD_UHC
3.00
3.30
3.6
V
—
Tsysramp
Ramp Rate
—
—
25.00
mV/s
—
AV D D 5_ U SB ( U S B O T G 5 V s u pp l y )
vccusb_0
Voltage applied on AVDD5_USB
4.5
5.0
5.5
V
—
Tsysramp
Ramp Rate
—
—
25.00
mV/s
—
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 37
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 7:
Sy m b o l
Voltage, Temperature, and Frequency Electrical Specifications (Continued)
D e s c r i p t io n
Min
Typical
Max
Units
N ot e s
NOTE:
1. Minimum/maximum junction temperature depends on SKU
2. The case temperature spec for Marvell® ARMADA 16x Applications Processor Family is a function of the jt value
that varies pending OEM system configuration. jt value should be modeled and/or tested for each system
configuration.
3. Allowable case temperature should be calculated using the following formula. Maximum jt can be used for
maximum allowable case temperature calculation where testing or modeling resources are not available or system can
absorb the extra guard band introduced using max jt values
4. Tcase(max) = Tj(max) - jt * P(max)
5. Tcase(max) = Maximum allowable case temperature (°C).
6. Tj(max) = Maximum allowable junction temperature (°C)
7. P(max) = Maximum Sustainable ARMADA Power (W)
8. System design must ensure that the device case temperature is maintained within the specified limits. In some system
applications it may be necessary to use external thermal management (for example, a package-mounted heat
spreader) or configure the device to limit power consumption and maintain acceptable case temperatures.
9. The voltage ranges specified for VDD_CORE are the targeted voltage ranges for the product. These ranges may
extend or narrow depending on actual product performance and product SKUs. Marvell recommends that extended
voltage and current capabilities be designed into the power management IC to accommodate future changes to this
specification without requiring changes to the power management IC.
10. Maximum allowable operating voltage on VDD_CORE.
11. Maximum allowable voltage on VDD_CORE to meet maximum 1.4 W Pmax
12. Mode 0 is PCLK = 156 MHz and DCLK = 156 MHz
13. Mode 1 is PCLK = 400 MHz and DCLK = 200 MHz
14. Mode 2 is PCLK = 624 MHz and DCLK = 312 MHz
15. Mode 2.3 is PCLK = 624 MHz and DCLK = 156 MHz
16. Mode 3 is PCLK = 800 MHz and DCLK = 400 MHz
17. Mode 3.1 is PCLK = 800 MHz and DCLK = 200 MHz
18. Mode 4 is PCLK = 1.066 GHz and DCLK = 533 MHz
19. Mode 4.1 is PCLK = 1.066 GHz and DCLK = 355 MHz
20. Maximum VDD_CORE power (Pmax) is 1.5W
21. Maximum full chip power (Pmax_fullchip) is 2.0W
22. Maximum full chip power (Pmax_fullchip) is 1.9W.
Doc. No. MV-S301545-00 Rev. A
Page 38
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Electrical Specifications
DC Voltage and Current Characteristics
6
Electrical Specifications
This chapter includes DC voltage and current characteristics as well as crystal and oscillator
specifications for the ARMADA 16x Applications Processor Family.


6.1
Section 6.1, DC Voltage and Current Characteristics
Section 6.2, Oscillator Electrical Specifications
DC Voltage and Current Characteristics
The DC characteristics for each pin include input-sense levels, output-drive levels, current and
pullup/down resistive values. These parameters can be used to determine maximum DC loading
and to determine maximum transition times for a given load.
Table 8 shows the DC operating conditions for the input, output, and I/O pins used by the Dynamic
Memory Controller. Table 9 shows operating conditions for DDR3.
Table 8:
LPDDR1/LPDDR2 Input, Output and I/O pins AC/DC Operating Conditions
S y m b o ls
D e s c r i p t io n
Min
Ty p ic a l
Max
U n it
N o te s
Vih(dc)
Input high voltage
VREF + 0.125
—
VDD_M
V
—
Vil(dc)
Input low voltage
VSS
—
VREF - 0.125
V
—
Vih(ac)
Input high voltage
VREF + 0.200
—
6
V
—
Vil(ac)
Input low voltage
6
—
VREF - 0.200
V
—
VOH
High-level output voltage
Absolute Load Current
achieving Voh
1.4
—
V
1, 2
VOL
Low-level output voltage
Absolute Load Current
achieving Vol
—
—
0.4
V
1, 2
120
150
180

3, 4, 5
RTT
Rtt Effective impedance value
60
75
90

3, 4, 5
4
4.5
5
pF
Cpin
Pin Capacitance
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 39
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 8:
S y m b o ls
LPDDR1/LPDDR2 Input, Output and I/O pins AC/DC Operating Conditions (Continued)
D e s c r i p t io n
Min
Ty p ic a l
Max
U n it
N o te s
NOTE:
1. IOH (min) = 13.4 mA
2. Measurement conditions VDDIO=1.8V, ZPDRV=ZNDRV=0xF, ZPR=ZNR=0xF, ZD=1
3. Refer to the Functional Description section in the DDR Memory Controller chapter in the Marvell® ARMADA 16x
Applications Processor Family Software Manual for ODT configuration.
4. Measurement definition for RTT:
Apply VREF +/- 0.25 to input pin separately, then measure current I(VREF + 0.25) and I(VREF - 0.25) respectively.
Current does not include the current flowing through the pullup/pulldown resistor.
5. RTT = 0.5 / (I(VREF + 0.25) - I (VREF - 0.25))
6. Input DC Operating Conditions (SSTL receiver)
VIH overshoot: VIH (max) = VDD_M + 0.7V for a pulse width less than or equal to 3ns and the pulse width can not be
greater than 1/3 the cycle rate.
VIL undershoot: VIL (min) = -1.0V for a pulse width less than or equal to 3ns and the pulse width can not be greater
than 1/3 the cycle rate
Where VDD_M <=1.8V
Table 9:
DDR3 Input, Output, and I/O Pins AC/DC Operating Conditions
Sy m b o ls
D e s c r i p t i o n / Te s t
C o n d iti o n
Min
Ty p ic a l
Max
Unit
N o te s
VIL (AC)
Input low level AC
Note 7
--
VREF - 0.175
V
--
VIH (AC)
Input high level AC
VREF + 0.175
--
Note 7
V
--
VIL (DC)
Input low level DC
VSS
--
VREF - 0.100
V
--
VIH (DC)
Input high level DC
VREF + 1.00
--
VDDIO
V
--
VDIL
Differential input low level
Note 6
--
-0.2
V
6
VDIH
Differential input high level
0.2
--
Note 6
V
6
VOL
Output low level/
See Note 6
--
--
0.2*VDDIO
V
7
VOH
Ouput high level/
See Note 6
0.8*VDDIO
--
--
V
7
RTT
Rtt effective impedance
value/See Note 2
48
60
72
0hm
1, 2
Cpin
Pin capacitance
--
4
4.5
pF
--
Doc. No. MV-S301545-00 Rev. A
Page 40
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Electrical Specifications
DC Voltage and Current Characteristics
Table 9:
DDR3 Input, Output, and I/O Pins AC/DC Operating Conditions
Notes:
1. See SDRAM functional description section for ODT configuration
2. Measurement defintion for RTT: Apply VREF +/-0.25 to input pin separately. Then measure current I(VREF + 0.25) and
I(VREF - 0.25), respectively. RTT = 0.35/I(VREF +0.175) - I(VREF - 0.175)
3. Includes pad + pkg cap
4. This current does not include the current flowing through the pullup/pulldown resistor.
5. Limitations are same as for single-ended signals.
6. Defined when driver impedance is calibrated to 21 ohm.
See JEDEC Overshoot and Undershoot Spec.
Table 10 applies to all signals powered by VCC_high. VCC_high is the term used to refer to the
collective groups of high voltage supplies which consist of VDD_IO0, VDD_IO1, VDD_IO2,
VDD_IO3, VDD_IO4, VDD_M, VDD_OTG, VDD_PLL and VDD_UHC.
Table 10: MFP Input, Output, and I/O Pins DC Operating Conditions
Sy m b o ls
D e s c r ip t i o n
Min
Typ i c a l
M ax
U ni t
Notes
In p u t D C O p e r a t i ng C o n d i t i o n s ( v c c = 1 .8 V Ty p ic a l )
Vih
Input high voltage
VCC_high *
0.8
—
VCC_high +
0.3
V
3
Vil
Input low voltage
-0.3
—
VCC_high *
0.2
V
3
Vhys
Hysteresis (VIT+ - VIT-)
0.4
—
VCC_high *
0.5
V
3
RPULLUP
Pullup Resistance
401
110
2002
K
4
RPULLDOWN
Pulldown Resistance
401
110
2002
K
5
In p ut D C O p e r a ti ng C o n di ti on s (3 .3 V Ty p i ca l )
Vih
Input high voltage
0.8 *
VCC_high
—
VCC_high +
0.3
V
3
Vil
Input low voltage
-0.3
—
VCC_high *
0.2
V
3
Vhys
Hysteresis (VIT+ - VIT-)
0.4
—
VCC_high *
0.5
V
3
RPULLUP
Pullup Resistance
201
45
1002
K
4
RPULLDOWN
Pulldown Resistance
201
45
1002
K
5
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 41
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 10: MFP Input, Output, and I/O Pins DC Operating Conditions (Continued)
Sy m b o ls
D e s c r ip t i o n
Min
Typ i c a l
M ax
U ni t
Notes
V
IOH = (mA min)
O u t p u t D C O p e r a t i n g C o n di ti o n s ( V C C = 1 .8 V Ty p ic a l ) ( N o r m a l I O P in s )
VOH6
1X
2X
3X
VOL6
1X
2X
3X
High-level output voltage
Absolute Load Current
achieving Voh
0.9 *
VCC_high
Low-level output voltage
Absolute Load Current
achieving Vol
VSS
—
VCC_high
-3
-6
-9
—
0.1 *
VCC_high
V
IOL = (mA min)
3
6
9
O u t p u t D C O p e r a t i n g C o n di ti o n s ( V C C = 1 .8 V Ty p ic a l ) ( F a st I O P i n s ( M F P _ < 5 6 : 8 5 > ) )
VOH6
1X
2X
3X
4X
VOL6
1X
2X
3X
4X
High-level output voltage
Absolute Load Current
achieving Voh
0.9 *
VCC_high
Low-level output voltage
Absolute Load Current
achieving Vol
VSS
—
VCC_high
V
IOH = (mA min)
-3
-6
-8
-10
—
0.1 *
VCC_high
V
IOL = (mA min)
3
6
8
10
O u t p u t D C O p e r a t i n g C o n di t i o n s ( v c c p = 3 .3 V Ty p ic a l ) ( N o r m a l I O P in s )
VOH6
1X
2X
3X
VOL6
1X
2X
3X
High-level output voltage
Absolute Load Current
achieving Voh
Low-level output voltage
Absolute Load Current
achieving Vol
VCC_high *
0.9
VCC_high
V
—
IOH = (mA min)
-3
-9
-11
VSS
—
0.1 *
VCC_high
V
IOL = (mA min)
3
6
11
O u t p u t D C O p e r a t i n g C o n d i ti o n s ( v c c p = 3 .3 V Ty p ic a l ) ( F as t I O P i n s ( M F P _ < 5 6 : 8 5 > ) )
Doc. No. MV-S301545-00 Rev. A
Page 42
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Electrical Specifications
Oscillator Electrical Specifications
Table 10: MFP Input, Output, and I/O Pins DC Operating Conditions (Continued)
Sy m b o ls
D e s c r ip t i o n
Min
Typ i c a l
VOH6
High-level output voltage
Absolute Load Current
achieving Voh
VCC_high *
0.9
—
1X
2X
3X
4X
VOL6
1X
2X
3X
4X
Low-level output voltage
Absolute Load Current
achieving Vol
M ax
U ni t
Notes
VCC_high
V
IOH = (mA min)
-5.0
-8.0
-10.0
-12.0
VSS
—
0.1 *
VCC_high
V
IOL = (mA min)
5.0
8.0
10.0
12.0
O u t p u t D C O p e r a t i n g C o n di ti o n s ( V C C = 1 .8 a n d 3. 3 V Ty p ic a l )
IOZ
Three-state output leakage
current
—
—
40
nA
—
IDDQ
Quiescent supply current
—
—
1
nA
—
NOTE:
1. Max voltage, Minimum temperature
2. Min voltage, Maximum temperature
3. VCC_high references to VDD_IO0, VDD_IO1, VDD_IO2, VDD_IO3, VDD_IO4, VDD_M, VDD_OTG, VDD_PLL and
VDD_UHC supplies.
4. Use MFPRxx[pull_sel] and MFPRxx[pullup_en] bits to enable or disable pullups.
5. Use MFPRxx[pull_sel] and MFPRxx[pulldown_en] bits to enable or disable pulldowns.
6. Multi-Function Pin (MFP) drive strength is programmable using MFPRxx[drive] bitfield. MFPR register definitions are
found in the Marvell® ARMADA 16x Applications Processor Family Software Manual.
6.2
Oscillator Electrical Specifications
6.2.1
26.000 MHz Oscillator Specifications
The 26.000 MHz crystal is connected between the PXTAL_IN (amplifier input) and PXTAL_OUT
(amplified output). Table 11 lists the 26.000 MHz crystal specifications.
To drive the 26.000 MHz crystal pins from an external source:
1.
2.
Drive the PXTAL_IN pin with a digital signal with low and high levels as listed in Table 12.
Float the PXTAL_OUT pin
Table 12 lists the 26.000 MHz oscillator specifications. Figure 7 shows recommended GND shielding
to xtal_in and xtal_out.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Figure 7: Recommended GND Shielding to xtal_in and xtal_out
Table 11: Typical 26.000 MHz Crystal Requirements
Parameter
M in i m u m
Ty p ic a l
Maximum
U n i ts
Frequency range
25.997
26.000
26.002
MHz
Frequency tolerance at 25°C
–50
—
+50
ppm
Oscillation mode
Fundamental Parallel Resonant
—
Maximum change over temperature range
–50
—
+50
ppm
Drive level
—
10
100
uW
Load capacitance (CL)
—
10
—
pf
Series resistance (RS)
—
50
—

NOTE:
Table 12: Typical External 26.000 MHz Oscillator Requirements
S y m b ol
D e s c r i p t io n
M in
Ty p i ca l
M ax
U n i ts
A m p l if ie r Sp e c if ic a t io n s
VIH_X
Input high voltage, PXTAL_IN
1.7
1.8
1.9
V
VIL_X
Input low voltage, PXTAL_IN
–0.10
0.00
0.10
V
IIN_XP
Input leakage, PXTAL_IN
—
—
10
A
CIN_XP
Input capacitance, PXTAL_IN/PXTAL_OUT
—
20
25
pf
tS_XP
Stabilization time
—
—
7
ms
SR_XP
Slew Rate
1
—
—
V/ns
Doc. No. MV-S301545-00 Rev. A
Page 44
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Electrical Specifications
Oscillator Electrical Specifications
Table 12: Typical External 26.000 MHz Oscillator Requirements (Continued)
S y m b ol
D e s c r i p t io n
M in
Ty p i ca l
M ax
U n i ts
B o a r d Sp e c if i c a t i o n s
RP_XP
Parasitic resistance, PXTAL_IN/PXTAL_OUT to any node
20
—
—
M
CP_XP
Parasitic capacitance, PXTAL_IN/PXTAL_OUT, total
—
—
5
pf
COP_XP
Parasitic shunt capacitance, PXTAL_IN to PXTAL_OUT
—
—
0.4
pf
a
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Doc. No. MV-S301545-00 Rev. A
Page 46
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
AC Electrical Characteristics
DDR SDRAM Timing Diagrams and Specifications
7
AC Electrical Characteristics
This chapter includes alternating-current (AC) characteristics, timing diagrams and timing
parameters for the ARMADA 16x Applications Processor Family controllers/interfaces listed below.
Section 7.1, DDR SDRAM Timing Diagrams and Specifications
Section 7.2, Static Memory Controller Timing Diagrams and Specifications
Section 7.3, NAND Timing Diagrams and Specifications
Section 7.4, SD Host Controller (SDH) Timing Diagrams and Specifications
Section 7.5, LCD Controller Timing Diagrams and Specifications
Section 7.6, Quick Capture Camera Interface (CCIC) Timing Diagrams and Specifications
Section 7.7, SSP Timing Diagrams and Specifications
Section 7.8, TWSI Timing Diagrams and Specifications
Section 7.9, AC ’97 Timing Diagrams and Specifications
Section 7.10, JTAG Interface Timing Diagrams and Specifications
Section 7.11, USB 2.0 Timing Diagrams and Specifications
Section 7.12, PCI Express Specifications
Section 7.13, Ethernet MAC (MII) Timing Diagrams and Specifications
Section 7.14, Powerup/Down Sequences
7.1
DDR SDRAM Timing Diagrams and Specifications
This section describes the timing diagrams and timing parameters for the DDR Controller.
The following diagrams are included in this section:











Figure 8, Differential Clock
Figure 9, SDRAM Timing Diagrams 1
Figure 10, SDRAM Timing Diagrams 2
Figure 11, SDRAM Timing Diagrams 3
Figure 12, SDRAM Timing Diagrams 4
Figure 13, Basic Write Timing Parameters
Figure 14, DDR3 SDRAM Timing Diagrams
Figure 15, DQ to DQS Write Skew
Figure 16, CLK to Address/Command Write Skew
Figure 17, DQS to CLK Write Skew
Figure 18, DQ to DQS Read Skew
Refer to Table 15 through Table 20 for the DDR specifications. Refer to the JEDEC Spec for
complete timing diagrams and specifications.
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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7.1.1
Measurement Conditions
The diagrams in the section use the following conventions:
Table 13: Standard Input, Output, and I/O-Pin AC Operating Conditions
Sy m b o l
D e s c r i p t io n
CIO
IO capacitance, all standard I/O pins
Min
Ty p i ca l
Max
U n i ts
—
—
5
Min
Ty p i ca l
Max
0.45*VDDQ
—
0.55*VDDQ
V
1.36
1.44
1.52
V
pf
Figure 8: Differential Clock
Clock Crossing
SDRAM_CLKn
VID
vx
SDRAM_CLK
Table 14:Clock Parameters
Sy m b o l
D e s c r i p t io n
Vx
Differential Clock Cross over point relative to gnd
VID
DC Differential Output Voltage
7.1.2
U n i ts
DDR SDRAM Timing Diagrams and Specifications
Figure 9 through Figure 12 shows the typical LPDDR1, DDR2 and DDR3 SDRAM timings. Figure 16
shows the skew timings. Refer to Table 15 for the DDR specifications. Refer to the JEDEC Spec for
complete timing diagrams and specifications.
Doc. No. MV-S301545-00 Rev. A
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AC Electrical Characteristics
DDR SDRAM Timing Diagrams and Specifications
Figure 9: SDRAM Timing Diagrams 1
SDCLK[1]
SDCKE
tRCD
Command NOP
ACT
NOP
tRP
tRAS
tRCD
tRC
READ
NOP
PRE
NOP
ACT
NOP
WRITE
NOP
PRE
NOP
nSDCS[0]
nSDRAS
nSDCAS
nWE
tRPSTmc
tRPREmc
DQS
tWPREmc
tWPSTmc
tDQSCKmc
tCL
tWR
tHZmc
MD[31:0]
tLZmc
DQM[1:0]
1111
mask0
mask1
mask6
mask7
Figure 10: SDRAM Timing Diagrams 2
trwd_ext_dly
BL
Data
DR0
tRP
CMD
BA
tRCD
tCCD
DR1
DR2
DW0
tCCD + trwd_ext_dly + 1
tRTP
PRE
ACT
RD
RD
PRE
RD
WR
ACT
a
a
a
a
a
b
b
a
CSn0
tRC
CSn1
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Figure 11: SDRAM Timing Diagrams 3
tWTR
Data
DW0
tRRD
CMD
BA
ACT
a
DW1
DW2
tCCD
ACT WR
b
ACT WR
a
c
ACT
b
WR
d
RD
c
d
CSn0
CSn1
Figure 12: SDRAM Timing Diagrams 4
tWR
Data
DW0
tRFC
CMD
REF
BA
DW1
DW2
DW3
tRC
ACT
ACT
a
b
ACT WR
c
a
ACT
WR
WR
PRE
WR
d
b
c
a
d
ACT ACT
a
e
WR
e
tFAW
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AC Electrical Characteristics
DDR SDRAM Timing Diagrams and Specifications
Figure 13 Basic Write Timing Parameters.
Figure 13: Basic Write Timing Parameters
tDQSSmc
tDSHmc
tDQSHmc
tDSHmc
tDQSLmc
DO n
tDQSSmc
tDSSmc
tDQSHmc
tDSSmc
tDQSLmc
DO n
1 ) DO n = Data Out for column n
2 ) 3 subsequent elements of Data Out are applied in the programmed order following DO n
3 ) tDQSS: each rising edge of DQS must fall within the +/-25 % window of the corresponding positive clock edge
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May 2013 PUBLIC RELEASE
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Figure 14: DDR3 SDRAM Timing Diagrams
7.1.3
DDR SDRAM Skew Timings
Figure 16 shows the Data, Command and Address skew parameters for read and write accesses.
Refer to Table 15 for timing specifications for these parameters.
Figure 15 Shows the DQ to DQS skew during write cycles.
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DDR SDRAM Timing Diagrams and Specifications
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Figure 15: DQ to DQS Write Skew
0ps
1000ps
2000ps
3000ps
DQS
DQS
t DQTVB
tDQTVA
tDQTVB
tDQTVA
DQ
Figure 16 Shows the CLK to Address/Command skew during write cycles.
Figure 16: CLK to Address/Command Write Skew
CLKn
CLK
tATVB
ADDR/CMD/CNTRL
tATVA
Figure 17 shows the DQS-to-CLK skew during Write cycles.
Figure 17: DQS to CLK Write Skew
0ps
1000ps
CLK
3000ps
CLK
CLK
DQS
2000ps
C LK#
tDQSSmc h
DQS
DQS
DQS#
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Figure 18 Shows the DQ to DQS allowable skew during read cycles.
Figure 18: DQ to DQS Read Skew
0ps
1000ps
2000ps
3000ps
DQS
DQS
tSUmch
tHDmch
tSUmch
tHDmch
DQ
Table 15: DDR Timing Specifications
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tRCD
ACTIVE to internal read or write delay
time
1
SDRAM_TIMING_2[tRCD]
15
DCLK
tRAS
Active to Precharge command period
1
SDRAM_TIMING_5[tRAS]
63
DCLK
tRC
ACTIVE-to-ACTIVE or REFRESH (same
bank) command delay
1
SDRAM_TIMING_1[tRC]
63
DCLK
tRP
Pre-charge command period
1
SDRAM_TIMING_2[tRP]
15
DCLK
tCCD
CAS# to CAS# command delay
1
SDRAM_TIMING_1[tCCD]
7
DCLK
tXP
Exit power down to next valid command
delay
1
SDRAM_TIMING_3[tXP]
SDRAM_TIMING_3[tXARDS]
7
DCLK
tCL
CAS Latency
1
SDRAM_CTRL4[CAS_LATENCY]
7
DCLK
tCCD_CCS
CAS# to CAS# read command delay
(System level requirement)
1
SDRAM_TIMING_5[tCCD_CCS_E
XT_DLY]
7
DCLK
READ to WRITE command delay (System
level requirement)
1
SDRAM_TIMING_4[tRWD_EXT_D
LY]
7
DCLK
_EXT_DLY
tRWD_EXT
_DLY
tCCD_CCS
_WR_EXT_
DDR3 CAS# to CAS# write command
delay
SDRAM[TIMING_5[tCCD_CCS_W
R_EXT_DLY]
DCLK
DLY
tWTR
Internal write to read delay
1
SDRAM_TIMING_1[tWTR]
15
DCLK
tRRD
ACTIVE bank A to ACTIVE bank B
command period
1
SDRAM_TIMING_2[tRRD]
15
DCLK
tWR
Write recovery
1
SDRAM_TIMING_2[tWR]
15
DCLK
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DDR SDRAM Timing Diagrams and Specifications
Table 15: DDR Timing Specifications (Continued)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tFAW
Maximum number of ACTIVE or per-bank
refreshes within this period.
2
SDRAM_TIMING_5[tFAW]
2
DCLK
tXSR
Self refresh exit to next valid command
delay
1
SDRAM_TIMING_3[tXSNR]
SDRAM_TIMING_3[ tXSRD]
511
DCLK
tCKE
CKE minimum pulse width (High and low
pulse width)
1
SDRAM_TIMING_4[tCKE]
7
DCLK
tMRD
Mode Register Set command cycle time
1
SDRAM_TIMING_2[tMRD]
7
DCLK
tREFI
Auto-Refresh Interval Counter
1
SDRAM_TIMING_1[tREFI]
65535
FCLK
tRFC
Refresh to Active or Refresh to Refresh
internal
1
SDRAM_TIMING_2[tRFC]
511
DCLK
tCCD
CAS# to CAS# command delay
1
SDRAM_TIMING_1[tCCD]
7
DCLK
tRTP
Internal Read to Precharge command
delay
1
SDRAM_TIMING_1[tRTP]
7
DCLK
tINIT_COU
Power up delay after stable power and
clocks
1
SDRAM_TIMING_4[INIT_COUNT]
255
DCLK
Power up delay after stable power and
clocks
1
SDRAM_TIMING_4[INIT_COUNT
_NOP]
255
DCLK
NT
tINIT_COU
NT_NOP
NOTE:
1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF)
2. The setup and hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply
100ps extra derating for setup/hold.
3. Drive Strength reference setting for timing ZPR=ZNR=0111
Table 16: DDR Timing Specifications for 533 MHz (VDD_M = 1.8V)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tCK(Jitter)
CLK Jitter at output pin (c-c)
-100
—
100
ps
tCL
Clock low level width
0.47
—
0.53
tCK
tCH
Clock high level width
0.47
—
0.53
tCK
tCK_DC
Duty Cycle at output pin
0.42
—
0.53
tCK
tDQTVB
DQ Valid time before DQS
0.27
—
—
ns
1
tDQTVA
DQ Valid time after DQS
0.3
—
—
ns
1
tATVB
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time before CK
0.6
—
—
ns
1
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Notes
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Table 16: DDR Timing Specifications for 533 MHz (VDD_M = 1.8V) (Continued)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
Notes
tATVA
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time after CK
0.64
—
—
ns
1
tDQSSmc
DQS Output access time from CLK pos edge
—
—
0.08
ns
1
tSUmc
Max Setup skew allowed between DQ and
DQS during READ from DQS transition
—
—
0.29
ns
2
tHDmc
Hold factor for valid DQ w.r.t DQS
rising/falling edge during READ
0.65
—
—
ns
2
tDIPWmc
DQ and DM output pulse width
0.45
—
—
tCK
tDQSHmc
DQS output high pulse width
0.45
—
—
tCK
tDQSLmc
DQS output low pulse width
0.45
—
—
tCK
tDSSmc
DQS falling edge to CLK-CLKn rising edge
0.4
—
—
tCK
tDSHmc
DQS falling edge from CLK-CLKn rising
edge
0.4
—
—
tCK
tDQSSmc
Write command to first DQS latching
transition
-0.1
—
0.1
tCK
tWPREmc
DQS write preamble
0.4
—
—
tCK
tWPSTmc
DQS write postamble
0.45
—
0.55
tCK
tIPWmc
Address and Control output pulse width
0.9
—
—
tCK
tRPREmc
DQS read preamble
0.9
—
1.1
tCK
tRPSTmc
DQS read postamble
0.4
—
0.6
tCK
tDQSCKmc
DQS input access time from CLK/CLKn
2.0
—
7.0
ns
tLZmc
DQ and DQS low-impedence time from
CLK/CLKn
1
—
—
ns
tHZmc
DQ and DQS high-impedence time from
CLK/CLKn
—
—
7
ns
NOTE:
1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF)
2. The setup & hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply
100ps extra derating for setup/hold.
3. Drive Strength reference setting for timing ZPR=ZNR=0111
Table 17: DDR Timing Specifications for 400 MHz (VDD_M = 1.8V)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tCK(Jitter)
CLK Jitter at output pin (c-c)
-100
—
100
ps
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AC Electrical Characteristics
DDR SDRAM Timing Diagrams and Specifications
Table 17: DDR Timing Specifications for 400 MHz (VDD_M = 1.8V) (Continued)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tCL
Clock low level width
0.47
—
0.53
tCK
tCH
Clock high level width
0.47
—
0.53
tCK
tCK_DC
Duty Cycle at output pin
0.42
—
0.53
tCK
tDQTVB
DQ Valid time before DQS
0.42
—
—
ns
1
tDQTVA
DQ Valid time after DQS
0.42
—
—
ns
1
tATVB
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time before CK
0.9
—
—
ns
1
tATVA
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time after CK
0.94
—
—
ns
1
tDQSSmc
DQS Output access time from CLK pos edge
—
—
0.06
ns
1
tSUmc
Max Setup skew allowed between DQ and
DQS during READ from DQS transition
—
—
0.41
ns
2
tHDmc
Hold factor for valid DQ w.r.t DQS
rising/falling edge during READ
0.84
—
—
ns
2
tDIPWmc
DQ and DM output pulse width
0.45
—
—
tCK
tDQSHmc
DQS output high pulse width
0.45
—
—
tCK
tDQSLmc
DQS output low pulse width
0.45
—
—
tCK
tDSSmc
DQS falling edge to CLK-CLKn rising edge
0.4
—
—
tCK
tDSHmc
DQS falling edge from CLK-CLKn rising
edge
0.4
—
—
tCK
tDQSSmc
Write command to first DQS latching
transition
-0.1
—
0.1
tCK
tWPREmc
DQS write preamble
0.4
—
—
tCK
tWPSTmc
DQS write postamble
0.45
—
0.55
tCK
tIPWmc
Address and Control output pulse width
0.9
—
—
tCK
tRPREmc
DQS read preamble
0.9
—
1.1
tCK
tRPSTmc
DQS read postamble
0.4
—
0.6
tCK
tDQSCKmc
DQS input access time from CLK/CLKn
2.0
—
7.0
ns
tLZmc
DQ and DQS low-impedence time from
CLK/CLKn
1
—
—
ns
tHZmc
DQ and DQS high-impedence time from
CLK/CLKn
—
—
7
ns
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Notes
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Table 17: DDR Timing Specifications for 400 MHz (VDD_M = 1.8V) (Continued)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
Notes
NOTE:
1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF)
2. The setup & hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply
100ps extra derating for setup/hold.
3. Drive Strength reference setting for timing ZPR=ZNR=0111
Table 18: DDR Timing Specifications for 200 MHz (VDD_M = 1.8V)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
Units
tCK(Jitter)
CLK Jitter at output pin (c-c)
-100
—
100
ps
tCL
Clock low level width
0.47
—
0.53
tCK
tCH
Clock high level width
0.47
—
0.53
tCK
tCK_DC
Duty Cycle at output pin
0.42
—
0.53
tCK
tDQTVB
DQ Valid time before DQS
1.02
—
—
ns
1
tDQTVA
DQ Valid time after DQS
1.05
—
—
ns
1
tATVB
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time before CK
2.1
—
—
ns
1
tATVA
ADDR/CMD/CNTRL (RAS, CS, CAS, WE,
CKE, ADDR) Valid time after CK
2.14
—
—
ns
1
tDQSSmc
DQS Output access time from CLK pos edge
—
—
0.05
ns
1
tSUmc
Max Setup skew allowed between DQ and
DQS during READ from DQS transition
—
—
1.04
ns
2
tHDmc
Hold factor for valid DQ w.r.t DQS
rising/falling edge during READ
1.46
—
—
ns
2
tDIPWmc
DQ and DM output pulse width
0.45
—
—
tCK
tDQSHmc
DQS output high pulse width
0.45
—
—
tCK
tDQSLmc
DQS output low pulse width
0.45
—
—
tCK
tDSSmc
DQS falling edge to CLK-CLKn rising edge
0.4
—
—
tCK
tDSHmc
DQS falling edge from CLK-CLKn rising
edge
0.4
—
—
tCK
tDQSSmc
Write command to first DQS latching
transition
-0.1
—
0.1
tCK
tWPREmc
DQS write preamble
0.4
—
—
tCK
tWPSTmc
DQS write postamble
0.45
—
0.55
tCK
tIPWmc
Address and Control output pulse width
0.9
—
—
tCK
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AC Electrical Characteristics
DDR SDRAM Timing Diagrams and Specifications
Table 18: DDR Timing Specifications for 200 MHz (VDD_M = 1.8V) (Continued)
Symbol
D e s c r i p t io n
M in
Ty p i c a l
Max
tRPREmc
Units
DQS read preamble
0.9
—
1.1
tCK
tRPSTmc
DQS read postamble
0.4
—
0.6
tCK
tDQSCKmc
DQS input access time from CLK/CLKn
2.0
—
7.0
ns
tLZmc
DQ and DQS low-impedence time from
CLK/CLKn
1
—
—
ns
tHZmc
DQ and DQS high-impedence time from
CLK/CLKn
—
—
7
ns
Notes
NOTE:
1. Timing Specified to Reference Load (50 Ohms T line connected to 20pF)
2. The setup & hold timing is for reference slew rate of 1V/ns for DQ and 1V/ns for DQS. For slower slew rates, apply
100ps extra derating for setup/hold.
3. Drive Strength reference setting for timing ZPR=ZNR=0111
Table 19: DDR3 Timing Specifications for 533 Mhz (VDDQ=1.5V)
S y m b ol
D e s c r i p t io n
Min
tCL
Clock low level width
tCH
Max
U n i ts
0.47
0.53
tCK(avg)
Clock high level width
0.47
0.53
tCk(avg)
tCK(Jitter)
CLK Jitter at output pin (period jitter)
-50
50
ps
tCK_DC
Duty Cycle at output pin
47
53
%
tDQTVB
DQ Valid time before DQS
0.3
—
—
ns
1
tDQTVA
DQ Valid time after DQS
0.3
—
—
ns
1
tATVB
CMD/CTL Valid time before CK
0.6
—
—
ns
1
tATVA
CMD/CTL Valid time after CK
0.6
—
—
ns
1
tDQSSmch
Skew between CK and DQS
-0.13
—
0.13
tCK
1
tSUmch
Max Setup skew allowed between DQ
and DQS during READ from DQS
transition
—
0.318
ns
2
tHDmch
Hold factor for valid DQ w.r.t DQS
rising/falling edge during READ
0.618
—
—
ns
2
tWPREmc
DQS, DQS# differential Write Preamble
0.9
—
—
tCK(avg)
tWPSTmc
DQS, DQS# differential Write Postamble
0.45
—
—
tCK(avg)
tIPWmc
Control and Address Input pulse width
0.8
—
—
tCK(avg)
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Ty p i c a l
N o te s
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Table 19: DDR3 Timing Specifications (Continued)for 533 Mhz (VDDQ=1.5V)
S y m b ol
D e s c r i p t io n
Min
Ty p i c a l
Max
U n i ts
tDIPWmc
DQ and DM Input pulse width
0.4
—
—
tCK(avg)
tDQSOH
DQS output high pulse width
0.47
0.53
tCK(avg)
tDQSOL
DQS output low pulse width
0.47
0.53
tCK(avg)
N o te s
NOTE: 1. Timing Specified to Reference Load (25 Ohms to VTT)
2. The setup & hold timing is for reference slew rate of 1V/ns for DQ and 2V/ns for DQS (diff). Refer to derating table below
for other slew rates.
Figure 19: Reference Load
Table 20: DDR3 Setup/Hold Derating table
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Static Memory Controller Timing Diagrams and Specifications
7.2
Static Memory Controller Timing Diagrams and
Specifications
7.2.1
Address Cycle
Figure 20 shows the timing for the address cycles during an A/D Operating mode access. Figure 21
shows the timing for the address cycles during an AA/D Operating mode access.The DFI
Configuration Control Register for Chip Selects (SMC_CSDFICFGx) determines each timing
parameter using the SMC_SCLK clock frequency. Refer to Table 21 for a list of registers used to
program the address phase timing paramaters.
Figure 20: A/D Address Phase
SMC_SCLK
SMC_NCSx
SMC_NOE
SMC_NWE
SMC_NBE[1:0]
Address[ 15:0]
ND_IO[15:0]
ALTS
A LW
A LTH
SMC_ADV
SMC_ADVMUX
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_CSDFICFGx[ADDMODE] = 0x0
4. SMC_WE_APx[WE_AP_VAL] = 0xFFF
5. SMC_OE_APx[OE_AP_VAL] = 0xFFF
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May 2013 PUBLIC RELEASE
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Figure 21: AA/D Address Phase
SMC_SCLK
SMC_NCSx
SMC_NOE
SMC_NWE
SMC_NBE[1:0]
Address[2 7:16]
ND_IO[15:0]
Address[1 5:0]
SMC_ADDR[20:16]
ALTS
ALW
A LTH
SMC_ADV
ALTS
ALW
ALTH
SMC_ADVMUX
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_CSDFICFGx[ADDMODE] = 0x1
4. SMC_WE_APx[WE_AP_VAL] = 0xFFF
5. SMC_OE_APx[OE_AP_VAL] = 0xFFF
7.2.2
Read Access Data Phases
Figure 22 - Figure 25 show timing diagrams of the data phase during Read accesses. The Static
Memory Control Register (SMC_MCSx) and Synchronous Static Memory Controller Register
(SMC_SXCNFGx) determines each timing parameter using the SMC_SCLK clock frequency. Refer
to Table 21 for a list of registers used to program the read data timing parameters.
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Static Memory Controller Timing Diagrams and Specifications
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Figure 22: Asynchronous Read With RDY Signal
SMC_NCSx
OE_GEN
SMC_NOE
SMC_NWE
SMC_NBE[1:0]
OE_SU
ND_IO[15:0]
Address[27:16]
OE_D_HO
Address[15:0]
OE_HO
Data
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTS
ALW
ALTH
SMC_ADVMUX
OE_D_SU
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFFF
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_MCSx[OE_SU] = 0x1
6. SMC_MCSx[OE_GEN] = 0x1
7. SMC_CSDFICFGx[RDY_SPEC4] = 0x1
8. SMC_CSDFICFGx[RDY_SPEC3] = 0x0
9. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x1 or 0x3
10. SMC_CSDFICFGx[RDY_SPEC0] = 0x1
11. SMC_CSDFICFGx[RDSYNC] = 0x2
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Figure 23: Asynchronous Read Without RDY Signal
SMC_NCSx
OE_GEN
SMC_NOE
SMC_NWE
OE_D_SU
SMC_NBE[1:0]
OE_SU
ND_IO[15:0]
Address[27:16]
Address[15:0]
OE_D_HO
OE_HO
Data
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTS
ALW
ALTH
SMC_ADVMUX
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFFF
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_MCSx[OE_SU] = 0x1
6. SMC_MCSx[OE_D_SU] = 0x3
7. SMC_MCSx[OE_D_HO] = 0x3
8. SMC_MCSx[OE_HO] = 0x1
9. SMC_MCSx[OE_GEN] = 0x1
10. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x0 or 0x2
11. SMC_CSDFICFGx[RDSYNC] = 0x0
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AC Electrical Characteristics
Static Memory Controller Timing Diagrams and Specifications
Figure 24: Synchronous Read With RDY Signal
tCLKL
tCLKH
SCLK
OE_GEN
SMC_NCSx
OE_SU
SMC_NOE
SMC_NWE
SMC_NBE[1:0]
tIH
tISU
ND_IO[15:0]
Address[27:16]
Address [15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTH
ALTS
ALW
Access time determiined by RDY
SMC_ADVMUX
SMC_RDY
NOTE:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFFF
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_SXCNFGx[SXRA] = 0x5
6. SMC_MCSx[OE_SU] = 0x1
7. SMC_MCSx[OE_GEN] = 0x1
8. SMC_CSDFICFGx[RDY_SPEC4] = 0x1
9. SMC_CSDFICFGx[RDY_SPEC3] = 0x0
10. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x1 or 0x3
11. SMC_CSDFICFGx[RDY_SPEC0] = 0x1
12. SMC_CSDFICFGx[RDSYNC] = 0x1
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Figure 25: Synchronous Read Without RDY Signal
tCLKL
tCLKH
SCLK
OE_GEN
SMC_NCSx
OE_SU
SMC_NOE
SMC_NWE
0b00
SMC_NBE[1:0]
tIH
tISU
ND_IO[15:0]
Address[27:16]
Address[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTH
ALTS
ALW
SXRA
SMC_ADVMUX
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFFF
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_SXCNFGx[SXRA] = 0x6
6. SMC_MCSx[OE_SU] = 0x1
7. SMC_MCSx[OE_GEN] = 0x1
8. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x0 or 0x2
9. SMC_CSDFICFGx[RDSYNC] = 0x1
7.2.3
Write Access Data Phases
Figure 26 - Figure 29 show timing diagrams of the data phase during Write accesses.The Static
Memory Control Register (SMC_MCSx) and Synchronous Static Memory Controller Register
(SMC_SXCNFGx) determines each timing parameter using the SMC_SCLK clock frequency. Refer
to Table 21 for a list of registers used to program the write data timing paramaters.
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Static Memory Controller Timing Diagrams and Specifications
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Figure 26: Asynchronous Write With RDY Signal
WE_GEN
SMC_NCSx
SMC_NOE
WE_HO
SMC_NWE
SMC_NBE[1:0]
WE_SU
ND_IO[15:0]
Address[27:16]
Address[15:0]
Data
SMC_ADDR[20:16]
AL TS
ALW
ALTH
SMC_ADV
ALTS
ALW
ALTH
SMC_ADVMUX
WE_LEN
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
2. SMC_CSDFICFGx[ALTH] = 0x1
3. SMC_CSDFICFGx[ALW] = 0x1
4. SMC_WE_APx[WE_AP_VAL] = 0xFFF
5. SMC_OE_APx[OE_AP_VAL] = 0xFFF
6. SMC_MCSx[WE_SU] = 0x1
7. SMC_MCSx[WE_LEN] = 0x1
8. SMC_MCSx[WE_D_HO] = 0x1
9. SMC_CSDFICFGx[RDY_SPEC4] = 0x1
10. SMC_CSDFICFGx[RDY_SPEC3] = 0x0
11. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x2 or 0x3
12. SMC_CSDFICFGx[RDY_SPEC0] = 0x1
13. SMC_CSDFICFGx[WRSYNC] = 0x0
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Figure 27: Asynchronous Write Data Phase Without RDY Signal
WE_GEN
SMC_NCSx
SMC_NOE
WE_LEN
WE_HO
SMC_NWE
SMC_NBE[1:0]
WE_SU
ND_IO[15:0]
Address[27:16]
A ddress[15:0]
Data
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTS
ALW
ALTH
SMC_ADVMUX
SMC_RDY
N ot e s:
1. SMC_CSDFICFGx[ALTS] = 0x1
2. SMC_CSDFICFGx[ALTH] = 0x1
3. SMC_CSDFICFGx[ALW] = 0x1
4. SMC_WE_APx[WE_AP_VAL] = 0xFFF
5. SMC_OE_APx[OE_AP_VAL] = 0xFFF
6. SMC_MCSx[WE_SU] = 0x1
7. SMC_MCSx[WE_LEN] = 0x1
8. SMC_MCSx[WE_D_HO] = 0x1
9. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x0 or 0x1
10. SMC_CSDFICFGx[WRSYNC] = 0x2
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AC Electrical Characteristics
Static Memory Controller Timing Diagrams and Specifications
Figure 28: Synchronous Write With RDY Signal
SMC_SCLK
WE_GEN
SMC_NCSx
SMC_NOE
ALW
ALTS
ALTH
SMC_NWE
SMC_NBE[1:0]
tODH
tODV
DF_IO[15:0]
Address[27:16]
Address[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
ALTH
ALTS
ALW
SXWA
SMC_ADVMUX
Access time depends on RDY
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFF7
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_CSDFICFGx[RDY_SPEC4] = 0x1
6. SMC_CSDFICFGx[RDY_SPEC3] = 0x0
7. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x2 or 0x3
8. SMC_CSDFICFGx[RDY_SPEC0] = 0x1
9. SMC_CSDFICFGx[WRSYNC] = 0x1
10. SMC_SXCNFGx[SXWA] = 0x5
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Figure 29: Synchronous Write Data Phase Without RDY Signal
SMC_SCLK
WE_GEN
SMC_NCSx
SMC_NOE
A LW
A LTS
ALTH
SMC_NWE
SMC_NBE[1:0]
tODH
tODV
DF_IO[15:0]
Address[27:16]
Address[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMC_ADDR[20:16]
ALTS
ALW
ALTH
SMC_ADV
A LTH
ALTS
ALW
SXWA
SMC_ADVMUX
A cces s time depends on RDY
SMC_RDY
Notes:
1. SMC_CSDFICFGx[ALTS] = 0x1
1. SMC_CSDFICFGx[ALTH] = 0x1
2. SMC_CSDFICFGx[ALW] = 0x1
3. SMC_WE_APx[WE_AP_VAL] = 0xFF7
4. SMC_OE_APx[OE_AP_VAL] = 0xFFF
5. SMC_SXCNFGx[SXWA] = 0x5
6. SMC_CSDFICFGx[RDY_SPEC2_1] = 0x0 or 0x1
7. SMC_CSDFICFGx[WRSYNC] = 0x1
S y m b ol
Table 21: Static Memory Controller Interface Timing Specifications
D e s c r i p t io n
Min 2
Min 3
Ty p i c a l
Max
U ni ts
tCK
SMC_SCLK frequency
31.2
62.4
PMUA_SMC_CLK_RES_CTRL[
SMC_CLK_SEL]
62.4
MHz
WE_GEN
Delay after the last data is
latched until the chip select is
de-asserted.
1
1
SMC_MCSx[WE_GEN]
3
SMC_SCLK
WE_D_HO
Data hold cycles after
SMC_nWE latches the data
1
1
SMC_MCSx[WE_D_HO]
7
SMC_SCLK
WE_D_SU
Data setup time prior to
SMC_nWE assertion
1
1
SMC_MCSx[WE_D_SU]
7
SMC_SCLK
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Static Memory Controller Timing Diagrams and Specifications
Table 21: Static Memory Controller Interface Timing Specifications (Continued)
Min 3
Ty p i c a l
Max
S y m bo l
Min 2
D e s c r i p t io n
U ni ts
WE_LEN
Length of the SMC_nWE latch
1
1
SMC_MCSx[WE_LEN]
63
SMC_SCLK
OE_GEN
Delay after the last data is
latched until the chip select is
de-asserted.
1
1
SMC_MCSx[OE_GEN]
7
SMC_SCLK
OE_HO
Data hold cycles after SMC_nOE
latches data
1
1
SMC_MCSx[OE_HO]
3
SMC_SCLK
OE_SU
Setup time prior to SMC_nOE
assertion
1
1
SMC_MCSx[OE_SU]
7
SMC_SCLK
OE_D_HO
Hold prior to SMC_NOE
de-assertion
1
1
SMC_MCSx[OE_D_HO]
7
SMC_SCLK
OE_D_SU
Read data setup prior to
SMC_nOE latching the data.
1
1
SMC_MCSx[OE_D_SU]
63
SMC_SCLK
ALTS
Address Latch setup time
0
0
SMC_CSDIFCFGx[ALTS]
2
SMC_SCLK
ALTH
Address Latch hold time
0
0
SMC_CSDIFCFGx[ALTH]
2
SMC_SCLK
ALW
Address latch width
1
1
SMC_CSDIFCFGx[ALTW]
7
SMC_SCLK
SXWA
Access time for synchronous
writes
3
3
SMC_SXCNFGx[SXWA]
10
SMC_SCLK
SXRA
Access time for synchronous
reads
3
3
SMC_SXCNFGx[SXRA]
10
SMC_SCLK
tISU
Synchronous Read data setup
time
4.04
4.04
—
—
ns
tIH
Synchronous Read data hold
time
2.0
2.0
—
—
ns
tODV
Synchronous Write data valid
before SMC_SCLK
14.7
6.7
—
—
ns
tODH
Synchronous Write data hold
time
17.3
9.3
—
—
ns
1. SMC_SCLK frequency depends on the APMU_SMC_CLK_RES_CTRL[SMC_CLK_SEL] programmed value
2. SMC_SCLK = 31.2 MHz (APMU_SMC_CLK_RES_CTRL[SMC_CLK_SEL = 0x1])
3. SMC_SCLK = 62.4 MHz (APMU_SMC_CLK_RES_CTRL[SMC_CLK_SEL = 0x0])
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7.3
NAND Timing Diagrams and Specifications
This section describes the timing diagrams for NAND flash programming, Erase, Read, Status Read,
and ID Read with timing parameters.
7.3.1
NAND Flash Program Timing
Figure 30 illustrates the programming sequence for a Flash device. The Flash device is addressed
with up to seven cycles depending on the value of Number of Address Cycles field (ADDR_CYC) in
the NAND Controller Command Buffer 0 (NDCB0) register and the external NAND device
requirements. Refer to Table 22 for the detailed descriptions of the timing parameters.
If the Auto-read Status bit (AUTO_RS) is set in the command, the NAND Flash Controller performs a
status check (Command 0x70) to determine whether the program operation was successful.
Figure 30: NAND Flash Program Timing Diagram
tWEH
tWEH
tWEH
ND_CLE
ND_nCSx
tADL
tw(WL)
tWES
tWES
tWRCYCLE
tw(WH)
tWES
tWES
ND_nWE
tWEH
ND_ALE
ND_nRE
tODH
tODLY
DF_IO<15:0>
80h
tODV
ADDR1
ADDR2
ADDR3
ADDR41
tODH
DOUT N
DOUT N+1
DOUT M2
10h
70h
Status
ND_RnB
1. The number of address cycles depends on the NAND device being accessed and NDCB0[ADDR_CYC].
2. M is defined by the NDCR[PAGE_SZ], NDCR[SPARE_EN] and NDCR[ECC_EN] values.
7.3.2
NAND Flash Erase Timing
Figure 31 illustrates the erase sequence for a Flash device. The block to be erased in the Flash
device is addressed in up to seven cycles depending on the value of Number of Address Cycles field
(ADDR_CYC) in the NAND Controller Command Buffer 0 (NDCB0) register and the external NAND
device requirements. Refer to Table 22 for the detailed descriptions of the timing parameters.
If the Auto-read Status bit (AUTO_RS) is set in the command, the NAND Flash Controller performs a
status check (Command 0x70) to determine whether the Erase operation was successful.
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AC Electrical Characteristics
NAND Timing Diagrams and Specifications
Figure 31: NAND Flash Erase Timing Diagram
tWEH
tWEH
ND_CLE
ND_nCSx
tw(W H)
tWES
tWES
tw(WL)
tWES
ND_nWE
ND_ALE
tw(RL)
ND_nRE
tODV
tODV
tODH
DF_IO<15:0>
60h
ADDR1
tODH
ADDR2
ADDR3
D0h
70h
Status
ND_RnB
7.3.3
Small Block NAND Flash Read Timing
Figure 32 illustrates the Read sequence for a Small-block Flash device. The Flash device is
addressed in four cycles. Refer to Table 22 for detailed descriptions of the timing parameters.
Figure 32: NAND Flash Small Block Read Timing Diagram
tWEH
ND_CLE
ND_nCSx
tWES
tWES
tw(WL)
tw(WH)
ND_nWE
tWEH
ND_ALE
td(WHRL)
tRDCYCLE
tw(RL)
tw(RH)
ND_nRE
tODV
tODH
DF_IO <15:0 >
00h
ADDR1
ADDR2
tISU
ADDR3
ADDR41
tIH
DIN N
DIN N+1
DIN M2
ND_RnB
1. The number of address cycles depends on the NAND device being accessed and NDCB0[ADDR_CYC].
2. M is defined by the NDCR[PAGE_SZ], NDCR[SPARE_EN] and NDCR[ECC_EN] values.
7.3.4
Large Block NAND Flash Read Timing
Figure 33 illustrates the Read sequence for a Large-block Flash device. The Flash device is
addressed in up to seven cycles depending on the value of Number of Address Cycles field
(ADDR_CYC) in the NAND Controller Command Buffer 0 (NDCB0) register and the external NAND
device requirements. Refer to Table 22 for detailed descriptions of the timing parameters.
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Figure 33: NAND Flash Large Block Read Timing Diagram
tWEH
ND_CLE
ND_nCSx
tWES
tWES
tw(WL)
tw(WH)
ND_nWE
tWEH
ND_ALE
td(WHRL)
tRDCYCLE
tw(RL)
tw(RH)
ND_nRE
tODV
tIH
tODH
DF_IO <15:0 >
00h
ADDR1
ADDR2
tISU
ADDR3
ADDR4
1
30h
DIN N
DIN N+1
DIN M2
ND_RnB
1. The number of address cycles depends on the NAND device being accessed and NDCB0[ADDR_CYC].
2. M is defined by the NDCR[PAGE_SZ], NDCR[SPARE_EN] and NDCR[ECC_EN] values.
7.3.5
NAND Flash Status Read Timing
Figure 34 illustrates the Status-Read sequence for a Flash device. Refer to Table 22 for detailed
descriptions of the timing parameters.
Figure 34: NAND Flash Status Read Timing Diagram
tWEH
ND_CLE
ND_nCSx
tWES
tw(WH)
tw(WL)
ND_nWE
td(WHSRL)
tw(RL)
ND_nRE
tODV
tODH
DF_IO<15:0>
7.3.6
70h
Status
NAND Flash ID Read Timing
Figure 35 illustrates the ID Read sequence for a Flash device. Refer to Table 22 for detailed
descriptions of the timing parameters.
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AC Electrical Characteristics
NAND Timing Diagrams and Specifications
Figure 35: NAND Flash ID Read Timing Diagram
ND_nCSx
tWEH
ND_CLE
tw(WL)
tWES
ND_NWE
tWES
tWEH
ND_ALE
td(ALRL)
tw(RL)
tw(RH)
ND_NRE
tODV
tODH
90h
DF_IO <7:0 >
00h
Byte N
Byte N+1
Byte M1
1. The total number of bytes is determined by the NDCR[RD_ID_CNT] value
7.3.7
NAND Flash Reset Timing
Figure 36 illustrates the reset sequence for a Flash device. Refer to Table 22 for detailed
descriptions of the timing parameters.
Figure 36: NAND Flash Reset Timing Diagram
ND_CLE
ND_nCSx
tWES
tWEH
ND_nWE
ND_ALE
ND_nRE
DF_IO<15:0 >
0xFF
ND_RnB
7.3.7.1
NAND Flash Timing Parameters
Table 22 provides the values for the timing parameters seen in Figure 30, Figure 31, Figure 32,
Figure 33, Figure 33, Figure 34, Figure 35 and Figure 36.
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Table 22: NAND Flash Interface Program Timing Specifications
Min 1
Min 2
Ty p i c a l
Max
U n i ts
Setup time of ND_CLE, ND_ALE,
ND_nCS to ND_nWE falling
1
1
NDTR0CS0[tCS] + 1
8
NCLK
tWEH
Hold time from ND_nWE rising to
ND_CLE and ND_ALE falling
2
2
Max (NDTR0CS0(tCH),
NDTR0CS0(tWH)) + 1
8
NCLK
tw(WL)
ND_nWE low pulse width
2
2
NDTR0CS0[tWP] + 1
8
NCLK
tw(WH)
ND_nWE high pulse width
2
2
Max (TR0CS0(tCH),
TR0CS0(tWH)) + 1
8
NCLK
tw(RL)
ND_nRE low pulse width
2
2
NDTR0CS0[etRP, tRP] + 1
16
NCLK
tw(RH)
ND_nRE high pulse width
2
2
NDTR0CS0[tRH] + 1
8
NCLK
td(WHRL)
ND_nWE rising to ND_nRE falling
delay for Read
3900
3900
(NDTR1CS0[tR] + 2) +
(NDTR0CS0[tCH] + 1)
655364
10485765
NCLK
td(WHRL)
ND_nWE rising to ND_nRE falling
delay for Status Read/ Read ID
8
8
max(tWH,tCH) + max(tAR, max(0,
tWHR-max(tWH,tCH) ) ) + 3
15
NCLK
td(ALRL)
ND_ALE falling to ND_nRE falling
delay for ID read
8
8
Max(NDTR1CS0(tAR),max(0,NDT
R1CS0(tWHR) max(NDTR0CS0(tWH, tCH))) + 2
15
NCLK
tADL
Final ND_nWE rising edge during
the Address cycle to first ND_nWE
rising edge during the Data cycle
1
1
max(tWH,tCH) + max(0,
tADL-tWP-3) + tWP + 8
28
NCLK
tRHW
Last ND_nRE rising edge to the
first falling edge of ND_nWE when
read command is immediately
followed by another command.
1
1
NDTR1CS0[tRHW]
3
NCLK
tODH
DF_IO<15:0> output data hold
time after ND_nWE rising
12.8
25.6
—
—
ns
tODV
DF_IO<15:0> data valid time
before ND_nWE rising
19.2
38.5
—
—
ns
tIsu
DF_IO<15:0> setup time
requirement to nRE rising
3.7
3.7
—
—
ns
tIH
DF_IO<15:0> hold time
requirement to nRE rising
3.2
3.2
—
—
ns
tRDCYCLE
Read cycle times
32
64
—
—
ns
tWRCYCLE
Write cycle times
32
64
—
—
ns
Sym bol
D e s c r i p t io n
tWES
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AC Electrical Characteristics
SD Host Controller (SDH) Timing Diagrams and Specifications
Table 22: NAND Flash Interface Program Timing Specifications (Continued)
Sym bol
Min 1
D e s c r i p t io n
Min 2
Ty p i c a l
Max
U n i ts
NOTE:
1. NCLK represents the clock period using a 156 MHz clock (APMU_NFC_CLK_RES_CTRL[NF_CLK_SEL] = 0)
2. NCLK represents the clock period using a 78 MHz clock (APMU_NFC_CLK_RES_CTRL[NF_CLK_SEL] = 1)
3. Refer to the Aspen (88AP168) Processor Software Specifications Manual for more information on the NDTR0CS0 and
NDTR0CS1 registers.
4. NDTR1CS0[Prescale] = 0
5. NDTR1CS0[Prescale] = 1
\
7.4
SD Host Controller (SDH) Timing Diagrams and
Specifications
Figure 37 and Table 23 define the MultiMedia Card Controller (MMC) AC timing specifications.
Figure 37 and Table 24 define the Secure Digital (SD), and Secure Digital I/O (SDIO) AC timing
specifications.
Figure 37: MultiMedia Card Timing Diagrams
SDH1
SDH2
SDH3
MMCx_CLK
SDH4
SDH5
CMD/DAT Input
SDH7
SDH6
CMD/DAT output
N ot e s:
1. CMD/DAT input are inputs to the SD Host Controller and outputs from the card
2. CMD/DAT output are outputs from the SD Host Controller and inputs to the card
Table 23: MultiMedia Card Timing Specifications
S y m b ol
P a r am e t e r
M in
Max
Unit
N ot e s
SDH1
MMCx_CLK Frequency in Full Speed MMC Data Transfer Mode
0
26
MHz
1
SDH1
MMCx_CLK Frequency in High Speed MMC Data Transfer Mode
0
52
MHz
1
SDH1
MMCx_CLK Frequency Identification Mode
0
400
kHz
1
SDH2
Clock low time
9.6
—
ns
SDH3
Clock high time
9.6
—
ns
SDH4
Data input setup time
3.3
—
ns
SDH5
Data input hold time
3
—
ns
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Table 23: MultiMedia Card Timing Specifications (Continued)
S y m b ol
P a r am e t e r
M in
Max
SDH6
SDH7
Unit
Output data setup time
6.6
—
ns
Output data hold time
10.8
—
ns
N ot e s
NOTE:
1. MMCx_CLK clock frequency is determined by the APMU_SDHx_CLK_RES_CTRL[SDH1_CLK_SEL] and
SD_CLOCK_CTRL[SD_FREQ_SEL] register fields.
Table 24: SD/SDIO Timing Specifications
S y m b ol
P a r am e t e r
M in
Max
Unit
N ot e s
SDH1
MMCx_CLK Frequency in Full Speed SD/SDIO Data Transfer
Mode
0
24
MHz
1
SDH1
MMCx_CLK Frequency in High Speed SD/SDIO Data Transfer
Mode
0
48
MHz
1
SDH1
MMCx_CLK Frequency Identification Mode
0
400
kHz
1
SDH2
Clock low time
10.4
—
ns
SDH3
Clock high time
10.4
—
ns
SDH4
Data input setup time
3.3
—
ns
SDH5
Data input hold time
3
—
ns
SDH6
Output data setup time
7.4
—
ns
SDH7
Output data hold time
11.6
—
ns
NOTE:
1. MMCx_CLK clock frequency is determined by the APMU_SDHx_CLK_RES_CTRL[SDH1_CLK_SEL] and
SD_CLOCK_CTRL[SD_FREQ_SEL] register fields.
7.5
LCD Controller Timing Diagrams and Specifications
Refer to the pins chapter in the Marvell® Armada 16x Applications Processor Datasheet for
descriptions of the signals shown in Figure 38 through Figure 41 and in Table 26.
7.5.1
LCD Smart Panel Timing and Specifications
This section details the LCD Smart Panel timing requirements. Additional registers as shown in
Table 26 are used to configure the LCD controller for smart panel operation.
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LCD Controller Timing Diagrams and Specifications
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Figure 38: Smart Panel Interface 8-bit 8080-Series Parallel Mode Read Interface Protocol
SMPN_A0
TCYCLE
SMPN_CSB[1:0]n
SMPN_WRB
TAS
TDSW_RD
SMPN_RDB
TAH_RD
TACC
Valid Data
SMPN_DB[7:0]
Figure 39: Smart Panel Interface 8-bit 8080-Series Parallel Mode Write Interface Protocol
SMPN_A0
TCYCLE
SMPN_CSB[1:0]n
SMPN_RDB
TAS
TAH_WR
SMPN_WRB
TDSW_WR
SMPN_DB[7:0]
Valid Data
TD_WRB
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Figure 40: Smart Panel Interface 8-bit 6800-Series Parallel Mode Read Interface Protocol
SMPN_A0
TCYCLE
TDSW_RD
SMPN_CSB[1:0]n
TAH_RD
TAS
SMPN_WRB
SMPN_RDB
TACC
Valid Data
SMPN_DB[7:0]
Figure 41: Smart Panel Interface 8-bit 6800-Series Parallel Mode Write Interface Protocol
SMPN_A0
TCYCLE
SMPN_CSB[1:0]n
TAH_WR
TAS
SMPN_WRB
SMPN_RDB
TDSW_WR
SMPN_DB[7:0]
Valid Data
TD_WRB
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AC Electrical Characteristics
LCD Controller Timing Diagrams and Specifications
Figure 42:
SPI Write/Read Protocol
TCYCLE
SPI_CSB[1:0]
SPI_CLK
Output Data to Smart Panel
Input Data from Smart Panel
Internal I/O Pad Output
Active Low Enable
Signal
SPI_DIN
SPI_DOUT
The SPI_CLK Enable signal and Internal I/O Pad Output Active Low Enable Signal enable the I/O Pad.
Table 25: LCD Smart Panel Controller Timing
Sy m b o l
Parameter
Min
Ty p
Max
TAS
U n i ts
Address setup time (A0)
—
Fixed 1
—
SCLK_SMPN cycles1
TDSW_RD
Read strobe time
1
LCD_SPU_SMPN_CTRL[CFG_ISA_RXLOW]
16
SCLK_SMPN cycles1
TDSW_WR
Write strobe time
1
LCD_SPU_SMPN_CTRL[CFG_ISA_TXLOW]
16
SCLK_SMPN cycles1
TAH_RD
Read data hold time
1
LCD_SPU_SMPN_CTRL[CFG_ISA_RXHIGH]
16
SCLK_SMPN cycles1
TAH_WR
Write data hold time
1
LCD_SPU_SMPN_CTRL[CFG_ISA_TXHIGH]
16
SCLK_SMPN cycles1
TD_WRB
Write data valid prior to
SMPN_WRB
6
—
—
ns
TACC
Smart Panel read
latency
—
—
20
ns
TCYCLE
SPI_CLK frequency
—
LCD_SPI_CTRL[CFG_SCLKCNT]
70
MHz2
TCYCLE
Read Cycle time
3
TAH_RD + TDSW_RD + 1 clock cycle
33
TCYCLE
Write Cycle time
3
TAH_WR + TDSW_WR + 1 clock cycle
33
1. TThe panel clock source frequency is derived from one of three sources (ACLK, HCLK, 312 MHz (PLL1) or external
LCD_PCLK) depending on the SCLK_SOURCE_SELECT, SCLK_AHB_AXI, and SCLK_INT_EXT fields in the
LCD_CFG_SCLK_DIV register. The panel clock source is then divided using LCD_SCLK_DIV[CLK_INT_DIV] and
LCD_SCLK_DIV[CLK_FRAC_DIV] to generate SCLK_SMPN. For more information on generating the SCLK_SMPN
frequency refer to the LCD chapter in the Marvell® Armada 16x Applications Processor Datasheet
2. LCD_SPU_SPI_CTRL[CFG_SCLKCNT] is used to divide PCLK to get SPI_CLK
7.5.2
LCD Dumb Panel Timing and Specifications
Figure 43 and Figure 44 show the horizontal and vertical dumb-panel timing diagrams. Refer to
Table 26 for the registers used to program the LCD controller for dumb-panel operation.
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Figure 43: Dumb LCD Panel Horizontal Timing
TH_TOTAL
Hsync Pulse
LCLK/HSYNC
THBP
THSW
TH_ACTIVE
THFP
DENA
1
PCLK
2
3
4
1
2
3
HTotal
Pixel Bus
1
2
3
4
HActive
Figure 44: Dumb LCD Panel Vertical Timing
TV_ACTIVE
TVBP
TVFP
TV_TOTAL
TVSW
Vsync Pulse
VCLK/VSYNC
HSYNC
N
1
2
3
4
1
2
3
VTotal
PCLK
Pixel Bus
1LINE
2LINE
1LINE
LINE
VActive
Table 26: LCD Dumb Panel Timing1
Sy m b o l
Parameter
Min
Ty p
Max
tPCLK
PCLK period
—
—
70
MHz
tCH
PCLK high time
7
—
—
ns
tCL
PCLK low time
7
—
—
ns
tDSU
Data Setup time
6
—
—
ns
tDH
Data Hold time
—
—
5
ns
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AC Electrical Characteristics
LCD Controller Timing Diagrams and Specifications
Table 26: LCD Dumb Panel Timing1 (Continued)
Sy m b o l
Parameter
Min
Ty p
Max
U ni ts
N ot e s
THBP
Horizontal back porch
0
LCD_SPU_H_PORCH[CFG_H_BACK_PORCH]
4096
PCLK
cycles
2
THFP
Horizontal front porch
0
LCD_SPU_H_PORCH[CFG_H_FRONT_PORCH]
4096
PCLK
cycles
2
THSW
Hsync pulse width
1
CFG_H_TOTAL – CFG_H_BACK_PORCH –
CFG_H_ACTIVE – CFG_H_FRONT_PORCH
4096
PCLK
cycles
2
TH_TOTAL
Total horizontal pixels
1
LCD_SPU_V_H_TOTAL[CFG_H_TOTAL]
4096
Lines
TH_ACTIVE
Number of active
horizontal lines
1
LCD_SPU_V_H_ACTIVE[CFG_H_ACTIVE]
4096
PCLK
cycles
2,4
TVBP
Vertical back porch
0
LCD_SPU_V_PORCH[CFG_V_BACK_PORCH]
4096
Lines
6
TVFP
Vertical front porch
0
LCD_SPU_V_PORCH[CFG_V_FRONT_PORCH]
4096
Lines
7
TVSW
Vsync pulse width
1
CFG_V_TOTAL – CFG_V_BACK_PORCH –
CFG_V_ACTIVE– CFG_V_FRONT_PORCH
4096
Lines
3
TV_ACTIVE
Panel Width
1
LCD_SPU_V_H_ACTIVE[CFG_V_ACTIVE]
4096
Lines
5
TV_TOTAL
Total Vertical Lines
1
LCD_SPU_V_H_TOTAL[CFG_V_TOTAL]
4096
Lines
Notes:
1. Pixel clock can be inverted to make its rising edge at the middle of pixel data cycle. It is always guaranteed
setup and hold requirement.
2. The panel clock source frequency is derived from one of three sources (ACLK, HCLK, 312 MHz (PLL1) or
external LCD_PCLK) depending on the SCLK_SOURCE_SELECT, SCLK_AHB_AXI, and SCLK_INT_EXT
fields in the LCD_CFG_SCLK_DIV register. The panel clock source is then divided using
LCD_SCLK_DIV[CLK_INT_DIV] and LCD_SCLK_DIV[CLK_FRAC_DIV] to generate PCLK. For more
information on generating the PCLK frequency refer to the LCD chapter in the Marvell® Armada 16x
Applications Processor Datasheet
3. Vsync pulse can be configured as small as 1 cycle.
4. Sets the active horizontal screen display width for both Dumb Panel and Smart Panel.
5. Sets the active vertical screen display size for both Dumb Panel and Smart Panel.
6. VSYNC active edge at pixel count = TH_ACTIVE + 1.
7. VSYNC inactive edge at pixel count = TH_TOTAL + 1.
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May 2013 PUBLIC RELEASE
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7.6
Quick Capture Camera Interface (CCIC) Timing
Diagrams and Specifications
7.6.1
CCIC Parallel Interface Timing Requirements
Figure 45: Parallel Timing Diagram
tCL
tCH
tpclk
CAM_PCLK(Sensor output)
tSU
tH
CAM_VSYNC/CAM_HSYNC/CAM_DATAx
Table 27: CCIC Parallel Timing
Sy m b o l
Parameter
Min
Ty p
Max
U n i ts
tPCLK
PCLK period
0.1
—
78
MHz
tSU
Vsync/Hsync/Pixel Data setup
2.5
—
—
ns
tH
Vsync/Hsync/Pixel Data hold
1.5
—
—
ns
tCH
PCLK high time
6.41
—
—
ns
tCL
PCLK low time
6.41
—
—
ns
7.7
N ot e s
SSP Timing Diagrams and Specifications
Figure 46 and Table 28 convey the SSP timing parameters with SSP in Master mode. The processor
drives SSPx_CLK and SSPx_FRM when in Master mode. Figure 47 and Table 29 convey the SSP
timing parameters with SSP in Slave mode. The processor receives SSPx_CLK and SSPx_FRM
when in Slave mode.
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SSP Timing Diagrams and Specifications
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SSP Master Mode Timing
Figure 46: SSP Master Mode Timing Diagram
Tw(CH)
Tw(CL)
SSPx_ CLK
t0FV
SSPx_ FRM
tOFH
tODV
tODH
SSPx_ TXD
tIsu
tIh
SSPx_ RXD
1. SCLKDIR field in the SSP Control Register 1 (SSP_SSCR1) = 0x0
2. SFRMDIR field in the SSP Control Register 1 (SSP_SSCR1) = 0x0
3. The SPO and SPH fields in the SSP Control Register 1 (SSP_SSCR1) are used to determine the polarity of
SSPx_CLK
Table 28: SSP Master Mode Timing Specifications
Sy m b o l
D e sc r ip ti o n
M in
Max
tw(CH)
U n i ts
SSPx_SCLK pulse width high duration
9.6
—
ns
tw(CL)
SSPx_SCLK pulse width low duration
9.6
—
ns
tODV
SSPx_TXD output valid prior to SSPx_CLK
1.1
—
ns
tODH
SSPx_TXD output hold time
7.6
—
ns
tOFH
SSPx_FRM output hold time
6.9
—
ns
tOFV
SSPx_FRM output valid prior to SSPx_CLK
0.6
—
ns
tIsu
SSPx_RXD to SSPx_CLK setup time
0.6
—
ns
tIh
SSPx_CLK to SSPx_RXD hold time
14.9
—
ns
NOTE:
1. Timing values are based on 52 MHz SSPx_CLK frequency.
2. SSPx_SCLK is configure using the APBC_SSPx_CLK_RST[FNCLKSEL] and MPMU_ASYSDR and
MPMU_SSPDR registers
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Doc. No. MV-S301545-00 Rev. A
Page 85
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
7.7.1
SSP Slave Mode Timing
Figure 47: SSP Slave Mode Timing Definitions
Tw(CH)
Tw(CL)
SSPx_ CLK
t0FV
SSPx_ FRM
tOFH
tODV
tODH
SSPx_ TXD
tIsu
tIh
SSPx_ RXD
1. SCLKDIR field in the SSP Control Register 1 (SSP_SSCR1) = 0x1
2. SFRMDIR field in the SSP Control Register 1 (SSP_SSCR1) = 0x1
3. The SPO and SPH fields in the SSP Control Register 1 (SSP_SSCR1) are used to determine the polarity of
SSPx_CLK
Table 29: SSP Slave Mode Timing Specifications
S y m b ol
D es c r ip t i o n
M in
Max
U n i ts
tw(CH)
SSPx_SCLK pulse width high duration
19.2
—
ns
tw(CL)
SSPx_SCLK pulse width low duration
19.2
—
ns
tODV
SSPx_TXD output valid prior to SSPx_CLK
16.1
—
ns
tODH
SSPx_TXD output hold time
26.7
—
ns
tFH
SSPx_CLK to SSPx_FRM hold time
19.3
—
ns
tFSU
SSPx_FRM to SSPx_CLK setup time
12.6
—
ns
tIsu
SSPx_RXD to SSPx_CLK setup time
13.2
—
ns
tIh
SSPx_CLK to SSPx_RXD hold time
21.54
—
ns
1. Timing values based on 26 MHz SSPx_CLK frequency
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AC Electrical Characteristics
TWSI Timing Diagrams and Specifications
7.8
TWSI Timing Diagrams and Specifications
Figure 48: TWSI Output Delay AC Timing Diagram
tHIGH
tLOW
Vih( min)
SCK
Vil( max)
Vih( min)
SDA
Vil( max)
tOV( min)
tOV( max)
TWSI Inpu
Figure 49: TWSI Output Delay AC Timing Diagram
tLOW
tHIGH
Vih( min)
SCK
Vil( max)
Vih( min)
SDA
Vil( max)
tSU
tHD
Table 30: TWSI Master AC Timing Table (Standard Mode 100 kHz)
Sy m b o l
Description
fCK
SCK clock frequency
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Min
Max
U n i ts
—
100
kHz
N ot e s
-
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Table 30: TWSI Master AC Timing Table (Standard Mode 100 kHz) (Continued)
Sy m b o l
Description
Min
Max
U n i ts
N ot e s
tLOW
SCK minimum low level width
0.47
—
tCK
1
tHIGH
SCK minimum high level width
0.40
—
tCK
1
tSU
SDA input setup time relative to SCK rising edge
250.0
—
ns
-
tHD
SDA input hold time relative to SCK falling edge
0.0
—
ns
3
tr
SDA and SCK rise time
—
1000.0
ns
1, 2
tf
SDA and SCK fall time
—
300.0
ns
1, 2
tOV
SDA output delay relative to SCK falling edge
0.0
0.4
tCK
1
Notes:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherwise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
3. For this parameter, the load is CL = 10 pF.
Table 31: TWSI Master AC Timing Table (Fast Mode 400 kHz)
Sy m b o l
D e s c r i p t io n
Min
M ax
U n i ts
fCK
SCK clock frequency
tLOW
N o te s
—
400
kHz
-
SCK minimum low level width
0.52
—
tCK
1
tHIGH
SCK minimum high level width
0.24
—
tCK
1
tSU
SDA input setup time relative to SCK rising edge
100.0
—
ns
-
tHD
SDA input hold time relative to SCK falling edge
0.0
—
ns
3
tr
SDA and SCK rise time
20.0
300
ns
1, 2
tf
SDA and SCK fall time
20.0
300
ns
1, 2
tOV
SDA output delay relative to SCK falling edge
0.0
0.4
tCK
1
Notes:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherwise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
3. For this parameter, the load is CL = 10 pF.
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AC Electrical Characteristics
TWSI Timing Diagrams and Specifications
Table 32: TWSI Master AC Timing Table(high speed 3.4 MHz)
Sy m b o l
Description
Min
Max
U n i ts
fCK
SCK clock frequency
tLOW
N ot e s
—
3.4
MHz
-
SCK minimum low level width
0.54
—
tCK
1
tHIGH
SCK minimum high level width
0.20
—
tCK
1
tSU
SDA input setup time relative to SCK rising edge
10.0
—
ns
-
tHD
SDA input hold time relative to SCK falling edge
0.0
—
ns
3
tr
SDA and SCK rise time
10.0
80.0
ns
1, 2
tf
SDA and SCK fall time
10.0
80.0
ns
1, 2
tOV
SDA output delay relative to SCK falling edge
0.0
0.4
tCK
1
Notes:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherwise specified.
General comment: tCK = 1/fCK.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
3. For this parameter, the load is CL = 10 pF.
7.8.1
TWSI Test Circuit
Figure 50: TWSI Test Circuit
VDDIO
Test Point
RL
CL
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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7.9
AC ’97 Timing Diagrams and Specifications
Figure 51 and Table 33 defines the AC ’97 CODEC interface AC timing specifications.
Figure 51: AC ’97 CODEC Timing Diagram
AC97_nACRESET
tw(B)
AC97_BITCLK
tSYNCV
AC97_SYNC
tODV
AC97_SDATA_OUT
tISU
tIH
AC97_SDATA_INx
tw(S)
ASYSCLK
1. The MPMU Audio SYSCLK Dithering Divider Register (MPMU_ASYSDR) is used to select the frequency for
ASYSCLK
Table 33: AC ’97 CODEC Timing Specifications
S y m bo l
P a r a m e te r
Min
Max
tw(B)
U ni ts
N ot e s
AC97_BITCLK pulse width constraint
36
—
ns
tSYNCV
AC97_BITCLK high to AC97_SYNC valid delay
—
13
ns
1
tODV
AC97_BITCLK high to AC97_SDATA_OUT valid delay
—
11
ns
1
tISU
AC97_SDATA_INx to AC97_BITCLK setup time
3
—
ns
1
tIH
AC97_BITCLK to AC97_SDATA_INx hold time
4
—
ns
1
tw(S)
ASYSCLK pulse width delay
—
—
ns
NOTE:
1. Transition time for input BITCLK is 2.5 ns.
7.10
JTAG Interface Timing Diagrams and Specifications
Refer to Table 34 for the timing specifications for Figure 52 and Figure 52
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AC Electrical Characteristics
JTAG Interface Timing Diagrams and Specifications
7.10.1
JTAG Interface Timing Diagrams
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Figure 52: JTAG Interface Output Delay AC Timing Diagram
Tprop
(max)
VIH
TCK
VIL
TDO
Tprop
(min)
Figure 53: JTAG Interface Input AC Timing Diagram
TCK
TMS, TDI
Tsetup
7.10.2
Thold
JTAG Interface AC Timing Table
Table 34: JTAG Interface 10 MHz AC Timing1
Sy m b o l
Description
fCK
TCK frequency
Tpw
TCK minimum pulse width
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Min
Ty p
Max
U n i ts
Notes
—
10
13.0
MHz
--
0.40
—
0.60
tCK
--
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 34: JTAG Interface 10 MHz AC Timing1 (Continued)
Sy m b o l
Description
Min
Ty p
Max
U n i ts
Sr/Sf
TCK rise/fall slew rate
0.50
—
—
V/ns
Notes
2
Trst
TRST_N active time
1.0
—
—
ms
--
Tsetup
TMS, TDI input setup relative to TCK
rising edge
10.0
—
—
ns
--
Thold
TMS, TDI input hold relative to TCK
rising edge
40.0
—
—
ns
--
Tprop
TCK falling edge to TDO output
delay
1.0
—
20.0
ns
3
1. tCK = 1/fCK.
2. Defined from VIL to VIH for rise time and from VIH to VIL for fall time
3. For TDO signal, the load is CL = 10 pF.
7.10.3
JTAG Interface Test Circuit
Figure 54: JTAG Interface Test Circuit
Test Point
CL
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AC Electrical Characteristics
USB 2.0 Timing Diagrams and Specifications
7.11
USB 2.0 Timing Diagrams and Specifications
7.11.1
USB Interface Driver Waveforms
Figure 55: Low/Full Speed Data Signal Rise and Fall Time
Rise Time
Fall Time
90%
90%
VCRS
10%
Differential
Data Lines
10%
TR
TF
Figure 56: High Speed TX Eye Diagram Pattern Template
+525 mV
+475 mV
+400 mV Differential
+300 mV
0 V Differential
-300 mV
-400 mV Differential
-475 mV
-525 mV
7.5%
0%
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
37.5%
62.5%
92.5%
100%
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Figure 57: High Speed RX Eye Diagram Pattern Template
+525 mV
+475 mV
+400 mV Differential
+175 mV
0 V Differential
-175 mV
-400 mV Differential
-475 mV
-525 mV
0%
7.11.2
12.5%
35%
65%
87.5%
100%
Differential Interface Electrical Characteristics
This section provides the reference clock, AC, and DC characteristics for the differential interface.
7.11.2.1
USB Driver and Receiver Characteristics
Table 35: USB Low Speed Driver and Receiver Characteristics1
Sy m b o l
D e s c r ip t i o n
L o w Sp e e d
Min
BR
Baud rate
Bppm
Baud rate tolerance
U ni ts
Notes
Max
1.5
—
Mbps
--
-15000.0
15000.0
ppm
--
Driver Parameters
VOH
Output single ended high
2.8
3.6
V
2
VOL
Output single ended low
0.0
0.3
V
3
VCRS
Output signal crossover voltage
1.3
2.0
V
4
TLR
Data fall time
75.0
300.0
ns
4,5
TLF
Data rise time
75.0
300.0
ns
4,5
TLRFM
Rise and fall time matching
80.0
125.0
%
--
TUDJ1
Source jitter total to next transition
-95.0
95.0
ns
5
TUDJ2
Source jitter total for paired transitions
-150.0
150.0
ns
6
Receiver Parameters
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AC Electrical Characteristics
USB 2.0 Timing Diagrams and Specifications
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Table 35: USB Low Speed Driver and Receiver Characteristics1 (Continued)
Sy m b o l
D e s c r ip t i o n
L o w Sp e e d
Min
U ni ts
Notes
Max
VIH
Input single ended high
2.0
—
V
--
VIL
Input single ended low
—
0.8
V
--
VDI
Differential input sensitivity
0.2
—
V
--
1. For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
The load is 100 ohm differential for these parameters, unless otherwise specified.
To comply with the values presented in this table, refer to your local Marvell representative for register
settings.
2. Defined with 1.425 kilohm pullup resistor to 3.6V.
3. Defined with 14.25 kilohm pulldown resistor to ground.
4. See Data Signal Rise and Fall Time waveform.
5. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
6. Including frequency tolerance. Timing difference between the differential data signals.
Defined at crossover point of differential data signals.
Table 36: USB Full Speed Driver and Receiver Characteristics1
Sy m b o l
D e s c r ip t i o n
L o w Sp e e d
Min
BR
Baud rate
Bppm
Baud rate tolerance
12.0
-2500.0
U n its
Notes
Max
2500.0
Mbps
--
ppm
--
Driver Parameters
VOH
Output single ended high
2.8
3.6
V
2
VOL
Output single ended low
0.0
0.3
V
3
VCRS
Output signal crossover voltage
1.3
2.0
V
4
TFR
Output rise time
4.0
20.0
ns
4,5
TFL
Output fall time
4.0
20.0
ns
4,5
TDJ1
Source jitter total to next transition
-3.5
3.5
ns
6, 7
TDJ2
Source jitter total for paired transitions
-4.0
4.0
ns
6,7
TFDEOP
Source jitter for differential transition to
SE0 transition
-2.0
5.0
ns
--
2.0
—
V
--
Receiver Parameters
VIH
Input single ended high
VIL
Input single ended low
—
0.8
V
--
VDI
Differential input sensitivity
0.2
—
V
--
tJR1
Receiver jitter to next transition
-18.5
18.5
ns
7
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
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Page 95
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 36: USB Full Speed Driver and Receiver Characteristics1 (Continued)
Sy m b o l
tJR2
D e s c r ip t i o n
L o w Sp e e d
Receiver jitter for paired transitions
Min
Max
-9.0
9.0
U n its
ns
Notes
7
1. For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
The load is 100 ohm differential for these parameters, unless otherwise specified.
To comply with the values presented in this table, refer to your local Marvell representative for register
settings.
2. Defined with 1.425 kilohm pullup resistor to 3.6V.
3. Defined with 14.25 kilohm pulldown resistor to ground.
4. See Data Signal Rise and Fall Time waveform.
5. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
6. Including frequency tolerance. Timing difference between the differential data signals.
Defined at crossover point of differential data signals.
7. Defined at crossover point of differential data signals.
Table 37: USB High Speed Driver and Receiver Characteristics1
Sy m b o l
D e s c r ip t i o n
L o w Spe e d
Min
BR
Baud rate
Bppm
U n its
Notes
Max
480.0
-500.0
500.0
Mbps
--
ppm
--
Driver Parameters
VHSOH
Data signaling high
360.0
440.0
mV
--
VHSOL
Data signaling low
-10.0
10.0
mV
--
THSR
Data rise time
500.0
—
ps
2
Data fall time
500.0
—
ps
THSF
See 3
Data source jitter
2
3
Receiver Parameters
See 4
Differential input signaling levels
VHSCM
Data signaling common mode voltage
range
Receiver jitter tolerance
-50.0
4
500.0
See 4
mV
-4
1. For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.
The load is 100 ohm differential for these parameters, unless otherwise specified.
To comply with the values presented in this able, refer to your local Marvell representative for register settings.
2. Defined from 10% to 90% for rise time and 90% to 10% for fall time.
3. Source jitter specified by the TX eye diagram pattern template figure
4. Receiver jitter specified by the RX eye diagram pattern template figure.
7.12
PCI Express Specifications
Refer to Table 38 and Table 39 for PCIE output and input characteristics. For more information on
PCIE timing requirements refer to the PCI Express Base Specification Revision 1.1
(http://www.pcisig.com/specifications/pciexpress/base).
7.12.1
PCIE Differential TX Output Electrical Characteristics
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AC Electrical Characteristics
PCI Express Specifications
Table 38: PCI Express TX Output Electrical Specifications
Sy m b o l
P ar a m e te r
UI
Unit Interval (UI)
399.88
400
400.12
ps
VTX_DIFFpp
Differential Peak to Peak Output Voltage
0.800
—
1.2
V
VTX_DE_RATIO
De-emphasized output voltage ratio
-3.0
-3.5
-4.0
dB
TTX_EYE
Transmitter eye including all jitter sources
0.75
—
—
UI
TTX_EYE_MEDIAN_MAX_J
Maximum time between the jitter median and
maximum deviation from the median
—
—
0.125
UI
0.125
—
—
UI
ITTER
Min
Ty p
Max
U ni ts
TTX_RISE,
TTX_FALL
D+/D- TX output rise/fall Time
VTX_CM_ACp
AC RMS common mode output voltage
—
—
20
mV
VTX_CM_DC_ACTIVE_IDL
Absolute Delta of DC Common Mode Voltage
During L0 and electrical idle
0
—
100
mV
VTX_CM_DC_LINE_DELTA
Absolute Delta of DC Common Mode Voltage
between D+ and D-
0
—
25
mV
VTX_IDLE_DIFFp
Electrical Idle Differential Peak Output Voltage
0
—
25
mV
VTX_RCV_DETECT
The amount of voltage change allowed during
Receiver Detection
—
—
600
mV
VTX_DC_CM
The TX DC Common Mode Voltage
0
—
3.6
V
ITX_SHORT
TX Short Circuit Current Limit
—
90
mA
TTX_IDLE_MIN
Minimum time spent in Electrical Idle
50
—
TTX_IDLE_SET_TO_IDLE
Maximum time to transition to a valid Electrical
Idle after sending an Electrical Idle ordered set
—
—
20
UI
TTX_IDLE_TO_DIFF_DATA
Maximum time to transition to valid TX
specifications after leaving an Electrical Idle
condition
—
—
20
UI
RLTX_DIFF
Differential Return Loss
10
—
—
dB
RLTX_CM
Common Mode Return Loss
6
—
—
dB
ZTX_DIFF_DC
DC Differential TX Impedance
80
100
120
Ohms
CTX
AC Coupling Capacitor
75
100
200
nF
Tcrosstalk
Crosstalk Random Timeout
0
—
1
ms
E_DELTA
7.12.2
UI
PCIE Differential RX Input Electrical Characteristics
Table 39: PCI Express RX Input Electrical Specifications
Sy m b o l
P ar a m e te r
UI
Unit Interval (UI)
399.88
400
400.12
ps
VRX_DIFFpp
Differential Peak to Peak Output Voltage
0..175
—
1.2
V
TRX_EYE
Receiver eye including all jitter sources
0.4
—
—
UI
TRX_EYE_MEDIAN_MAX_J
Maximum time between the jitter median and
maximum deviation from the median
—
—
0.3
UI
ITTER
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Min
Ty p
Max
U ni ts
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Table 39: PCI Express RX Input Electrical Specifications
Sy m b o l
P ar a m e te r
VRX_CM_ACp
AC RMS common mode output voltage
—
—
150
mV
RLRX_DIFF
Differential Return Loss
10
—
—
dB
RLRX_CM
Common Mode Return Loss
6
—
—
dB
ZRX_DIFF_DC
DC Differential RX Impedance
80
100
120
Ohms
ZRX_DC
RX DC input impedance
40
50
60
Ohms
ZRX_HIGH_IMP_DC
Power Down DC input impedance
200
—
—
kOhms
VRX_IDLE_DET_DIFFp
Electrical Idle detect threshold
65
—
175
mV
TRX_IDLE_DET_DIFF_ENT
—
—
10
ms
ERTIME
Unexpected electrical idle enter detect threshold
integration time
LRX_SKEW
Total skew
—
—
20
ns
7.13
Min
Ty p
Max
U ni ts
Ethernet MAC (MII) Timing Diagrams and
Specifications
MII Tx Mode timing diagram is shown in Figure 58 and timing parameters are provided in Table 40.
MII Rx Mode timing diagram is shown in Figure 59 and timing parameters are defined in Table 41. In
Tx mode, the media access controller (MAC) receives TX_CLK from the Ethernet transceiver (PHY)
and drives TX data and control signals. In Rx mode, the controller receives RX_CLK, data and
control signals from the Ethernet transceiver.
MII Management interface timing diagram is shown in Figure 60 and timing values are defined in
Table 42.
Figure 58: MII Tx Mode Interface Timing Diagrams
Tp
TX_CLK
Tco
Tco
TXD, TX_EN, TX_ER
Table 40: MII Tx Mode Interface Timing Specifications
S y m bo l
Parameter
Min
Max
Unit
Tp
TX_CLK frequency
—
25
MHz
Tco
TX_CLK in to TX data and control out
0
14
ns
N o te s
1
NOTE:
1. Timing values are based on 30pf reference load.
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AC Electrical Characteristics
Ethernet MAC (MII) Timing Diagrams and Specifications
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Figure 59: MII Rx Model Interface Timing Diagrams
Tp
RX_CLK
Thd
Tsu
RXD, RX_DV, RX_ER
Table 41: MII Rx Mode Interface Timing Specifications
S y m bo l
Parameter
Min
Max
Unit
Tp
RX_CLK Frequency
—
25
MHz
Tsu
Input setup time
6
—
ns
Thd
Input hold time
4
—
ns
N o te s
Figure 60: MII Management Interface Timing Diagrams
Tp
MDC
Tva
Tvb
MDIO_Output
Thd
Tsu
MDIO_Input
Table 42: MII Management Interface Timing Specifications
S y m bo l
Parameter
Min
Max
Tp
MDC Frequency
—
2.5
MHz
Tva
MDIO output valid time before MDC rising
20
—
ns
Tvb
MDIO output valid time after MDC rising
20
—
ns
Tsu
MDIO input setup time
50
—
ns
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Unit
N o te s
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Page 99
Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 42: MII Management Interface Timing Specifications (Continued)
S y m bo l
Parameter
Thd
MDIO input hold time
7.14
Min
Max
0
—
Unit
N o te s
ns
Powerup/Down Sequences
This section includes specifications for the following:


Section 7.14.1, Power Up Timings
Section 7.14.2, Powerdown Timings
Table 43: Terminology
7.14.1
Te r m
Description
VDD_M
ASIC DRAM IO power (1.8V nominal +/- 10%)
VDD_CORE
Core power (assume 1.0V nominal)
AVDD_USB
ASIC USB power including AVDD_OTG and AVDD_UHC (3.3V
nominal)
AVDD5_USB
ASIC USB 5V power (5 V nominal)
VDD_OSC
Quiet 1.8V analog power for ASIC PLL/Crystal.
VDD_IOx
3.3/1.8V IO power Includes VDD_IO0, VDD_IO1, VDD_IO2,
VDD_IO3, VDD_IO4
RESET_IN_N
External Master Reset In pin
Power Up Timings
The external voltage regulators and other power-on devices must provide the processor with a
specific sequence of power and resets to ensure proper operation (see Figure 61 and Table 44).
7.14.1.1
Host Side PMIC USB Signals

AVDD5_USB - Supply
•
Host Mode Only: Connect to 5V to supply a maximum of 10mA on USBVBUS. For higher
current requirements, an external PMIC must be used to drive VBUS.
• Device Mode Only: Not used; can remain floating.
• OTG Mode: Connect to 5V to provide a maximum of 10mA on USBVBUS during session
negation. For higher current requirements as external PMIC must be used to drive VBUS.
Note
Doc. No. MV-S301545-00 Rev. A
Page 100
When the USBVBUS is driven from AVDD5_USB, the USBHPEN signal is pulled high
(3.3V).
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AC Electrical Characteristics
Powerup/Down Sequences
When USBHPEN = 3.3V, do not supply both AVDD5_USB and USBVBUS with 5V.
Caution

USBVBUS - Input/Output
• Host Mode: USB power output ([email protected]) when USBHPEN = 3.3V
• Device Mode: 5V VBUS input from host
• OTG Mode: Input/Output to supply +5V during session negotiation

USBHPEN - Output
•
Note
Copyright © 2013 Marvell
May 2013 PUBLIC RELEASE
Controls external power management chip to provide 5v power to VBUS
a) OV: Does not drive VBUS
b) 3.3V: Drives 5V power source on to VBUS
If the application does not need more than 10mA, float USBHPEN and connect
AVDD5_USB to 5V power. VBUS is not dirven inside the PHY.
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Figure 61: Power-Up Reset Timing
V D D _IO
80 %
t1
80 %
AVDD_O SC
80 %
A V D D _ P C IE
t4
t3
V D D _C O R E
80 %
t2
t5
80 %
V D D _M
t6
80 %
AVDD_UHC
t6
A V D D _O T G
80 %
A V D D 5 _U S B
USBVBUS
tP O R
R E S E T _ IN _N
nCS0
Table 44: Power-Up Timing Specifications
S y m b ol
D e s c r i p t io n
M in
Typical
Max
t1
t2
Delay from the start of the high voltage IO
supplies ramp prior to AVDD_OSC ramp start.
0
—
Delay from VDD_IO prior to VDD_CORE ramp
start
0
—
Doc. No. MV-S301545-00 Rev. A
Page 102
U n i ts
N ot e s
—
µs
1
—
µs
2
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AC Electrical Characteristics
Powerup/Down Sequences
Table 44: Power-Up Timing Specifications (Continued)
S y m b ol
D e s c r i p t io n
M in
Typical
Max
t3
U n i ts
N ot e s
Delay from AVDD_OSC reaching 80% of its
final value prior to VDD_CORE ramp start
0
—
—
µs
3
t4
Delay from AVDD_PCIE reaching 80% of its
final value prior to VDD_CORE ramp start.
0
—
—
µs
4,5
t5
Delay from VDD_CORE reaching 80% of its
final value prior to VDD_M reaching 80% of its
final value
-500
300
—
µs
6, 7
t6
Delay from VDD_CORE reaching 80% of its
final value prior to AVDD_UHC and
AVDD_OTG ramp start
0
—
—
µs
8, 9
tPOR
Time required before de-asserting
RESET_IN_N after AVDD_UHC and
USB_OTG reach 80%.
153
—
—
µs
1.
2.
3.
4.
5.
6.
7.
VDD_IO and AVDD_OSC can be enabled at the same time.
VDD_IO must power to 80% prior to enabling VDD_CORE
AVDD_OSC must power to 80% prior to enabling VDD_CORE.
AVDD_PCIE must power to 80% prior to enabling VDD_CORE.
AVDD_PCIE includes AVDD_PCIE and AVDDT_PCIE.
VDD_M must not exceed VDD_CORE by more than 1.2V
Ideally VDD_CORE and VDD_M will ramp to 80% of their final value at the same time. Due to voltage level differences
between VDD_M and VDD_CORE, VDD_M may reach 80% of its final value after VDD_CORE depending on the ramp
rates for each supplies. To reduce the power up time keep the delay after VDD_CORE at a minimum.
8. Enable AVDD_UHC and AVDD_OTG after VDD_CORE reaches a minimum of 80% of its final value.
9. Do not power AVDD_UHC and AVDD_OTG prior to VDD_CORE
10. The AVDD5_USB supply can left on while the other supplies are powered off. Powering up AVDD5_USB is only
required for USB OTG functionality when using host mode.
11. USBVBUS is not a power supply but is included in this diagram for completeness. USBVBUS can be supplied with 5V
while the other supplies are turned off.
7.14.2
Powerdown Timings
When powering down the ARMADA 16x Applications Processor, all voltage rails can be removed
simultaneously. Ideally, the power to VDD_M is removed prior to VDD_CORE. When the power to
VDD_CORE is removed prior to removing VDD_M, refer to Table 45 for timing constraints between
the voltage rails.
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May 2013 PUBLIC RELEASE
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Figure 62: Powerdown Timing
AVDD5_ USB
USBVBUS
AVDD_ UHC
AVDD_ OTG
VDD_M
VDD_ CORE
t1
AVDD_ PCIE
AVDD_ OSC
VDD_IOx
Table 45: PowerdownTiming Specifications
S y m bo l
D e s cr ip t i o n
t1
VDD_CORE to VDD_M
M in
Typ i c a l
Max
—
—
10
U ni ts
Notes
ms
2,3,4
1.
2.
3.
4.
AVDD5_USB can remain active while the other supplies are removed
VDD_M must not exceed VDD_CORE by more than 1.8V
The start of ramp down time when VDD_CORE is removed prior to VDD_M
When powering down VDD_CORE prior to VDD_M, VDD_M must not exceed VDD_CORE by 1.26V for a maximum of
200ms.
5. VDD_IO can remain active while the other supplies are removed. Recommended for Hibernate mode.
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Design Guidelines and Checklist
DDR Interface General Routing Guidelines
8
Design Guidelines and Checklist
This chapter discusses:



8.1
Section 8.1, “DDR Interface General Routing Guidelines”
Section 8.2, “EPD Controller Design Guidelines”
Section 8.3, “Schematic Checklist”
DDR Interface General Routing Guidelines
The basic routing rules for DDR devices on a PCB are shown in subsequent subsections in this
chapter. For specific guidelines, refer to the appropriate sections below.
8.1.1
General Rules:


8.1.1.1
Ground Reference Routing for all signals
DQ byte groups routed on the same layer
Data and QS Signals
•
•
•
•
•
•
•
•
•
•
•
•
Signals within the same Data byte of must be routed to within +/-50 mils (1.27mm) of their
respective QS signals. QS line length should be centered within their respective data groups
and matched to within 0.05" (1.27mm). A Data byte consists of: 8 data lines (DQ), 1 data mask
(DQM), 1 QS and 1 QS#.
Data signals should be less than or equal to 3.0" (76.2mm) long.
Whenever possible, the QS lines are to be ground guarded as GND-QS-QS#-GND.
Data/DQM traces to have impedance of 50 ohms. DQS-DQS# to have differential 100-ohm
traces.
Signals within the same Data byte must be routed to within +/-50mils (1.27mm) of their respective QS signals. QS line length should be centered within their respective data groups and
matched to within 0.05" (1.27mm). A Data byte consists of: 8 data lines (DQ), 1 data mask
(DQM), 1 QS and 1 QS#.
Data and QS signals must be routed as stripline traces, if possible.
Data signals should be less than or equal to 3.0" long. Longer lengths should be simulated for
timing margins.
Whenever possible, the QS lines are to be ground guarded as GND-QS-QS#-GND. If ground
guarding is not possible, the spacing of QS, QS# to other signals should be at-least twice the
minimum trace width.
Differential signals, QS and QS#, must be routed to a length within 0.025" (0.635mm) of each
other.
Data/DQM traces to have single-ended impedance of 50 ohms.
Differential signals, QS, QS#, must be routed with a differential impedance of about 100 ohms.
QS, QS# traces to be terminated with a resistor placement on the controller side close to the
pins. Use 1k ohm resistor from QS pin to gnd and 1k ohm resistor from QS# pin to VDDQ as
close to the pins (controller side) as possible.
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8.1.1.2
Address/Command Signals
•
•
•
•
•
8.1.1.3
Clock Signals
•
•
•
•
•
•
•
•
•
•
•
•
•
8.1.2
Address/Control lines to the same DRAM must be routed to within 0.5 inch of the clock signals
and routed on the same layer.
Address/Control lines must have trace impedance of 50 ohms.
Address/Control lines must have a shunt termination of 50 ohms to VTT.
Max length of stub (connecting from SDRAM pins to termination) should be less than 0.2" as
close to the pins of DRAM as possible.
CKE must have pulldown of 4.7k to gnd. A CKE termination to VTT is not required.
Whenever possible, clock routing should be the Ground Guarded configuration for as long as
possible.
Terminate differential clock signals, CLK and CLK#, at the end of the lines between them with a
100-ohm termination resistor.
Route differential clock signals, CLK and CLK# to a length within 0.025" (0.635mm) of each
other, and routed with at least a 2:1 spacing to each other.
The differential impedance of CLK,CLK# traces is 100 ohms.
Route clock signals (T0 length) to within 0.5 inch of the Address/Command signals.
Route clock signals (T0 length) to be within 1.0" (+/-12.7mm) of their respective QS signals to
the same DRAM, with CKs in the middle.
Make the max length of stub (connecting from DRAM pins to termination) less than 0.1" as
close to the pins of DRAM as possible.
Whenever possible, clock routing should be the Ground Guarded configuration for as long as
possible. If ground guarding is not possible, the spacing of CLK, CLK# to other signals should
be at least three times the minimum trace width.
Differential clock signals, CLK and CLK#, must be routed to a length within 0.025" (0.635mm) of
each other.
Route clock signals to within 0.5 inch of the Address/Command signals.
CLK, CLK# traces to have single-ended impedance of 50 ohms. Differential clock signals, CLK
and CLK#, must be routed with at least a 2:1 spacing to each other. Make the spacing from
CLK/CLK# to other signals three times the trace width.
Terminate differential clock signals, CLK and CLK#, at the end of the lines between them with a
100-ohm termination resistor with a common mode (termination midpoint) capacitor of 1nF.
Make the max length of stub (connecting from SDRAM pins to termination) less than 0.1" as
close to the pins of DRAM as possible.
DDR Interface Detailed Routing Guidelines
For detailed routing guidelines, refer to the ARMADA 16x Applications Processor Family DDR
Routing Guidelines Application note.
8.2
EPD Controller Design Guidelines
This chapter describes:






Section 8.2.1, “Introduction”
Section 8.2.2, “Panel Power Up Sequence”
Section 8.2.3, “Display Common Power Signal”
Section 8.2.4, “Source Driver Interface”
Section 8.2.5, “Gate Driver Interface”
Section 8.2.6, “Start Pulse Control”
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Design Guidelines and Checklist
EPD Controller Design Guidelines
8.2.1
Introduction
The EPD Controller (EPDC) is an IP block optimized for products using ElectroPhoretic Displays
(EPDs). It enables an SoC solution with a direct connection to the EPD module. The EPD controller
differentiates itself through





High-level integration
Presentation of complex content on EPDs
Ease of software implementation
Content security
Significant power savings
Due to its intrinsic bi-stable nature, power is not required when there is no change to the display
image. EPDs are reflective displays so backlighting is not necessary.
If an EPD Display Controller is in a typical EPD display system, it can drive an EPD panel through
the source driver and gate driver chips.
Major EPDC features include:
Frame resolution:

• From SVGA (600x800) up to UXGA (1200x1600)
• ~150 dpi A size sheet










8.2.2
Partial and Parallel Update
Capable of displaying videos and animations
Conventional software programming model
Flexible interface to various EPD panels
Elimination of the separate EPD SDRAM
Power management
Faster update - Each pixel can detect its own waveform length and stops at the end. Shorter
waveforms end sooner.
Support content security though NDS secure IC
Appear as conventional Frame buffer
Host interrupt capability
Panel Power Up Sequence
EPD panel power-up must follow a fixed sequence as described below and in Figure 63:
Power on sequence: VCC => GVEE => VNEG => VPOS => Input Signals: OE, GVDD
Power off sequence: Input Signals,OE => GVDD, VPOS, VNEG,VCOM => GVEE => VCC
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Figure 63: Panel Power Sequence
The panel power supplies are controlled by the EPDC PWR[4:0] pins. PWR[4:0] timings are
controlled by the POWER_[3:0] registers.
8.2.3
Display Common Power Signal
The PWRCOM signal controls the common driver output Vcom to the display panel. The signal is
asserted during image updates; it is asserted when entering normal operation mode, and negated
when exiting normal operation mode.
8.2.3.1
Vcom Setting by DPOT (Digital Potentiometer)
Vcom is the common voltage of the EPD panel, typically between -0.5V and -3.5V. Each EPD panel
has a different Vcom voltage, therefore the EPDC must program a DPOT to drive the Vcom voltage.
A 10-bit value is used to program the DPOT in the following sequence (see Figure 64):
1. Assert the VCOM_VOLT[DPOT_CE_n] bit. Transmit an 8-bit “write wiper register” command to
the DPOT.
2. Transmit a 10-bit voltage value to DPOT, followed by six “don’t care” bits and then de-assert the
VCOM_VOLT[DPOT_CE_n] bit.
3. Assert the VCOM_VOLT[DPOT_CE_n] bit. Transmit an 8-bit “copy wiper to NVRAM” command
to the DPOT and then de-assert the VCOM_VOLT[DPOT_CE_n] bit.
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Design Guidelines and Checklist
EPD Controller Design Guidelines
Figure 64: DPOT Programming Sequence
With the EPDC, the VCOM_VOLT register is used for DPOT programming and is defined in
Appendix A - Register Tables.
The SCLK frequency should be PCLK divided by 64 in hardware DPOT mode.
8.2.4
Source Driver Interface
The EPDC Output Controller signals, SDDO[7:0], are connected to the source drivers. Currently
each source driver can drive up to 400 columns. Therefore, as many as four source drivers are used
for 1600 columns (see Figure 65). The source driver timing is shown in Figure 66.
The signals to the source driver are all outputs, as listed in Table 46.
Table 46:
Source Driver Signals
S ig n a l
D e s cr ip t i o n
SDCLK
Clock
SDLE[3:0]
Latch Enables
SDDO[7:0]
8-Bit Data Output
SDCE_L
Chip Enable
SEOE
Output Enable
SDSHR
Shift-right (for 6” panel)
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Figure 65: Source Driver Connections
The EPDC uses the SDSHR pin to control the source driver data shifting direction.
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EPD Controller Design Guidelines
Figure 66: Source Driver Timing
8.2.5
Gate Driver Interface
The gate driver turns on each panel row after the source drivers are filled with up to 1600 pixels split
across up to four driver ICs.
The gate driver signals are all output, as listed in Table 47.
Table 47:
Output Gate Driver Signals
S ig n a l
D e s c r ip t i o n
GDCLK
Clock
GDSP
Start Pulse
GDRL
Shift right/left (6” panel)
The GDRL pin controls gate driver shift up or down functionality.
The gate driver connections are shown in Figure 67.
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Figure 67: Gate Driver Connections
8.2.6
Start Pulse Control
The signal, GDSP, is the gate driver start-pulse signal. It determines the beginning of a frame
scanning. The timing is shown in Figure 68.
Figure 68: Gate Driver Output Enable Timing
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Design Guidelines and Checklist
Schematic Checklist
8.3
Schematic Checklist
Table 48 briefly describes requirements to add in schematics reviews. Refer to the various sections
within this chapter for more information about these requirements.
Table 48: ARMADA 16x Applications Processor Family Schematic Checklist

S i g na l N a m e
Recommended Connection
R e c o m m e n d ed Va lu e
N ot e s
Clocks, Power and Reset Signals
RESET_IN_IN
Weak pull-up
4.7 - 10 k to VDD_IO3
PXTAL_IN
Filtering capacitor
10 pF
3
PXTAL_OUT
Filtering capacitor
10 pF
3
A_ISET
Pulldown
6.04 k
PXTAL_IN,
PXTAL_OUT
External clock source
Connect 26 MHz clock to PXTAL_IN
and leave PXTAL_OUT floating.
JTAG Interface
PRI_TCK
Pulldown
10 - 100 k
PRI_TDI
Pullup
10 - 100 k to VDD_IO3
1
PRI_TMS
Pullup
10 - 100 k to VDD_IO3
1
PRI_TRST_N
Pullup
10 - 100 k to VDD_IO3
JTAG_SEL
Pulldown
Pulldown to VSS
DDR SDRAM
CALPAD
Pulldown (for LPDDR1 or DDR2)
300 
CALPAD
Pulldown (for DDR3)
240 
SEC_CS_SEL
2nd Chip Select and DDR3 Enable
When using the second DDR chip
select (nSDCS1) or DDR3, connect to
VDD_IO3
nDDR_RESET
Connect to DDR3 device reset signal
3, 4
nSDCS1
Connect to second DDR device Chip
Select
3, 4
ODT1
ODT for nSDCS1
3, 4
SDCKE1
Clock Enable of nSDCS1
3, 4
VREF
VDDQ/2 +/-1%
Use separate VREF supplies for SOC
and SDRAM
5
SDCKE
Pulldown to GND
4.7 k
6
DQS<1:0>
Pulldown to GND
1 k
7
nDQS<1:0>
Pullup to VDD_M
1 k
7, 5
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6, 7
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Marvell® ARMADA 16x Applications Processor Family Hardware Manual
Table 48: ARMADA 16x Applications Processor Family Schematic Checklist (Continued)

S i g na l N a m e
Recommended Connection
Series
Termination
Resistors
Not Required
Shunt
Termination to
VTT
Required for address and control
signals
R e c o m m e n d ed Va lu e
N ot e s
NAND Flash Controller
ND_RnB<1:0>
2.7k - 4.7k
Pullup to VDD_IO0
Static Memory Controller
SMC_RDY
2.7k - 4.7k
Pullup to VDD_IO0
Compact Flash Controller
CF_nRESET
Connect to the hardware reset of the
Compact Flash Card
8
XD Controller
XD_RnB
2.7k - 4.7k
Pullup to VDD_IO0
SD/MMC Controller
MMCx_CMD
Pullup to MFP VDD_IOx supply
4.7k - 10k
9
MMCx_DAT0
Pullup to MFP VDD_IOx supply
4.7k - 10k
10
MMCx_DAT3
Pullup to MFP VDD_IOx supply
4.7k - 10k
11
XD Controller
I2C_SDA,
PWR_SDA
Pullup to MFP VDD_IOx supply
1.2k - 4.7k
I2C_SDA,
PWR_SDA
Pullup to MFP VDD_IOx supply
1.2k - 4.7k
One-Wire Controller
One_wire
Pullup to MFP VDD_IOx supply
4.7k
USB OTG Controller
AVDD5_USB
Connect to [email protected] when using
host mode
Current limiting resistor needed to limit
current to 10 mA.
USBVBUS
Connect to Host Controller VBUS
Current limiting resistor needed to limit
current to 10 mA.
Ethernet Controller
MDIO
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Pullup to MFP VDD_IOx supply
1.5k
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Design Guidelines and Checklist
Schematic Checklist
Table 48: ARMADA 16x Applications Processor Family Schematic Checklist (Continued)

S i g na l N a m e
Recommended Connection
RJ-45 Capacitor
Ensure at least 2kV voltage rating
R e c o m m e n d ed Va lu e
N ot e s
PCI Express Controller
Routing
Dedicated clock pair for processor and
connector / peripheral (no tee/daisy
chain routing)
Differential pairs
PCIe 2.5GHz- 75..200nF AC blocking
caps on all diff pairs
Multi-Function Pins
Unused
Multi-Function
Pins
Leave floating
Pullup/down
resistors
Ensure external pull resistors match
the internal pull resistor states
12, 13
NOTE:
1. Required for test logic reset sequence
2. Capacitor values depend on crystal requirements. Contact crystal manufacturer for correct capacitor
values required for crystal accuracy and functionality.
3. SEC_CS_EN must be connected to the same voltage level as VDD_IO3 prior to using
4. Do not connect to VSS when SEC_CS_EN is connected to VDD_IO3
5. Must be connected to the same power supply as ARMADA 16x Application Processor
6. Needed to allow DDR device to go into low power modes.
7. Place as close as possible to the DQS<1:0> pins.
8. Without this connection software cannot reset the CF card through the card register accesses.
9. Response corruption occurs if the CMD signal does not rise fast enough when operating in open-drain
mode during card initialation.
10. The DAT0 can float near GND, which can incorrectly signaling a device BUSY status to the host controller.
11. The DAT3 can float near GND during CMD0 transmission, which can incorrectly place some devices into
SPI mode.
12. Check the Pull state in the alternate function spreadsheet to verify internal Pull states.
13. Pull resistors are valid only when the MFP is configured as an output
Note
Copyright © 2013 Marvell
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Marvell’s schematic review checklist does not replace a customer’s in-house design
review or substitute for training in design or Marvell architecture basics. Although
Marvell makes a good faith effort to find potential design problems, customers remain
responsible for the success of their design. Marvell makes no claims or guarantees that
the Marvell checklist will uncover all defects, or that the design will work. Neither does
Marvell accept responsibility for any impact to the customer’s project schedules.
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Schematic Checklist
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