a Serial-Port 16-Bit SoundPort Stereo Codec AD1849K speaker and stereo headphone drive circuits that require no additional external components. Dynamic range exceeds 80 dB over the 20 kHz audio band. Sample rates from 5.5 kHz to 48 kHz are supported from external crystals, from an external clock, or from the serial interface bit clock. FEATURES Single-Chip Integrated SD Digital Audio Stereo Codec Multiple Channels of Stereo Input and Output Digital Signal Mixing On-Chip Speaker and Headphone Drive Capability Programmable Gain and Attenuation On-Chip Signal Filters Digital Interpolation and Decimation Analog Output Low-Pass Sample Rates from 5.5 kHz to 48 kHz 44-Lead PLCC and TQFP Packages Operation from +5 V and Mixed +5 V/+3.3 V Supplies Serial Interface Compatible with ADSP-21xx FixedPoint DSmPs Compatible with CS4215 (See Text) The Codec includes a stereo pair of Σ∆ analog-to-digital converters and a stereo pair of Σ∆ digital-to-analog converters. Analog signals can be input at line levels or microphone levels. A software controlled programmable gain stage allows independent gain for each channel going into the ADC. The ADCs’ output can be digitally mixed with the DACs’ input. The left and right channel 16-bit outputs from the ADCs are available over a single bidirectional serial interface that also supports 16-bit digital input to the DACs and control information. The AD1849K can accept and generate 8-bit µ-law or A-law companded digital data. PRODUCT OVERVIEW The Serial-Port AD1849K SoundPort® Stereo Codec integrates the key audio data conversion and control functions into a single integrated circuit. The AD1849K is intended to provide a complete, single-chip audio solution for multimedia applications requiring operation from a single +5 V supply. External signal path circuit requirements are limited to three low tolerance capacitors for line level applications; anti-imaging filters are incorporated on-chip. The AD1849K includes on-chip monaural The Σ∆ DACs are preceded by a digital interpolation filter. An attenuator provides independent user volume control over each DAC channel. Nyquist images and shaped quantization noise are removed from the DACs’ analog stereo output by on-chip switched-capacitor and continuous-time filters. Two independent stereo pairs of line-level (or one line-level and one headphone) outputs are generated, as well as drive for a monaural (mono) speaker. SoundPort is a registered trademark of Analog Devices, Inc. (Continued on page 8) FUNCTIONAL BLOCK DIAGRAM DIGITAL SUPPLY ANALOG SUPPLY CRYSTALS 2 POWER DOWN 2 DIGITAL I/O LINE L LINE R ANALOG OUT OSCILLATORS L MIC L MIC R 20 dB GAIN ∑∆ A/D CONVERTER µ/A LAW GAIN ∑∆ A/D CONVERTER µ/A LAW MUX R LOOPBACK MONITOR MIX L LINE 0 L MUTE R LINE 0 R ANALOG IN DATA/CONTROL MODE DATA/CONTROL TRANSMIT L ANALOG FILTER ATTENUATE ∑∆ D/A CONVERTER INTERPOL ATTENUATE ANALOG FILTER ATTENUATE ∑∆ D/A CONVERTER INTERPOL ATTENUATE ∑ ∑ µ/A LAW µ/A LAW S E R I A L P O R T L O O P B A C K 2 LINE 1 L HEADPHONE RETURN LINE 1 R MUTE R ∑ MUTE REFERENCE OUT DATA/CONTROL RECEIVE PARALLEL I/O BIT CLOCK FRAME SYNC AD1849K RESET RETURN MONO SPEAKER 2.25V CHAINING OUTPUT CHAINING INPUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1849K–SPECIFICATIONS ELECTRICAL SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Clock (SCLK) Master Mode Word Rate (FS) Input Signal Analog Output Passband VIH VIL External Load Impedance (Line 0) External Load Impedance (Line 1) External Load Capacitance (Line 0, 1) 25 5.0 5.0 256 256 Bits per Frame 48 1 20 Hz to 20 kHz 2.4 0.8 10 °C V V FS 48 Ω 100 pF DAC Input Conditions 0 dB Attenuation Full-Scale Digital Inputs 16-Bit Linear Mode OLB = 1 ADC Input Conditions 0 dB PGA Gain –3.0 dB Relative to Full Scale Line Input 16-Bit Linear Mode kHz kHz V V kΩ All tests are performed on all ADC and DAC channels. ANALOG INPUT Input Voltage* (RMS Values Assume Sine Wave Input) Line and Mic with 0 dB Gain Mic with +20 dB Gain Min Typ Max Units 0 94 2.66 0.094 0.266 0.99 2.80 0.099 0.280 1.04 2.94 0.104 0.294 15 V rms V p-p V rms V p-p pF Min Typ Max Units 1.3 1.5 1.7 dB 22.7 42.7 dB dB Min Max Units 0 0.45 × FS ± 0.1 0.55 × FS Hz dB Hz Hz dB Input Capacitance *Accounts for Sum of Worst Case Reference Errors and Worst Case Gain Errors. PROGRAMMABLE GAIN AMPLIFIER—ADC Step Size (0 dB to 22.5 dB) (All Steps Tested, –30 dB Input) PGA Gain Range* Line and Mic with 0 dB Gain Mic with +20 dB Gain –0.2 19.8 DIGITAL DECIMATION AND INTERPOLATION FILTERS* Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband 0.45 × FS ≥0.55 × FS 74 30/FS 0.0 –2– µs REV. 0 AD1849K ANALOG-TO-DIGITAL CONVERTERS Min Resolution* ADC Dynamic Range, A-Weighted Line and Mic with 0 dB Gain (–60 dB Input, THD+N Referenced to Full Scale) Mic with +20 dB Gain (–60 dB Input, THD+N Referenced to Full Scale) Typ Max Units 16 Bits 78 83 dB 72 74 dB ADC THD+N, (Referenced to Full Scale) Line and Mic with 0 dB Gain 0.013 –78 0.032 –70 0.020 –74 0.056 –65 % dB % dB –80 dB –60 dB Gain Error (Full-Scale Span Relative to Nominal) 0.75 dB ADC Interchannel Gain Mismatch (Line and Mic) (Difference of Gain Errors) 0.3 dB Max Units Mic with +20 dB Gain ADC Crosstalk Line to Line (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to Mic (Input LINL & R, Ground and Select MINL & R, Read Both Channels) DIGITAL-TO-ANALOG CONVERTERS Min Resolution* DAC Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale) 80 DAC THD+N (Referenced to Full Scale) Line 0 and 1 (10 kΩ Load) Typ 16 Bits 86 dB 0.010 –80 0.022 –73 0.045 –67 0.020 –74 0.100 –60 0.100 –60 % dB % dB % dB DAC Crosstalk (Input L, Zero R, Measure LOUT0R & 1R; Input R, Zero L, Measure LOUT0L & 1L) –80 dB Gain Error (Full-Scale Span Relative to Nominal) 0.75 dB DAC Interchannel Gain Mismatch (Line 0 and 1) (Difference of Gain Errors) 0.3 dB Total Out-of-Band Energy* (Measured from 0.55 × FS to 100 kHz) –60 dB Audible Out-of-Band Energy* (Measured from 0.55 FS to 22 kHz, All Selectable Sampling Frequencies) –72 dB Line 1 (48 Ω Load) Mono Speaker (48 Ω Load) *Guaranteed, not tested. REV. 0 –3– AD1849K MONITOR MIX ATTENUATOR Step Size (0.0 dB to –60 dB)* Step Size (–61.5 dB to –94.5 dB)* Output Attenuation* Min Typ Max Units 1.3 1.0 –95 1.5 1.5 1.7 2.0 0.2 dB dB dB Min Typ Max Units 1.3 1.5 1.7 dB 1.0 –95 1.5 2.0 0.2 dB dB Min Typ Max Units +0.2 dB ± 0.9 5 LSB Degrees Max Units DAC ATTENUATOR Step Size (0.0 dB to –60 dB) (Tested at Steps –1.5 dB, –19.5 dB, –39 dB and –60 dB) Step Size (–61.5 dB to –94.5 dB)* Output Attenuation* SYSTEM SPECIFICATIONS System Frequency Response* (Line In to Line Out, 0 to 0.45 × FS) Differential Nonlinearity* Phase Linearity Deviation* –0.5 ANALOG OUTPUT Min Full-Scale Output Voltage (Line 0 & 1) [OLB = 1] Full-Scale Output Voltage (Line 0) [OLB = 0] Full-Scale Output Voltage (Line 1) [OLB = 0] Full-Scale Output Voltage (Mono Speaker) [OLB = 1] Full-Scale Output Voltage (Mono Speaker) [OLB = 0] CMOUT Voltage (No Load) CMOUT Current Drive* CMOUT Output Impedance Mute Attenuation of 0 dB Fundamental* (LINE 0, 1, & MONO) Typ 0.707 2.0 1.0 2.8 4.0 1.85 1.80 2.1 V rms V p-p V rms V p-p V p-p 4.0 V p-p 8.0 V p-p 2.25 100 4 2.50 –80 V µA kΩ dB Min Max Units 2.4 2.4 –0.3 2.4 (VDD+) + 0.3 (VDD+) + 0.3 0.8 STATIC DIGITAL SPECIFICATIONS High Level Input Voltage (VIH) Digital Inputs XTAL1/2I Low Level Input Voltage (VIL) High Level Output Voltage (VOH) at IOH = –2 mA Low Level Output Voltage (VOL) at IOL = 2 mA Input Leakage Current (GO/NOGO Tested) Output Leakage Current (GO/NOGO Tested) –4– –10 0.4 10 V V V V V µA –10 10 µA REV. 0 AD1849K DIGITAL TIMING PARAMETERS (Guaranteed over +4.75 V to +5.25 V, 08C to +708C) Min SCLK Period (tCLK) Slave Mode, MS = 0 Master Mode, MS = 1* SCLK HI (tHI)* Slave Mode, MS = 0 SCLK LO (tLO)* Slave Mode, MS = 0 CLKIN Frequency CLKIN HI CLKIN LO Crystals Frequency Input Setup Time (tS) Input Hold Time (tIH) Output Delay (tD) Output Hold Time (tOH) Output Hi-Z to Valid (tZV) Output Valid to Hi-Z (tVZ) Power Up RESET LO Time Operating RESET LO Time Typ 80 Max Units ns s 1/(FS × Bits per Frame) 25 ns 25 13.5 30 30 ns MHz ns ns 27 15 10 25 0 15 20 50 100 ns ns ns ns ns ns ms ns POWER SUPPLY Min Power Supply Voltage Range* –Digital and Analog Power Supply Current—Operating (50% IVDD, 50% IVCC, Unloaded Outputs) Power Supply Current—Power Down Power Supply Rejection (@ 1 kHz)* (At Both Analog and Digital Supply Pins, Both ADCs and DACs) Typ Max Units 5.25 V 100 130 mA 20 200 µA dB Min Max Units 5.5125 27 ± 10 50 MHz % kHz 4.75 40 CLOCK SPECIFICATIONS* Input Clock Frequency, Crystals Clock Duty Cycle Tolerance Sample Rate (FS) *Guaranteed, not tested. Specifications subject to change without notice. REV. 0 –5– AD1849K ABSOLUTE MAXIMUM RATINGS* Min –0.3 –0.3 Units 6.0 6.0 V V ± 10.0 mA 0.048 (1.21) 0.042 (1.07) 6 0.025 (0.63) 0.015 (0.38) 0.020 (0.50) R 40 PIN 1 IDENTIFIER 7 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 39 PIN 1 IDENTIFIER 0.021 (0.53) 0.013 (0.33) 0.63 (16.00) 0.59 (14.99) V V °C °C V 0.032 (0.81) 0.026 (0.66) TOP VIEW BOTTOM VIEW 0.050 (1.27) BSC 17 29 28 18 of MIL-STD-883B) 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) WARNING: CMOS device. May be susceptible to high voltage transient-induced latchup. 0.110 (2.79) 0.085 (2.16) 0.695 (17.65) SQ 0.685 (17.40) *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 39 38 TSOUT 37 36 35 34 TSIN 41 40 SDRX 42 SDTX 43 GNDD VDD 44 CLKOUT CIN1 44-Lead TQFP SCLK (VCC+) + 0.3 (VDD+) + 0.3 +70 +150 FSYNC –0.3 –0.3 0 –65 500 CLKIN Power Supplies Digital (VDD) Analog (VCC) Input Current (Except Supply Pins and MOUT, MOUTR, LOUT1R, LOUT1L, LOUT1C) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature ESD Tolerance (Human Body Model per Method 3015.2 44-Lead Plastic Leaded Chip Carrier Pinout Max ORDERING GUIDE 2 32 VDD GNDD 3 31 PIO1 30 PIO0 CIN2 4 COUT2 5 AD1849KST 29 D/C RESET 6 28 N/C PDN 7 SoundPort® STEREO CODEC 27 LOUT0R C0 8 26 LOUT0L MINR 25 LOUT1L 24 LOUT1C MINL 11 23 LOUT1R 20 21 MOUT 18 19 22 MOUTR 16 17 N/C 15 GNDA 13 14 VCC 12 VCC 9 LINR 10 VREF P-44A 33 VDD GNDA 44-Lead PLCC GNDD COUT1 1 C1 Package Option LINL AD1849KP 0°C to +70°C Package Description CMOUT Model Temperature Range N/C = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1849K features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– WARNING! ESD SENSITIVE DEVICE REV. 0 AD1849K PIN DESCRIPTION Digital Signals Pin Name PLCC TQFP I/O Description SDRX SDTX SCLK FSYNC TSOUT TSIN D/C CIN1 COUT1 CIN2 COUT2 CLKIN CLKOUT PDN RESET PIO1 PIO0 1 44 43 42 41 40 35 6 7 10 11 4 5 13 12 37 36 39 38 37 36 35 34 29 44 1 4 5 42 43 7 6 31 30 I O I/O O O I I I O I O I O I I I/O I/O Receive Serial Data Pin Transmit Serial Data Pin Bidirectional Serial Bit Clock Frame Sync Output Signal Chaining Word Output Chaining Word Input Data/Control Select Input Crystal 1 Input Crystal 1 Output Crystal 2 Input Crystal 2 Output External Sample Clock Input (256 × FS) External Sample Clock Output (256 × FS) Power Down Input (Active HI) Reset Input (Active LO) Parallel Input/Output Bit 1 Parallel Input/Output Bit 0 Analog Signals Pin Name PLCC TQFP I/O Description LINL LINR MINL 18 16 17 12 10 11 I I I MINR 15 9 I LOUT0L LOUT0R LOUT1L LOUT1R LOUT1C MOUT MOUTR C0 C1 N/C N/C VREF CMOUT 32 33 31 29 30 27 28 14 20 26 34 21 19 26 27 25 23 24 21 22 8 14 20 28 15 13 O O O O I O I O O Left Channel Line Input Right Channel Line Input Left Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line Level if MB = 1) Right Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line Level if MB = 1) Left Channel Line Output 0 Right Channel Line Output 0 Left Channel Line Output 1 Right Channel Line Output 1 Common Return Path for Large Current from External Headphones Mono Speaker Output Mono Speaker Output Return External 1.0 µF Capacitor (± 10%) Connection External 1.0 µF Capacitor (± 10%) Connection No Connect (Do Not Connect) No Connect (Do Not Connect) Voltage Reference (Connect to Bypass Capacitor) Common Mode Reference Datum Output (Nominally 2.25 V) O O Power Supplies Pin Name PLCC TQFP I/O Description VCC GNDA VDD GNDD 23 & 24 22 & 25 3, 8, 38 2, 9, 39 17, 18 16, 19 41, 2, 32 40, 3, 33 I I I I Analog Supply Voltage (+5 V) Analog Ground Digital Supply Voltage (+5 V) Digital Ground REV. 0 –7– AD1849K (Continued from page 1) FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1849K and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. The user is not expected to refer repeatedly to this section. Analog Inputs The AD1849K SoundPort Stereo Codec accepts stereo line-level and mic-level inputs. These analog stereo signals are multiplexed to the internal programmable gain amplifier (PGA) stage. The mic inputs can be amplified by +20 dB prior to the PGA to compensate for the voltage swing difference between line levels and typical condenser microphones. The mic inputs can bypass the +20 dB fixed gain block and go straight to the input multiplexer, which often results in an improved system signal-to-noise ratio. The PGA following the input multiplexer allows independent selectable gains for each channel from 0 to 22.5 dB in +1.5 dB steps. The Codec can operate either in a global stereo mode or in a global mono mode with left-channel inputs appearing at both channel outputs. Analog-to-Digital Datapath The AD1849K ∑∆ ADCs incorporate a proprietary fourth-order modulator. A single pole of passive filtering is all that is required for anti-aliasing the analog input because of the ADC’s high 64 times oversampling ratio. The ADCs include linear-phase digital decimation filters that low-pass filter the input to 0.45 × FS (“FS” is the word rate or “sampling frequency”). ADC input overrange conditions will cause a sticky bit to be set that can be read. Digital-to-Analog Datapath The ∑∆ DACs are preceded by a programmable attenuator and a low-pass digital interpolation filter. The attenuator allows independent control of each DAC channel from 0 dB to –94.5 dB in 1.5 dB steps plus full digital mute. The anti-imaging interpolation filter oversamples by 64 and digitally filters the higher frequency images. The DACs’ ∑∆ noise shapers also oversample by 64 and convert the signal to a single-bit stream. The DAC outputs are then filtered in the analog domain by a combination of switched-capacitor and continuous-time filters. They remove the very high frequency components of the DAC bitstream output, including both images at the oversampling rate and shaped quantization noise. No external components are required. Phase linearity at the analog output is achieved by internally compensating for the group delay variation of the analog output filters. Attenuation settings are specified by control bits in the data stream. Changes in DAC output level take effect only on zero crossings of the digital signal, thereby eliminating “zipper” noise. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guarantees that requested volume changes will occur even in the absence of an input signal that changes sign. The time-out period is 10.7 milliseconds at a 48 kHz sampling rate and 64 milliseconds at an 8 kHz sampling rate (Time-out [ms] ≈ 512/ Sampling Rate [kHz]). Monitor Mix A monitor mix is supported that digitally mixes a portion of the digitized analog input with the analog output (prior to digitization). The digital output from the ADCs going out of the serial data port is unaffected by the monitor mix. Along the monitor mix datapath, the 16-bit linear output from the ADCs is attenuated by an amount specified with control bits. Both channels of the monitor data are attenuated by the same amount. (Note that internally the AD1849K always works with 16-bit PCM linear data, digital mixing included; format conversions take place at the input and output.) Sixteen steps of –6 dB attenuation are supported to –94.5 dB. A “0” implies no attenuation, while a “14” implies 84 dB of attenuation. Specifying full scale “15” completely mutes the monitor datapath, preventing any mixing of the analog input with the digital input. Note that the level of the mixed output signal is also a function of the input PGA settings since they affect the ADCs’ output. The attenuated monitor data is digitally summed with the DAC input data prior to the DACs’ datapath attenuators. Because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the DACs’ datapath attenuators. The digital sum of digital mix data and DAC input data is clipped at plus or minus full scale and does not wrap around. Analog Outputs One stereo line-level output, one stereo headphone output, and one monaural (mono) speaker output are available at external pins. Each of these outputs can be independently muted. Muting either the line-level stereo output or the headphone stereo output mutes both left and right channels of that output. When muted, the outputs will settle to a dc value near CMOUT, the midscale reference voltage. The mono speaker output is differential. The chip can operate either in a global stereo mode or in a global mono mode with left channel inputs appearing at both outputs. Digital Data Types The AD1849K supports four global data types: 16-bit twoscomplement linear PCM, 8-bit unsigned linear PCM, 8-bit companded µ-law, and 8-bit companded A-law, as specified by control register bits. Data in all four formats is always transferred MSB first. Sixteen-bit linear data output from the ADCs and input to the DACs is in twos-complement format. Eight-bit data is always left-justified in 16-bit fields; in other words, the MSBs of all data types are always aligned; in yet other words, full-scale representations in all three formats correspond to equivalent full-scale signals. The eight least-significant bit positions of 8-bit linear and companded data in 16-bit fields are ignored on input and zeroed on output. The 16-bit PCM data format is capable of representing 96 dB of dynamic range. Eight-bit PCM can represent 48 dB of dynamic range. Companded µ-law and A-law data formats use nonlinear coding with less precision for large-amplitude signals. The loss of precision is compensated for by an increase in dynamic range to 64 dB and 72 dB, respectively. –8– REV. 0 AD1849K On input, 8-bit companded data is expanded to an internal linear representation, according to whether µ-law or A-law was specified in the Codec’s internal registers. Note that when µ-law compressed data is expanded to a linear format, it requires 14 bits. A-law data expanded requires 13 bits, see Figure 1. 15 COMPRESSED INPUT DATA MSB 0 8 7 3/2 MSB 2/1 0 2/1 0 During the autocalibration sequence, the serial data output from the ADCs is meaningless and the ADI bit is asserted. Serial data inputs to the DACs are ignored. Even if the user specified the muting of all analog outputs, near the end of the autocalibration sequence, dc analog outputs very close to CMOUT will be produced at the line outputs and mono speaker output. LSB 15 DAC INPUT The AD1849K supports an autocalibration sequence to eliminate DAC and ADC offsets. The autocalibration sequence is initiated in the transition from Control Mode to Data Mode, regardless of the state of the AC bit. The user should specify that analog outputs be muted to prevent undesired outputs. Monitor mix will be automatically disabled by the Codec. LSB 15 EXPANSION Autocalibration 3/2 MSB LSB 000/00 An autocalibration sequence is also performed when the AD1849K leaves the reset state (i.e., RESET goes HI). The RESET pin should be held LO for 50 ms after power up or after leaving power-down mode to delay the onset of the autocalibration sequence until after the voltage reference has settled. Figure 1. A-Law or µ -Law Expansion When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified prior to output. See Figure 2. Note that all format conversions take place at input or output. Internally, the AD1849K always uses 16-bit linear PCM representations to maintain maximum precision. 15 ADC OUTPUT LSB 3/2 MSB 15 COMPRESSION MSB Digital and analog loopback modes are supported for device and system testing. The monitor mix datapath is always available for loopback test purposes. Additional loopback tests are enabled by setting the ENL bit (Control Word Bit 33) to a “1.” 0 MSB 15 TRUNCATION Loopback 2/1 Analog loopback mode D-A-D is enabled by setting the ADL bit (Control Word Bit 32) to a “1” when ENL is a “1.” In this mode, the DACs’ analog outputs are re-input to the PGAs prior to the ADCs, allowing digital inputs to be compared to digital outputs. The monitor mix will be automatically disabled by the Codec during D-A-D loopback. The analog outputs can be individually attenuated, and the analog inputs are internally disconnected. Note that muting the line 0 output mutes the looped-back signal in this mode. 0 LSB 0 8 7 LSB 00000000 Figure 2. A-Law or µ -Law Compression Power Supplies and Voltage Reference The AD1849K operates from +5 V power supplies. Independent analog and digital supplies are recommended for optimal performance, though excellent results can be obtained in single supply systems. A voltage reference is included on the Codec and its 2.25 V buffered output is available on an external pin (CMOUT). The CMOUT output can be used for biasing op amps used in dc coupling. The internal reference is externally bypassed to analog ground at the VREF pin. Note that VREF should only be connected to its bypass capacitors. REV. 0 Digital loopback mode D-D is enabled by resetting the ADL bit (Control Word Bit 32) to a “0” when ENL is a “1.” In this mode, the control and data bit pattern presented on the SDRX pin is echoed on the SDTX pin with a two frame delay, allowing the host controller to verify the integrity of the serial interface starting on the third frame after D-D loopback is enabled. During digital loopback mode, the output DACs are operational. –9– AD1849K The loopback modes are shown graphically in Figure 3. LINE, MIC INPUT DISCONNECTED GAIN A/D AD1849K Clocks and Sample Rates µ/A-LAW ENCODE SDTX µ/A-LAW DECODE SDRX MONITOR DISABLE MUTE LINE 0 OUTPUT LINE 1 FUNCTIONAL 0 1 D/A Σ AD1849K Analog Loopback D-A-D LINE, MIC INPUT GAIN A/D AD1849K LINE 0, LINE 1 OUTPUT FUNCTIONAL MUTE D/A µ/A-LAW ENCODE SDTX µ/A-LAW DECODE SDRX MONITOR Σ AD1849K Digital Loopback D-D Figure 3. AD1849K Loopback Modes The AD1849K can operate from external crystals, from a 256 × FS input clock, from an input clock with a programmable divide factor, or from the serial port’s bit clock (at 256 × FS), selected under software control. Two crystal inputs are provided to generate a wide range of sample rates. The oscillators for these crystals are on the AD1849K, as is a multiplexer for selecting between them. They can be overdriven with external clocks by the user, if so desired. The recommended crystal frequencies are 16.9344 MHz and 24.576 MHz. From them the following sample rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz. Regardless of clock input source, a clock output of 256 × FS is generated (with some skew). If an external input clock or the serial port’s bit clocks are selected to drive the AD1849K’s internal operation, they should be low jitter clocks. If no external clock will be used, Analog Devices recommends tying the clock input pin (CLKIN) to ground. If either external crystal is not used, Analog Devices recommends tying its input (CIN1 and/or CIN2) to ground. –10– REV. 0 AD1849K CONTROL REGISTERS The AD1849K SoundPort Stereo Codec accepts control information through its serial port when in Control Mode. Some control information is also embedded in the data stream when in Data Mode. (See Figure 8.) Control bits can also be read back for system verification. Operation of the AD1849K is determined by the state of these control bits. The 64-bit serial Control Mode and Data Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states after RESET or Power Down. Those control bits that cannot be changed in Control Mode are initialized to defaults on the transition from Data Mode to Control Mode. See below for a definition of these defaults. Control Mode Control Registers Control Byte 1, Status Register MB OLB DCB AC REV. 0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 1 MB OLB DCB 0 AC 63 62 61 60 59 58 57 56 Mic bypass: 0 Mic inputs applied to +20 dB fixed gain block. 1 Mic inputs bypass +20 dB fixed gain block. Output level bit: 0 Full-scale line 0 output is 2.8 V p-p (1 V rms). Full-scale line 1 output is 4.0 V p-p. Full-scale mono speaker output is 8.0 V p-p. 1 Full-scale line 0 output is 2.0 V p-p. Full-scale line 1 output is 2.0 V p-p. Full-scale mono speaker output is 4.0 V p-p. Data/control bit. Used for handshaking in data/control transitions. See “DCB Handshake Protocol.” Autocalibration. Autocalibration will always occur on the Control-to-Data mode transition. The AC bit is ignored. Autocalibration requires an interval of 194 frames. Offsets for all channels of ADC and DAC are zeroed. The user should specify that analog outputs are muted to prevent undesired outputs, i.e., OM0 = “0,” OM1 = “0,” and SM =“0.” Monitor mix will be automatically disabled by the Codec. –11– AD1849K Control Byte 2, Data Format Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 DFR2 DFR1 DFR0 ST DF1 DF0 55 54 53 52 51 50 49 48 DFR2:0 ST DF1:0 Data conversion frequency (FS) select tin kHz): DFR Divide Factor 0 3072 1 1536 2 896 3 768 4 448 5 384 6 512 7 2560 XTAL1 (24.576 MHz) 8 16 27.42857 32 N/A N/A 48 9.6 XTAL2 (16.9344 MHz) 5.5125 11.025 18.9 22.05 37.8 44.1 33.075 6.615 Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin (COUT1 or COUT2) should be left unconnected. The external clock source need not be at the recommended crystal frequencies, and it will be divided down by the selected Divide Factor. Global stereo mode. Both converters are placed in the same mode. 0 Mono mode. The left analog input appears at both ADC outputs. The left digital input appears at both DAC outputs. 1 Stereo mode Codec data format selection: 0 16-bit twos-complement PCM linear 1 8-bit µ-law companded 2 8-bit A-law companded 3 8-bit unsigned PCM linear Control Byte 3, Serial Port Control Register ITS MCK2:0 FSEL1:0 MS TXDIS Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 ITS MCK2 MCK1 MCK0 FSEL1 FSEL0 MS TXDIS 47 46 45 44 43 42 41 40 Immediate three-state: 0 FSYNC, SDTX and SCLK three-state within 3 SCLK cycles after D/C goes LO 1 FSYNC, SDTX and SCLK three-state immediately after D/C goes LO Clock source select for Codec internal operation: 0 Serial bit clock (SCLK) is the master clock at 256 × FS 1 24.576 MHz crystal (XTAL1) is the clock source 2 16.9344 MHz crystal (XTAL2) is the clock source 3 External clock (CLKIN) is the clock source at 256 × FS 4 External clock (CLKIN) is the clock source, divided by the factor selected by DFR2:0 (External clock must be stable and valid within 2000 periods after it is selected.) Frame size select: 0 64 bits per frame 1 128 bits per frame 2 256 bits per frame 3 Reserved Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is providing the 256 × FS clock for internal Codec operation, 256 bits per frame is effectively selected, regardless of FSEL’s contents. Master/slave mode for the serial interface: 0 Receive serial clock (SCLK) and TSIN from an external device (“slave mode”) 1 Transmit serial clock (SCLK) and frame sync (FSYNC) to external devices (“master mode”) Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for internal Codec operation, slave mode is effectively selected, regardless of the contents of MS. Transmitter disable: 0 Enable serial output 1 Three-state serial data output (high impedance) Note that Control Mode overrides TXDIS. In Control Mode, the serial output is always enabled. –12– REV. 0 AD1849K Control Byte 4, Test Register ENL ADL Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 0 0 0 0 ENL ADL 39 38 37 36 35 34 33 32 Enable loopback testing: 0 Disabled 1 Enabled Loopback mode: 0 Digital loopback from Data/Control receive to Data/Control transmit (D-D) 1 Analog loopback from DACs to ADCs (D-A-D) Control Byte 5, Parallel Port Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 PIO1 PIO0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 PIO1:0 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation. Control Byte 6, Reserved Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 Reserved bits should be written as 0. Control Byte 7, Revision Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 1 0 REVID3 REVID2 REVID1 REVID0 15 14 13 12 11 10 9 8 REVID3:0 Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K. Control Byte 8, Reserved Register Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Reserved bits should be written as 0. REV. 0 –13– AD1849K Data Mode Data and Control Registers Data Byte 1, Left Audio Data—Most Significant 8 Bits Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 L15 L14 L13 L12 L11 L10 L9 L8 63 62 61 60 59 58 57 56 In 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte contains the left audio data sample. In mono mode, only the left audio data is used. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode. Data Byte 2, Left Audio Data—Least Significant 8 Bits Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 L7 L6 L5 L4 L3 L2 L1 L0 55 54 53 52 51` 50 49 48 In 16-bit linear PCM mode, this byte contains the lower eight bits of the left audio data sample. In the 8-bit companded and linear modes, this byte is ignored on input, zeroed on output. In mono mode, only the left audio data is used. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode. Data Byte 3, Right Audio Data—Most Significant 8 Bits Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 R15 R14 R13 R12 R11 R10 R9 R8 47 46 45 44 43 42 41 40 In 16-bit linear PCM mode, this byte contains the upper eight bits of the right audio data sample. In the 8-bit companded and linear modes, this byte contains the right audio data sample. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes, and twos complement coding is used in 16-bit linear PCM mode. Data Byte 4, Right Audio Data—Least Significant 8 Bits Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 R7 R6 R5 R4 R3 R2 R1 R0 39 38 37 36 35 34 33 32 In 16-bit linear PCM mode, this byte contains the lower eight bits of the right audio data sample. In the 8-bit companded and linear modes, this byte is not used. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes, and twos-complement coding is used in 16-bit linear PCM mode. Data Byte 5, Output Setting Register 1 OM1 OM0 LO5:0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 OM1 OM0 LO5 LO4 LO3 LO2 LO1 LO0 31 30 29 28 27 26 25 24 Output Line 1 Analog Mute: 0 Mute Line 1 1 Line 1 on Output Line 0 Analog Mute: 0 Mute Line 0 1 Line 0 on Output attenuation setting for the left DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62” represents 93 dB of attenuation. Attenuation = 1.5 dB × LO, except for LO = “63,” which represents full digital mute. –14– REV. 0 AD1849K Data Byte 6, Output Setting Register 2 ADI SM RO5:0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 ADI SM RO5 RO4 RO3 RO2 RO1 RO0 23 22 21 20 19 18 17 16 ADC Invalid. This bit is set to “1” during the autocalibration sequence, indicating that the serial data output from the ADCs is meaningless. Mono Speaker Analog Mute: 0 Mute mono speaker 1 Mono speaker on Output attenuation setting for the right DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62” represents 93 dB of attenuation. Attenuation = 1.5 dB × RO, except for RO = “63,” which represents full digital mute. Data Byte 7, Input Setting Register 1 PIO1:0 OVR IS LG3:0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 PIO1 PIO0 OVR IS LG3 LG2 LG1 LG0 15 14 13 12 11 10 9 8 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation. ADC input overrange. This bit is set to “1” if either ADC channel is driven beyond the specified input range. It is “sticky,” i.e., it remains set until explicitly cleared by writing a “0” to OVR. A “1” written to OVR is ignored, allowing OVR to remain “0” until an overrange condition occurs. Input selection: 0 Line-level stereo inputs 1 Microphone (condenser-type) level inputs if MB = 0 (+20 dB gain), or line-level stereo inputs if MB = 1 (0 dB gain). Input gain for left channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain. Gain = 1.5 dB × LG. Data Byte 8, Input Setting Register 2 MA3:0 RG3:0 REV. 0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 MA3 MA2 MA1 MA0 RG3 RG2 RG1 RG0 7 6 5 4 3 2 1 0 Monitor mix. “0” represents no attenuation, i.e., the ADCs’ output is fully mixed with the DACs’ input. Step size is 6 dB; “14” represents an attenuation of both channels of the ADCs’ output along the monitor datapath of 84 dB. Mix attenuation = 6 dB × MA, except for MA = “15,” which disables monitor mix entirely. Input gain for right channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain. Gain = 1.5 dB × RG. –15– AD1849K Control Register Defaults Upon coming out of RESET or Power Down, internal control registers will be initialized to the following values: Defaults Calming Out of RESET or Power Down MB OLB 0 0 DCB AC DFR2:0 ST DF1:0 ITS MCK2:0 FSEL1:0 MS TXDIS ENL ADL PIO1:0 OM1:0 LO5:0 ADI SM RO5:0 OVR IS LG3:0 MA3:0 RG3:0 1 0 0 0 1 0 0 2 0 1 0 0 3 0 63 1 0 63 0 0 0 15 0 Mic Input Applied to +20 dB Fixed Gain Block Full-Scale Line 0 Output 2.8 V p-p, Full-Scale Line 1 Output 4.0 V p-p, Full-Scale Mono Speaker Output 8.0 V p-p Data/Control Bit HI Autocalibration Disabled 8 or 5.5125 kHz Monophonic Mode 8-Bit µ-Law Data FSYNC, SDTX and SCLK Three-State within 3 SCLK Cycles after D/C Goes LO Serial Bit Clock [SCLK] is the Master Clock 256 Bits per Frame Slave Mode Three-State Serial Data Output Loopback Disabled Digital Loopback “1”s, i.e., Three-State for the Open Collector Outputs Mute Line 0 and Line 1 Outputs Mute Left DAC ADC Data Invalid, Autocalibration in Progress Mute Mono Speaker Mute Right DAC No Overrange Line-Level Stereo Inputs No Gain on Left Channel No Mix No Gain on Right Channel Also, when making a transition from Control Mode to Data Mode, those control register values that are not changeable in Control Mode get reset to the defaults above (except PIO). The control registers that can be changed in Control Mode will have the values they were just assigned. The subset of the above list of control registers that are assigned default values on the transition from Control Mode to Data Mode are: Defaults at a Control-to-Data Mode Transition OM1:0 LO5:0 SM RO5:0 OVR IS LG3:0 MA3:0 RG3:0 0 63 0 63 0 0 0 15 0 Mute Line 0 and Line 1 Mute Left DAC Mute Mono Speaker Mute Right DAC No Overrange Line-Level Stereo Inputs No Gain No Mix No Gain Note that all these defaults can be changed with control information in the first Data Word. Note also that the PIO bits in the output serial streams always reflect the values most recently read from the external PIO pins. (See “Parallel I/O Bits” below for timing details.) A Control-to-Data Mode transition is no exception. An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word input signal (TSIN) initially. (See “Codec Startup, Modes, and Transitions” below for more details.) –16– REV. 0 AD1849K SERIAL INTERFACE A single serial interface on the AD1849K provides for the transfer of both data and control information. This interface is similar to AT&T’s Concentrated Highway Interface (CHI), allowing simple connection with ISDN and other telecommunication devices. The AD1849K’s implementation also allows a no-glue direct connection to members of Analog Devices’ family of fixed-point DSP processors, including the ADSP-2101, the ADSP-2105, the ADSP-2111, and the ADSP-2115. Frames and Words The AD1849K serial interface supports time-division multiplexing. Up to four AD1849K Codecs or compatible devices can be daisy-chained on the same serial lines. A “frame” can consist of one, two, or four 64-bit “words.” Thus, frames can be 64, 128, or 256 bits in length as specified by the FSEL bits in Control Byte 3. Only 64 bits of each frame, a “word,” contain meaningful data and/or control information for a particular Codec. See Figure 4 below. ONE WORD/FRAME TWO WORDS/FRAME 0 FOUR WORDS/FRAME WORD #2 63 64 WORD #1 0 63 64 127 WORD #2 WORD #3 127 128 WORD #4 191 192 255 Figure 4. Frames and Words The AD1849K supports two types of words: Data Words and Control Words. The proper interpretation of a word is determined by the state of the asynchronous Data/Control (D/C) pin. The D/C pin establishes whether the SoundPort Codec is in the “Data” mode or “Control” mode. Transitions between these modes require an adherence to a handshaking protocol to prevent ambiguous bus ownership. The Data/ Control transition protocol is described below in a separate section. Clocks and the Serial Interface The primary pins of the AD1849K’s serial interface are the serial data receive (SDRX) input pin. The serial data transmit (SRTX) pin, the serial data bit clock (SCLK) pin, the frame sync output (FSYNC) pin, the chaining word input (TSIN) pin, and the chaining word output (TSOUT) pin. The AD1849K can operate in either master mode—in which case SCLK and FSYNC are outputs and TSIN is an input—or in slave mode— in which case SCLK and TSIN are inputs and FSYNC is threestated. If the AD1849K is in master mode, the internally selected clock source is used to drive SCLK and FSYNC. Note that in Control Mode, the Codec always behaves as a slave, regardless of the current state of the MS (Master/Slave) bit. The five possible combinations of clock source and master/slave are summarized in Figure 5. MASTER SLAVE In master mode, the SCLK output frequency is determined by the number of bits per frame selected (FSEL) and the sampling frequency, FS. In short, SCLK = FSEL × FS in master mode. Input data (except PIO) is clocked by the falling edge of SCLK. Data outputs (except PIO) begin driving on the rising edge of SCLK and are always valid well before the falling edge of SCLK. 63 WORD #1 The internal oscillators or CLKIN can be the clock source when the serial interface is in slave mode provided that all clocks applied to the AD1849K SoundPort Codec are derived from the same external source. Precise phase alignment of the clocks is not necessary, rather the requirement is that there is no frequency drift between the clocks. Timing Relationships WORD #1 0 Recommended modes are indicated above by “yes.” Note that Codec performance is improved with a clean clock source, and in many systems the lowest jitter clocks available will be those generated by the Codec’s internal oscillators. Conversely, SCLK in many systems will be the noisiest source. The master/SCLK clock source combination is impossible because selecting SCLK as the clock source overrides the MS control bit, forcing slave mode. (The SCLK pin cannot be driving out if it is simultaneously receiving an external clock.) INTERNAL OSCILLATORS CLKIN SCLK YES YES IMPOSSIBLE CONDITIONAL CONDITIONAL YES Word chaining input, TSIN, indicates to a particular Codec the beginning of its word within a frame in both slave and master modes. The master mode Codec will generate a FSYNC output which indicates the beginning of a frame. In single Codec systems, the master’s FSYNC output should be tied to the master’s TSIN input to indicate that the beginning of the frame is also the beginning of its word. In multiple Codec daisy-chain systems, the master’s FSYNC output should be tied to the TSIN input of the Coded (either the master or one of the slaves) which is intended to receive the first word in the frame. FSYNC and TSIN are completely independent, and nothing about the wiring of FSYNC to TSIN is determined by master or slave status (i.e., the master can own any one of the words in the frame). The master Codec’s FSYNC can also be tied to all of the slave Codecs’ FSYNC pins. When a slave, a Codec’s FSYNC output is three-stated. Thus, it can be connected to a master’s FSYNC without consequence. See “Daisy-Chaining Multiple Codecs” below for more details. The FSYNC rate is always equal to the data conversion sampling frequency, FS. In Data Mode, the key significance of “frames” are to synchronize the transfer of digital data between an AD1849K’s internal ADCs and DACs and its serial interface circuitry. If, for example, a Codec has been programmed for two words per frame (FSEL = “1”), then it will trigger the data converters and transfer data between the converters and the interface every 128 SCLKs. The TSIN input signals the Codec where its word begins within the frame. In Control Mode, frame size is irrelevant to the operation of any particular Codec; TSIN and TSOUT are sufficient to convey all the information required. Figure 5. Clock Source and Master/Slave Combinations REV. 0 –17– AD1849K TSIN is sampled on the falling edge of SCLK. A LO-to-HI transition of TSIN defines the beginning of the word to occur at the next rising edge of SCLK (for driving output data). The LO-to-HI transition is defined by consecutive LO and HI samples of TSIN at the falling edges of SCLK. Both input and output data will be valid at the immediately subsequent falling edge of SCLK. See Figures 6 and 7. tCLK tHI tLO SCLK tIH tS SDRX AND TSIN INPUTS SCLK tZV SDTX CONTROL OR DATA BYTE 1, BIT 7 OUTPUT FSYNC, TSIN, & TSOUT tOH tD SDTX, FSYNC, AND TSOUT OUTPUTS tVZ SDTX CONTROL OR DATA BYTE 8, BIT 0 OUTPUT SDRX & SDTX tS FIRST DATA BIT OF WORD tIH PIO INPUTS Figure 6. AD1849K Timing Relationships tD PIO OUTPUTS After the beginning of a word has been recognized, TSIN is a “don’t care”; its state will be ignored until one SCLK period before the end of the current word. tOH Figure 7. AD1849K Timing Parameters The AD1849K comes out of reset with the default conditions specified in “Control Register Defaults.” It will be in the mode specified by the D/C pin. If in Control Mode, the SoundPort Codec can be configured by the host for operation. Subsequent transitions to Control Mode after initialization are expected to be relatively infrequent. Control information that is likely to change frequently, e.g., gain levels, is transmitted along with the data in Data Mode. See Figure 8 for a complete map of the data and control information into the 64-bit Data Word and the 64-bit Control Word. 16-BIT STEREO DATA WORD 63 48 47 Left-Channel Audio 32 31 Right-Channel Audio 30 29 24 23 OM LO 22 21 ADI SM 16 15 14 RO PIO 13 OVR 12 11 8 7 4 3 IS LG MA 0 RG 16-BIT MONO DATA WORD 63 48 47 Left-Channel Audio 32 31 Left-Channel Audio 30 29 24 23 OM LO 22 21 ADI SM 16 15 14 RO PIO 13 OVR 12 11 8 7 4 3 IS LG MA 0 0000 8-BIT STEREO DATA WORD 63 56 55 48 47 40 39 32 31 30 29 24 23 Left Audio 0000 0000 Right Audio 0000 0000 OM LO 22 21 ADI SM 16 15 14 RO PIO 13 OVR 12 11 8 7 4 3 IS LG MA 0 RG 8-BIT MONO DATA WORD 63 56 55 32 31 Left Audio 0000 0000 Left Audio 0000 0000 30 29 24 23 OM LO 22 21 ADI SM 16 15 14 RO PIO 13 OVR 12 11 8 7 4 3 IS LG MA 0 0000 CONTROL WORD 63 61 60 59 58 57 56 55 54 53 51 50 49 48 47 46 44 43 42 41 001 MB OLB DCB 0 AC 00 DFR ST 40 39 34 33 32 31 30 29 24 23 16 15 12 11 8 7 0 DF ITS MCK FSEL MS TXDIS 0000 00 ENL ADL PIO 00 0000 0000 0000 0010 REVID 0000 0000 Figure 8. AD1849K Bit Positions for Data and Control –18– REV. 0 AD1849K bits per frame, and SCLK as an input. The slaves FSYNC outputs will be three-stated and thus can be connected to the master’s FSYNC without contention. Daisy-Chaining Multiple Codecs Up to four SoundPort Codecs can be daisy-chained with frame sizes in multiples of 64 bits. The serial data is time-division multiplexed (TDM), allocating each Codec its own 64-bit word in the frame. If SCLK is the clock source, it must run at 256 × FS, and therefore the frame size must be 256 bits, i.e., four words. By contrast, if the master Codec’s CLKOUT is used as the clock source, then it can run at either 256 × FS or 128 × FS. The pins that support TDM daisy-chaining of multiple Codecs are the word chaining input (TSIN) and the word chaining output (TSOUT ). As described above, TSIN is used to indicate the position of the first bit of a particular Codec’s 64-bit word within the total frame. Parallel I/O Bits The word chaining output (TSOUT) is generated by every Codec during the transmission of the last bit of its 64-bit word. The first device in any Codec chain uses an externally generated or self-generated FSYNC signal as an input to TSIN. The TSOUT of the first Codec is wired directly to the TSIN of the second Codec and so on. The waveform of TSOUT is a pulse of one SCLK period in duration. All Codecs share the same SCLK, FSYNC, SDRX, and SDTX lines since they are selecting different words from a common frame. Note that a powered-down Codec immediately echoes TSIN on TSOUT. Thus, a Codec can be added or removed from the chain simply by using the PDN pin. See “Reset and Power Down” below for more details. See Figure 9 for an illustration of daisy-chained Codecs. EXTERNAL DEVICE SCLK SCLK SDTX SDRX AD1849K #1 SDRX SDTX MASTER FSYNC D/C PDN1 PDN2 RESET TSIN CLKOUT D/C PDN RESET The PIO pins are driven very shortly after the PIO data bits in the input Data Word are read (Data Mode only). They are driven on the falling edge of SCLK (unlike any other output). The PIO data bits in the input are located at Bits 15 and 14 in the Data Word and at Bits 31 and 30 in the Control Word (Figure 8). Due to the five (5) SCLK period delay, the PIO pins will be driven out with new values for Data Mode on the SCLK falling edge when Bit 8 is read in, and for Control Mode on the SCLK falling edge when Bit 24 is read in. SCLK SDRX SDTX FSYNC AD1849K #2 SLAVE TSIN TSOUT The PIO pins are open-drain and should be pulled HI externally. They can be read (through serial output data) in either Control or Data Mode and can be written (through serial input data) in Data Mode exclusively. The values in the PIO field of the Control Word serial input in Control Mode will be ignored. An external device may drive either PIO pin LO even when written HI by the Codec, since the pin outputs are open-drain. Thus, a PIO value read back as a serial output bit may differ from the value just written as a serial input bit. The PIO pins are read on the rising edge of SCLK five (5) SCLK periods before the first PIO bit is transmitted out over the serial interface. In Data Mode, the PIO pins are sampled as Bit 20 starts to be driven out. In Control Mode, the PIO pins are sampled as Bit 36 starts being driven out. Timing parameters are as shown in Figure 7; PIO pin input data is relative to the rising edge of SCLK. (Note that only the PIO pins are read on SCLK rising edges.) FSYNC TSOUT Both Data and Control Words allocate Bit positions for “parallel I/O,” PIO1:0. This provides a convenient mechanism for transferring signaling information between the serial data and control streams and the external pair of bidirectional pins also named “PIO1” and “PIO0.” The states of the parallel I/O bits and pins do not affect the internal operation of the Codec in any way; their exclusive use is for system signaling. CLKIN D/C PDN CODEC STARTUP, MODES, AND TRANSITIONS RESET Reset and Power Down The AD1849K Stereo Codec can be reset by either of two closely related digital input signals, RESET and Power Down (PDN). RESET is active LO and PDN is active HI. Asserting PDN is equivalent to asserting RESET with two exceptions. First, if PDN is asserted (when RESET is HI), then the TSIN and TSOUT chaining pins remain active. TSOUT will immediately echo whatever signal is applied to TSIN during power down. This feature allows a very simple system test to detect “life” even in a power-down state. It also allows the user to selectively shut off Codecs in a daisy chain by powering down the unwanted Codecs. The down-stream Codecs will simply move up a word position in frame. The second difference is that power consumption will be lower in power-down mode than in exclusive reset mode. The CMOUT and LOUT1C pins will not supply current while the AD1849K is in the power-down state since all outputs collapse to ground. Figure 9. AD1849K Daisy-Chaining Note that at most, one Codec in a daisy-chain can be in master mode without contention. All other Codecs must be in slave mode, receiving SCLK and TSIN externally. Each slave can use SCLK as its clock source. However, as an alternative, it is possible to connect the CLKOUT pin of the master Codec to the CLKIN pins of the slaves, so that the sample frequency selected by the master (from one of its two crystals) will be automatically applied to the slaves. The master must be programmed for the desired sample frequency and the correct number of bits per frame. The slaves must be programmed for CLKIN as the clock source, the correct number of REV. 0 –19– AD1849K RESET should be asserted when power is first applied to the AD1849K. RESET should be asserted for a minimum of 50 ms at power-up or when leaving the power-down mode to allow the power supplies and the voltage reference to settle. Any time RESET is asserted during normal operation, it should remain asserted for a minimum of 100 ns to insure a complete reset. Note that an autocalibration sequence will always occur when RESET is deasserted, in addition to on the Control Mode to Data Mode transition. protocol to ensure a smooth transition between serial bus masters (i.e., the external controller and the Codec) and guarantee unambiguous serial bus ownership. This software handshake protocol for Control Mode to Data Mode transitions makes use of the Data/Control Bit (DCB) in the Control Mode Control Word (Bit 58). Prior to initiating the change to Control Mode, the external controller should gradually attenuate the audio outputs. The DCB handshake protocol requires the following steps: Coming out of either reset or power down, the state of the Data/ Control pin (D/C) will determine whether the Codec is in Data Mode or Control Mode. In the unlikely event that the control register defaults are desired for Codec operation, it is possible to go directly from reset or power down to Data Mode and begin audio operation. Enter Control Mode Control Mode More typically, users coming out of reset or power down will want to change the control register defaults by transmitting a Control Word in Control Mode. The user of the AD1849K SoundPort Codec can also enter Control Mode at any time during normal Data Mode operation. The D/C pin is provided to make this possible. The Codec enters Control Mode when the D/C pin is driven LO or held LO when coming out of reset and/or power down. In Control Mode, the location of a word within a frame is determined solely by the behavior of the TSIN and TSOUT signals. Each Codec by itself does not care where the frame boundaries fall as defined by the system. The contents of the frame size select (FSEL1:0, Control Word Bits 43 and 42) bits are irrelevant to the operation of each AD1849K in Control Mode. In Control Mode, a Codec requires 64 SCLK cycles to be fully programmed. Additional SCLK cycles (more than 64) that occur before the end of the frame will be ignored. If four Codecs, for example, were daisy-chained, then each Codec would receive TSIN every 256 bits. In this case, Codec #2’s input Control Word will be positioned between Bit 64 and Bit 127 in the input frame. Control Word Echo While in Control Mode, the AD1849K Codec will echo the Control Word received as a serial input on the SDRX pin as a serial output in the next frame on the SDTX pin. (SDTX will be enabled regardless of the setting of the TXDIS bit, Control Word Bit 40.) This echoing of the control information allows the external controller to confirm that the Codec has received the intended Control Word. For the four Codec daisy chain example above, the Control Word will be echoed bit for bit as an output between Bit 64 and Bit 127 in the next output frame. In general, in Control Mode, the location of the echo Control Word within a frame will be at the same word location as the input Control Word. In the first frame of Control Mode, the AD1849K will output a Control Word that reflects the control register values operative during the most recent Data Mode operation. If Control Mode was entered prior to any Data Mode operation, this first output word will simply reflect the standard default settings. DCB will always be “1” in the first output echoed Control Word. DCB Handshaking Protocol The D/C pin can make transitions completely asynchronously to internal Codec operation. This fact necessitates a handshaking The external controller drives the D/C pin LO, forcing the Codec into Control Mode as a slave. The DCB transmitted from the external controller to the Codec may be “0” or “1” at this point in the handshake. When ITS = 0 (Control Word Bit 47) and the Codec was operating as the master in the preceding Data Mode, immediately after D/C goes LO, the Codec will drive FSYNC and TSOUT LO for one SCLK period, then three-state FSYNC. SDTX is three-stated immediately after D/C goes LO. TSOUT is not three-stated. The Codec will drive SCLK for three (3) SCLK periods after D/C goes LO and then three-state SCLK. The external controller must wait at least three (3) SCLK periods after it drives D/C LO, and then start driving SCLK. When ITS = 1 (Control Word Bit 47) and the Codec was operating as the master in the preceding Data Mode, the Codec will three-state FSYNC, SDTX, and SCLK immediately after D/C goes LO. TSOUT is driven LO immediately after D/C goes LO and is not three-stated. The external controller may start driving SCLK immediately. When ITS = 0 and the external controller was operating as the master in the preceding Data Mode, the external controller must continue to supply SCLK to the slave Codec for at least three (3) SCLK periods after D/C goes LO before a Control Mode TSIN is issued to the Codec. TSIN must be held LO externally until the first Control Word in Control Mode is supplied by the external controller. This prevents false starts and can be easily accomplished by using a pull-down resistor on TSIN as recommended. The slave Codec drives TSOUT and SDTX LO, then three-states SDTX, all within 1 1/2 (one and one half) SCLK periods after D/C goes LO. TSOUT is not three-stated. When ITS = 1 and the external controller was operating as the master in the preceding Data Mode, the external controller must continue to supply SCLK to the slave Codec. A Control Mode TSIN should be issued to the Codec three or more SCLK periods after D/C goes LO. The slave Codec drives TSOUT LO and three-states SDTX immediately after D/C goes LO. TSOUT is not three-stated. The Codec initializes its Data Mode Control Registers to the defaults identified above, which among other actions, mutes all audio outputs. First DCB Interlock When the external controller is ready to continue with the DCB handshake, the Control Word sent by the external controller should have the DCB reset to “0” along with arbitrary control information (i.e., the control information does not have to be valid, although if it is valid, it allows the external controller to verify that the echoed Control Word is correct). The external controller should continue to transmit this bit pattern with –20– REV. 0 AD1849K DCB = “0” until the echoed DCB from the Codec also is reset to “0” (i.e., it must poll DCB until a “0” is read). This is the first interlock of the DCB handshake. The DCB = “0” is echoed on SDTX in the next frame after it was received on SDRX if a sample rate has been consistently selected AND the clock source is generated using the internal oscillator. Otherwise DCB = “0” will be echoed on SDTX in the frame after at least 2 ms of consistent sample rate selection expires. If SCLK or CLKIN is used as the clock source, the user must guarantee that the source selection and sample rate are stable for 2 ms before D/C is driven HI. recognize a complete FSYNC LO-to-HI transition. If an AD1849K Codec enters Data Mode as a slave, it can recognize a TSIN LO-to-HI transition even if SCLK is simultaneously making its first LO-to-HI transition. In fact, the AD1849K serial interface will operate properly even if D/C, SCLK, and TSIN all go HI at the same time. See Figure 10 for a flow chart representation of a typical startup sequence, including the DCB handshake. Apply power while RESET is pulled LO and wait 50 milliseconds Note that after sending a Control Word with DCB = “0,” the external controller must take care not to set (or glitch) DCB = “1” until after the echoed DCB = “0” has been received from the Codec. Provide TSIN and SCLK signals to Codec. Drive RESET HI (inactive) while D/C is LO Transmit a Control Word to Codec with DCB LO Second DCB Interlock After it sees the DCB = “0” (and has optionally verified that the echoed Control Word is correct), and when it is ready to continue with the DCB handshake, the external controller should transmit the desired and valid control information, but now with DCB set to “1.” The external controller can then transmit arbitrary control information until the echoed DCB from the Codec is also set to “l” (i.e., it must poll DCB until a “l” is read). After this Control Word with DCB = “1,” all future control information received by the Codec during Control Mode (i.e., while D/C is LO) will be ignored. This is the second and final interlock of the DCB handshake. The Codec will echo DCB = “l” in the next frame after it was received on SDRX if a sample rate has been consistently selected AND the clock source is generated using the internal oscillator. Otherwise DCB = “1” will be echoed on SDTX once one sample rate selection has been held constant for at least 2 ms. If SCLK or CLKIN is used as the clock source, the user must guarantee that the source selection and sample rate are stable for 2 ms before D/C is driven HI. The Codec will transmit the full 64-bit Control Word with DCB = “1” and then three-state the SDTX pin. The external controller must continue to supply SCLK to the Codec until all 64 bits of the Control Word with DCB = “1” have been transmitted by the Codec, plus at least one [1] more SCLK after this 64-bit Control Word (i.e., at least 65 SCLKs). Note that echoing the full 64-bit Control Word makes the AD1849K match the behavior of the CS4215. Exit Control Mode Control mode DCB handshake is now complete. The Codec will remain inactive until D/C goes HI or RESET and or PDN are asserted. Note that if a sample rate and a clock source have been consistently selected throughout the handshake, the AD1849K and the CS4215 DCB protocols are equivalent. Control Mode to Data Mode Transition and Autocalibration The AD1849K will enter Data Mode when the asynchronous D/C signal goes HI. The serial interface will become active immediately and begin receiving and transmitting Data Words in accordance with the SCLK, FSYNC, TSIN, and TSOUT signals as shown in Figure 6. If the Codec enters Data Mode as a master, it will generate one complete SCLK period before it drives FSYNC HI; FSYNC will go HI with the second rising edge of SCLK. This allows external devices driven by SCLK to REV. 0 ENTER CONTROL MODE Wait for Codec to transmit back a DCB LO FIRST DCB INTERLOCK 0 – 2ms Transmit desired Control Word to Codec with DCB HI Wait for Codec to transmit back a DCB HI Bring D/C HI Transmit 194 Data Words to Codec SECOND DCB INTERLOCK 0 – 2ms EXIT CONTROL MODE AUTOCALIBRATION Begin audio operation Figure 10. Typical AD1849K Startup Sequence APPLICATIONS CIRCUITS The AD1849K Stereo Codec has been designed to require a minimum of external circuitry. The recommended circuits are shown in Figures 11 through 20 and summarized in Figure 21. Analog Devices estimates that the total cost of all the components shown in these Figures, including crystals, to be less than $5 in 10,000 piece quantities. Industry-standard compact disc “line-levels” are 2 V rms centered around analog ground. (For other audio equipment, “line level” is much more loosely defined.) The AD1849K SoundPort is a +5 V only powered device. Line level voltage swings for the AD1849K are defined to be 1 V rms for ADC input and 0.707 V rms for DAC output. Thus, 2 V rms input analog signals must be attenuated and either centered around the reference voltage intermediate between 0 V and + 5 V or ac-coupled. The CMOUT pin will be at this intermediate voltage, nominally 2.25 V. It has limited drive but can be used as a voltage datum to an op amp input. Note, however, that dc-coupled inputs are not recommended, as they provide no performance benefits with the AD1849K architecture. Furthermore, dc offset differences between multiple dc-coupled inputs create the potential for “clicks” when changing the input mux selection. –21– AD1849K A circuit for 2 V rms line-level inputs is shown in Figure 11. Note that this is approximately a divide-by-two resistive divider. 0.33µF 5.1k LINL Figure 13 shows ac-coupled line outputs. The resistors are used to center the output signals around analog ground. If dccoupling is desired, CMOUT could be used with op amps as mentioned below. 1µF 5.1k 560pF LOUT0L NPO 47k 0.33µF 5.1k LINR 1µF LOUT0R 5.1k 560pF NPO 47k Figure 11. AD1849K 2 V rms Line-Level Input Circuit An external passive antialias filter is required. If line-level inputs are already at the 1 V rms levels expected by the AD1849K, the resistors in parallel with the 560 pF capacitors should be omitted and the series 5.1 kΩ resistor should be decreased to 2.5 kΩ. The AD1849K Codec contains a bypassable +20 dB gain block to accommodate condenser microphones. Particular system requirements will depend upon the characteristics of the intended microphone. Figure 12 illustrates one example of how an electret condenser mike requiring phantom power could be connected to the AD1849K. CMOUT is shown buffered by an op amp; a transistor like a 2N4124 will also work fine for this purpose. Note that if a battery-powered microphone is used, the buffer and R2s are not needed. The values of R1, R2, and C should be chosen in light of the mic characteristics and intended gain. Typical values for these might be R1 = 20 kΩ, R2 = 2 kΩ, and C = 220 pF. C 1µF R1 5k 0.33µF MINL R2 LEFT ELECTRET CONDENSER MICROPHONE INPUT 1/2 SSM-2135 OR AD820 C R2 1µF RIGHT ELECTRET CONDENSER MICROPHONE INPUT CMOUT 1/2 SSM-2135 OR AD820 R1 5k 0.33µF MINR 1/2 SSM-2135 OR AD820 Figure 13. AD1849K Line Output Connections A circuit for headphone drive is illustrated in Figure 14. Drive is supplied by +5 V operational amps. The circuit shown ac couples the headphones to the line output. 8.66k 10k 470µF LOUT1L HEADPHONE LEFT LOUT1C SSM-2135 470µF HEADPHONE RIGHT 10k LOUT1R 8.66k Figure 14. AD1849K Headphone Drive Connections The AD1849K has a common return path LOUT1C which is biased up to the CMOUT voltage, nominally 2.25 V. The AD1849K allows for 6 dB larger output voltage swings by resetting the OLB bit (Bit 59 of the Control Word) to “0.” Figure 15 illustrates an alternative headphone connection for the AD1849K which uses the LOUT1C pin to eliminate the need for ac coupling. The 12 Ω resistors minimize output level variations caused by different headphone impedances. LOUT1L, LOUT1R and LOUT1C are short-circuit protected. Note that driving headphones directly as shown in Figure 15 with OLB = 0 will cause clipping for large input signals and will only work with very efficient “Walkman-type” headphones. For high quality headphone listening, Analog Devices recommends the circuit shown in Figure 14 with OLB = 1. 12Ω 1/2W CMOUT LOUT1L Figure 12. AD1849K “Phantom-Powered” Microphone Input Circuit HEADPHONE LEFT 12Ω 1/2W LOUT1R HEADPHONE RIGHT LOUT1C HEADPHONE RETURN Figure 15. AD1849K Optional Headphone Drive Connections –22– REV. 0 AD1849K No external circuitry is required for driving a single speaker from the AD1849K’s mono outputs as shown in Figure 16. Note that this output is differential. Analog Devices guarantees specified distortion performance for speaker impedances of 48 Ω or greater. Lower impedance speakers can be used, but at the cost of some distortion. When driving speakers much less than 48 Ω, a power amp should be used. The AD1849K can drive speakers of 32 Ω or greater. clock sources can be used to overdrive the AD1849K’s internal oscillators. (See the description of the MCK1:0 control bits above.) If using an external clock source, apply it to the crystal input pins while leaving the crystal output pins unconnected. Attention should be paid to providing low jitter external input clocks. CIN1 CIN2 COUT1 COUT2 MOUT 20–64pF 20–64pF Z ≥ 32Ω 20–64pF 20–64pF 24.576MHz 16.9344MHz Figure 19. AD1849K Crystal Connections MOUTR Good, standard engineering practices should be applied for power-supply decoupling. Decoupling capacitors should be placed as close as possible to package pins. If a separate analog power supply is not available, we recommend the circuit shown in Figure 20 for using a single +5 V supply. Ferrite beads suffice for the inductors shown. This circuitry should be as close to the supply pins as is practical. Figure 16. AD1849K External Mono Speaker Connector Figure 17 illustrates reference bypassing. VREF should only be connected to its bypass capacitors, which should be located as close to Pin 21 as possible (especially the 0.1 µF capacitor). VREF CMOUT FERRITE 0.1µF 10µF 10µF +5V SUPPLY 0.1µF 1µF 0.1µF VDD Figure 17. AD1849K Voltage Reference Bypassing Figure 18 illustrates signal-path filtering capacitors, C0 and C1. The AD1849K must use 1.0 µF capacitors. C0 FERRITE 0.1µF 0.1µF VDD VDD 1.6Ω C1 0.1µF 1µF 1µF 0.1µF VCC 1µF VCC 1µF Figure 20. AD1849K Recommended Power Supply Bypassing Figure 18. AD1849K External Filter Capacitor Connections The crystals shown in the crystal connection circuitry of Figure 19 should be fundamental-mode and parallel-tuned. Two sources for the exact crystals specified are Component Marketing Services in Massachusetts, U.S. at 617-762-4339 and Cardinal Components in New Jersey, U.S. at 201-746-0333. Note that using the exact data sheet frequencies is not required and that external REV. 0 The two PIO pins must be pulled HI, as they have open drain outputs. Analog Devices also recommends pull-down resistors for SCLK, FSYNC, SDTX, SDRX, and TSIN to provide margin against system noise. CLKIN, CIN1, and CIN2, if not used, should be grounded. A typical connection diagram is shown in Figure 21, which serves to summarize the preceding application circuits. –23– AD1849K FERRITE FERRITE +5V SUPPLY Low level ADSP-21xx software drivers for the AD1849K are supplied with the AD1849K Evaluation Board. Source and object codes arc available from your Analog Devices Sales Representative or on the Analog Devices DSP Bulletin Board. The DSP Bulletin Board telephone number is (617) 461-4258, 8 data bits, no parity, 1 stop bit, 300 to 2400 baud. 1.6 Ω 0.1µF 1µF 0.1µF 1µF 0.1µF 0.33µF 5.1k 0.1µF VDD VDD VDD LINL VCC 1µF 0.1µF MOUT MONO SPEAKER LINE IN MOUTR 0.33µF 5.1k LINR LOUT0L ANALOG GROUND PLANE DIGITAL GROUND PLANE 1µF 5.1k 560pF NPO Note that the interface to the Texas Instruments TMS320C25 must be significantly more complicated than these three examples because the C25’s serial port cannot be a master, which is required of the external controller during Control Mode. VCC 5.1k 560pF NPO 0.1µF 47k AD1849K N/C LINE OUT 0 LOUT0R LOUT0R PREFERRED MICROPHONE INPUT CIRCUIT 10µF 1µF CMOUT LOUT1L VREF LOUT1R LOUT1C 10µF 0.1µF AD1849K 47k MINL MINR LINE OUT 1 OR PREFERRED HEADPHONE CIRCUIT PDN C0 COUT1 Figure 22. AD1849K Recommended Ground Plane C0 24.576MHz CIN1 1µF 1µF GNDA SCLK0 RFS0 20–64pF C1 COUT2 ADSP-2111 AD1849K DT0 DR0 FL0 16.9344MHz GNDA SCLK FSYNC TSIN CIN2 SDRX SDTX D/C TSIN PDN RESET FSYNC PIO0 PIO1 47k SCLK0 RFS0 SCLK SDTX ADSP-2101 GNDD GNDD GNDD SDRX ADSP-2115 20k VDD SCLK FSYNC TSIN AD1849K DT0 DR0 FO SDRX SDTX D/C UNUSED INPUTS SHOULD BE GROUNDED AND NC'S LEFT UNCONNECTED 10k Figure 21. Typical Connection Diagram Analog Devices recommends a split ground plane as shown in Figure 22. The analog plane and the digital plane are connected directly under the AD1849K. Splitting the ground plane directly under the SoundPort Codec is optimal because analog pins will be located above the analog ground plane and digital pins will be located directly above the digital ground plane for the best isolation. The digital ground and analog grounds should be tied together in the vicinity of the AD1849K. Other schemes may also yield satisfactory results. Figure 23 illustrates the “zero-chip” interfaces of the AD1849K SoundPort Codec to four of Analog Devices’ Fixed-Point DSµPs. The ADSP-2111, ADSP-2101 and ADSP-2115 use their multichannel serial port for the data interface and flag outputs for D/C. The ADSP-2105 has a single serial port which operates in its frameless mode. Because the ADSP-2105 lacks a flag output, it alone does require additional circuitry to generate D/C. Shown is an implementation using a single D-flop, an OR-gate, and two pull-down resistors. ADSP-2105 SCLK RFS TFS DT DR D8 SCLK FSYNC TSIN 10k D AD1849K Q SDRX SDTX D/C CLR RESET WR DMS RESET Figure 23. Interfaces to Analog Devices’ Fixed-Point DS µPs –24– REV. 0 AD1849K CS4215 COMPATIBILITY The Analog Devices AD1849K SoundPort Stereo Codec is pincompatible with the CS4215. These chips were independently codeveloped to a common specification provided by Sun Microsystems, Inc. Because of their independent development, they will differ in performance and in minor details. A board can be designed to accommodate either chip by attending to a few differences in their required support circuitry. • If consistent control information is transmitted to the Codec during Control Mode, the AD1849K DCB handshake is compatible with the CS4215. See text for more details. • The Analog Devices AD1849K uses two external capacitors to complete its internal input filter as shown in Figure 18. The CS4215 calls the two pins on the AD1849K for these capacitor connections, “no connects.” By laying out a board with these capacitors, either chip will work. • Pin 38 (PLCC) and Pin 32 (TQFP) on the AD1849K is used as a digital power supply. On the CS4215, this pin is a “no connect.” We strongly recommend connecting this pin to the digital supply. Both chips should operate in this configuration. Pin 39 (PLCC) and Pin 33 (TQFP) on the AD1849K is used as a digital ground. On the CS4215, this pin is a “no connect.” We strongly recommend connecting this pin to the digital ground plane. Both chips should operate in this configuration. • Analog Devices recommends a 10 µF bypass capacitor on the voltage reference output, CMOUT (Pin 19). Using a 0.47 µF capacitor may be acceptable in many systems, however DAC performance at low sample rates will be improved with the larger capacitor. • The AD1849K requires an external passive antialias filter as shown in Figure 11. In contrast, the recommended input circuit for the CS4215 is a single-pole active filter requiring a dual op amp. Though overkill for the AD1849K, this input circuit will work with the AD1849K as well. • The AD1849K was designed to require no external low-pass filters on analog outputs. As shown in Figure 13, the AD1849K only requires ac coupling capacitors and resistors for line-level dc bias. In contrast, the CS4215 has a singlepole passive filter for its recommended line-level output circuit. Though overkill for the AD1849K, this output circuit will work with the AD1849K as well. REV. 0 –25– AD1849K FREQUENCY RESPONSE PLOTS 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 dB –50 dB –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 –120 1.0 0.0 0.1 0.2 SAMPLE FREQUENCY (F S) 0.5 0.6 0.7 0.8 0.9 1.0 Figure 26. AD1849K Digital-to-Analog Frequency Response (Full-Scale Inputs, 0 dB Attenuation) 10 10 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 dB –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 0.40 0.4 SAMPLE FREQUENCY (F S) Figure 24. AD1849K Analog-to-Digital Frequency Response to FS (Full-Scale Line-Level Inputs, 0 dB Gain) dB 0.3 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 –120 0.40 0.60 Figure 25. AD1849K Analog-to-Digital Frequency Response – Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain) 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 SAMPLE FREQUENCY (F S) SAMPLE FREQUENCY (F S) Figure 27. AD1849K Digital-to-Analog Frequency Response – Transition Band (Full-Scale Inputs, 0 dB Attenuation) –26– REV. 0 AD1849K INDEX PAGE PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . 2 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AD1849K PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 8 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . 8 Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . 8 Monitor Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Supplies and Voltage Reference . . . . . . . . . . . . . . . 9 Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . 10 CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control Mode Control Registers . . . . . . . . . . . . . . . . . . 11 Data Mode Data and Control Registers . . . . . . . . . . . . . 14 Control Register Defaults . . . . . . . . . . . . . . . . . . . . . . . . 16 SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Frames and Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clocks and the Serial Interface . . . . . . . . . . . . . . . . . . . . 17 Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Daisy-Chaining Multiple Codecs . . . . . . . . . . . . . . . . . . 19 Parallel I/O Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CODEC STARTUP, MODES, AND TRANSITIONS . . 19 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Word Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DCB Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . 20 Control Mode to Data Mode Transition and Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . 21 APPLICATIONS CIRCUITS . . . . . . . . . . . . . . . . . . . . . . 21 CS4215 COMPATIBILITY . . . . . . . . . . . . . . . . . . . . . . . . 25 FREQUENCY RESPONSE PLOTS . . . . . . . . . . . . . . . . 26 PACKAGE—Outline Dimension Drawings . . . . . . . . . . . . 28 REV. 0 –27– AD1849K OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (PLCC) 6 0.020 (0.50) R 40 PIN 1 IDENTIFIER 7 0.025 (0.63) 0.015 (0.38) C1885–5–3/94 0.048 (1.21) 0.042 (1.07) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 39 PIN 1 IDENTIFIER 0.021 (0.53) 0.013 (0.33) 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) TOP VIEW BOTTOM VIEW 0.050 (1.27) BSC 17 29 28 18 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.110 (2.79) 0.085 (2.16) 0.695 (17.65) SQ 0.685 (17.40) 44-Lead Thin Quad Flatpack (TQFP) 0.006 ± 0.002 (0.145 ± 0.055) 0.024 ± 0.006 (0.6 ± 0.15) 0.472 (12.00) SQ 0° MIN 33 23 34 22 0.394 (10.0) SQ TOP VIEW SEATING PLANE PIN 1 44 12 1 0.004 ± 0.002 (0.1 ± 0.05) 0.093 (1.6) MAX 0.018 (0.45) 0.012 (0.30) 0.0315 (0.80) BSC PRINTED IN U.S.A. 0.055 ± 0.002 (1.40 ± 0.05) 11 –28– REV. 0