AS28F128J3A Q

PEM
PEM
AS28F128J3M
AS28F128J3A
Q-Flash
Q-Flash
Austin Semiconductor, Inc.
Plastic Encapsulated Microcircuit
Plastic
Microcircuit
128Mb,Encapsulated
x8 and x16 Q-FLASH
Memory
PIN ASSIGNMENT
Even Sectored,
Bit per CellMemory
Architecture
128Mb,
x8 andSingle
x16 Q-FLASH
Even Sectored, Single Bit per Cell Architecture
FEATURES
• 100% Pin and Function compatible to Intel’s MLC Family
Features
NOR Cell Architecture
2.7VPin
to 3.6V
VCC compatible to Intel’s MLC Family
100%
and Function
2.7V
to
3.6V
or 5V VPEN (Programming Voltage)
NOR Cell Architecture
Asynchronous
Page Mode Reads
2.7V to 3.6V VCC
Manufacturer’s
IDVPEN
Code:(Programming Voltage)
2.7V
to 3.6V or 5V
Numonyx
0x89h
Asynchronous
Page
Mode Reads
Industry Standard
Pin-Out
Manufacturer’s
ID Code:
compatible TTL Input and
Outputs
Fully
MT28F128J3MRG
Micron
0x2Ch
Industry
Standard
Pin-Out [CFI]
Common
Flash Interface
Fully
compatible
TTL Set
Input and Outputs
Scalable
Command
Common
Flash
Interface
Automatic
WRITE
and[CFI]
ERASE Algorithms
Scalable
Command
Set
5.6us per
Byte effective
programming time
Automatic
WRITE and
ERASE Algorithms
128 bit protection
register
5.6us
per Byte
effective
programming
64-bit
unique
device
identifier time
128
bit protection
register
64-bit
user programmable
OTP cells
Enhanced
64-bit unique
device identifier
data protection
feature with use of VPEN=VSS
Security
64-bit OTP
user programmable
block feature OTP cells
Enhanced
data
protection
with use of VPEN=VSS
100,000 ERASE cyclesfeature
per BLOCK
Security
OTP
block
feature
Automatic Suspend Options:
100,000 ERASE cycles per BLOCK
Block ERASE SUSPEND-to-READ
Automatic Suspend Options:
Block ERASE SUSPEND-to-PROGRAM
 Block ERASE SUSPEND-to-READ
PROGRAM SUSPEND-to-READ
 Block ERASE SUSPEND-to-PROGRAM
• Available
Operating
Ranges:
PROGRAM
SUSPEND-to-READ
o
Enhanced[-ET]-40
C to +105oC
• Available Operating Ranges:
o
o
o
to +125
C C
Mil-Temperature[-XT]-55
Enhanced
[-ET] -40oC toC +105
o
o
 Mil-Temperature [-XT] -55 C to +125 C
For in-depth functional product detail and Timing Diagrams,
please reference Numonyx’s full product Datasheet:
For in-depth functional product detail and Timing Diagrams,
please
referenceFLASH
Micron’s
full product
Datasheet:
EMBEDDED
MEMORY
(J3-65nm)
Dated: March 2010
MT28F640J3
Rev. L Dated 04/16/04
•
• •
• •
• •
• •
•
• •
•
• •
• •
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•
•
•
•
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•
General Description
GENERAL DESCRIPTION
AS28F128J3A
Rev. 5.8 8/13
2
3
4
5
6
7
8
A1
A6
A8
VPEN
A13
VCC
A18
A22
A2
VSS
A9
CE0
A14
DNU
A19
CE1
A3
A7
A10
A12
A15
DNU
A20
A21
A4
A5
A11
RP\
DNU
DNU
A16
A17
DQ8
DQ1
DQ9
DQ3
DQ4
DNU
DQ15
STS
BYTE\
DQ0
DQ10
DQ11 DQ12
DNU
DNU
OE\
A23
A0
DQ2
VCCQ
DQ5
DQ6
DQ14
WE\
CE2
DNU
VCC
VSS
DQ13
VSS
DQ7
DNU
A
B
C
D
E
F
G
H
64-Ball FBGA
A22
1
56
CE1
A21
A20
A19
2
55
NC
WE\
3
54
OE\
4
53
STS
5
52
A18
A17
6
51
7
50
DQ15
DQ7
DQ14
A16
VCC
8
49
9
48
A15
A14
10
47
11
46
A13
12
45
A12
CE0
13
44
DQ5
DQ12
DQ4
14
43
VCCQ
VPEN
15
42
VSS
RP\
A11
A10
16
41
17
40
18
39
A9
19
38
DQ11
DQ3
DQ10
DQ2
A8
VSS
20
37
VCC
21
36
DQ9
A7
22
35
DQ1
A6
A5
23
34
24
33
DQ8
DQ0
A4
25
32
A0
A3
A2
26
31
27
30
A1
28
29
BYTE\
A23
CE2
DQ6
VSS
DQ13
This device
device features
features in-system
in-system block
locking. They
They also
also have
have a
This
block locking.
Common FLASH Interface [CFI] that permits software algorithms
a Common FLASH Interface [CFI] that permits software
to be used for entire families of devices. The software is devicealgorithms
be used
for entire families
of devices.
The
independent,toJEDEC
ID-independent
with forward
and backward
software
is
device-independent,
JEDEC
ID-independent
with
compatibility.
forward and backward compatibility.
ASI’s,
AS28F128J3M
Enhanced
or Mil-Temp
variant variant
of Micron’s
Micross'
AS28F128J3A
Enhanced
or Mil-Temp
of
Q-Flash
family
of
devices,
is
a
nonvolatile,
electrically
blockNumonyx’s Q-Flash family of devices, is a nonvolatile,
erasable
(FLASH),
programmable
memory
device manufactured
electrically
block-erasable
(FLASH),
programmable
memory
using Micron’s 0.15um process technology.
This device
device manufactured using Numonyx’s 0.15um process
containing 134,217,728 bits organized as either 16,777,218 (x8)
This device
134,217,728
bits
organized
ortechnology.
8,388,608 bytes
(x16). containing
The device
is uniformly
sectored
with
as
either
16,777,218
(x8)
or
8,388,608
bytes
(x16).
The
device
one hundred and twenty eight 128KB ERASE blocks.
is uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
AS28F128J3MRG
Revision 5.0 11/23/04
1
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1
1
Micross Components reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc.
PEM
PEM
AS28F128J3M
AS28F128J3A
Q-Flash
Q-Flash
Functional Block Diagram:
Input
Buffer
I/O
CNTL
Logic
ADDR
Buffer/
Latch
Power
(Current)
Control
X
Decode
Bus
Configuration
Register [BCR]
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
128KB Memory Block (3)
ADDR.
Counter
WRITE
Buffer
Block
Erase
Control
CEx
OE\
WE\
RP\
Command
Execution
Logic
[CEL]
128KB Memory Block (n)
ISM
WP\
Y
Dec.
CLK
DQ0-8 or
DQ0-15
Y - Select
Control
STS
VPEN
WAIT
Sense Amplifiers
WRITE/ERASE Bit
Compare and
Verify
VPP
Switch
Pump
Status
Register
Identification
Register
Query
Output
Buffer
Additionally, the Scaleable Command Set [SCS] allows a single,
Additionally,
the Scaleable
Set [SCS]
allowswith
a single,
2.7V,
3.3V
or or
5V 5V
levels
for for
simple software
driver inCommand
all host systems
to work
all SCSVPEN
VPENserves
servesasasananinput
inputwith
with
2.7V,
3.3V
levels
simple
software
driver
in all host
systems
work
with all
inthis
thisQ-Flash
Q-Flashdevice
device
compliant
FLASH
memory
devices.
ThetoSCS
provides
theSCS
fastestapplication
applicationprogramming.
programming. VPEN
VPEN in
cancan
system/device
datamemory
transfer devices.
rates and The
minimizes
the device
provide
data
protectionwhen
whenconnected
connected to ground.
compliant
FLASH
SCS provides
theandprovide
data
protection
ground. This
Thispin
pinalso
system-level
implementation
costs. rates and minimizes the also
enables
PROGRAM
or ERASE
LOCKOUT
functions/controls
fastest
system/device
data transfer
enables
PROGRAM
or ERASE
LOCKOUT
functions/
during during
power transitions.
device and system-level implementation costs.
controls
power transitions.
To optimize the processor-memory interface, the device
accommodates VPEN, which is switchable during BLOCK This device is an even-sectored device architecture offering
ToERASE,
optimizePROGRAM,
the processor-memory
interface, the device This device is an even-sectored device architecture offering
or LOCK BIT configurations and in individual BLOCK LOCKING that can LOCK and UN-LOCK a
accommodates
VPEN,
which
is
switchable
during BLOCK
BLOCK
LOCKING
thatBITS
can LOCK
andsequence.
UN-LOCK
addition can be hard-wired to VCC all dependent
on the endindividual
block using
the SECTOR
LOCK
command
ERASE,
PROGRAM,
or
LOCK
BIT
configurations
and
in
a
block
using
the
SECTOR
LOCK
BITS
command
sequence.
application(s). VPEN is treated as an input pin to enable
addition
can be
hard-wired to VCC
dependent
on the end
ERASING,
PROGRAMMING,
andall
BLOCK
LOCKING.
When Status [STS] is a logic signal output that gives an additional
VPEN is lower
than isthetreated
VCC as
lockout
voltage
(VLKO),
indicator
of the
state machine
[ISM]
activity
by providing
application(s).
VPEN
an input
pin to
enable allStatus
[STS]
is ainternal
logic signal
output that
gives
an additional
program functions
are disabled. and
BLOCK
ERASE
SUSPENDindicator
a hardware
signal
of bothstate
the status
and [ISM]
status masking.
ERASING,
PROGRAMMING,
BLOCK
LOCKING.
of the
internal
machine
activity byThis
mode
enables
the user
ERASE (VLKO),
to READalldataproviding
status indicator
minimizes
central
processing
unit and
overhead
When
VPEN
is lower
than to
thestop
VCCBLOCK
lockout voltage
a hardware
signal
of both
the status
statusand
from
or
PROGRAM
data
to
any
other
blocks.
Similarly,
system
power
consumption.
In
the
default
mode,
STS
acts
as an
program functions are disabled. BLOCK ERASE SUSPEND masking. This status indicator minimizes central processing
PROGRAM SUSPEND mode enables the user to SUSPEND RY/BY\ pin. When LOW, STS indicates that the ISM is
mode enables the user to stop BLOCK ERASE to READ unit overhead and system power consumption. In the default
PROGRAMMING to READ data or execute code from any un- performing a BLOCK ERASE, PROGRAM, or LOCK BIT
data
from or block(s).
PROGRAM data to any other blocks. Similarly, mode,
STS acts asWhen
an RY/BY\
LOW,
indicates
suspended
configuration.
HIGH, pin.
STS When
indicates
thatSTS
the ISM
is ready
PROGRAM SUSPEND mode enables the user to SUSPEND that
the
ISM
is
performing
a
BLOCK
ERASE,
PROGRAM,
for a new command.
PROGRAMMING to READ data or execute code from any or LOCK BIT configuration. When HIGH, STS indicates that
AS28F128J3MRG
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
un-suspended
block(s).
the ISM is ready for a new command.
Revision 5.0 11/23/04
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
2
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
2
PEM
AS28F128J3A
Q-Flash
Three Chip Enable (CEx) pins are used for enabling and
disabling the device by activating the device’s control logic,
input buffer, decoders, and sense amplifiers.
BYTE\ enables the device to be used in x8 or x16 configuration.
Byte=Low (logic 0) selects and 8-bit mode with address zero
(A0) selecting the High or Low Byte and Byte=High (logic 1)
selects the 16-bit or Word mode. When the device is in Word
mode, address one (A1) becomes the low order address bit and
address zero (A0) becomes a no-connect (NC).
RP\ is used to reset the device. When the device is disabled
and RP\ is at VCC, the STANDBY mode is enabled. A reset
time (tRWH) is required after RP\ switches to a High (logic 1)
and the outputs become valid. Likewise, the device has a wake
time (tRS) from RP\ High until WRITES to the Command User
Interface [CUI] are recognized, RESETS the ISM and clears
the status register.
Capacitance
Parameter/Condition
Input Capacitance
Symbol
Typ
Max
Units
Cin
5
8
pF
Cbyte
14
16
pF
Output Capacitance
Cout
5
12
pF
Stress greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
conditions for any duration or segment of time may affect device
reliability.
Chip Enable Truth Table
CE2CE1CE0Device
VILVILVILEnabled
VILVILVIHDisabled
VILVIHVILDisabled
VIL VIHVIHDisabled
VIHVILVILEnabled
VIHVIL VIHEnabled
VIHVIHVIL Enabled
VIHVIHVIHDisabled
Absolute Maximum Ratings
Voltage
Temperature Under Bias
Storage Temperature
Short Circuit Current
Min
‐55
‐65
Max
125
125
100
Units
o
C
o
C
mA
Notes
1
Notes
1: All specified voltages are with respect to GND. Minimum DC
voltage is -0.5v on input/output pins and -0.2v on Vcc and VPEN
pins. During transitions, this level may undershoot to -2.0v for
periods </= 20ns. Maximum DC voltage on input/output pins,
Vcc and VPEN is VCC+0.5V which, during transitions, may
overshoot to Vcc + 2.0v for periods <20ns.
Pin Description Table
Signal Name
Symbol
A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12,A13,A14,A15, A16,A17,A18,A19, A20,A21,A22,A23
CE0, CE1, CE2
WE\
Input
Input
Pin
32,28,27,26, 25,24,23,22,
20,19,18,17,
13,12,11,10,
8,7,6,5, 4,3,1,30
14, 2, 29
55
Reset/Power Down
RP\
Input
16
Output Enable
OE\
Input
54
Byte Mode Control
BYTE\
Input
31
Programming Voltage
VPEN
Input
15
STS
Output
53
Input/Output Voltage
VCCQ
Supply
43
Supply Voltage
Digital Ground
No Connect(s)
VCC
GND
NC
Supply
Supply
‐
9, 37
21,42,48
1,30,56
Address
Chip Enables
Write Enable
Status Pin/Flag
AS28F128J3A
Rev. 5.8 8/13
Type
Input
Description
Address Inputs during READ and WRITE Operations. A0 is only used in x8 mode and will be a NC in x16 mode.
Three Chip Enable pins for Multiple devices. See chart for function
Write Control
Reset/Power‐Down, When Low the control pin resets the status Reg.and ISM to array READ mode.
Output Enable control enable data output buffers when Low, and when High the output buffers are disabled
Configuration Control pin. When High the device is in x16 mode, when Low the device is in Byte mode (x8)
Necessary Voltage pin for Programming, Erasing or configuring lock bits. Typically connected to VCC. When VPEN</=VPENLK, this
enables Hardware Write Protect.
Indicates the status of the ISM. When configured in level mode, STS acts as a RY/BY\ pin. When configured in its pulse mode, it can
pulse to indicate PROGRAM and or ERASE completion.
Separate/Isolated Voltage supply for Input/Output bus. Allows
voltage matching to different interface standards.
Power Supply: 2.7V‐3.6V
Ground
No electrical connection or function
Micross Components reserves the right to change products or specifications without notice.
3
PEM
AS28F128J3A
Q-Flash
Bus Operations
Mode
Read Array
Output Disable
Standby
Reset/Power‐Down
Read Identifier Codes
Read Query
Read Status (ISM off)
Read Status (ISM on)
Write
RP\
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
CE0
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
CE1
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
CE2
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
OE\
VIL
VIH
X
X
VIL
VIL
VIL
VIL
VIH
WE\
VIH
VHI
X
X
VIH
VIH
VIH
VIH
VIL
VPEN
X
X
X
X
X
X
X
X
VPENH
DQ
Dout
High‐Z
High‐Z
High‐Z
Notes
1,2,3
4
5
Dout
Din
3,6,7
Address
X
X
X
X
See Table 31 of Numonyx DS
See CFI Query of Numonyx DS
X
X
X
STS Default Mode
High‐Z (VOH with External PU)
X
X
High‐Z (VOH with External PU)
High‐Z (VOH with External PU)
High‐Z (VOH with External PU)
X
X
X
Notes
1 Refer to DC Characteristics. When VPEN</= VPENLK, memory contents can be read but not altered
2 X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages
3 In default mode, STA is VOL when the ISM is executing internal Block Erase, Program, or lock bit configuration algorithms. It is VOH when the ISM is not busy, in block erase suspend
mode, program suspend mode, or reset/power-down mode.
4 See Read Identifier codes of the Numonyx Datasheet (DS)
5 See Read Query Mode Command section of the Numonyx Datasheet (DS)
6 Command Writes involving block erase, program, or lock bit configuration are reliably executed when VPEN=VPENH and VCC is within Specification
7 Refer to Table 19 on page 35 of the Numonyx Datasheet (DS)
DC Electrical Characteristics
(TA=Min/Max temperatures of Operational Range chosen)
2.7 ‐ 3.6V
VCCQ
Symbol
VCC
Parameter
Typ
2.7 ‐ 3.6V
Max
Test Conditions
Units
ILI
Input and V PEN Load Current
‐ ±1
µA
VCC = VCC Max; V CCQ = VCCQ Max
VIN = VCCQ or VSS
ILO
Output Leakage Current
‐ ±10
µA
VCC = VCC Max; V CCQ = VCCQ Max
VIN = VCCQ or VSS
50
400
µA
CMOS Inputs, V CC = VCC Max; V CCQ =
VCCQ Max, Device is disabled,
RP# = VCCQ ± 0.2 V
ICCS
ICCD
ICCR
VCC Standby Current
VCC Power‐Down Current
VCC Program or Set Lock‐Bit Current
ICCE
VCC Block Erase or V CC Blank Check or
Clear Block Lock‐Bits Current
ICCWS
ICCES
2
mA
50
400
µA
RP# = VSS ± 0.2 V, I OUT (STS) = 0 mA
15
20
mA
CMOS Inputs, V CC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads. Device is enabled. f = 5 MHz, I OUT = 0 mA
8‐Word Page
ICCW
ICCBC
0.71
TTL Inputs, V CC = VCC Max,
VCCQ = VCCQ Max, Device is disabled, RP# = V IH
VCC Program Suspend or Block Erase
Suspend Current
30
54
mA
35
60
mA
CMOS Inputs, V CC = VCC Max, VCCQ = VCCQ
Max using standard 8 word page mode
reads. Device is enabled. f = 33 MHz, I OUT = 0 mA
CMOS Inputs, V PEN = VCC
40
70
mA
TTL Inputs, V PEN = VCC
35
70
mA
CMOS Inputs, V PEN = VCC
40
80
mA
TTL Inputs, V PEN = VCC
‐
10
mA
Device is enabled
Notes
1
1
1,2,3
1,3
1,4
1,4
1,5
Notes
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or VSS ± 0.2 V. TTL inputs are either VIL or VIH.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the
device’s current draw is ICCR and ICCWS.
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
4
PEM
AS28F128J3A
Q-Flash
DC Voltage specifications
2.7 ‐ 3.6V
VCCQ
Symbol
VIL
VCC
Parameter
Input Low Voltage
Min
‐0.5
2.7 ‐ 3.6V
Max
0.8
Units
V
Test Conditions
Notes
‐ 2,5,6
VIH
Input High Voltage
2.0
VCCQ+0.5
V
‐ 2,5,6
‐ 0.4
V
VCC = VCCMin
VCCQ = VCCQ Min
IOL = 2 mA
V
VCC = VCCMin
VCCQ = VCCQ Min
IOL = 100 µA
VOL
VOH
VPENLK
VPENH
VLKO
Output Low Voltage
‐ 0.2
0.85 × VCCQ
‐ Output High Voltage
VPEN Lockout during Program,
Erase and Lock‐Bit Operations
VPEN during Block Erase, Program,
or Lock‐Bit Operations
VCC Lockout Voltage
V
1,2
VCC = VCCMin
VCCQ = VCCQ Min
IOH = 2.5 mA
1,2
VCC = VCCMin
VCCQ = VCCQ Min
IOH = 100 µA
VCCQ – 0.2
‐ ‐ 2.2
V
‐ 2,3
2.7
3.6
V
‐ 3
‐ 2.0
V
‐ 4
Notes
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min),
and above VPENH (max).
4. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above
VCC (max).
5. Includes all operational modes of the device.
6. Input/Output signals can undershoot to -1.0V referenced to VSS and can overshoot to VCCQ + 1.0V for duration of 2ns or less, the VCCQ valid range is referenced to VSS.
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
5
PEM
AS28F128J3A
Q-Flash
Read Operations
#
R1
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
Sym
Parameter
Min
Max
Unit
tAVAV
Read/Write Cycle Time
115
‐ ns
R2
tAVQV
Address to Output Delay
115
‐ ns
1,2
R3
tELQV
CEX to Output Delay
115
‐ ns
1,2
R4
tGLQV
OE# to Non‐Array Output Delay
‐ 50
ns
1,2,4
R5
tPHQV
RP# High to Output Delay
‐ 210
ns
1,2
R6
tELQX
CEX to Output in Low Z
0
‐
ns
1,2,5
R7
tGLQX
OE# to Output in Low Z
0
‐
ns
1,2,5
R8
tEHQZ
CEX High to Output in High Z
‐
25
ns
1,2,5
R9
tGHQZ
OE# High to Output in High Z
‐
15
ns
1,2,5
R10
tOH
Output Hold from Address, CEX, or OE# Change, Whichever Occurs First
0
‐
ns
1,2,5
R11
tELFL/tELFH
CEX Low to BYTE# High or Low
‐
10
ns
1,2,5
R12
tFLQV/tFHQV
BYTE# to Output Delay
‐
1
ns
1,2
R13
tFLQZ
BYTE# to Output in High Z
‐
1
µs
1,2,5
R14
tEHEL
CEx High to CEx Low
0
‐
µs
1,2,5
R15
tAPA
Page Address Access Time
‐
25
ns
5,6
R16
tGLQV
OE# to Array Output Delay
‐
25
ns
1,2,4
Notes
1,2
Notes
1. CEX low is defined as the combination of pins CE0, CE1 and CE2 that enable the device. CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable
the device
2. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX
4. See Figure 13, “AC Input/Output Reference Waveform” , “Transient Equivalent Testing Load Circuit” for testing characteristics.
5. Sampled, not 100% tested.
6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
6
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
PEM
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Figure 8:
AS28F128J3A
Q-Flash
Single-Word Asynchronous Read Waveform
Single-Word
Read
Waveform
Figure 8: Asynchronous
Single-Word
Asynchronous
Read Waveform
R1
R1
R2
Address [A]
R2
Address [A]
R8
R3
CEx [E]
R8
R3
R4
CEx [E]
OE # [G]
R9
R4
OE # [G]
WE# [W]
R7
WE# [W]
R10
R7
R6
R10
R6
DQ[15:0] [Q]
R9
DQ[15:0] [Q]
R13
R11
R12
R11
BYTE# [F]
BYTE# [F]
R13
R12
R5
RP# [P ]
R5
RP# [P ]
Notes:
1.
CE low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE high is defined as the
X
X
Notes
Notes:
combination
of
pins CE0,
CE1,CE0,
andCE1,
CE2and
that
disable
the device
(see Table
17,
“Chip
Enable
Truth
Table
for
32-that disable
1. CEX
defined
combination
of pins
CE2
that
enable
device.
is defined
as the combination
CE0,
CE1,
and CE2
lowasisthe
defined
as the
combination
of pins
CE0,
CE1,the
and
CE2CEX
thathigh
enable
the device.
CEX highofispins
defined
as the
1. low is CE
X
64-, 128-Mb”
on page 30).
the device ,combination
of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 32When
flashtGLQV
a faster
t For non-array
(R16) applies.
For
non-array
reads,
R4 applies
(i.e.,
Status
Register
reads,
2. 2.
When reading
the reading
flash
arraythe
a faster
(R16)
applies.
reads, R4
applies
(i.e., Status
Register
reads,query
reads,
or device
identifier
reads).
, 64-,
128-Mb”
on array
page
30
). GLQV
2.
query reads, or device identifier reads).
When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
query reads, or device identifier reads).
8-Word
Asynchronous
Mode Read Page Mode Read
Figure
9: 8-WordPage
Asynchronous
Figure 9:
8-Word Asynchronous Page Mode Read
R1
R1
R2
A[MAX :4] [A]
R2
A[MAX :4] [A]
000
A [3:1] [A]
A [3:1] [A]
CEx [E]
R7
WE# [W]
RP# [P]
110
111
111
R4
OE # [G]
WE# [W]
DQ[15:0] [Q]
110
001
R3
R4
CEx [E]
OE # [G]
DQ[15:0] [Q]
001
R3000
R6
R6
R5
R10
R10R15
2
R15
R7
1
1
2
R8
R10
7
7
R10
8
R9
R8
R9
8
R5
RP# [P]
BYTE # [F]
BYTE # [F]
Notes
Notes:
1. 1.
CEX low isCE
defined
combination
of pins
CE0, CE1, of
andpins
CE2CE0,
that enable
device.
is defined
as the combination
CE0, CE1,
and CE2 that disable
isthe
defined
as the
combination
CE1, the
and
CE2 CEX
that high
enable
the device.
CEX high of
ispins
defined
as the
X lowas
Notes:
the device combination of pins CE0, CE1, and CE2 that disable the device (see Table 17, “Chip Enable Truth Table for 321.
CE
low
is
defined
as
the
combination
of
pins
CE0,
CE1,
and
CE2
that
enable
the
device.
CE
high
is
defined
as
the
X
X
2. In this diagram,
BYTE#
is assertedon
high.page 30).
, 64-,
128-Mb”
2.
2.
combination of pins CE0, CE1, and CE2 that disable the device (see
In this diagram, BYTE# is asserted high.
, 64-, 128-Mb” on page 30).
In this diagram, BYTE# is asserted high.
March 2010
208032-02
March 2010
AS28F128J3A
208032-02
Rev. 5.8 8/13
7
Table 17, “Chip Enable Truth Table for 32-
Datasheet
25
Datasheet
Micross Components reserves the right to change products or specifications without notice.
25
PEM
AS28F128J3A
Q-Flash
Write Operations
#
W1
Symbol
tPHWL (tPHEL)
Parameter
RP# High Recovery to WE# (CEX) Going Low
Valid for all speeds
Min
Max
210
‐
Unit
Notes
W2
tELWL (tWLEL)
CEx (WE#) Low to WE# (CEx) Going Low
0
1,2,3,5
W3
tWP
Write Pulse Width
60
1,2,3,5
W4
tDVWH (tDVEH)
Data Setup to WE# (CEx) Going High
50
1,2,3,6
W5
tAVWH (tAVEH)
Address Setup to WE# (CEx) Going High
55
1,2,3,6
W6
tWHEH (tEHWH)
CEx (WE#) Hold from WE# (CEx) High
0
1,2,3
W7
tWHDX (tEHDX)
Data Hold from WE# (CEx) High
0
W8
tWHAX (tEHAX)
Address Hold from WE# (CEx) High
0
W9
tWPH
Write Pulse Width High
30
1,2,3,7
W11
tVPWH (tVPEH)
VPEN Setup to WE# (CEx) Going High
0
1,2,3,4
W12
tWHGL (tEHGL)
Write Recovery before Read
35
1,2,3,8
W13
tWHRL (tEHRL)
WE# (CEx) High to STS Going Low
‐ W15
tQVVL
VPEN Hold from Valid SRD, STS Going High
0
ns
500
1,2,3
1,2,3
1,2,3,9
1,2,3,4,9,1
0
Notes
1. CEX low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CEX high is defined as the combination of pins CE0, CE1, and CE2 that disable
the device
2. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics–
Read-Only Operations.
3. A write operation can be initiated and terminated with either CEX or WE#.
4. Sampled, not 100% tested.
5. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH =
tELEH = tWLEH = tELWH.
6. Refer to Table 18, “Enhanced Configuration Register” on page 32 for valid AIN and DIN for block erase, program, or lock-bit configuration.
7. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH =
tWHWL = tEHEL = tWHEL = tEHWL.
8. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
9. STS timings are based on STS configured in its RY/BY# default mode.
10. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1] = 0).
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
8
PEM
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
AS28F128J3A
Q-Flash
Asynchronous Write Waveform
Figure 10: Asynchronous Write Waveform
Figure 10: Asynchronous Write Waveform
W5
W5
Address [A]
Address [A]
W8
W8
W6
W6
CEx (WE#) [E (W)]
CEx (WE#) [E (W)]
W2
W2
WE# (CEx) [W (E)]
WE# (CEx) [W (E)]
W3
W3
W9
W9
OE# [G]
OE# [G]
W4
W4 D
D
DATA [D/Q ]
DATA [D/Q ]
W7
W7
W13
W13
STS [R]
STS [R]
RP# [P]
RP# [P]
W1
W1
W11
W11
VPEN [V]
VPEN [V]
Asynchronous
Write to Read Waveform
Figure 11: Asynchronous
Write to Read Waveform
Figure 11: Asynchronous Write to Read Waveform
W5
W5
Address [A]
Address [A]
W8
W8
W6
W6
CEx [E]
CEx [E]
W2
W2
WE# [W]
WE# [W]
W3
W3
W12
W12
OE # [G]
OE # [G]
DATA [D/Q]
DATA [D/Q]
RP# [P]
RP# [P]
W4
W4
March
2010
208032-02
208032-02
W7
W7
W1
W1
W11
W11
VPEN [V ]
VPEN [V ]
AS28F128J3A
Rev. 5.8
8/13
March
2010
D
D
Micross Components reserves the right to change products or specifications without notice.
9
Datasheet
Datasheet
27
27
PEM
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.2
AS28F128J3A
Q-Flash
Program, Erase, Block-Lock Specifications
Configuration Performance
#
W200
Parameter
Single word
Symbol
tPROG/W Program Time
Typ
40
Table 13: Configuration Performance
#
Symbol
W200
tPROG/W
tPROG
W250
t
W501
Buffer Program Time
Aligned 16 Words BP Time (32Byte)Typ
Single
word
40
Aligned 256 Words BP Time (512Byte)
Block Erase Time
Aligned 16 Words BP Time (32Byte)
Set Lock‐Bit Time
Aligned 256 Words BP Time (512Byte)
Program Time
ERS/AB Buffer Program Time
tPROG
W250
Parameter
Max
175
128
128
175
720
654
1.0
Unit
654
µs
3600
µs
4.0
µs Notes
1,2,3,4,5,6
µs1,2,3,4,6
1,2,3,4,5,6
1,2,3,4,5,6
sec
1,2,3,4,6
1,2,3,4,5,6
µs
1,2,3,4,6
720
3600
50
60µs
tERS/AB
Block Erase Time
1.0
4.0
sec
W650
tlks
Set Lock-Bit Time
50
60
W651
tlkc
Clear Block Lock-Bits Time
0.5
1
W600
tSUSP/P
Program Suspend Latency Time to Read
15
W601
tSUSP/E
Erase Suspend Latency Time to Read
15
W602
STS
tERS/SUSP
tlks
tlkc
W651
tSUSP/P
W600
tSUSP/E
W601
Clear Block Lock‐Bits Time
Program Suspend Latency Time to Read
Erase Suspend Latency Time to Read
tERS/SUSP Erase to Suspend
W602
t
W652
tBC/MB
tSTS
W702
W652
STS Pulse Width Low Time
Erase to Suspend
blank check
STS
Pulse Width Low Time
Array Block
Notes
1,2,3,4,6
Max
W501
W650
Unit
µs
1,2,3,4,6
0.5
1
sec
1,2,3,4,6
15
20
µs
1,2,3,6
15
20
µs
500
‐
µs
500
500
—
‐µs
ns
500
3.2
—
‐ns
ms
20
20
µs
sec
µs
µs
1,2,3,4,6
1,2,3,4,6
1,2,3,6
1,2,3,6
1,2,3,6
1,7
1
1,7
1
‐ Notes
W702
tBC/MB
blank check
Array Block
3.2
—
ms
—
1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization.
Notes:
2. These
performance numbers are valid for all speed versions.
1.
Typical
values
measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
3. Sampled
but
not 100%
tested.
change based
on device characterization.
4. Excludes system-level
overhead.
2. values
These
performance
numbers
arethe
valid
all speed
versions.
5. These
are valid
when the buffer
is full, and
start for
address
is aligned.
3. valuesSampled
butatnot
100%
6. Max
are measured
worst
case tested.
temperature, data pattern and VCC corner within 100K cycles. But for W650, W651, W600 and W601, the Max value are expressed
4. °C or -40
Excludes
system-level overhead.
at +25
°C.
5. is theThese
are valid
when
buffer
is full,
andcommand
the start
address
is aligned.
7. W602
typical values
time between
an initial
blockthe
erase
or erase
resume
and
then a subsequent
erase suspend command. Violating the specification repeatedly
6. any particular
Max values
are measured
at worst
case temperature, data pattern and VCC corner within 100K cycles. But for W650, W651,
during
block erase
may cause erase
failures.
7.
W600 and W601, the Max value are expressed at +25 °C or -40 °C.
W602 is the typical time between an initial block erase or erase resume command and then a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
7.3
Reset Specifications
AC Waveform for Reset Operation
Figure 12: AC Waveform for Reset Operation
STS (R)
P1
P2
RP# (P)
P3
Vcc
Note:
STS is shown in its default mode (RY/BY#).
AS28F128J3A
Datasheet
Rev. 28
5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
10
March 2010
208032-02
PEM
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
AS28F128J3A
Q-Flash
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Reset
Specifications
Table
14: Reset Specifications
Symbol
## 14:
Symbol
Table
Reset Specifications
#
P1
Symbol
tPLPH
P1
P2
tPLPH
tPHRH
P1
Min
Parameter
RP#
is asserted during block erase,
RP# is asserted during block erase,
RP#
Pulse Low Time
RP# Pulse Low Time
program or lock-bit configuration
(If RP# is tied to VCC, this Parameter
program or lock‐bit configuration
operation
(If RP# is tied to VCC, this
specification
is not
RP#
is asserted during block erase,
operation
RP#
Pulse
Low
Time
applicable)
specification is not
RP# isorasserted
during
read
program
lock-bit
configuration
(If RP# is tied to VCC, this
operation
RP# is asserted during read
applicable)
specification
is
not
RP# High to Reset during Block Erase, Program, or Lock-Bit
applicable)
Configuration
RP# High to Reset during Block Erase, Program, or Lock‐Bit
RP# is asserted during read
tPLPH
tPHRH
P2
Parameter
Min
Min
25
100
25
—
100
Max
—
25
100
‐ Max
—
—
100
—
Unit
Max
Unit
µs
‐
‐
ns
µs
ns
ns
100
Notes
Unit
Notes
1
µs
1
11
ns
1
ns
1,2
1,2
1
Configuration
P3
tVCCPH
Vcc
Power
to during
RP# de-assertion
60
—
µs
—
RP#
High toValid
Reset
Block Erase,(high)
Program, or Lock-Bit
P2
tPHRH
—
100
ns
1,2
Configuration
t
60
‐
µs
P3
Vcc Power Valid to RP# de‐assertion (high)
VCCPH
Notes:
1.P3
These
valid
allde-assertion
product versions
tVCCPHspecifications
Vcc Powerare
Valid
to for
RP#
(high)(packages and speeds).
60
—
µs
—
Notes2.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
1. These
specifications are valid for all product versions (packages and speeds).
Notes:
2. A reset
tPHQV,specifications
is required from the
of for
STSall
(inproduct
RY/BY# mode)
or RP#
going highand
until speeds).
outputs are valid.
1. time,These
arelatter
valid
versions
(packages
2.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
7.4
Notes
‐ AC Test Conditions
AC Input/Output Reference Waveform
7.4
AC
Test Conditions
Figure 13: AC
Input/Output
Reference Waveform
Figure 13: AC Input/Output
Reference Waveform
V
CCQ
Note:
Input VCCQ/2
VCCQ
0.0
Input VCCQ/2
Test Points
VCCQ/2
Output
Test Points
VCCQ/2
Output
AC test inputs are
0.0driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Notes
AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times
(10% to 90%) < 5 ns.
Note:
test Transient
inputs are driven
at VCCQ for a Testing
Logic "1" and
0.0 VCircuit
for a Logic "0." Input timing begins, and output timing ends, at
FigureAC14:
Equivalent
Load
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Transient
Testing
Load Circuit
Figure Equivalent
14: Transient
Equivalent
Testing Load Circuit
Device
Under Test
Device
Under Test
Note:
CL
CL
Out
Out
CL Includes Jig Capacitance
TableC15:
Test Configuration
Note:
L Includes Jig Capacitance
Test Configuration
CL (pF)
Table 15: Test Configuration
Test Configuration
30
VCCQ = VCCQMIN
Test Configuration
VCCQ = VCCQMIN
Test Configuration
VCCQ = VCCQMIN
CL (pF)
CL (pF)
30
March 2010
AS28F128J3A
208032-02
Rev. 5.8 8/13
March 2010
208032-02
30
Datasheet
29
Micross Components reserves the right to change products or specifications without notice.
11
Datasheet
29
PEM
AS28F128J3A
Q-Flash
Memory Command Set Operations
Command
READ ARRAY
READ IDENTIFIER CODES
READ QUERY
READ STATUS REGISTER
CLEAR STATUS REGISTER
WRITE TO BUFFER
WORD/BYTE PROGRAM
BLOCK ERASE
BLOCK ERASE/PROGRAM SUSPEND
BLOCK ERASE/PROGRAM RESUME
CONFIGURATION
SET BLOCK LOCK BITS
CLEAR BLOCK LOCK BITS
PROTECTION PROGRAM
First Bus Cycle
Second Bus Cycle
Scalable or Basic Command Set [SCS or BCS]
Bus Cycles Operation Address
Data
Operation Address
SCS/BCS
1
WRITE
X
FFh
SCS/BCS
>/=2
WRITE
X
90h
READ
IA
SCS WRITE
X
98h
READ
QA
SCS/BCS
2
WRITE
X
70h
READ
X
SCS/BCS
1
WRITE
X
50h
SCS/BCS
>2
WRITE
BA
E8h
WRITE
BA
SCS/BCS
2
WRITE
X
40h or 10h
WRITE
PA
SCS/BCS
2
WRITE
BA
20h
WRITE
BA
SCS/BCS
1
WRITE
X
B0h
SCS/BCS
1
WRITE
X
D0h
SCS
2
WRITE
X
B8h
WRITE
X
SCS
2
WRITE
X
60h
WRITE
BA
SCS
2
WRITE
X
60h
WRITE
X
2
WRITE
X
C0h
WRITE
PA
Data
Notes
ID
QD
SRD
1
N
PD
D0h
3,4,5
6,7
5,6
7,8
7
CC
01h
D0h
PD
Key:
[IA] [ID] [BA] [QA] [PA] [QD] [SRD] Identifier Code address
Data read from identifier Code
Address within a Block
Query data base Address
Address of Memory location to be programmed
Data read from Query data base
Data read from Status Register
Notes
[1] [2] [3] [4] [5]
[6] [7] [8] Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes.
If the ISM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 are placed in High-Z
After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for WRITING
The number of Bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. Count ranges on this device for byte mode are n=00H to n=1Fh and for word mode, n=0000h to 000Fh. The third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command (D0h) is expected after exactly n+1 WRITE cycles; any other command at that point in the sequence aborts the WRITE-to-BUFFER operation.
The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued
Attempts to issue a BLOCK ERASE or PROGRAM to a locked block will fail
Either 40h or 10h is recognized by the ISM as the byte/word program setup
PROGRAM SUSPEND can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.
AS28F128J3A
Rev. 5.8 8/13
2
Micross Components reserves the right to change products or specifications without notice.
12
PEM
PEM
AS28F128J3M
AS28F128J3A
Q-Flash
Q-Flash
Austin Semiconductor, Inc.
Mechanical Diagram
Mechanical
Diagram
TSOP, Type
1, 56 Pin
TSOP,
Type I, 56inPin
(Dimensions
mm)
(Dimensions in mm)
20.00 +/- 0.25
18.40 +/- 0.08
14.00 +/- 0.08
0.50 TYP.
0.20 +/- 0.05
0.25
0.15 +0.03, -0.02
0.10
1.20 MAX.
SEE DETAIL A
0.25 Gage Plane
0.10 + 0.10, -0.05
DETAIL A
0.50 +/- 0.10
0.80 TYP.
AS28F128J3MRG
AS28F128J3A
Revision
5.0 8/13
11/23/04
Rev. 5.8
Austin Semiconductor, Inc. reserves the right to change products
or modifyreserves
product
specifications
with
appropriate
notification
Micross Components
the right
to change products
or specifications
without
notice.
For Additional Products and Information visit 13
out Web site at www.austinsemiconductor.com
7
PEM
PEM
AS28F128J3A
AS28F128J3M
Q-Flash
Q-Flash
Austin Semiconductor, Inc.
Mechanical Diagram
PBGA, 10mm x 13mm, 64 Ball w/ 1.00 Pitch
Mechanical
Diagram
(Dimensions
in mm)
PBGA, 10mm x 13mm, 64 Ball w/1.00mm Pitch
(Dimensions in mm)
0.85 +/-0.075
C
0.10 C
Ball A1
Ball A1 ID
7.00
Seating Plane
(Bottom View)
Alt. Ball A1 ID
Ball A1 Corner ID
1.00 Typ.
6.50 +/-0.05
XT
3.50 +/-0.05
OEU86
13.00 +/-0.10
AS28F128J3APBG-15
LOT CODE
DATE CODE
7.00
1.20 Max.
10.00 +/-0.10
x64 @ 0.45 diameter, post reflow
Solder Ball Material: 62% Sn., 36% Pb., 2% Ag.
ASI Ordering Information
Ordering Information
Part Number
Configuration
Speed (ns)
o
o
C to +105
C)
Enhanced Operating Range (‐40
ASI Part Number
Configuration
0
Pkg.
Speed
(ns)
Pkg.
115
TSOP1-56
128Mb, x8/x16 Q-Flash
Consult Factory, MOQ's Apply
AS28F128J3APBG‐15/ET
128Mb, x8/x16 Q‐Flash
115
FBGA‐64
128Mb, x8/x16 Q-Flash
115
FBGA-64
AS28F128J3MPBG-15/ET
Extended Operating Range (‐550C to +1250C)
Extended Operating Range (-550C to +1250C)
AS28F128J3ARG‐15/XT
128Mb, x8/x16 Q‐Flash
AS28F128J3MRG-15/XT
115
TSOP1‐56
128Mb, x8/x16 Q-Flash
115
Consult Factory, MOQ's
Apply
TSOP1-56
Consult Factory, AS28F128J3APBG‐15/XT
128Mb, x8/x16 Q‐Flash
115Q-Flash
FBGA‐64 MOQ's Apply
AS28F128J3MPBG-15/XT
128Mb, x8/x16
115
FBGA-64
AS28F128J3A
Rev. 5.8 8/13
AS28F128J3MRG
Revision 5.0 11/23/04
Comments
0
Enhanced Operating
Range (-40 C to 115
+105 C)TSOP1‐56
AS28F128J3ARG‐15/ET
128Mb, x8/x16 Q‐Flash
AS28F128J3MRG-15/ET
Comments
Consult Factory, MOQ's
Apply
Micross Components reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc. reserves the right14
to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
8
PEM
AS28F128J3A
Q-Flash
DOCUMENT TITLE
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture
REVISION HISTORY
Rev #
HistoryRelease Date
5.5
Updated with Numonyx Info
March 2009
Status
Release
5.6
Added Micross Information
March 2010
Release
5.7
Updated DC Electrical Characteristics May 2011
table, added DC Voltage Characteristics
table, Added read operations table, added
single word asych read waveform, added
8-word asych page mode read diagram,
added write operations table, added asynch
write waveform diagram, added asynch write
to read waveform diagram, added config
performance table, added ac waveform for
reset operation diagram, added reset
specifications table, added ac test conditions,
changed reference to Numonyx J3-65nm device
datasheet dated March 2010, page 1
Release
5.8
Updated DC Electrical Characteristics August 2013
Release
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
15