MYXN25Q512 Serial NOR Flash Memory

Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
512Mb, 3V, Multiple I/O, 4KB Sector Erase
Features
• Single die erase
• Write protection
• Tin-lead ball metallurgy
ƒƒ Software write protection applicable to every 64KB
sector via volatile lock bit
• Stacked device (two 256Mb die)
• SPI-compatible serial bus interface
ƒƒ Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2, BP3,
and TB)
• Double transfer rate (DTR) mode
• 2.7–3.6V single supply voltage
• 108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
ƒƒ Additional smart protections, available upon request
• Electronic signature
• 54 MHz (MAX) clock frequency supported for all protocols
in DTR mode
ƒƒ JEDEC-standard 2-byte signature (BA20h)
• Dual/quad I/O instruction provides increased throughput
up to 54 MB/s
ƒƒ Unique ID code (UID): 17 read-only bytes, including:
Two additional extended device ID bytes to identify
device factory options; and customized factory data
(14 bytes)
• Supported protocols
ƒƒ Extended SPI, dual I/O, and quad I/O
ƒƒ DTR mode supported on all
• Minimum 100,000 ERASE cycles per sector
• Execute-in-place (XIP) mode for all three protocols
• More than 20 years data retention
ƒƒ Configurable via volatile or nonvolatile registers
ƒƒ Enables memory to work in XIP mode directly after
power-on
OptionsCode
• PROGRAM/ERASE SUSPEND operations
• Packages
• Available protocols
ƒƒ T-PBGA-24b05/6mm x 8mm
(also known as TBGA25), with
Sn63/Pb37 ball metallurgy
ƒƒ Available READ operations
ƒƒ Quad or dual output fast read
ƒƒ Quad or dual I/O fast read
• Flexible to fit application
12
• Temperature Ranges
ƒƒ Configurable number of dummy cycles
ƒƒ Industrial (-40°C to 85°C)
ƒƒ Output buffer configurable
• Software reset
• 3-byte and 4-byte addressability mode supported
IT
ƒƒ Automotive (-40°C to 125°C)
AT
ƒƒ Military (-55°C to +125°C)
XT
• 64-byte, user-lockable, one-time programmable (OTP)
dedicated area
• Erase capability
ƒƒ Subsector erase 4KB uniform granularity blocks
ƒƒ Sector erase 64KB uniform granularity blocks
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
1
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Contents
1
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
3-Byte Address and 4-Byte Address Modes . . . . . . . . . . 3
1.3
Operating Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4
XIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5
Device Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Memory Configuration and Block Diagram . . . . . . . . . . . 7
4
Memory Map – 512Mb Density . . . . . . . . . . . . . . . . . . . 9
5
Serial Peripheral Interface Modes . . . . . . . . . . . . . . . . 10
6
SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Nonvolatile and Volatile Registers . . . . . . . . . . . . . . . 13
7.1
Extended Address Register . . . . . . . . . . . . . . . . . . . . . 14
8
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 15
9
RESET Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
9.1
RESET ENABLE and RESET MEMORY Command . . . . . . 17
9.2
RESET Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10
ADDRESS MODE Operations:
Enter and Exit 4-Byte Address Mode . . . . . . . . . . . . . 18
11
Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . 19
11.1
Power-Up and Power-Down Requirements . . . . . . . . . . 19
11.2
Power Loss Recovery Sequence . . . . . . . . . . . . . . . . . 20
12
AC Reset Specifications . . . . . . . . . . . . . . . . . . . . . . . . 21
13
Absolute Ratings and Operating Conditions . . . . . . . . 24
14
DC Characteristics and Operating Conditions . . . . . . 26
15
AC Characteristics and Operating Conditions . . . . . . 27
16
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
2
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
1
Device Description
The MYXN25Q512A13G12 is a high-performance multiple input/output serial Flash memory device
manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionality, advanced write
protection mechanisms, and a high-speed SPI-compatible bus interface. Innovative, high-performance,
dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and
PROGRAM operations.
1.1
Features
The 512Mb MYXN25Q512A13G12 stacked device contains two 256Mb die. From a user standpoint this
stacked device behaves as a monolithic device, except with regard to READ MEMORY and ERASE operations
and status polling.
The memory is organized as 1024 (64KB) main sectors that are further divided into 16 subsectors each (16,384
subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or single
die (256Mb) at a time.
The memory can be write protected by software through volatile and nonvolatile protection features, depending
on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections.
The device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP
and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP
command.
The device can also pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE
SUSPEND and RESUME instructions.
1.2
3-Byte Address and 4-Byte Address Modes
The device features 3-byte or 4-byte address modes to access memory beyond 128Mb.
When 4-byte address mode is enabled, all commands requiring an address must be entered and exited with a
4-byte address mode command: ENTER 4-BYTE ADDRESS MODE command and EXIT 4-BYTE ADDRESS
MODE command. The 4-byte address mode can also be enabled through the nonvolatile configuration register.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
3
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
1.3
Operating Protocols
The memory can be operated with three different protocols:
• Extended SPI (standard SPI protocol upgraded with dual and quad operations)
• Dual I/O SPI
• Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI
and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting
commands, addresses, and data across two or four data lines.
Each protocol contains unique commands to perform READ operations in DTR mode. This enables high data
throughput while running at lower clock frequencies.
1.4
XIP Mode
Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then
receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode
offers maximum flexibility to the application, saves instruction overhead, and reduces random access time.
XIP mode requires only an address (no instruction) to output data, improving random access time and
eliminating the need to shadow code onto RAM for fast execution.
Nonvolatile configuration register bits can set XIP mode as the default mode for applications that must enter XIP
mode immediately after powering up.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available.
1.5
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile configuration register
for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatileenhanced configuration registers. These configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, dual SPI, or quad SPI)
• Required XIP mode
• Enabling/disabling HOLD
• Enabling/disabling wrap mode
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
4
Form #: CSI-D-685 Document 002
•
•
•
•
SPI protocol types (extended SPI, dual SPI, or quad SPI)
Required XIP mode
Enabling/disabling HOLD (RESET function)
Enabling/disabling wrap mode
Serial NOR Flash Memory
MYXN25Q512A13G12*
ogic Diagram
*Advanced information. Subject to change without notice.
Figure 1: Logic Diagram
VCC
DQ1
DQ0
C
NOR die 2
S#
NOR die 1
VPP/W#/DQ2
HOLD#/DQ3
RESET
512Mb, Multiple I/O Serial Flash Memory
Signal Assignments
VSS
1. Reset
functionality
is available in devices with a dedicated part number. See Part
Figure 4: Note:
TBGA
(Balls
Down)
Figure24-Ball
2: 24-Ball
TBGA
(Balls
Down)
ber Ordering Information for more details. The RESET pin is available only for pa
bers N25Q512A83G1240X and N25Q512A83GSF40X, and N25Q512A83GSFA0F. On
1
2
3
4
5
parts, the additional RESET pin must be connected to an external pull-up.
A
NC
NC
RESET/NC
NC
NC
C
VSS
VCC
NC
NC
S#
NC W#/VPP/DQ2 NC
NC
DQ1
NC
NC
B
C
D
nm.pdf - Rev. Q 11/13 EN
7
Micron Technology, Inc. reserves the right to change products or specifications
DQ0 HOLD#/DQ3 NC
© 2011 Micron Technology, Inc. All
E
Note:
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
NC
NC
NC
1. See Part Number Ordering Information for complete package names and details. Ball A4
is NC except for part numbers N25Q512A83G1240X for which it is used as a RESET pin.
5
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
2
Signal Descriptions
The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed
may not be supported on this device.
Table 1: Signal Descriptions
Symbol
Type
C
Input
Clock: Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are
latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock.
Input
Chip select: When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with
the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle
is in progress, the device enters standby power mode (not deep power-down mode). Driving S# LOW enables the
device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any
command.
Input and
I/O
Serial data: Transfers data serially into the device. It receives command codes, addresses, and the data to be
programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following
operations: DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD
INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI,
DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the
PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then
returns to QIO-SPI as soon as VPP goes LOW.
S#
DQ0
DQ1
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
Description
Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used
for input/output during the following operations: DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL
INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is
Output and
latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always
I/O
acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program
supply voltage (VPP). In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI
as soon as VPP goes LOW.
DQ2
Input and
I/O
DQ2: When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions
as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micross
recommends customers drive the data signals normally (to avoid unnecessary switching current) and float the signals
before the memory device drives data on them.
DQ3
Input and
I/O
DQ3: When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as
DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected.
6
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Symbol
Type
Description
Control
Input
HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z.
DQ0 (input) and the clock are Don't Care. To enable HOLD, the device must be selected with S# driven LOW. HOLD#
is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST
READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an
I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. The HOLD# functionality
can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the
HOLD# functionality is disabled as soon as a DTR operation is recognized.
Control
Input
Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with
single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If
voltage range is low (0V to VCC), the signal acts as a write protection control input. The memory size protected against
PROGRAM or ERASE operations is locked as specified in the status register block protect bits 3:0. W# is used as an
input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations
and in QIO-SPI.
VPP
Power
Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in
the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible
to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is
necessary to set bit 3 of the VECR to 0. In this case, VPP is used as an I/O until the end of the operation. After the
last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal
operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed.
The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled.
VCC
Power
Device core power supply: Source voltage.
VSS
Ground
Ground: Reference for the VCC supply voltage.
DNU
–
Do not use.
NC
–
No connect.
HOLD#
W#
3
Memory Organization
3.1
Memory Configuration and Block Diagram
The memory is a stacked device comprised of two 256Mb chips. Each chip is internally partitioned into two
128Mb segments. Each page of memory can be individually programmed. Bits are programmed from one
through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are
erased from zero through one. The memory is configured as 67,108,864 bytes (8 bits each); 1024 sectors
(64KB each); 16,384 subsectors (4KB each); and 262,144 pages (256 bytes each); and 64 OTP bytes are
located outside the main memory array.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
7
Form #: CSI-D-685 Document 002
Memory Configuration and Block Diagram
The memory is a stacked device comprised of two 256Mb chips. Each chip is internally
partitioned into two 128Mb segments. Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector,
or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through
one. The memory is configured as 67,108,864 bytes (8 bits each); 1024 sectors (64KB
each); 16,384 subsectors (4KB each); and 262,144 pages (256 bytes each); and 64 OTP
bytes are located outside the main memory array.
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Figure 5: Block Diagram
Figure 3: Block Diagram
HOLD#
W#/VPP
High voltage
generator
Control logic
64 OTP bytes
S#
C
DQ0
DQ1
DQ2
DQ3
I/O shift register
Status
register
256 byte
data buffer
Address register
and counter
Y decoder
03FFFFFFh
0000000h
00000FFh
256 bytes (page size)
X decoder
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. Q 11/13 EN
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
8
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
4
Memory Map – 512Mb Density
Table 2: Sectors[1023:0]
Sector
1023
⋮
511
⋮
255
⋮
127
⋮
63
⋮
0
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
Subsector
Address Range
Start
End
16383
03FF F000h
03FF FFFFh
⋮
⋮
⋮
16368
03FF 0000h
03FF 0FFFh
⋮
⋮
⋮
8191
01FF F000h
01FF FFFFh
⋮
⋮
⋮
8176
01FF 0000h
01FF 0FFFh
⋮
⋮
⋮
4095
00FF F000h
00FF FFFFh
⋮
⋮
⋮
4080
00FF 0000h
00FF 0FFFh
⋮
⋮
⋮
2047
007F F000h
007F FFFFh
⋮
⋮
⋮
2032
007F 0000h
007F 0FFFh
⋮
⋮
⋮
1023
003F F000h
003F FFFFh
⋮
⋮
⋮
1008
003F 0000h
003F 0FFFh
⋮
⋮
⋮
15
0000 F000h
0000 FFFFh
⋮
⋮
⋮
0
0000 0000h
0000 0FFFh
9
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
5
Serial Peripheral Interface Modes
The device can be driven by a microcontroller while its serial peripheral interface is in either of the two modes
shown here. The difference between the two modes is the clock polarity when the bus master is in standby
mode and not transferring data. Input data is latched in on the rising edge of the clock, and output data is
available from the falling edge of the clock.
Table 3: SPI Modes
Note 1 applies to the entire table.
SPI Modes
Clock Polarity
CPOL = 0, CPHA = 0
C remains at 0 for (CPOL = 0, CPHA = 0)
CPOL = 1, CPHA = 1
C remains at 1 for (CPOL = 1, CPHA = 1)
Note:
1. The listed SPI modes are supported in extended, dual, and quad SPI protocols.
Shown below is an example of three memory devices in extended SPI protocol in a simple connection to an
MCU on an SPI bus. Because only one device is selected at a time, that one device drives DQ1, while the other
devices are High-Z.
Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus master might enter a
state in which all input/output is High-Z simultaneously, such as when the bus master is reset. Therefore, the
serial clock must be connected to an external pull-down resistor so that S# is pulled HIGH while the serial clock
is pulled LOW. This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH is met.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
10
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
512Mb, Multiple I/O Serial Flash Memory
512Mb, Multiple
I/O SerialInterface
Flash Memory
Serial Peripheral
Modes
Serial*Advanced
Peripheral
Interface
Modes
information. Subject to change without notice.
Figure
4: Bus
Master
and Memory
Devices Devices
on the SPIon
Bus
Figure
6: Bus
Master
and Memory
the SPI Bus
Figure 6: Bus Master and Memory Devices on the SPI Bus
VSS
VSS
VCC
VCC
R
R
SDO
SDO
SDI
SDI
SCK
SCK
SPI interface:
SPI
interface:
(CPOL,
CPHA) =
(CPOL,
(0, 0)CPHA)
or (1, =1)
(0, 0) or (1, 1)
C
SPI bus master
SPI bus master
VCC
VCC
C
DQ1 DQ0
DQ1 DQ0
R
CS3
CS2 CS1
CS3
CS2 CS1
R
SPI memory
SPI memory
device
device
S#
S#
VSS
VSS
R
R
W# HOLD#
W# HOLD#
C
VCC
VCC
C
DQ1 DQ0
DQ1 DQ0
SPI memory
SPI memory
device
device
S#
S#
VSS
VSS
R
R
W# HOLD#
W# HOLD#
C
VCC
VCC
C
DQ1 DQ0
DQ1 DQ0
VSS
VSS
SPI memory
SPI memory
device
device
S#
S#
W# HOLD#
W# HOLD#
Figure 7: SPI Modes
Figure 7: SPI Modes
Figure 5: SPI Modes
CPOL CPHA
CPOL CPHA
0
1
0
1
0
1
0
C
1
C
C
C
DQ0
DQ0
MSB
MSB
DQ1
DQ1
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf
- Rev. Q 11/13 EN
PDF:
09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. Q 11/13 EN
MSB
MSB
11
17
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011products
Micron Technology,
Inc. All
rightsnotice.
reserved.
Micron Technology, Inc. reserves the right to change
or specifications
without
Form
#: CSI-D-685
© 2011 Micron Technology, Inc.
All rights
reserved. Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
6
SPI Protocols
Table 4: Extended, Dual, and Quad SPI Protocols
Protocol
Name
Command
Input
Address Input
Extended
DQ0
Multiple DQn lines,
depending on the
command
Dual
DQ[1:0]
DQ[1:0]
Data Input/Output
Description
Multiple DQn lines, Device default protocol from the factory. Additional commands
depending on the extend the standard SPI protocol and enable address or data
command
transmission on multiple DQn lines.
DQ[1:0]
Volatile selectable: When the enhanced volatile configuration
register bit 6 is set to 0 and bit 7 is set to 1, the device enters
the dual SPI protocol immediately after the WRITE ENHANCED
VOLATILE CONFIGURATION REGISTER command. The device
returns to the default protocol after the next power-on. In
addition, the device can return to default protocol using the
rescue sequence or through new WRITE ENHANCED VOLATILE
CONFIGURATION REGISTER command, without power-off or
power-on.
Nonvolatile selectable: When nonvolatile configuration register
bit 2 is set, the device enters the dual SPI protocol after the next
power-on. Once this register bit is set, the device defaults to the
dual SPI protocol after all subsequent power-on sequences until
the nonvolatile configuration register bit is reset to 1.
Quad1
DQ[3:0]
DQ[3:0]
DQ[3:0]
Volatile selectable: When the enhanced volatile configuration
register bit 7 is set to 0, the device enters the quad SPI
protocol immediately after the WRITE ENHANCED VOLATILE
CONFIGURATION REGISTER command. The device re- turns to the
default protocol after the next power-on. In addition, the device can
return to default protocol using the rescue sequence or through
new WRITE ENHANCED VOLATILE CONFIGURATION REGISTER
command, without poweroff or power-on.
Nonvolatile selectable: When nonvolatile configuration register
bit 3 is set to 0, the device enters the quad SPI protocol after the
next power-on. Once this register bit is set, the device defaults to
the quad SPI protocol after all subsequent power-on sequences
until the nonvolatile configuration register bit is reset to 1.
Note: 1. In quad SPI protocol, all command/address input and data I/O are transmitted on four lines except
during a PROGRAM and ERASE cycle performed with VPP. In this case, the device enters the extended SPI
protocol to temporarily allow the application to perform a PROGRAM/ERASE SUSPEND operation or to check
the write-in-progress bit in the status register or the program/erase controller bit in the flag status register. Then,
when VPP goes LOW, the device returns to the quad SPI protocol.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
12
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
7
Nonvolatile and Volatile Registers
The device features the following volatile and nonvolatile registers that users can access to store device
parameters and operating configurations:
512Mb, Multiple I/O Serial Flash Memory
• Status register
Nonvolatile and Volatile Registers
• Nonvolatile and volatile configuration registers
Nonvolatile and Volatile Registers
• Extended address register
The device features the following volatile and nonvolatile registers that users can access
to store deviceregister
parameters and operating configurations:
• Enhanced volatile configuration
• Flag status register• Status register
• Nonvolatile and volatile configuration registers
• Extended address register
• Enhanced volatile configuration register
Flag status
registerLOCK REGISTER Command.
Note: The lock register is• defined
in READ
• Lock register
• Lock register
The working condition of
memory
is register
set byisan
internal
configuration
registerCommand.
that is not directly accessible
Note:
The lock
defined
in READ
LOCK REGISTER
to users. As shown below,
parameters
in the
internal is
configuration
register
are loaded
fromthat
theis nonvolatile
The working
condition
of memory
set by an internal
configuration
register
not
directly
accessible
users.phase
As shown
below, parameters
in the
configuration register during
each
devicetoboot
or power-on
reset. In
thisinternal
sense,configuration
then, the nonvolatile
register are loaded from the nonvolatile configuration register during each device boot
configuration register contains
the default settings of memory.
phase or power-on reset. In this sense, then, the nonvolatile configuration register contains the default settings of memory.
Also, during the life of an application, each time a WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION
Also, during the life of an application, each time a WRITE VOLATILE or ENHANCED
REGISTER command executes
set configuration
parameters
in these
respective
registers,pathese new
VOLATILE to
CONFIGURATION
REGISTER
command
executes
to set configuration
rameters
in
these
respective
registers,
these
new
settings
are
copied
to
the
internal
consettings are copied to the internal configuration register. Therefore, memory settings can be changed in real
figuration register. Therefore, memory settings can be changed in real time. However, at
time. However, at the next
power-on reset, the memory boots according to the memory settings defined in the
the next power-on reset, the memory boots according to the memory settings defined
nonvolatile configurationinregister
parameters.
the nonvolatile
configuration register parameters.
Figure 8:
Configuration Register
Register
Figure
6: Internal
Internal Configuration
Volatile configuration register
and enhanced volatile
configuration register
Nonvolatile configuration register
Register download is executed after a
WRITE VOLATILE or ENHANCED
VOLATILE CONFIGURATION REGISTER
command, overwriting configuration
register settings on the internal
configuration register.
Register download is executed only
during the power-on phase or after
a reset, overwriting configuration
register settings on the internal
configuration register.
Internal configuration
register
Device behavior
MYXN25Q512A13G12*
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13
19
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© 2011 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
7.1
Extended Address Register
information.
Subject
to change without notice.
512Mb, Multiple*Advanced
I/O Serial
Flash
Memory
Nonvolatile and Volatile Registers
Extended Address Register
In the case of 3-byte addressability mode, the device includes an extended address register that provides a
In the case of 3-byte addressability mode, the device includes an extended address regfourthister
address
A[31:24],
enabling
access
toA[31:24],
memory beyond
128Mb.
extendedbeyond
address register bits
thatbyte
provides
a fourth
address
byte
enabling
accessThe
to memory
[1:0] are
used The
to select
one ofaddress
the four register
128Mb segments
of the
memory
array.
128Mb.
extended
bits [1:0] are
used
to select
one of the four 128Mb
segments of the memory array.
Figure 9: Upper and
Lower
Memory
Array Memory
Segments
Figure
7: Upper
and Lower
Array Segments
03FFFFFFh
A[25:24] = 11
02FFFFFFh
A[25:24] = 10
03000000h
01FFFFFFh
A[25:24] = 01
02000000h
00FFFFFFh
01000000h
A[25:24] = 00
00000000h
The PROGRAM and ERASE operations act upon the 128Mb segment selected in the extended address register.
The PROGRAM and ERASE operations act upon the 128Mb segment selected in the extended
The
READ operation begins reading in the selected 128Mb segment. It is bound by the
address
register.
256Mb (die segment) to which the 128Mb segment belongs. In a continuos read, when
the last
byte ofbegins
the diereading
segment
selected
is read,
thesegment.
next byteIt output
is by
thethe
first
byte of
The READ
operation
in the
selected
128Mb
is bound
256Mb
(die segment)
the
same
die
segment;
therefore,
a
download
of
the
whole
array
is
not
possible
with
oneselected is
to which the 128Mb segment belongs. In a continuos read, when the last byte of the die segment
READ operation. The value of the extended address register does not change when a
read, the next byte output is the first byte of the same die segment; therefore, a download of the whole array
READ operation crosses the selected 128Mb boundary.
is not possible with one READ operation. The value of the extended address register does not change when a
READ operation crosses the selected 128Mb boundary.
MYXN25Q512A13G12*
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14
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
8
Command Definitions
Table 5: Command Set
Command
Code
Extended Dual I/O
Quad I/O
Data Bytes
RESET Operations
RESET ENABLE
66h
Yes
Yes
Yes
0
RESET MEMORY
99h
Yes
Yes
Yes
0
9E/9Fh
Yes
No
No
1 to 20
MULTIPLE I/O READ ID
AFh
No
Yes
Yes
1 to 3
READ SERIAL FLASH DISCOVERY PARAMETER
5Ah
Yes
Yes
Yes
1 to ∞
IDENTIFICATION Operations
READ ID
READ Operations
READ
03h
Yes
No
No
1 to ∞
FAST READ
0Bh
Yes
Yes
Yes
1 to ∞
DUAL OUTPUT FAST READ
3Bh
Yes
Yes
No
1 to ∞
0Bh, 3Bh, BBh
Yes
Yes
No
1 to ∞
6Bh
Yes
No
Yes
1 to ∞
0Bh, 6Bh, EBh
Yes
No
Yes
1 to ∞
FAST READ – DTR
0Dh
Yes
Yes
Yes
1 to ∞
DUAL OUTPUT FAST READ – DTR
3Dh
Yes
Yes
No
1 to ∞
0Dh, 3Dh, BDh
Yes
Yes
No
1 to ∞
6Dh
Yes
No
Yes
1 to ∞
0Dh, 3Dh, EDh
Yes
No
Yes
1 to ∞
4-BYTE READ
13h
Yes
Yes
Yes
1 to ∞
4-BYTE FAST READ
0Ch
Yes
Yes
Yes
1 to ∞
4-BYTE DUAL OUTPUT FAST READ
3Ch
Yes
Yes
No
1 to ∞
4-BYTE DUAL INPUT/OUTPUT FAST READ
BCh
Yes
Yes
No
1 to ∞
4-BYTE QUAD OUTPUT FAST READ
6Ch
Yes
No
Yes
1 to ∞
4-BYTE QUAD INPUT/OUTPUT FAST READ
ECh
Yes
No
Yes
1 to ∞
DUAL INPUT/OUTPUT FAST READ
QUAD OUTPUT FAST READ
QUAD INPUT/OUTPUT FAST READ
DUAL INPUT/OUTPUT FAST READ – DTR
QUAD OUTPUT FAST READ – DTR
QUAD INPUT/OUTPUT FAST READ – DTR
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
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Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Command
Code
Extended Dual I/O
Quad I/O
Data Bytes
WRITE Operations
WRITE ENABLE
06h
Yes
Yes
Yes
0
WRITE DISABLE
04h
Yes
Yes
Yes
0
REGISTER Operations
READ STATUS REGISTER
05h
Yes
Yes
Yes
1 to ∞
WRITE STATUS REGISTER
01h
Yes
Yes
Yes
1
READ LOCK REGISTER
E8h
Yes
Yes
Yes
1 to ∞
WRITE LOCK REGISTER
E5h
Yes
Yes
Yes
1
READ FLAG STATUS REGISTER
70h
Yes
Yes
Yes
1 to ∞
CLEAR FLAG STATUS REGISTER
50h
Yes
Yes
Yes
0
READ NONVOLATILE CONFIGURATION REGISTER
B5h
Yes
Yes
Yes
2
WRITE NONVOLATILE CONFIGURATION REGISTER
B1h
Yes
Yes
Yes
2
READ VOLATILE CONFIGURATION REGISTER
85h
Yes
Yes
Yes
1 to ∞
WRITE VOLATILE CONFIGURATION REGISTER
81h
Yes
Yes
Yes
1
READ ENHANCED VOLATILE CONFIGURATION REGISTER
65h
Yes
Yes
Yes
1 to ∞
WRITE ENHANCED VOLATILE CONFIGURATION REGISTER
61h
Yes
Yes
Yes
1
READ EXTENDED ADDRESS REGISTER
C8h
Yes
Yes
Yes
0
WRITE EXTENDED ADDRESS REGISTER
C5h
Yes
Yes
Yes
0
PROGRAM Operations
PAGE PROGRAM
02h
Yes
Yes
Yes
1 to 256
DUAL INPUT FAST PROGRAM
A2h
Yes
Yes
No
1 to 256
02h, A2h, D2h
Yes
Yes
No
1 to 256
32h
Yes
No
Yes
1 to 256
02h, 32h, 12h
Yes
No
Yes
1 to 256
EXTENDED DUAL INPUT FAST PROGRAM
QUAD INPUT FAST PROGRAM
EXTENDED QUAD INPUT FAST PROGRAM
ERASE Operations
SUBSECTOR ERASE
20h
Yes
Yes
Yes
0
SECTOR ERASE
D8h
Yes
Yes
Yes
0
DIE ERASE
C4h
Yes
Yes
Yes
0
PROGRAM/ERASE RESUME
7Ah
Yes
Yes
Yes
0
PROGRAM/ERASE SUSPEND
75h
Yes
Yes
Yes
0
MYXN25Q512A13G12*
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Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Command
Code
Extended Dual I/O
Quad I/O
Data Bytes
ONE-TIME PROGRAMMABLE (OTP) Operations
READ OTP ARRAY
4Bh
Yes
Yes
Yes
1 to 64
PROGRAM OTP ARRAY
42h
Yes
Yes
Yes
1 to 64
4-BYTE ADDRESS MODE Operations
ENTER 4-BYTE ADDRESS MODE
B7h
Yes
Yes
Yes
0
EXIT 4-BYTE ADDRESS MODE
E9h
Yes
Yes
Yes
0
Note: “Yes” in the protocol columns indicates that the command is supported and has the same functionality
and command sequence as other commands marked “Yes.”
9
RESET Operations
Table 6: Reset Command Set
9.1
Command
Command Code (Binary)
Command Code (Hex)
Address Bytes
RESET ENABLE
0110 0110
66
0
RESET MEMORY
1001 1001
99
0
RESET ENABLE and RESET MEMORY Command
To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY command. To
execute each command, S# is driven LOW. The command code is input on DQ0. A minimum de-selection
time of tSHSL2 must come between the RESET ENABLE and RESET MEMORY commands or a reset is not
guaranteed. When these two commands are executed and S# is driven HIGH, the device enters a power-on
reset condition. A time of tSHSL3 is required before the device can be re-selected by driving S# LOW. It is
recommended that the device exit XIP mode before executing these two commands to initiate a reset.
If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or suspended, the operation
is aborted and data may be corrupted.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
17
Form #: CSI-D-685 Document 002
is input on DQ0. A minimum de-selection time of tSHSL2 must come between the RESET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these
two commands are executed and S# is driven HIGH, the device enters a power-on reset
condition. A time of tSHSL3 is required before the device can be re-selected by driving
S# LOW. It is recommended that the device exit XIP mode before executing these two
commands to initiate a reset.
Serial NOR Flash Memory
MYXN25Q512A13G12*
If a reset is initiated while a WRITE, PROGRAM, or ERASE
operation is in progress or
suspended, the operation is aborted and data may be corrupted.
*Advanced information. Subject to change without notice.
Figure 35: RESET ENABLE and RESET MEMORY Command
Figure 8: Figure 35: RESET ENABLE and RESET MEMORY Command
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C
Reset enable
Reset memory
S#
DQ0
Note:
9.2
1. The number of lines and rate for transmission varies with extended, dual, or quad SPI.
RESET Conditions
RESET Conditions
All volatile
bits,configuration
the volatile configuration
register, the
enhanced
volatile
configuraAll volatile lock
bits, thelock
volatile
register, the enhanced
volatile
configuration
register,
and the
tion
register,
and
the
extended
address
register
are
reset
to
the
power-on
reset
default
extended address register are reset to the power-on reset default condition. The power-on reset condition
Thenonvolatile
power-onconfiguration
reset condition
depends on settings in the nonvolatile configdepends on condition.
settings in the
register.
uration register.
Reset is effective
bit 7 of
the bit
flag7 of
status
register
outputs
1 with
at least
oneatbyte
A RESET
Reset once
is effective
once
the flag
status
register
outputs
1 with
leastoutput.
one byte
ENABLE command
accepted
in the
cases ofisWRITE
STATUSinREGISTER
and
WRITESTATUS
NONVOLATILE
output. isA not
RESET
ENABLE
command
not accepted
the cases of
WRITE
REGISTER
and WRITE
NONVOLATILE CONFIGURATION REGISTER operations.
CONFIGURATION
REGISTER
operations.
10
ADDRESS MODE Operations:
Enter and Exit 4-Byte Address Mode
Both ENTER 4-BYTE ADDRESS MODE and EXIT 4-BYTE ADDRESS MODE commands share the same
requirements.
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To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write
enable latch bit to 1.
S# must be driven LOW. The command must be input on DQn. The effect of the command is immediate; after
the command has been executed, the write enable latch bit is cleared to 0.
The default address mode is three bytes, and the device returns to the default upon exiting the 4-byte address
mode.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
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Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
512Mb, Multiple I/O Serial Flash Memory
MYXN25Q512A13G12*
Power-Up
and Power-Down
Power-Up and Power-Down
*Advanced information. Subject to change without notice.
11 Power-UpPower-Up
and Power-Down
and Power-Down
Requirements
11.1
Power-Up
At power-up and power-down, the device must not be selected; that is, S# must follow
the voltage applied on V CC until V CC reaches the correct values: V CC,min at power-up and
and
VSS Power-Down
at power-down. Requirements
To avoid data corruption and inadvertent WRITE operations during power-up, a powerAt power-up and power-down, the device must not be selected; that is, S# must follow the voltage applied on
on reset circuit is included. The logic inside the device is held to RESET while V CC is less
VCC until VCC reaches
the power-on
correct values:
and VSShere;
at power-down.
CC,min at power-up
than the
resetVthreshold
voltage shown
all operations are disabled, and
the device does not respond to any instruction. During a standard power-up phase, the
To avoid data corruption and inadvertent WRITE operations during power-up, a power-on reset circuit is
device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS
included. The logic
inside the
device
is held tocan
RESET
while
than the internal
power-onstate.
resetAfter
threshold
CC is less
REGISTER.
These
operations
be used
to Vcheck
the memory
voltage shown here;
all
operations
are
disabled,
and
the
device
does
not
respond
to
any
instruction.
power-up, the device is in standby power mode; the write enable latch bit is reset; During
the
write in
progress
bit is reset;
and
lock registers
configured
(write lock
bit,READ
lock
a standard power-up
phase,
the device
ignores
allthe
commands
exceptare
READ
STATUSas:REGISTER
and
down bit) =These
(0,0). operations can be used to check the memory internal state. After power-up,
FLAG STATUS REGISTER.
the device is in standby
mode; the
write
latch
bit is reset;
the write in progress
bit isthe
reset;
the
Normalpower
precautions
must
be enable
taken for
supply
line decoupling
to stabilize
V CCand
supply.
Each device
in a system
havebit)
the
line
decoupled
by
a
suitable
capacitor
lock registers are
configured
as: (write
lock bit,should
lock down
=V
(0,0).
CC
(typically 100nF) close to the package pins. At power-down, when V CC drops from the
Normal precautions
must voltage
be takentofor
supply
decoupling tothreshold
stabilize the
VCC supply.
device
in a
operating
below
theline
power-on-reset
voltage
shown Each
here, all
operations
are
disabled
and
the
device
does
not
respond
to
any
command.
system should have the VCC line decoupled by a suitable capacitor (typically 100nF) close to the package pins.
At power-down,When
whenthe
VCCoperation
drops from
theprogress,
operatingthe
voltage
to below
the controller
power-on-reset
is in
program
or erase
bit ofthreshold
the statusvoltage
regshown here, all operations
are0.disabled
andthe
theoperation
device does
not respond
any command.
ister is set to
To obtain
status,
the flag to
status
register must be polled
twice, with S# toggled twice in between commands. When the operation completes, the
When the operation
is in or
progress,
the program
erase controller
bit of is
the
status register
is set
0. To
program
erase controller
bit isorcleared
to 1. The cycle
complete
after the
flagtostatus
register
outputs
the program
or erase
controller
to 1 both
times.
obtain the operation
status,
the flag
status register
must
be polledbit
twice,
with S#
toggled twice in between
commands. When
the
operation
completes,
the
program
or
erase
controller
bit
is
cleared
1. progress,
The cycle is
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle to
is in
complete after the
flag
status register
data
corruption
mayoutputs
result. the program or erase controller bit to 1 both times.
VPPH must
applied
only when
V CC is stable
andcycle
in theisVinCC,min
to V CC,max
voltage may
Note: If power-down
occursbewhile
a WRITE,
PROGRAM,
or ERASE
progress,
data corruption
range.
result. VPPH must be applied only when VCC is stable and in the VCC,min to VCC,max voltage range.
Figure 39: Power-Up Timing
Figure 9: Power-Up Timing
VCC
VCC,max
Chip selection not allowed
tVTW
= tVTR
Device fully accessible
VCC,min
Chip reset
tVTP
Polling allowed
VWI
SPI protocol
Starting protocol defined by NVCR
WIP = 1
WEL = 0
WIP = 0
WEL = 0
Time
MYXN25Q512A13G12*
09005aef84752721
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1.3
- 04/10/2015
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19
76
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Table 7: Power-Up Timing and VWI Threshold
Parameters listed are characterized only.
11.2
Symbol
Parameter
Min
Max
Unit
tVTR
VCC,min to read
–
150
µs
tVTW
VCC,min to device fully
accessible
–
150
µs
VWI
Write inhibit voltage
1.5
2.5
V
tVTP
VCC,min to polling allowed
–
100
µs
Power Loss Recovery Sequence
If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER command, after the
next power-on, the device might begin in an undetermined state (XIP mode or an unnecessary protocol). If
this occurs, until the next power-up, a recovery sequence must reset the device to a fixed state (extended SPI
protocol without XIP). After the recovery sequence, the issue should be resolved definitively by running the
WRITE NONVOLATILE CONFIGURATION REGISTER command again. The recovery sequence is composed
of two parts that must be run in the correct order. During the entire sequence, tSHSL2 must be at least 50ns.
The first part of the sequence is DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed
below:
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)
The second part of the sequence is exiting from dual or quad SPI protocol by using the following FFh sequence:
DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S# becomes HIGH before 9th clock cycle.
After this two-part sequence the extended SPI protocol is active.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
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Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
12
AC Reset Specifications
Table 8: AC RESET Conditions
Note 1 applies to entire table.
Parameter
Symbol
Reset pulse width
tRLRH2
Reset recovery
time
Software reset
recovery time
S# deselect to
reset valid
tRHSL
tSHSL3
tSHRV
Conditions
Min
Typ
Max
Unit
50
–
–
ns
Device deselected (S# HIGH) and is in XIP mode
–
–
40
ns
Device deselected (S# HIGH) and is in standby mode
–
–
40
ns
Commands are being decoded, any READ operations are in progress
or any WRITE operation to volatile registers are in progress
–
–
40
ns
Any device array PROGRAM/ERASE/SUSPEND/RESUME, PROGRAM
OTP, NONVOLATILE SECTOR LOCK, and ERASE NONVOLATILE
SECTOR LOCK ARRAY operations are in progress
–
–
30
µs
While a WRITE STATUS REGISTER operation is in progress
–
tW
–
ms
While a WRITE NONVOLATILE CONFIGURATION REGISTER operation
is in progress
–
tWNVCR
–
ms
On completion or suspension of a SUBSECTOR ERASE operation
–
tSSE
–
s
Device deselected (S# HIGH) and is in standby mode
–
–
40
ns
Any Flash array PROGRAM/ERASE/SUSPEND/RESUME, PROGRAM
OTP, NONVOLATILE SECTOR LOCK, and ERASE NONVOLATILE
SECTOR LOCK ARRAY operations are in progress
–
–
30
µs
While WRITE STATUS REGISTER operation is in progress
–
tW
–
ms
While a WRITE NONVOLATILE CONFIGURATION REGISTER operation
is in progress
–
tWNVCR
–
ms
On completion or suspension of a SUBSECTOR ERASE operation
–
tSSE
–
s
Deselect to reset valid in quad output or in QIO-SPI
2
–
–
ns
Notes:
1. Values are guaranteed by characterization; not 100% tested.
2. The device reset is possible but not guaranteed if tRLRH < 50ns.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
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Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
512Mb,
512Mb, Multiple
Multiple I/O
I/O Serial
Serial Flash
Flash Memory
Memory
AC
Reset
Specifications
AC
Reset
Specifications
*Advanced information. Subject to change without notice.
Figure 10: Reset AC Timing During PROGRAM or ERASE Cycle
Figure
Figure 40:
40: Reset
Reset AC
AC Timing
Timing During
During PROGRAM
PROGRAM or
or ERASE
ERASE Cycle
Cycle
S#
S#
tSHRH
tSHRH
tRHSL
tRHSL
tRLRH
tRLRH
RESET#
RESET#
Don’t
Don’t Care
Care
Figure 41: Reset Enable
Figure
41: Reset
Enable
Figure
11: Reset
Enable
C
C
0
0
1
1
2
2
3
3
4
4
5
5
Reset enable
Reset enable
S#
S#
6
6
7
7
0
0
t
tSHSL2
SHSL2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
t
tSHSL3
SHSL3
Reset memory
Reset memory
DQ0
DQ0
Figure
Figure 42:
42: Serial
Serial Input
Input Timing
Timing
Figure 12: Serial Input Timing
tSHSL
tSHSL
S#
S#
tCHSL
tCHSL
tSLCH
tSLCH
tCHSH
tCHSH
tSHCH
tSHCH
C
C
tDVCH tCHDX
tDVCH tCHDX
DQ0
DQ0
DQ1
DQ1
tCHCL
tCHCL
tCLCH
tCLCH
MSB in
MSB in
LSB in
LSB in
High-Z
High-Z
High-Z
High-Z
Don’t Care
Don’t Care
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
PDF: 09005aef84752721
PDF:
09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf
- Rev. Q 11/13 EN
n25q_512mb_1ce_3V_65nm.pdf - Rev. Q 11/13 EN
22
79
79
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Micron Technology, Inc. reserves the right to©change
products
or specifications
without
notice.
Form
#: rights
CSI-D-685
Document 002
2011 Micron
Technology,
Inc. All
reserved.
© 2011 Micron Technology, Inc. All rights reserved.
512Mb, Multiple I/O Serial Flash Memory
SerialI/O
NOR
Flash
Memory
AC
Reset
Specifications
512Mb, Multiple
Serial
Flash
Memory
AC
Reset
Specifications
MYXN25Q512A13G12*
Figure 43: Hold Timing
Figure 43: Hold Timing
Figure 13: Hold Timing
*Advanced information. Subject to change without notice.
S#
S#
C
C
tCHHL
tHLCH
tHHCH
tCHHL
tHLCH
tHHCH
tHLQZ
tHLQZ
DQ0
tCHHH
tCHHH
tHHQX
tHHQX
DQ0
DQ1
DQ1
HOLD#
HOLD#
Don’t Care
Don’t Care
Figure 44: Output Timing
Figure
14: Output
TimingTiming
Figure
44: Output
S#
S#
C
C
DQ0
tCLQV
tCLQV
tCL
tCH
tCLQV
tCLQV
tCL
tCH
tCLQX
tCLQX
tCLQX
tCLQX
tSHQZ
LSB out
DQ0
tSHQZ
LSB out
512Mb, Multiple I/O Serial Flash Memory
AC Reset Specifications
DQ1 Address
LSB in
DQ1 Address
LSB in
Don’t Care
Don’t Care
Figure 45: VPPH Timing
Figure 15: VPPH Timing
End of command
(identified by WIP polling)
S#
C
DQ0
tVPPHSL
VPPH
VPP
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. Q 11/13 EN
MYXN25Q512A13G12*
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf
Revision
1.3 - 04/10/2015- Rev. Q 11/13 EN
80
80
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
13
Absolute Ratings and Operating Conditions
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only.
Exposure to absolute maximum rating for extended periods may adversely affect reliability. Stressing the device
beyond the absolute maximum ratings may cause permanent damage.
Table 9: Absolute Ratings
Symbol
Parameter
Min
Max
Units
Notes
TSTG
Storage temperature
–65
150
°C
TLEAD
Lead temperature during soldering
–
See note 1
°C
VCC
Supply voltage
–0.6
4.0
V
VPP
Fast program/erase voltage
–0.2
10
V
VIO
Input/output voltage with respect to ground
–0.6
VCC + 0.6
V
3, 4
VESD
Electrostatic discharge voltage (human body model)
–2000
2000
V
2
Notes:
1. JEDEC Standard JESD22-A114A (C1 = 100pF, R1 = 1500Ω, R2 = 500Ω).
2. During signal transitions, minimum voltage may undershoot to –1V for periods less than 10ns.
3. During signal transitions, maximum voltage may overshoot to VCC + 1V for periods less than 10ns
Table 10: Operating Conditions
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
Symbol
Parameter
Min
Max
Units
VCC
Supply voltage
2.7
3.6
V
VPPH
Supply voltage on VPP
8.5
9.5
V
TA
Ambient operating temperature
–40
85
°C
24
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Table 11: Input/Output Capacitance
These parameters are sampled only, not 100% tested. TA = 25°C at 54 MHz.
Symbol
Description
Test Condition
Min
Max
Units
CIN/OUT
Input/output capacitance (DQ0/DQ1/DQ2/DQ3)
VOUT = 0V
–
8
pF
CIN
Input capacitance (other pins)
VIN = 0V
–
6
pF
Table 12: AC Timing Input/Output Conditions
Symbol
Description
CL
Load capacitance
–
Input rise and fall times
Min
Max I/O Serial
UnitsFlash Memory
Notes
512Mb,
Multiple
Absolute
Ratings
and
Operating
Conditions
30
30
pF
1
Input pulse
voltages
Table 39: AC Timing Input/Output
Conditions
Symbol
Description
Input timing reference voltages
CL
Output timing reference voltages
Load capacitance
–
Input rise and fall times
–
5
ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC/2
V
Min
VCC30
/2
–
Max
30
V
V
5
2
Units
Notes
pF
1
ns
Input
Notes:pulse voltages
0.2VCC to 0.8VCC
Input timing reference voltages
0.3VCC to 0.7VCC
V
Output timing reference voltages
VCC/2
V
1. Output buffers are configurable by user.
2. For quad/dual operations: 0V to VCC.
Notes:
VCC/2
V
2
1. Output buffers are configurable by user.
2. For quad/dual operations: 0V to VCC.
Figure 16: AC Timing Input/Output Reference Levels
Figure 46: AC Timing Input/Output Reference Levels
Input levels1
I/O timing
reference levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
Note:
1. 0.8VCC = VCC for dual/quad operations; 0.2VCC = 0V for dual/quad operations.
Note: 0.8VCC = VCC for dual/quad operations; 0.2VCC = 0V for dual/quad operations.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
25
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
14
DC Characteristics and Operating Conditions
Table 13: DC Current Characteristics and Operating Conditions
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input leakage current
ILI
–
±2
µA
Output leakage current
ILO
–
±2
µA
Standby current
ICC1(1)
S = VCC, VIN = VSS or VCC
–
150
µA
Standby current
ICC1 (automotive)
S = VCC, VIN = VSS or VCC
–
300
µA
C = 0.1VCC/0.9VCC at 108 MHz, DQ1 = open
–
15
mA
C = 0.1VCC/0.9VCC at 54 MHz, DQ1 = open
–
6
mA
C = 0.1VCC/0.9VCC at 108 MHz
–
18
mA
C = 0.1VCC/0.9VCC at 108 MHz
–
20
mA
Operating current (fast-read extended I/O)
Operating current (fast-read dual I/O)
ICC3
Operating current (fast-read quad I/O)
Operating current (program)
ICC4
S# = VCC
–
20
mA
Operating current (write status register)
ICC5
S# = VCC
–
20
mA
Operating current (erase)
ICC6
S# = VCC
–
20
mA
Note 1: Automotive & Military temperature ranges.
Table 14: DC Voltage Characteristics and Operating Conditions
Min
Max
Unit
VIL
–0.5
0.3VCC
V
Input high voltage
VIH
0.7VCC
VCC + 0.4
V
Output low voltage
VOL
IOL = 1.6mA
–
0.4
V
Output high voltage
VOH
IOH = –100µA
VCC - 0.2
–
V
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
Parameter
Symbol
Input low voltage
Conditions
26
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
15
AC Characteristics and Operating Conditions
Table 15: Table 42: AC Characteristics and Operating Conditions
Parameter
Symbol Min
Typ1
Max
Unit
Notes
Clock frequency for all commands other than READ (SPI-ER, QIO-SPI protocol)
fC
DC
–
108
MHz
Clock frequency for READ commands
fR
DC
–
54
MHz
Clock HIGH time
tCH
4
–
–
ns
2
Clock LOW time
tCL
4
–
–
ns
1
Clock rise time (peak-to-peak)
tCLCH
0.1
–
–
V/ns
3, 4
Clock fall time (peak-to-peak)
tCHCL
0.1
–
–
V/ns
3, 4
S# active setup time (relative to clock)
tSLCH
4
–
–
ns
S# not active hold time (relative to clock)
tCHSL
4
–
–
ns
Data in setup time
tDVCH
2
–
–
ns
Data in hold time
tCHDX
3
–
–
ns
S# active hold time (relative to clock)
tCHSH
4
–
–
ns
S# not active setup time (relative to clock)
tSHCH
4
–
–
ns
S# deselect time after a READ command
tSHSL1
20
–
–
ns
S# deselect time after a nonREAD command
tSHSL2
50
–
–
ns
Output disable time
tSHQZ
–
–
8
ns
–
–
7
ns
–
–
8
ns
–
–
5
ns
–
–
6
ns
STR
Clock LOW to output valid under 30pF
DTR
STR
Clock LOW to output valid under 10pF
tCLQV
DTR
3
Output hold time (clock LOW)
tCLQX
1
–
–
ns
Output hold time (clock HIGH)
tCHQX
1
–
–
ns
HOLD command setup time (relative to clock)
tHLCH
4
–
–
ns
HOLD command hold time (relative to clock)
tCHHH
4
–
–
ns
HOLD command setup time (relative to clock)
tHHCH
4
–
–
ns
HOLD command hold time (relative to clock)
tCHHL
4
–
–
ns
HOLD command to output Low-Z
tHHQX
–
–
8
ns
3
HOLD command to output High-Z
tHLQZ
–
–
8
ns
3
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
27
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Parameter
Symbol Min
Typ1
Max
Unit
Notes
Write protect setup time
tWHSL
20
–
–
ns
5
Write protect hold time
tSHWL
100
–
–
ns
5
tVPPHSL
200
–
–
ns
6
tW
–
1.3
8
ms
tWNVCR
–
0.2
3
s
CLEAR FLAG STATUS REGISTER cycle time
tCFSR
–
40
–
ns
WRITE VOLATILE CONFIGURATION REGISTER cycle time
tWVCR
–
40
–
ns
tWRVECR
–
40
–
ns
tWREAR
–
40
–
ns
tPP
–
0.5
5
ms
7
PAGE PROGRAM cycle time (n bytes)
–
int(n/8) × 0.0158
5
ms
7
PAGE PROGRAM cycle time, VPP = VPPH ( 256 bytes)
–
0.4
5
ms
7
PROGRAM OTP cycle time (64 bytes)
–
0.2
–
ms
7
tSSE
–
0.25
0.8
s
tSE
–
0.7
3
s
–
0.6
3
s
Enhanced VPPH HIGH to S# LOW for extended and dual I/O page program
WRITE STATUS REGISTER cycle time
Write NONVOLATILE CONFIGURATION REGISTER cycle time
WRITE VOLATILE ENHANCED CONFIGURATION REGISTER cycle time
WRITE EXTENDED ADDRESS REGISTER cycle time
PAGE PROGRAM cycle time (256 bytes)
Subsector ERASE cycle time
Sector ERASE cycle time
Sector ERASE cycle time (with VPP = VPPH)
Notes:
1. Typical values given for TA = 25 °C.
2. tCH + tCL must add up to 1/fC.
3. Value guaranteed by characterization; not 100% tested.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRITE STATUS REGISTER command when STATUS REGISTER
WRITE is set to 1.
6. VPPH should be kept at a valid level until the PROGRAM or ERASE operation has completed and its result
(success or failure) is known.
7. When using the PAGE PROGRAM command to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes
(1 < n < 256).
8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
28
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
16
512Mb, Multiple I/O Serial Flash Memory
Package Dimensions
Package Dimensions
Figure 49: T-PBGA-24b05/6mm x 8mm
Figure 17: T-PBGA-24b05/6mm x 8mm
0.79 TYP
Seating
plane
A
0.1 A
24X Ø0.40 ±0.05
Ball A1 ID
5
4
3
2
Ball A1 ID
1
A
B
C
4.00
8 ±0.10
D
1.00 TYP
E
1.00 TYP
1.20 MAX
4.00
0.20 MIN
6 ±0.10
Notes:
1. All dimensions are in millimeters.
2. Seeare
Part
Ordering Information for complete package names and details.
Note: All dimensions
in Number
millimeters.
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
29
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
17
Ordering Information
Table 16: Ordering Information
Part Number
Device Grade
MYXN25Q512A13G12BG-ITRL
Industrial
MYXN25Q512A13G12BG-ATRL
Automotive
MYXN25Q512A13G12BG-XTRL
Military
Please contact a Micross sales representative for IBIS or thermal models at [email protected].
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
30
Form #: CSI-D-685 Document 002
Serial NOR Flash Memory
MYXN25Q512A13G12*
*Advanced information. Subject to change without notice.
Document Title
512MB, 3V, Multiple I/O, 4KB Sector Erase - Serial NOR Flash Memory
Revision History
Revision #
History
Release Date
Status
1.0
Initial Release
September 2014
Preliminary
1.1
Added ECN #; changed “Marking” to “Code” in blue box on pg. 1
October 21, 2014
Preliminary
1.2
Changed part # from MYXN25Q512 to MYXN25Q512A13G12
October 30, 2014
Preliminary
1.3
Added Military device grade
April 10, 2015
Preliminary
MYXN25Q512A13G12*
Revision 1.3 - 04/10/2015
31
Form #: CSI-D-685 Document 002