AN055 TRIAC-Dimmable, Offline, LED Controller The Future of Analog IC Technology with Primary-Side Control and Active PFC MP4030: Application Note for a TRIAC-Dimmable, Offline LED Controller with Primary-Side Control and Active PFC Prepared by JiaLi Cai Dec. 14, 2011 AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 AN055 – TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Table of Contents 1. Introduction........................................................................................................................................ 4 2. Primary-Side Control, Boundary-Conduction Mode with Active PFC.................................................. 5 A. Primary-Side Control .................................................................................................................. 5 B. Boundary-Conduction Mode ....................................................................................................... 6 C. Active PFC ................................................................................................................................. 8 3. Pin Function and Operation Information........................................................................................... 10 A. PIN Introduction........................................................................................................................ 10 Pin1 (MULT) .......................................................................................................................... 10 Pin2 (ZCD) ............................................................................................................................ 11 Pin3 (VCC) ............................................................................................................................ 13 Pin4 (DP)............................................................................................................................... 14 Pin5 (S) ................................................................................................................................. 14 Pin6 (D) ................................................................................................................................. 15 Pin7 (GND)............................................................................................................................ 15 Pin8 (COMP) ......................................................................................................................... 15 B. TRIAC Dimming ....................................................................................................................... 16 4. Design example: .............................................................................................................................. 18 TRIAC-Dimmable, High-Performance, 8W LED Luminaire Driver ........................................................ 18 A. Specifications ........................................................................................................................... 18 B. Schematic ................................................................................................................................ 18 C. Turn Ratio (N), Primary MOSFET, and Secondary-Rectifier–Diode Voltage Rating Selection .. 18 D. Transformer Design.................................................................................................................. 20 Primary Inductance, LP .......................................................................................................... 20 The Primary-Winding RMS Current: ...................................................................................... 22 The secondary winding RMS current: .................................................................................... 22 The Transformer Core Selection............................................................................................ 22 Primary and Secondary Winding Turns.................................................................................. 23 Wire Size ............................................................................................................................... 24 Auxiliary Winding Wire Size ................................................................................................... 24 Window-Area Fill-Factor Calculation...................................................................................... 24 Air Gap .................................................................................................................................. 25 Instructions for Transformer Manufacturing ........................................................................... 25 AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 AN055 – TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC E. Input EMI Filter (L1, L2, L3, CX1, CY1, C6).............................................................................. 26 F. Input Bridge (BD1).................................................................................................................... 26 G. Input Capacitor (C2)................................................................................................................. 26 H. Passive Bleeder (C6, R6, R9) and Active Damper (Q2, Q3, D3, D8, C8, R4, R8, R12, R13).... 26 I. Output Capacitor (C3, C4) ......................................................................................................... 27 J. RCD Snubber (R6, C8, D2)....................................................................................................... 28 K. High-Side MOSFET Gate Driver (R5, R10, C7, D4, D6) ........................................................... 30 L. VCC Power Supply (R11, C12, D5, D10) .................................................................................. 30 M. ZCD and OVP Detector (R14, R19, C11)................................................................................. 30 N. MULT Pin Resistor Divider (R3, R17, C10) .............................................................................. 31 O. Current Sensing Resistor (R20, R21, R24) .............................................................................. 31 P. OCP Detector (R18, R22, D9) .................................................................................................. 31 Q. Layout Guideline ...................................................................................................................... 31 R. BOM......................................................................................................................................... 33 5. Experimental Result......................................................................................................................... 34 5.1 Performance Data................................................................................................................... 34 5.2 Steady State ........................................................................................................................... 34 5.3 Input Voltage and Current ....................................................................................................... 34 5.4 Boundary Conduction Operation............................................................................................. 35 5.5 Start Up .................................................................................................................................. 35 5.6 OVP (Open load at normal operation)..................................................................................... 36 5.7 SCP (Short LED+ to LED– at normal operation) ..................................................................... 36 5.8 Triac Dimming......................................................................................................................... 37 5.9 Thermal Performance ............................................................................................................. 39 5.10 Conducted EMI ..................................................................................................................... 39 AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 1. INTRODUCTION The MP4030 is a TRIAC-dimmable, offline, LED lighting controller with primary-side control and active PFC. The proprietary TRIAC dimming scheme increases the dimming range and avoids random flickering. The primary-side-control significantly simplifies the LED lighting driving system by eliminating the optocoupler and the secondary feedback components for an isolated single stage converter. Its proprietary real-current control method can accurately control the LED current from primary-side information. The MP4030 has a power factor correction (PFC) function that can achieve a power factor (PF)>0.9 within a universal input voltage range. The device also works in boundary conduction mode to reduce switching loss and improve EMI performance. The MP4030 has an integrated charging circuit at the VCC pin to start-up with a delay of less than 200ms when using a 22µF bulk capacitor. The low-voltage current source outputs a maximum 16mA charging current. The MP4030 provides multiple advanced fault protections to enhance the system safety, including overvoltage protection, short–circuit protection, primary-side over-current protection, VCC under-voltage lockout, and thermal shutdown: all protections features auto-restart. Figure 1 shows a typical application. Figure 1: Typical Application AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 2. PRIMARY-SIDE CONTROL, BOUNDARY-CONDUCTION MODE WITH ACTIVE PFC Conventional off-line LED drivers use secondary-side control that senses the LED current directly. An error amplifier compares this current level against a reference produced by a device such as a TL431, and the compensated output determines the primary-side duty cycle to regulate the LED current. Although this control method can directly control the LED current and current accuracy under any condition, it requires additional secondary-side components—including a sensing circuit, comparison and compensation circuits, an opto-coupler, and bias power supplies—that significantly increase system complexity and cost. In addition, the primary-side input stage typically uses a full-wave rectifier bridge with an E-cap filter to generate a DC voltage. The E-cap must be large enough to limit the DC voltage ripple. This means the instantaneous input line voltage is lower than the DC voltage on the E-cap for most of a line half-cycle, and that the rectifier diodes only conduct a small portion of the voltage. This voltage limitation causes the input line current to act like a series of narrow pulses whose amplitudes are about 10x higher than the average DC level. The drawbacks include: a high current peak and RMS current drawn from the line, line-input–current distortion limiting the power factor to about 0.5 to 0.6, and large induced harmonics. Figure 1 shows that the MP4030 uses primary-side control, which eliminates secondary feedback components to significantly reduce the component count and cost. The MP4030 also works in boundary-conduction mode with active PFC, with a power factor >0.9 for the input, and reduce THD to meet IEC61000-3-2 requirements. A. PRIMARY-SIDE CONTROL Figure 2: Transformer Currents Relative to the BCM Flyback Converter Given that the LED current is the average current of the transformer’s secondary side, Io = Is _ avg , as shown in Figure 2, the average secondary-side current in boundary-conduction mode can be calculated as: AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Is _ avg 1 ⋅ N ⋅ Ip _ pk ⋅ t off = 2 t on + t off Where Is_avg is the average secondary-side current, and Ip_pk is the peak primary-side current. The MP4030 samples the primary-side peak current to calculate the average current. Since the average current is proportional to the output current, if the average current is a controlled constant, the output current is also constant, allowing for primary-side control. B. BOUNDARY-CONDUCTION MODE The MP4030 works in boundary conduction mode where the transformer functions at the boundary between the continuous and discontinuous mode. In a conventional fixed-frequency flyback converter working in discontinuous conduction mode (DCM), the primary switch (MOSFET) turns on at a fixed frequency and turns off when the current reaches the desired level. When the MOSFET turns off, the energy stored in the inductor forces the secondary side diode to turn on, and the inductor current decreases linearly from the peak value to zero. When the current drops to zero, the parasitic resonance of the magnetizing inductor and the sum of the parasitic capacitance causes the MOSFET drain-source voltage to oscillate. The MOSFET can turn on at any point during the parasitic resonance, including when the drain voltage is lower than the bus voltage (meaning low switching losses and high efficiency), and when the drain voltage is much higher than the bus voltage (meaning high switching loss). This feature is observable in the efficiency curves of a discontinuous flyback converter with a constant load as input-voltage efficiency fluctuations as the turnon switching loss changes with the turn-on drain voltage. In boundary conduction mode, the switch does not have a fixed switching frequency. Instead, the controller always turns on the switch when the drain voltage goes low by detecting the auxiliary winding voltage, VZCD, the ZCD voltage is a ratio of primary winding and auxiliary winding. Figure 3 shows that by setting the falling-edge detection near zero, the parasitic resonance causes the ZCD voltage to decrease when the secondary side current deceases to zero: Conversely, when VZCD reaches the detection threshold, the MOSFET turn-on signal triggers. The transformer magnetizing inductance, parasitic capacitance, and ZCD filtering capacitor determine the detection time delay. The feedback loop determines the switch-on time, similar to conventional peak-current–mode control. The energy stored in the magnetizing inductor then transfers to the output. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC N:1 + + VOUT Is VAC line Ip ZCD VDS VAC line + N V OUT turn on VAC line Ip Inductor current Is/N Ton Toff VZCD 0 Figure 3: Boundary Conduction Mode Compared to conventional flyback under continuous conduction mode (CCM) and DCM operation, boundary-conduction mode operation minimizes the turn-on switching loss, thus increasing efficiency and suppressing the MOSFET temperature rise. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC C. ACTIVE PFC Figure 4: Functional Block Diagram and LED Driver The MP4030 integrates active an PFC function. Figure 4 shows the functional block diagram and the LED converter driver. The converter consists of an EMI filter, a diode bridge rectifier, a flyback circuit using the MP4030. The following description summarizes converter operation with active PFC: The diode bridge rectifies the AC line voltage, which then goes to the flyback circuit. When the internal main MOSFET turns on, the transformer’s primary-side current ramps up from zero. The S pin senses this primary-side current through a sensing resistor, and this signal goes to the real-current calculation block to calculate its average value. The internal error amplifier compares the average value against an internal reference to generate an error signal that is proportional to the difference between them. If the bandwidth of the error amplifier is narrow enough (below 20Hz), then the error signal is a DC value for over a line half-cycle and kept constant until the average value equals the reference: This regulates the output LED current to a required constant value. The error signal goes to the multiplier block with a portion of the rectified mains voltage. The resulting signal is a rectified sinusoid with a peak amplitude that depends on the peak line voltage and the value of the error signal. The output of the multiplier goes to the negative input of the current comparator to act as a sinusoidal reference for the PWM. When the S-pin voltage equals the value on the negative input of the current comparator, the external MOSFET turns off. The rectified signal envelops the peak primary current. and has the same phase as the main input voltage to implement a good power factor. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Figure 5: Primary and Secondary Transformer Currents and MOSFET Gate Timing Figure 5 shows both transformer currents and the gate timing. The operating frequency increases as the instantaneous line voltage decreases; when the line voltage approaches the zero-crossing point, the frequency increases dramatically. The MP4030 has an internally-set 5µs minimum off-time to limit the maximum switching frequency and to improve efficiency and reduce EMI. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 3. PIN FUNCTION AND OPERATION INFORMATION A. PIN INTRODUCTION Pin1 (MULT) The MULT pin provides one of the inputs to the internal multiplier. Connect this pin to the tap of the resistor divider from the rectified instantaneous line voltage, which will produce a sinusoidal multiplier output. This output signal provides the reference for the current comparator, which shapes the primary peak current into a sinusoid that is in-phase, with the input line voltage. The MULT pin also provides for TRIAC dimming phase detector (page 16) and DP MOSFET gate control (page 14). Figure 6: MULT Circuit For the multiplier to operate at linear zone, select a MULT voltage range smaller than 3V. The multiplier output is then given by: Vmultiplier _ out = k ⋅ VMULT ⋅ (VCOMP − 1.5) Where k is the gain of the multiplier. The MULT voltage also determines the COMP voltage level for the system control loop. In real applications, setting the MULT pin too low cause the COMP voltage to saturate the 5V SCP point; setting the MULT pin too high causes the COMP voltage to below its 1.9V clamp voltage. For TRIAC dimming, the COMP voltage directly influences the dimming curve (page 17), so tune the MULT voltage carefully. The multiplier output has two clamps: The 2.3V high clamp is for primary cycle-by-cycle current limiting, the 0.1V low clamp signals the output gate driver to pull down the line voltage during the TRIAC dimming OFF interval. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Pin2 (ZCD) Figure 7: ZCD Circuit Figure 7 shows the ZCD pin circuitry. The ZCD pin connects to the auxiliary winding through a resistor divider (Rzcd1, Rzcd2). The ZCD pin integrates three functions: One detects the secondary-side–current zero-crossing condition by monitoring the auxiliary winding voltage for BCM; The second function is to implement the output over voltage protection by comparing the ZCD voltage to the internal 5.5V reference; The third function is to activate the over-current protection (OCP) by sensing the primaryside current. The internal gate turn-on signal triggers when the ZCD pin voltage falling-edge from the resistor divider goes below 0.35V, with a 0.55V hysteresis. The MP4030 switching frequency varies instantaneously with the input line voltage. To limit the maximum frequency and improve EMI and efficiency performance, the MP4030 employs an internal minimum OFF-time limiter of 5μs, as shown in Figure 8. When the input line voltage crosses the zero point, the primary current is very small and cannot turn the secondary diode on, so the ZCD does not receive the turn-on signal for the next duty cycle. To avoid unnecessary IC shutdown, the MP4030 integrates an auto starter that starts timing when the MOSFET turns off. If the ZCD fails to send out another turn-on signal after 122µs, the starter will automatically send out a turn-on signal. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Figure 8: Minimum Off Time Output over-voltage protection (OVP) works by detecting the auxiliary-winding voltage’s positive plateau, which is proportional to the output voltage. Once the ZCD pin voltage exceeds 5.5V, the OVP signal triggers and latches, the gate driver turns off, and the VCC voltage decreases. When the VCC drops below 7V, the IC resets and restarts. The following equation estimates the output OVP set point: Vout _ OVP ⋅ Naux R zcd2 ⋅ = 5.5V Nsec Rzcd1 + R zcd2 Where Vout_OVP is the output OVP setting voltage, Naux is the number of transformer auxiliary windings, and Nsec is number of secondary windings. Consider that the ZCD falling-edge detection delay time (when coupled with the ceramic bypass capacitor) increases with larger resistor values, reducing the output LED current: limit the delay time to <1.5μs. To avoid OVP mis-triggers caused by switch-off oscillation spikes, the MP4030 integrates an internal τOVPS blanking time for the OVP detection— typically 2μs (see Figure 9). Figure 9: ZCD Voltage with Blanking Time Selecting for RZCD1 and RZCD2 requires taking the ABS voltage and ZCD current into consideration. The ZCD pin’s negative ABS voltage of ZCD pin is internally clamped at –8V and its source current is 5mA. Turning the primary MOSFET on applies a large negative voltage to the auxiliary winding, and may cause the ZCD pin to reach its negative voltage limit—the RZCD1 and RZCD2 values must be large enough to limit the ZCD pin source current to below 5mA. Connecting a resistor divider from the S pin sensing resistor to ZCD pin, as shown in Figure 7, implement over-current protection (OCP). When the main MOSFET on the primary-side turns on, the ZCD pin monitors the rising primary-side current through the resistor divider. Once the ZCD pin reaches OCP threshold (typically 0.9V) after a 700ns blanking time, the OCP signal triggers and latches. The gate driver turns off to prevent over-current damage. The IC works in quiescent mode: VCC d AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC ecreases, and when VCC drops below the 7V UVLO threshold, the IC resets and the system restarts. The primary-side OCP setting point can be calculated as: Ip _ OCP ⋅ Rs ⋅ ROCP2 − VD = 0.9 ROCP1 + ROCP2 Where IP_OCP is primary-side OCP value and VD is the diode voltage drop. Note that when the MOSFET is on, the taps of the ZCD resistor divider and the OCP resistor divider are connected by a diode. Therefore, set the resistor values of the OCP threshold (ROCP1 & ROCP2) much smaller than the ZCD resistors (RZCD1 & RZCD2) to minimize the ZCD influence. The primary OCP method is also a good protection method for output SCP because it can be considered an over-load condition: The COMP voltage rises, causing the primary peak current to also rise. The primary OCP triggers when the primary peak current reaches the setting threshold. Pin3 (VCC) Figure 10: VCC Circuit and Power Supply Flow-Chart VCC powers both the internal logic circuit and the gate driver signal. Figure 10 shows the VCC circuit and the power supply flow-chart. The gate of high-side MOSFET charges quickly in the presence of an AC power supply, then VCC is charged through the internal charging circuit from the AC line. When VCC reaches 10V, the internal charging ceases, then the control logic and the internal main MOSFET begin to function. Then the auxiliary winding provides power. The initial auxiliary-winding positive voltage is low and so the VCC level drops. Once VCC drops below a 9V threshold, the internal charging circuit triggers and to charge VCC to 10V again until the auxiliary winding can take over. If any fault occurs, the switching and the internal charging circuit will stop and latch, and VCC will drop. When the VCC drops to 7V, the internal charging circuit recharges to restart the device. A bulk capacitor connected to VCC determines the system start-up time and the VCC fall time under fault and TRIAC-dimming conditions. A large bulk capacitor results a long start up time but slows the VCC voltage drop under deep TRIAC-dimming conditions. Most applications call for a 22µF electrolytic capacitor. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Pin4 (DP) VAC line Primary Winding D S MULT 0.35 V 0.25V 0.25V/0.35V 200us delay 200us MULT DP MOSFET Gate Figure 11: DP Circuit and Gate Driver Logic The DP pin is the drain of the internal pull-down dimming MOSFET. The MULT voltage controls the MOSFET, as shown in Figure 11. If the IC detects the system is connected as dimming mode, the DP MOSFET turns on when the MULT voltage drops below 0.25V,. Conversely, when the MULT voltage exceeds 0.35V, the MOSFET turns off after a 200µs delay. For TRIAC dimming, connect a resistor from the DP pin to D to pull down the input line voltage during the TRIAC OFF interval and accurately detect the dimming phase on the MULT pin to avoid unwanted flickering. This resistor also provides a pulldown current branch when TRIAC dimming starts, and improves TRIAC turn-on performance during short dimming phases by supplementing the latch current to the TRIAC. Pin5 (S) The S pin senses the primary-side current through a sensing resistor. The resulting voltage goes to the current comparator with the multiplier output to determine the MOSFET turn-off time, and the averagecurrent calculation block to calculate the average primary-current value. A stable system loop produces a primary average value, Ip_avg×RS, equal to the internal reference, Vref. Combined with the equation on page 5, the output LED mean current can approximated as: Io = N ⋅ Vref 2 ⋅ Rs Where N is the turn ratio of the primary and secondary windings, Vref is the internal reference voltage (typically 0.4V), and Rs is the sensing resistor connected between the main MOSFET source and GND. An internal leading-edge blanking (LEB) unit between the S pin and the internal feedback avoids premature switching-pulse termination due to the parasitic capacitance discharging during turn-on. The internally-fed path is blocked during the blanking time. Figure 12 demonstrates the leading-edge blanking time. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC VS TLEB=700nS t Figure 12: Leading-Edge Blanking Pin6 (D) Figure 13 shows the D-pin circuit. The D pin is the drain of the main, internal, low-side MOSFET. This pin also connects the internal VCC charging path to the source of the external high-side MOSFET. Under normal conditions, the main, internal, low-side MOSFET has a break-down voltage of 30V. When the MOSFET is OFF, the D voltage is the ratio of the high-side MOSFET and the low-side MOSFET voltages. The D voltage may exceed the break-down voltage and damage the device: Adding a Zener diode from the D-pin to the high-side MOSFET gate helps to clamp the D-pin voltage. VAC line Primary Winding D S Auxiliary Winding VCC + Figure 13: D-Pin Circuit Pin7 (GND) The Ground (GND) pin provides the current return for both the control and the gate-drive signals. Connect the power and analog GNDs at this pin only for PCB layout. The power GND (PGND) provides the reference for the power switches, and the analog GND (AGND) for the control signals. Pin8 (COMP) Loop compensation pin. Connect a compensation capacitor from this pin to AGND. Use a low-ESR ceramic capacitor, such as X7R. The COMP pin is the output of the internal error amplifier. To limit the loop bandwidth <20Hz for good PFC performance, select a capacitor value between 2.2µF and 10µF. A larger capacitor results in a smaller COMP voltage ripple for better thermal, EMI, steady-state performance, but also means a longer soft-start time. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC The COMP is also used for SCP. An output short can be considered an over-load, so the COMP voltage rises. Once the COMP voltage reaches 5V, the SCP signal triggers and latches, switching stops, and VCC decrease. When VCC drops below the 7V UVLO threshold, the IC resets and the system restarts. B. TRIAC DIMMING The MP4030 can implement TRIAC-based dimming. The TRIAC dimmer consists of a bi-directional SCR with adjustable turn-on phase. Figure 14 shows the leading-edge TRIAC dimming waveforms. Figure 14: TRIAC Dimming Waveforms The MP4030 will detect the dimming turn on cycle on MULT pin and fed into the control loop for adjusting the internal Reference voltage. When MULT voltage is higher than 0.35V, it will be recognized as dimmer turn on, when MULT voltage is lower than 0.15V, it will be recognized as dimmer turn off. The MP4030 has a 25% of line cycle detection blanking time at each line cycle, the real phase detector output is plus this time, shown in figure 15. That means if the turn on cycle is bigger than 75% of the line cycle, the output is kept at the same maximum current. It can help improve the line regulation in maximum TRIAC turn on cycle or without dimmer application. Figure 15: Dimmer Turn-On Cycle Detection If the turn-on cycle decreases to <75%×(line cycle), the internal reference voltage decreases linearly with the falling dimming turn-on phase, and the output current decreases accordingly. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC The COMP voltage decreases with the falling dimming turn-on cycle. Once the COMP voltage reaches 1.9V, it is clamped so that the output current decreases slowly. This clamping helps maintain the TRIAC holding current to shift the TRIAC turn-off point closer to the line-voltage zero-crossing point to avoid random flicker caused by large phase differences between the TRIAC-current zero-crossing point and the input-line–voltage zero-crossing point. Figure 16 shows the relationship between the dimming turn-on phase and the output current. The output current turning point happens when COMP voltage is clamped at 1.9V, so the COMP voltage will influence the output current dimming curve. The MULT pin voltage also adjusts the COMP voltage level. However, a low COMP voltage narrows the dimming range, and a high COMP voltage can cause random flickering. For typical applications, the COMP voltage is usually set between 2.2V and 2.3V without dimming. Figure 16: Dimming Curve AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 4. DESIGN EXAMPLE: TRIAC-DIMMABLE, HIGH-PERFORMANCE, 8W LED LUMINAIRE DRIVER A. SPECIFICATIONS Parameter Input Supply Voltage AC Line Frequency Output Voltage Symbol VIN fLINE VOUT LED Current ILED(MAX) Continuous Output Power Efficiency Condition 2 Wire Min 108 7 LEDs in series Without connecting dimmer POUT η Full load, with out connecting dimmer Power Factor Conducted EMI Harmonics Surge Typ 120 60 22 Max 132 Units VAC Hz V 350 mA 8 W 80% 0.9 Meets EN55015 Meets IEC61000-3-2 Class C Limitation Meets IEC61547 surge requirement B. Schematic Figure 17: Example Application Schematic—8W Luminaire Driver C. TURN RATIO (N), PRIMARY MOSFET, AND SECONDARY-RECTIFIER–DIODE VOLTAGE RATING SELECTION The following provides a design example given the following conditions: • Vac_min=108V • Vac_max=132V • Vin_max= 2 ⋅ Vac _ max • Vin (Vac ,t) = 2 ⋅ Vac ⋅ sin(2 ⋅ π ⋅ fline ⋅ t) Figure 18 shows a typical drain-source voltage waveform for the primary high-side MOSFET and he secondary rectifier diode. From the waveform, the maximum primary high side MOSFET Drain-Source AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC voltage rating VP-MOS_max is VP−MOS _ max = Vin _ max + N ⋅ Vo + 150 (1) Where 150V is the assumed maximum spike voltage, and is related to the RCD snubber. The maximum secondary rectifier diode voltage rating, VDIODE_max, is VDIODE _ max = Vin _ max N + Vo + 40 (2) Assuming the maximum voltage spike is 40V. Figure 18: Drain-Source Voltage of the Primary MOSFET and the Secondary Rectifier Diode Figure 19 shows the voltage rating curves of the primary MOSFET and secondary rectifier diode versus the turn ratio, N, based on equations (1) and (2). N can be determined by the required MOSFET and rectifier diode voltage ratings. 700 700 200 200 670 640 162.5 610 580 Vp_MOSFET ( N ) 550 Vs_diode ( N ) 125 520 490 87.5 460 400 430 400 50 2 2 3 4 5 6 N 7 8 9 10 10 50 2 2 3 4 5 6 7 8 N 9 10 10 Figure 19: Votage Ratings for the Primary MOSFET and the Secondary Rectifier Diode as a function of Turn Ration, N Some applications allow for N to be selected from within a range, which then requires the following considerations: • A small N means a smaller τon/τoff ratio, as per equation (5), which leads to a poor THD • A large N leads to a large primary inductance and a physically larger transformer. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Based on the stated conditions, N=5, so 600V or 650V MOSFET and a 100V or 200V Schottky or fastrecovery diode suffices for this particular design example. D. TRANSFORMER DESIGN Primary Inductance, LP It is possible to demonstrate that the MP4030 produces a constant ON-time over each line half-cycle, given: τon , and Lm • VS = R s ⋅ Vin ⋅ • VMultipier = K1 ⋅ K 2 ⋅ Vin ⋅ ( VCOMP − 1) , since • VCS = VMultiplier , • then τon = L m ⋅ K1 ⋅K 2 ⋅( VCOMP − 1) Rs Where Lm is the primary inductance, Rs is the current sensing resistor, K1 is the multiplier gain, K2 is the ratio of the MULT pin voltage vs. the line voltage, and VCOMP can a constant DC value when decoupled with a large COMP capacitor. The turn-off time varies with the instantaneous line voltage. τon = Lp ⋅ Ip Vin (Vac ,t) τoff = for Lp ⋅ Ip N ⋅ Vo τoff ( τon ,Vac ,t) = Vin (Vac ,t) ⋅ τon N ⋅ Vo (3) (4) (5) Considering the τoff limit within MP4030, the τoff equation should be modified as: Vin ( Vac , t ) ⋅ τON Vin ( Vac , t ) ⋅ τON if > 5μs N ⋅ Vo N ⋅ Vo τOFF ( τON, Vac , t ) = 5μs, otherwise (6) Figure 20 shows that the output LED current equals the average value of the secondary winding current during a half-line cycle. Equation (7) shows that the output current is the sum of the secondary current in each cycle to produce an average value. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC t1 ← a sum ← 0 Io ( a, b, T o n , V a c ,L p ) = w h ile ( t1 < b ) (7) ⎪⎧ ⎡ V ( V , t1 + τ o n ) ⋅ τ o n ⋅ ⎨ ⎢ in a c Lp ⎪⎩ ⎢⎣ + τ o ff ( τ o n , V a c , t1 + τ o n ) sum ← sum + t1 ← t1 + τ o n 1 2 ⎤ ⎪⎫ ⎥ ⋅ N ⎬ ⋅ τ o ff ( τ o n , V a c , t1 + τ o n ) ⎥⎦ ⎪⎭ sum b −a Figure 20: Secondary-Side Current Usually, the system will define a minimum frequency, fs_min, at Vin = π 2 ⋅ 108 sin( ) , and sets the 2 minimum switching frequency, fs_min=80kHz. Io (0,0.01, τON _ 108 V ,108,Lp ) = 0.35A fs _ min = 1 τON _ 108 V + τOFF ( τON _ 108V ,108,0.005) (8) = 80kHz (9) Combining (8) and (9) gets LP=1.9 mH, τON_108=5μs. The maximum primary-peak current is: Ipk _ max = τON _ 108 V ⋅ Vin (108,0.005) = 0.398A Lp (10) When estimating LP, the maximum operation frequency occurs when Vin approaches the zero crossing at 132VAC. fs _ max = AN055 Rev. 1.1 12/30/2013 τON _ 132 V 1 = 107kHz + τOFF ( τON _ 132 V ,132,0) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (11) 21 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC The Primary-Winding RMS Current: t1 ← a su m ← 0 (12) Ip ri _ rm s (a,b, To n , V a c ,L p ) = w h ile( t1 < b ) τ on V ( V , t1 + τ o n ) ⋅ t 2 1 ⎪⎧ ⎪⎫ su m ← su m + ⎨ ( in a c ) ⋅ dt⎬ ⋅ ∫ 0 τ + τ τ + τ ( , V , t1 ) L o ff on ac on p ⎩⎪ o n ⎭⎪ [τ on + τ o ff ( τ o n , V a c , t1 + τ o n ) ] t1 ← t1 + τ o n + τ o ff ( τ o n , V a c , t1 + τ o n ) su m b−a The maximum primary RMS current is then: Ipri _ rms _ max = Ipri _ rms (0,0.01, τON _ 108 V ,108,1.9 ⋅ 10 −3 ) = 0.11 A (13) The secondary winding RMS current: (14) t1 ← a sum ← 0 Isec_ rms (a,b,Ton ,Vac ,Lp ) = while(t1 < b) N4 ⋅ Vo2 Lp2 τoff ( τon ,Vac ,t1+τon ) V (V ,t1 + τ ) ⋅ τ ⎪⎧ ⎪⎫ on on − t)2 ⋅ dt ⎬ ⋅ sum ← sum + ⎨ ( in ac ∫0 N ⋅ Vo ⎩⎪ τon + τoff (τon ,Vac ,t1 + τon ) ⎭⎪ [ τon + τoff (τ on ,Vac ,t1+ τon )] t1 ← t1 + τon + τ off (τon ,Vac ,t1 + τon ) sum b−a The maximum secondary winding RMS current is: Isec_ rms _ max = Isec_ rms (0,0.01, τON _ 108 V ,108,1.9 ⋅ 10 −3 ) = 0.62 A (15) The Transformer Core Selection Select the transformer core based on output power for the entire operating frequency. Ferrite is common in flyback transformers. The core area product (AE·AW)—which is the core magnetic crosssection area multiplied by the available window area for winding—typically provides an initial core-size estimate for a given application. The following provides a rough estimate of the required area product: AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC ⎛ L ⋅I ⎞ ⋅I A E ⋅ A W = ⎜ p Pk _ max rms _ max ⎟ cm4 ⎜ B ⋅K ⋅K ⎟ max u j ⎝ ⎠ (16) Where: • Ku is winding factor which is usually 0.2 to 0.3 for an off-line transformer, • Kj is the current-density coefficient (typically 0.06 A/m2 for ferrite core), • IPk_max and Irms_max are the maximum peak current and RMS current of the primary inductor, and • Bmax is the maximum-allowed flux density under normal operation—which is usually preset to the saturation flux density of the core material (0.3T to 0.4T). So the estimated minimum core area product is 0.026 cm4. Refer to the manufacture’s datasheet to select an appropriate core with sufficient margins. Also, select a core shape to best meet the layout dimensions and audible noise limits. For this example, choosing an RM6 core provides better mechanical construction for suppressing audible noise compared to EE or EFD cores such that: • AE = 0.36 cm2, AW = 0.26 cm2, AE×AW=0.095 cm4. • The core magnetic path length: lc=2.86 cm • The relative permeability of the core material: μ γ = 2400 Primary and Secondary Winding Turns The transformer’s primary size requires a minimum number of turns to avoid saturating a given core size. The normal saturation specification is E-t, or the volt-second rating. The E-t rating is the maximum voltage, E, applied over t seconds (The E-t rating is identical to the product of inductance, L, and the peak current). Equation (17) estimates the minimum value of NP to avoid the core saturation: NP = Lp ⋅ Ipk _ max Bmax ⋅ A E × 10 4 (17) Where: Lp = the primary inductance of the transformer (H) Bmax= the maximum allowable flux density (T) AE= the effective cross sectional core area (cm2) Ipk_max= the maximum primary peak current (A) Select Bmax to be smaller than the saturation flux density, Bsat. Bmax selection also requires taking the transformer’s high-temperature characteristics into account because Bsat decreases as the temperature increases. Bmax also influences the transformer’s audible noise: a small Bmax can reduce audible noise given a narrow window area. For PC40 material, the Bmax is set to 0.27 to get NP=80. The number secondary windings is a function of the turn ratio, N, and primary turn count, NP: Ns = AN055 Rev. 1.1 12/30/2013 Np N = 16 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (18) 23 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Wire Size Once the number of windings have been determined, select the wire size to minimize the winding conduction loss and the leakage inductance. The winding loss depends on the RMS current value, and the wire length and cross section. Determine the wire size from the winding’s RMS current: Spri = Ipri _ rms _ max S sec = J = 1.83 ⋅ 10 −2 (mm 2 ) Isec_ rms _ max J = 1⋅ 10 −1(mm2 ) (19) (20) Where J is the current density of the wire, which is typically 6A/mm2. Due to the skin effect and proximity effect of the conductor, select a wire diameter less than 2×Δd (where Δd is the skin-effect depth): Δd = 1 π ⋅ fs _ min ⋅ μ ⋅ σ = 0.27(mm) (21) Where μ is the conductor’s magnetic permeability, which is usually equal to the permeability of a vacuum for most conductors (i.e. 4π × 10−7 H/m). σ is the wire’s conductivity (typically 6 × 107 S/m at 0° for copper, which increases with temperature). If the requires wire diameter exceeds 2×Δd, use multiple strands of thinner wire or Litz wire to minimize the AC resistance. Select enough strands such that the effective cross sectional area meets the current density requirement. In offline isolated applications, the whole system needs to pass the Hipot test, which requires taking the primary to secondary isolation distance into consideration. Small power systems typically use tripleinsulated wire (TIW) as the secondary winding wire to enhance the isolation distance. Using TIW negates the need for a retaining wall and conserves the transformer window area. This example uses 0.18mm×1 wire for the primary winding, 0.35mm×1 T.I.W for the secondary winding, so the wire area for the primary winding is S1=2.54×10-2 mm2, and for the secondary winding it is S2=0.97×10-1 mm2. Auxiliary Winding Wire Size The auxiliary winding’s current requirement is relatively small because it primarily provides power to VCC and detects the current zero crossing for boundary-mode operation. The auxiliary winding’s output DC voltage is proportion to the output LED voltage with a turn ratio of Naux/Ns. VCC requires high stability so that the IC can continue to function even when dimming function goes very low. Most applications VCC to go as high as 25V. Given an LED output voltage of 16V, select Naux as Naux=25/16×Ns, so Naux=19 for a 0.18mm wire. Window-Area Fill-Factor Calculation After selecting appropriate wire sizes, check whether the core window area can accommodate the windings. Calculate each winding’s required window area, respectively, then add the areas together— be sure to take the interwinding insulation and spaces into consideration. The fill factor—the winding area relative to the whole core window area—should be well below 1 due to these interwinding insulation and spaces between turns. Select a fill factor no greater than 20%. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 24 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Np ⋅ S1 + Ns ⋅ S2 + Naux ⋅ S3 A W _ RM6 = 0.15 < 0.2 (22) If the required window area exceeds the selected one, reduce either the wire size or use a larger core. However, reducing the wire size increases the transformer copper loss. Air Gap With a selected core and winding turns, the core air gap is approximately: 2 G = μ0 ⋅ AE ⋅ NP l − c = 0.3 (mm) L p μr (23) Where AE is the cross sectional area of the selected core, μ0 is the permeability of vacuum which equals 4π × 10 −7 H/m., Lp and NP is the primary winding inductance and turns respectively, lc is the core magnetic path length and μr is the relative magnetic permeability of the core material. Instructions for Transformer Manufacturing The coupling between the transformer primary side and the secondary side must be as tight as possible to minimize leakage inductance. This can be accomplished be interleaving the primary and secondary windings during transformer manufacture, as shown in Figure 21. Start with the winding connected to the drain of the high-side MOSFET first, followed by the auxiliary winding, and then the secondary winding to isolate the secondary wind from the drain to reduce parasitic capacitance and to improve the CM EMI. To meet the safety requirements, separate the transformer’s primary side and secondary side and keep a safe creepage distance of at least 6mm. Do not directly connect the auxiliary winding pin (AUX+) and the two secondary winding pins (W and B) to the transformer pins. Instead, use jumpers and connect externally, as per Figure22. 3Ts N4 1Ts N3 1Ts N2 1Ts N1 Figure 21: Transformer Winding Diagram 1 X N4 W N1 N3 2 B 6 AUX+ N2 P ri. Side 一次侧 S ec. Side 二次侧 WINDING START起绕脚 TEFLON TUBE 套管 Figure 22: Transformer Pin Out and the Connection Diagram AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 25 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC E. INPUT EMI FILTER (L1, L2, L3, CX1, CY1, C2) The input EMI filter is comprised of L1, L2, L3, CX1, with the Y-class capacitor, CY1, and input film capacitor, C2. The EMI filter has two stages with –80dB attenuation for the DM noise. Soldering the L2 and L3 inductors to the L and N lines, respective, also acts as a CM noise filter. Select component values to pass EMI test standards, as well as to account for the power factor and inrush current when dimming turns on. The input capacitance plays the primary role: a small input capacitance increase the power factor and decreases the inrush current, so select a relatively small X capacitor. F. INPUT BRIDGE (BD1) The input bridge can use standard, slow-recovery, low-cost diodes. When selecting diodes, take into account these three items: the maximum input RMS current; the maximum input-line voltage; and thermal performance. The maximum input-line voltage occurs during surge conditions, where the surge voltage across the line may exceed 600V. This example uses MB6S as the BD, with a 600V, 0.5A rating. G. INPUT CAPACITOR (C2) The input capacitor, C2, mainly provides the transformer’s switching frequency magnetizing current. The maximum current occurs at the peak of the input voltage. Limit the capacitor’s maximum highfrequency voltage ripple to 10%, or the voltage ripple can cause the primary peak current to spike and worsen both the power loss and the EMI performance. C2 > Ipk _ max − 2Ipri _ rms _ max 2 ⋅ π ⋅ fs _ min ⋅ Vac _ min ⋅ 0.1 = 44nF (24) Input capacitor selection requires taking into account the EMI filter, the power factor, and the surge current at the dimming turn-on time. A large capacitor improves EMI, but limits the power factor and increases the inrush current. This example uses a 100nF, 400V, film capacitor. H. PASSIVE BLEEDER (C5, R6, R9) AND ACTIVE DAMPER (Q2, Q3, D3, D8, C8, R4, R8, R12, R13) Since the LED lamp impedance is relatively large, significant ringing occurrs at leading edge TRIAC dimmer turn on due to a inrush current charging the input capacitance (shown in Figure 23). The ringing may cause the TRIAC current fall below the holding current and turn off the TRIAC, which can cause flickering. Figure 23: Input Current Ringing at the TRIAC's Leading-Edge Turn-On Period AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 26 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC This example incorporates both a passive bleeder and an active damper circuit to address this issue. The passive bleeder consists of an RC circuit (C5, R6, and R9 in Figure 17) installed across the input line right before the bridge rectifier. Select a bleeder capacitance larger than the input capacitor, C2, and X capacitor, CX1, to limit the bleeder current-ringing frequency below the C2 and CX1 current ringing, as shown in Figure 24; the current through the TRIAC rises when the TRIAC turns on. However, increasing the capacitance increases the power dissipation and therefore decrease efficiency. Use the minimum acceptable value. The bleeder resistor limits the bleeder current and damps the input current. The resistance requires fine-tuning: large resistors limit bleeder functionality, while small resistors limit damping and can lead to high-amplitude bleeder-current ringing. This examples uses 200nF, a total of 1.02kΩ, and a power rating of 2W. Figure 24: Input Ringing with Passive Bleeder However, Only the passive bleeder is not enough to maintain conduction in the TRIAC for many kinds of different TRIACs, then a damper is needed. The purpose of the damper is to limit the inrush current that charges the input capacitance at TRIAC turning on. There are tow kinds of dampers, passive and active. Passive damper is simple, only need hire a resistor in series with the AC input line, limited by the power dissipation, values can not be large, the values are typically from 10 to 100Ω.The passive damper may suit for power less than 5W and the effective is strongly limited by the efficiency requirement. For higher power or higher efficiency design, an active damper is required. `Shown in figure 17, the active damper is consisted of Q2, Q3, D3, D8, C8, R4, R8, R12, and R13. Resistor R13 is used for limiting the inrush current and the value can be much higher than the passive case. R4, R12, C8 forms a 1ms delay time for R13 conduction, then the MOSFET turns on and short R13. Increasing the delay time by increasing the value of capacitor C8 can improve the damping result, but cause more power dissipation. When the rectified input voltage decreasing to low, the gate of Q2 is discharged by Q3 and turned off for the next turn on interval. Figure 25 shows the effect of adding both bleeder and active damper. The ringing is effectively suppressed. I. OUTPUT CAPACITOR (C3, C4) The output voltage ripple has two components: the switching-frequency ripple associated with the flyback converter, and the low-frequency ripple associated with the input-line voltage (120Hz). Selecting the output bulk capacitor depends on the output current, the allowable overvoltage, the desired voltage ripple, and with an LED load the LED current ripple. This example has a load of 7 LEDs in series, a 350mA output current, and a current ripple set within 40% without dimming. Since the LED impedance is not resistive, the output voltage ripple refers to the LED V-I characteristics as provided by the LED manufacturer to design the output voltage ripple within 2.5%. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 27 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC The maximum RMS current of the output capacitor is: Iout _ cap _ rms _ max = Isec_ rms _ max 2 − Io _ rms2 (25) Where Io_rms is the output RMS current and Isec_rms_max is the maximum secondary RMS current from equation (15). Design the maximum RMS current to be smaller than the capacitor’s RMS current specification. The maximum switching voltage ripple occurs at the peak of the minimum-rated input line voltage, and the ripple (peak-to-peak) can be estimated by: ΔVo _ swtiching = Io _ max ⋅ τoff ( τon _ 108 V ,108, 0.005) + (Isec_ pk _ max − Io _ max ) ⋅ RESR Cout (26) Where Io_max is the maximum instantaneous output LED current with a mean value of 350mA plus a 20% peak ripple; τoff ( τon _ 108 V ,108, 0.005) is the turn-off time at the peak of the minimum-rated input line, RESR is the ESR of output capacitor (typically 0.03Ω per capacitor), and Isec_pk_max is the maximum peak current of the secondary winding. Estimate the maximum low-frequency ripple (2x the line frequency, 120Hz) from the capacitor impedance and the peak capacitor current (Io_max). ΔVo _ line = Io _ max 1 (2π ⋅ 2fline ⋅ Cout )2 + RESR 2 (27) Based on this equation, the 120Hz low-frequency ripper dominates the output voltage ripple. Set ΔVo _ line = 0.55V for Cout=1000μF. Selecting 470μF/35V bulk capacitors in parallel minimizes the ESR and distributes the capacitor RMS value. Add a 30kΩ pre-load resistor to discharge the output voltage under open-load conditions. J. RCD Snubber (R2, C1, D2) The peak voltage across the high-side MOSFET at turn-off includes the instantaneous input line voltage, the voltage reflected from the secondary side, and the voltage spike due to leakage inductance. The RCD snbber (shown in Figure 25) protects the MOSFET from over-voltage damage by absorbing the leakage inductance energy and clamping the drain voltage. The values of C1 and R2 depend on the leakage inductance energy dissipated by the RC network during each cycle. Figure 26 shows the primary high-side MOSFET output voltage ripple and the snubber capacitor at point A during the turnoff interval. Figure 25: Primary-Side RCD Snubber AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 28 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC Figure 26: A Point Voltage with a High-Side MOSFET Drain Voltage and Snubber Capacitor Estimate the energy stored in the leakage inductor at the maximum input voltage as: ELk _ max = 1 ⋅ Lleakage ⋅ Ipk _ Vin _ max 2 2 (28) Where Ipk_Vin_max is the peak current for the primary side at the maximum input voltage. Assume all the leakage inductance energy transfers to the snubber capacitor. The secondary relationship is: ELk _ max = 1 ⋅ C1⋅ ⎡⎣(Vin _ max + N ⋅ Vo + Vspike )2 − (Vin _ max + N ⋅ Vo + Vspike − ΔVC1 )2 ⎤⎦ 2 (29) Where Vspike is the spike voltage clamped by the RCD snubber, ∆VC1 is the snubber capacitor’s voltage change caused by the leakage inductance. Assuming ∆VC1 << Vspike, and the 1 ⋅ 2π ⋅ L leakage ⋅C1 < τVin _ max , 4 ΔVC1 = Vspkie（ ⋅ 1− e Where t1 is the time τ Vin _ max − − t1 R2⋅C1 ） (30) 1 ⋅ 2π ⋅ L leakage ⋅C1 , and τVin_max is the switching period at Vin_max. 4 To select R2, take into account the secondary-side reflecting voltage because it contributes to the snubber resistance after the MOSFET turns off. Select R2 to be large enough to reduce the reflecting voltage loss, but avoid contributing to a clamping voltage that exceeds the selected MOSFET based on equation (1). Based on equations (6), (7), and (10), Ipk_Vin_max=0.36A, τon_132V=3.7μs, and τvin_max=10.5μs. The leakage inductance is estimated as 1% of the primary inductance, 20μH. Select the snubber parameters: C1=22nF, R2=499kΩ for VSPIKE=150V and ∆VC1=0.13V. Select a snubber capacitor with a higher voltage rating than the spike voltage, and a diode voltage rating higher than Vin_max + Vspike—use a normal-recovery diode, such as a 1N4007, which has better EMI performance than a fast-recovery diode. Given the difficulty in theoretically calculating the power dissipation of the snubber resistor R1, monitor the resistor’s thermal performance during testing to determine the final appropriate value. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 29 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC K. HIGH-SIDE MOSFET GATE DRIVER (R5, R10, C7, D4, D6) The rectified line voltage initially charges the high-side MOSFET gate through R5. C7 To stabilizes the gate voltage when line voltage goes low; typically 100nF suffices for most dimming conditions. Zener diode, D6, clamps the gate voltage to avoid damaging the MOSFET. Select a clamping voltage that exceeds 16V to ensure the VCC voltage can charge to 10V through point D. R5 and C7 introduces a delay; reducing R5 reduces the delay, but increases power dissipation. For C7 = 100nF, select R5 in the 510kΩ-to-1MΩ range for a delay time of less than 10ms— much shorter than the system start-up time. Under deep dimming conditions the low line voltage can not remain the gate voltage ON without another power supply and ultimately limits dimming range or causes flickers. Connect an auxiliary winding through a rectifying diode improves the high-side MOSFET gate voltage for deeper dimming. Select the rectifying diode based on the voltage rating (as per equation (31)). Since the positive auxiliary winding voltage is 25V—which is higher than the 16V gate-clamping voltage—it needs a resistor to limit the current. The resistor value balance power dissipation and charging capability—this example uses a 357Ω resistor with a 0.25W power tolerance. L. VCC POWER SUPPLY (R11, C12, D5, D10) Page 13 shows the detailed VCC operation timing sequence. After system starts up, the auxiliary winding takes over the VCC power supply through a rectifying diode (D5) with a current-limiting resistor (R11). The bulk capacitor (C12) stabilizes the VCC voltage to limit the ripple—most applications use 22μF. Since the VCC maximum voltage is 30V, use a Zener diode (D10) to protect the VCC pin under open-load conditions, and to minimize the power dissipation. Set the clamping voltage as high as 27V. Use a relatively small current-limit resistor (R11) because of the limited power dissipation. Use the following equation to determine the D5 voltage rating: VD5 > VCCmax + Naux ⋅ Vin _ max + Vaux _ negtive _ spike Np (31) Where VCCmax is the maximum VCC voltage, in this case, VCCmax= 27V, Naux and Np are the auxiliary winding and primary winding turns, Vaux_negtive_spike is the maximum negative spike on auxiliary winding, in this case, Vaux_negtive_spike= 40V, so D5 need a voltage rating higher than 100V. M. ZCD AND OVP DETECTOR (R14, R19, C11) Refer to information starting on page 11 for additional information. The resistor divider, R14 and R19, sets the OVP threshold: Vo _ ovp ⋅ Naux R19 ⋅ = 5.5V Ns R14 + R19 (32) Where Vo _ ovp is the output OVP voltage, Naux is the number of transformer auxiliary winding turns, and Ns is the number of transformer secondary winding turns. Given Naux=19, Ns=16, set Vo_ovp=30V for R14/R19=5.4. Consider Vin _ max = 132 ⋅ 2 and the ZCD source current limitation, select R14=39kΩ, R19=7.2kΩ. Add a 10pF ceramic bypass capacitor (C11) to the ZCD pin to absorb the high-frequency ring on ZCD due to the MOSFET turning off and can cause the OVP function to mis-trigger. The resistor and capacitor form a delay time for the ZCD turn-on signal detector, and influences the output current-line regulation accuracy, so avoid large RC values. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 30 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC N. MULT PIN RESISTOR DIVIDER (R3, R17, C10) The MULT pin resistor divider needs to be carefully tuned because the MULT voltage determines the COMP voltage level, which directly influences the dimming curve and performance (refer to information on page 10). Test the estimated divider values with different types of TRIAC dimmers to determine accurate resistor values: this example uses R3=1MΩ and R17=11kΩ for a COMP level of 2.3V at 120VAC input. The C10 is absorbs the switching frequency ripple on the ZCD voltage for accurate dimming-phase detection. Increasing the capacitance can further smooth the ZCD voltage, but increase the input-line voltage phase shift and cause diminish the power factor. Here, C10 is tuned to 2.2nF. O. CURRENT SENSING RESISTOR (R20, R21, R24) As described on page 14, approximate the current sensing resistor with the following equation: Rs ≈ Vref ⋅ N 2 ⋅ Io (33) Where N is the turn ratio of primary winding to secondary winding, Vref is the feedback reference voltage (typically 0.4V), and Rs is the sense resistor between the S pin and GND. Equation (33) describes RS under BCM, but the device may enter DCM during a line cycle due to the minimum off-time limitation and a missing ZCD turn-on signal. The DCM influences and other factors also influence the output current through primary-side control, such as the IC’s internal logic delay, the transformer inductance, and the ZCD detection delay. These factors make estimating the output current difficult, and why designing the current sensing resistor last provides allows for better fine-tuning for the required output current. In this case, the sensing resistor is tuned to 2.2Ω, using two 1.1 Ω/0.25W resistors in series to distribute the power dissipation. P. OCP DETECTOR (R18, R22, D9) Refer to page 11 for detailed design information. Calculate the primary-side OCP set-point as: Ip _ OCP ⋅ Rs ⋅ R22 − VD9 = 0.9 R22 + R18 (34) Where IP_OCP is the primary-side over-current–protection value and VD9 is the D9 diode voltage drop. Using the 1N4148 diode, the VD9 is approximately 0.4V. Using equation (10), the primary maximum current is 0.398A to set the primary OCP current to about 2x the primary maximum current, IP_OCP=0.8A. Then R18/R22=0.35, where R22=510Ω and R18=180Ω. Q. LAYOUT GUIDELINE • Design the main power flow path as short as possible using wide wires. Design the sense resistor GND return to directly connect to the input capacitor, C2. Use the largest-possible cooper pour for the power devices for good thermal performance. • Separate the power GND and the analog GND, and connect them together only at an IC GND pin. • Placed the IC pin components as close as possible to the corresponding pins. Provide the ZCD pin bypass capacitor and the COMP pin capacitor layout priority. • Isolate the primary side and the secondary side by at least 4mm to meet safety requirements and the Hipot test. Tune the transformer installation position to keep the primary side far away from secondary side. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 31 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC • In order to pass the surge test, separate the input high voltage wire from other components and GND. Connect R3, R4, and R5 to the rectified input line for the DIP package. • On the secondary side, place the rectifying diode as close as possible to the output filter capacitor, and use a short trace from the transformer output return pin to the return point of the output filter capacitor. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 32 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC R. BOM Quantity 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 3 2 1 1 1 1 1 2 1 1 1 3 1 2 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Designator BD1 C1 C2 C3,C4 C5 C6 C7 C8 C9 C10 C11 C12 CX1 CY1 D1 D2 D3,D7,D9 D4,D5 D6 D8 D10 F1 L1 L2, L3 Q1 Q2 Q3 R1,R16,R15 R2 R3,R4 R5 R6,R9 R7 R8 R10,R11 R12 R13 R14 R17 R18 R19 R20 R21 R22 R23 R24 RV1 T1 U1 AN055 Rev. 1.1 12/30/2013 Value Description MB6S BRIDGE, 600V, 0.5A 22nF/630V Ceramic Cap, 630V，X7R 100nF/400V 104/400v 470uF/35V Electrolytic Capacitor, 35V, Electrolytic 220nF/400V CBB,400V 68pF/630V Ceramic Cap,COG,630V 0.1uF/50V Ceramic Cap,X7R,50V 33nF Ceramic Cap,50V,X7R 10uF/10V Ceramic Capacitor;16V;X7R;0805 2.2nF/50V Ceramic Cap,X7R,50V 10pF Ceramic Cap,50V,COG 22uF/50V Electrolytic Capacitor;50V;Electrolytic 10nF X Capacitor,275V 2.2nF Y Capacitor,250V MURS320T3 Diodes,200V,3A 1N4007 Diodes,1000V,1A 1N4148W DIODES/SOD-123 ES1D Diode, 1A,200V BZT52C16 Zener DIODES/16V, 5mA BZT52C15 Zener Diode, 15V, 5mA BZT52C27 Zener Diode, 27V, 2mA 250V/2A SS-5-2A Inductor,1.8mH Inductor,1.8mH/0.3A 4.7mH Inductor, 4.7mH/0.24A AP03N70I 600V/3.3A MMBT3906LT1 PNP, transistor SMK0260D MOSFET, 600V, 2A 1kΩ Film RES,1% 499kΩ Film RES, 1% 1MΩ DIP,0.25W RESISTOR 510k DIP,0.5W RESISTOR 510Ω DIP,1W RESISTOR 30kΩ Film RES,1% 10Ω Film RES, 1% 357Ω Film RES,1% 130kΩ Film RES,1% 510Ω DIP,2W RESISTOR 39kΩ Film RES,1% 11kΩ Film RES, 1% 180Ω Film RES,1% 7.2kΩ Film RES,1% NC 1.1Ω Film RES,1% 510Ω Film RES,1% 510Ω DIP,0.25W RESISTOR 1Ω Film RES,1% TVR10431KSY 430V/2500A RM6 RM6, Np:Ns:Naux=80:16:19, Lp=1.9mH MP4030 MP4030 Package SOIC-4 1206 DIP DIP DIP 1206 0603 0603 0805 0603 0603 DIP DIP DIP SMC DO-41 SOD-123 SMA SOD-123 SOD-123 SOD-123 DIP DIP DIP TO-220 SOT-23 TO-252 1206 1206 DIP DIP DIP 1206 0603 1206 0603 DIP 0603 0603 0603 0603 Manufacturer Taiwan Semiconductor TDK Panasonic Rubycon Panasonic muRata muRata muRata muRata muRata muRata Jianghai Kaili Hongke ON Semi Diodes Diodes Premier Diodes Diodes Diodes any Wurth Wurth APEC ON Semi AUK Royalohm Panasonic Manufactuer_P/N MB6S C3216X7R2J223K CBB 0.1uF/400V 470uF/35V ECQE4224KF GRM31A7U2J680JW31D GRM188R71H104KA93D GRM188R71H333KA61D GRM21BR61C106KE15 GRM188R71H222KA01 GRM1885C1H100JA01 Royalohm Yageo Yageo Yageo 1206F3002T5E RC0603FR-0710RL RC1206FR-07357RL RC1206FR-07130KL Yageo Yageo Yageo Yageo RC1206FR-0739KL RC0603FR-0711KL RC1206FR-07180L RC1206FR-077K2L 1206 0603 DIP 1206 DIP RM6 SOIC8 Yageo Yageo RC1206FR-071R1L RC1206FR-07510L Yageo TKS EMEI MPS RC1206FR-071RL TVR10431KSY PX103K3ID49L270D9R JY10F332MY72N MURS320T3 1N4007 1N4148W ES1D BZT52C16 BZT52C15 BZT52C27 758772182 744772472 AP03N70I MMBT3906LT1 SMK0260D 1206F1001T5E ERJ8EF4993V www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. MP4030 33 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 5. EXPERIMENTAL RESULT All measurements performed at room temperature 5.1 PERFORMANCE DATA Vin (VAC) Pin (W) PF THD Io (A) Vo (V) efficiency 108 9.58 0.993 7.00% 0.36 21.62 81.2% 120 9.54 0.99 9.50% 0.364 21.65 82.6% 132 9.47 0.982 11.60% 0.364 21.64 83.1% 5.2 STEADY STATE IO, 200mA/div VCC, 10V/div VCOMP, 1V/div VD, 10V/div Figure 28: 120VAC, Full Load, 10ms/div 5.3 INPUT VOLTAGE AND CURRENT Figure 29: 120VAC, Full Load, 10ms/div AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 34 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 5.4 BOUNDARY CONDUCTION OPERATION VS, 1V/div VZCD, 2V/div VD, 10V/div Figure 30: 120VAC, Full Load, 10µs/div 5.5 START UP IO, 200mA/div VCC, 10V/div VCOMP, 1V /div VD, 10V/div Figure 31: 120VAC, Full Load, 40ms/div AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 35 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 5.6 OVP (OPEN LOAD AT NORMAL OPERATION) IO, 200mA/div VCC, 10V/div VCOMP, 1V /div VD, 10V/div Figure 32: 120VAC, 1s/div VO, 10V/div Figure 33: 120VAC, 1s/div 5.7 SCP (SHORT LED+ TO LED– AT NORMAL OPERATION) IO, 200mA/div VCC, 10V/div VCOMP, 2V /div VD, 10V/div Figure 34: 120V, 400ms/div AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 36 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC VD, 10V/div IO, 200mA/div Figure 35: 120VAC, 100ms/div 5.8 TRIAC DIMMING VCOMP, 1V /div IO, 100mA/div VMULT, 1V/div IIN, 200mA/div Figure 36: 120VAC, D=60%, 4ms/div VCOMP, 1V /div IO, 100mA/div VMULT, 1V/div IIN, 200mA/div Figure 37: 120VAC, D=40%, 4ms/div AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 37 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC VCOMP, 1V /div IO, 5mA/div VMULT, 1V/div IIN, 200mA/div Figure 38: 120VAC, D=20%, 4ms/div Dimming Curve 400 Io (mA) 350 300 250 200 150 100 50 0 0.0% 20.0% 40.0% 60.0% Dimming duty 80.0% 100.0% Figure 39: Dimming Curve AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 38 AN055 –TRIAC-DIMMABLE, PRIMARY-SIDE–CONTROL, OFFLINE LED CONTROLLER WITH ACTIVE PFC 5.9 THERMAL PERFORMANCE Test Conditions: Full load, Normal operation for 30min, room temp=18°C 5.10 CONDUCTED EMI NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN055 Rev. 1.1 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 39