Memory ICs 1, 2, and 4k bit EEPROMs for direct connection to serial ports BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Features ••BR9010 / F / FV (1k bit): 64 words × 16 bits BR9020 / F (2k bit): 128 words × 16 bits BR9040 / F (4k bit): 256 words × 16 bits •Single power supply operation •Serial data input and output •Automatic erase-before-write •Low current consumption –1.5mA (max.) active current: 3V –2µA (max.) standby current: 3V •Noise filter built into SK pin •Compact DIP8, SOP8, SSOP-B8 packages (SSOPB8 is available only with BR9010). •100,000 ERASE / WRITE cycles •10 years Data Retention •Easily connects to serial port •Pin assignments 8 VCC R / B∗ 1 7 R / B∗ VCC 2 3 6 WC CS 3 4 5 GND SK 4 CS 1 SK 2 DI DO BR9010 / BR9020 / 9040 BR9010F / BR9010FV / BR9020F / BR9040F 8 WC 7 GND 6 DO 5 DI ∗ This pin is N.C. (non connection) on BR9010. •Pin description Pin name Function CS Chip select input SK Serial data clock input DI Operating code, address, and serial data input DO Serial data output GND Reference voltage for all I / O, 0V WC Write control input R /B READY, BUSY status signal output VCC Power supply connection •TheOverview BR90 series are serial EEPROMs that can be connected directly to a serial port and can be erased and written electrically. Writing and reading is performed in word units, using four types of operation commands. Communication occurs through CS, SK, DI, and DO pins, WC pin control is used to initiate a write disabled state, enabling these EEPROMs to be used as one-time ROMs. During writing, operation is checked via the internal status check. 1 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs •Block diagram BR9010 / F / FV CS Command decode Power supply voltage detector Control Clock generation SK Command register DI Write disable Address buffer High voltage generator Address decoder 6bit 6bit WC 1024bit EEPROM Data register DO 16bit array R/W amplifier 16bit BR9020 / F, BR9040 / F R/B CS Command decode Power supply voltage detector Control SK DI Clock generation Command register Write disable Address buffer 7 (8) bit High voltage generator Address decoder 7 (8) bit WC 2,048 (4,096) bit EEPROM Data register DO ∗ Values in parentheses are for the BR9040 / F. 2 16bit R/W amplifier 16bit array BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs •Absolute maximum ratings (Ta = 25°C) Parameter Applied voltage Power dissipation Symbol VCC Pd Limits Unit – 0.3 ~ + 7.0 DIP8 500∗1 SOP8 350∗2 SSOP-B8 300∗3 V mW Storage temperature Tstg – 65 ~ + 125 °C Operation temperature Topr – 40 ~ + 85 °C Input voltage — – 0.3 ~ VCC + 0.3 V ∗ Reduced by 5.0mw∗1 / 3.5mw∗2 / 3.0mw∗3 for each increase in Ta of 1°C over 25°C. •Recommended operating conditions Parameter Symbol Power supply voltage VCC Input voltage VIN Limits Unit 2.7 to 5.5 (write) V 2.0 to 5.5 (read) V 0 ~ VCC V 3 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs Electrical characteristics •BR9010 / F / FV: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter Symbol Min. Typ. Input low level voltage 1 VIL1 — — Input high level voltage 1 VIH1 0.7 × — Input low level voltage 2 VIL2 — Max. 0.3 × = 5V ± 10%) Unit Conditions V DI Pin — V DI Pin 0.2 × V CS, SK, WC Pin — V CS, SK, WC Pin — 0.4 V IOL = 2.1mA — VCC V IOH = – 0.4mA µA VIN = 0V ~ VCC VCC VCC — VCC VIH2 Input high level voltage 2 0.8 × — VCC Output low level voltage VOL Output high level voltage VOH 0 VCC – 0.4 ILI –1 — 1 Output leak current ILO –1 — 1 µA VOUT = 0V ~ VCC CS = VCC Consumption current during operation ICC1 — — 2 mA f = 1MHz tE / W = 10ms (WRITE) ICC2 — — 1 mA f = 1MHz (READ) Standby current ISB µA CS, SK, DI, WC, = VCC DO = OPEN fSK — — 3 SK frequency — — 1 MHz Input leak current — BR9010 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, VCC = 3V ± 10%) Parameter Symbol Min. Typ. VIL1 — — Input low level voltage 1 Max. 0.3 × Unit Conditions V DI Pin VCC Input high level voltage 1 VIH1 Input low level voltage 2 VIL2 Input high level voltage 2 VIH2 Output low level voltage VOL Output high level voltage VOH 0.7 × — — V DI Pin — — 0.2 × V CS, SK, WC Pin 0.8 × — — V CS, SK, WC Pin — 0.4 V IOL = 100µA — VCC V IOH = – 100µA VCC VCC VCC 0 VCC – 0.4 Input leak current ILI –1 — 1 µA VIN = 0 ~ VCC Output leak current ILO –1 — 1 µA VOUT = 0 ~ VCC CS = VCC Consumption current during operation ICC1 — — 1.5 mA f = 1MHz tE / W = 15ms (WRITE) ICC2 — — 500 µA f = 1MHz (READ) Standby current ISB — — µA CS, SK, DI, WC, = VCC DO = OPEN fSK — — 2 SK frequency 1 MHz 䊊 Not designed for radiation resistance 4 — BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs characteristics •Electrical BR9020 / F: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V • CC Parameter = 5V ± 10%) Symbol Min. Typ. Max. Unit Input low level voltage 1 VIL1 — — 0.3 × VCC V DI Pin Conditions Input high level voltage 1 VIH1 0.7 × VCC — — V DI Pin Input low level voltage 2 VIL2 — — 0.2 × VCC V CS, SK, WC Pin Input high level voltage 2 VIH2 0.8 × VCC — — V CS, SK, WC Pin Output low level voltage VOL 0 — 0.4 V IOL = 2.1mA Output high level voltage VOH VCC – 0.4 — VCC V IOH = – 0.4mA Input leak current ILI –1 — 1 µA VIN = 0V ~ VCC Output leak current ILO –1 — 1 µA VOUT = 0V ~ VCC CS = VCC Consumption current during operation ICC1 — — 2 mA fSK = 1MHz tE / W = 10ms (WRITE) ICC2 — — 1 mA fSK = 1MHz (READ) Standby current ISB — — 3 µA CS, SK, DI, WC, = VCC DO, R / B = OPEN SK frequency fSK — — 1 MHz •BR9020 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter — = 3V ± 10%) Symbol Min. Typ. Max. Unit Conditions Input low level voltage 1 VIL1 — — 0.3 × VCC V DI Pin Input high level voltage 1 VIH1 0.7 × VCC — — V DI Pin Input low level voltage 2 VIL2 — — 0.2 × VCC V CS, SK, WC Pin Input high level voltage 2 VIH2 0.8 × VCC — — V CS, SK, WC Pin Output low level voltage VOL 0 — 0.4 V IOL = 100µA Output high level voltage VOH VCC – 0.4 — VCC V IOH = – 100µA ILI –1 — 1 µA VIN = 0V ~ VCC Output leak current ILO –1 — 1 µA VOUT = 0V ~ VCC CS = VCC Consumption current during operation ICC1 — — 1.5 mA fSK = 1MHz tE / W = 15ms (WRITE) ICC2 — — 500 µA fSK = 1MHz (READ) Standby current ISB — — 2 µA CS, SK, DI, WC, = VCC DO, R / B = OPEN SK frequency fSK — — 1 MHz Input leak current — 5 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs characteristics •Electrical BR9040 / F: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V • CC Parameter = 5V ± 10%) Symbol Min. Typ. Max. Unit Input low level voltage 1 VIL1 — — 0.3 × VCC V DI Pin Conditions Input high level voltage 1 VIH1 0.7 × VCC — — V DI Pin Input low level voltage 2 VIL2 — — 0.2 × VCC V CS, SK, WC Pin Input high level voltage 2 VIH2 0.8 × VCC — — V CS, SK, WC Pin Output low level voltage VOL 0 — 0.4 V IOL = 2.1mA Output high level voltage VOH VCC – 0.4 — VCC V IOH = – 0.4mA Input leak current ILI –1 — 1 µA VIN = 0V ~ VCC Output leak current ILO –1 — 1 µA VOUT = 0V ~ VCC CS = VCC Consumption current during operation ICC1 — — 2 mA fSK = 1MHz tE / W = 10ms (WRITE) ICC2 — — 1 mA fSK = 1MHz (READ) Standby current ISB — — 3 µA CS, SK, DI, WC, = VCC DO, R / B = OPEN SK frequency fSK — — 1 MHz •BR9040 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter Symbol — = 3V ± 10%) Min. Typ. Max. Unit Conditions Input low level voltage 1 VIL1 — — 0.3 × VCC V DI Pin Input high level voltage 1 VIH1 0.7 × VCC — — V DI Pin Input low level voltage 2 VIL2 — — 0.2 × VCC V CS, SK, WC Pin Input high level voltage 2 VIH2 0.8 × VCC — — V CS, SK, WC Pin Output low level voltage VOL 0 — 0.4 V IOL = 100µA Output high level voltage VOH VCC – 0.4 — VCC V IOH = – 100µA Input leak current ILI –1 — 1 µA VIN = 0V ~ VCC Output leak current ILO –1 — 1 µA VOUT = 0V ~ VCC CS = VCC Consumption current during operation ICC1 — — 1.5 mA fSK = 1MHz tE / W = 15ms (WRITE) ICC2 — — 500 µA fSK = 1MHz (READ) Standby current ISB — — 2 µA CS, SK, DI, WC, = VCC DO, R / B = OPEN SK frequency fSK — — 1 MHz VCC = 3.0 ~ 3.3V — — 750 kHz VCC = 2.7 ~ 3.0V 6 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs Operation timing characteristics •BR9010 / F / FV: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 5V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time tPD1 — — 350 ns DO fall delay time tPD0 — — 350 ns Self-timing programming cycle tE / W — — 10 ms tCS 1 — — µs CS minimum high level time Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time tWH 450 — — ns Data clock low level time tWL 450 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns •BR9010 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 3V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time tPD1 — — 350 ns DO fall delay time tPD0 — — 350 ns Self-timing programming cycle tE / W — — 15 ms tCS 1 — — µs CS minimum high level time Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time tWH 450 — — ns Data clock low level time tWL 450 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns 7 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs Operation timing characteristics •BR9020 / F / FV: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 5V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time tPD1 — — 350 ns DO fall delay time tPD0 — — 350 ns Self-timing programming cycle tE / W — — 10 ms tCS 1 — — µs READY / BUSY display valid time tSV — — 1 µs Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time tWH 450 — — ns Data clock low level time tWL 450 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns CS minimum high level time •BR9020 / F / FV: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 3V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time tPD1 — — 350 ns DO fall delay time tPD0 — — 350 ns Self-timing programming cycle tE / W — — 15 ms CS minimum high level time tCS 1 — — µs READY / BUSY display valid time tSV — — 1 µs Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time tWH 450 — — ns Data clock low level time tWL 450 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns 8 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs Operation timing characteristics •BR9040 / F: At 5V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 5V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time tPD1 — — 350 ns DO fall delay time tPD0 — — 350 ns Self-timing programming cycle tE / W — — 10 ms tCS 1 — — µs READY / BUSY display valid time tSV — — 1 µs Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time tWH 500 — — ns Data clock low level time tWL 500 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns CS minimum high level time •BR9040 / F: At 3V (unless otherwise noted, Ta = – 40 to + 85°C, V CC Parameter = 3V ± 10%) Symbol Min. Typ. Max. Unit CS setup time tCSS 200 — — ns CS hold time tCSH 0 — — ns Data setup time tDIS 150 — — ns Data hold time tDIH 150 — — ns DO rise delay time VCC = 3.0 ~ 3.3V tPD1 — — 350 ns DO fall delay time VCC = 3.0 ~ 3.3V tPD0 — — 350 ns DO rise delay time VCC = 2.7 ~ 3.0V tPD1 — — 500 ns DO fall delay time VCC = 2.7 ~ 3.0V tPD0 — — 500 ns Self-timing programming cycle tE / W — — 15 ms CS minimum high level time tCS 1 — — µs READY / BUSY display valid time tSV — — 1 µs Time when DO goes High-Z (via CS) tOH 0 — 400 ns Data clock high level time VCC = 3.0 ~ 3.3V tWH 500 — — ns Data clock low level time VCC = 3.0 ~ 3.3V tWL 500 — — ns Data clock high level time VCC = 2.7 ~ 3.0V tWH 650 — — ns Data clock low level time VCC = 2.7 ~ 3.0V tWL 650 — — ns Write control setup time tWCS 0 — — ns Write control hold time tWCH 0 — — ns 9 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs •Input / output circuits (1) Input circuits RESET int. CS int. CS SK CS int. WC DI (2) Output circuits DO DO / F / FV ∗ DO: BR9010 BR9020 / F ∗ DO: BR9040 / F OE int. OE int. R/B R / B: BR9020 / F, BR9040 / F operation •(1)Circuit Command mode Command Start bit Operating code Address Data Read (READ) 1010 1000 A0 A1 A2 A3 A4 A5 (A6) 夽2 (A7) 夽1 Write (WRITE) 1010 0100 A0 A1 A2 A3 A4 A5 (A6) 夽2 (A7) 夽1 Erase / Write enabled (EWEN) 1010 0011 Erase / Write disable (EWDS) 1010 0000 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Either VIH or VIL With BR9020 / F, With BR9010 / F / FV, 10 夽1 is ‘0’ 夽1 and 2 are ‘0’ ∗ ∗ D0 D1—D14 D15 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs (2) Timing chart tCS CS tWH tCSS tCSH SK tWL tDIH tDIS DI tPD tPD tOH DO WC • Data is read in on the rising edge of SK. Data is output in synchronism with the SK falling edge. • During a READ operation, data is output from DO in synchronization with the SK rise. • WC is related to the write command only. Read, erase / write enable, erase / write disable commands can be executed irrespective of the state of WC. (3) Writing enabled / disabled H 1 SK L 4 8 12 16 ENABLE = 1 1 DISABLE = 0 0 H CS L H DI 1 0 1 0 0 0 L High-Z DO H R/B WC H or L Fig.1 1) When the power supply is turned on, the latch used to acknowledge writing is reset in the same way as when the write disable command is executed. Before entering the write mode, the write enabled mode must first be entered. Once the write enabled mode has been recognized, it remains valid until the write disabled mode is entered, or the power supply is turned off. 2) The clock is no longer necessary after the first 16 clock pulses have been received. Any subsequent input will be ignored. 3) WC does not exist for either the write enabled or write disabled command, so WC may be either HIGH or LOW when the command is being input. 4) Commands are received in these modes by means of 8-bit operating codes. Please be aware that, after an operating code has been entered, commands will not be canceled even if CS is set to HIGH. (To cancel a command, either turn off the power supply, or input the command once again.) 11 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs operation •(4)Circuit Read cycle H SK 1 L 4 8 16 32 tCS H CS L STANDBY H DI 1 0 1 0 1 0 0 0 A0 A5 0 0 L High-Z DO D0 High-Z D15 tOH WC H or L Fig.2 BR9010 / F / FV H SK 1 L 4 8 16 32 tCS H CS L STANDBY H DI 1 0 1 0 1 0 0 0 A0 A6 0 L High-Z DO D0 High-Z D15 tOH H R/B WC H or L Fig.3 BR9020 / F H SK 1 L 4 8 16 32 tCS H CS L STANDBY H DI 1 0 1 0 1 0 0 0 A0 A6 A7 L High-Z DO D0 High-Z D15 tOH H R/B WC H or L Fig.4 BR9040 / F 1) After the fall of the 16th clock pulse, 16-bit data is output from the DO pin in synchronization with the falling edge of the SK signal. (DO output changes at a time lag of tPD0, tPD1 because of internal circuit delay following the falling edge of the SK signal. During the tPD0 and tPD1 timing, the tPD time should be assured before data is read, to avoid the previous data being lost. See the synchronized data input / output timing chart in Fig. 1.) 12 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs operation •(5)Circuit Writing cycle H 4 1 SK 16 8 32 L H CS L tCS H DI L 1 0 1 0 0 1 0 0 A0 A5 0 0 D0 D15 High-Z DO High-Z tE / W H WC L tWCH tWCS Fig.5 BR9010 / F / FV H SK 4 1 L 8 16 32 H CS L tCS H 1 DI 0 1 0 1 0 0 A0 0 A6 0 D15 D0 High-Z High-Z DO tSV tE / W H R/B H WC tWCS L tWCH Fig.6 BR9020 / F H SK 1 L 4 8 16 32 H CS L tCS H 1 DI 0 1 0 0 1 0 0 A0 A6 A7 D0 D15 High-Z High-Z DO tSV tE / W H R/B H WC L tWCS tWCH Fig.7 BR9040 / F 13 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs 1) During input in the write mode, CS must be LOW, but once writing starts, CS may be either HIGH or LOW. However, if CS and WC share the same connection, both CS and WC should be set to LOW during writing operations. (If the WC pin is set to HIGH during a writing operation, writing will be forcibly interrupted at that point. If this happens, the data for that address may be lost, in which case it should be rewritten to that address.) 2) Following input of a write command, CS goes HIGH. If CS is then set to LOW, data will be received from SK and DI, because the command reception status has been entered. If CS remains LOW following command input, however, without first going HIGH, command input will be canceled until CS is set to HIGH. 3) Starting from the rising edge of the 32nd clock, the R / B pin goes LOW after RSV has elapsed. 4) The R / B pin is LOW during writing operations. (Following the rising edge of SK after the last data D15 has been read, the internal timer circuit is activated, and writing of data in the memory cell is automatically completed during tE / W.) At this point, SK input may be either HIGH or LOW during tE / W. 5) Following input of a write command, if CS falls while SK is LOW, the R / B status can be displayed from the DO pin. (See the section on READY / BUSY states.) (6) READY / BUSY display (R / B pin and DO pin) 1) This display outputs the internal status signal; the R / B pin outputs the HIGH or LOW status at all times. The display can also be output from the DO pin. Following completion of the writing command, if CS falls while SK is LOW, either HIGH or LOW is output. (The display can also be output without using the R / B pin, leaving it open.) 2) When writing data to a memory cell, the READY / BUSY display is output from the rise of the 32nd clock pulse of the SK signal after tSV, from the R / B pin. R / B display = LOW: writing in progress (The internal timer circuit is activated, and after the tE / W timing has been created, the timer circuit stops automatically. Writing of data to the memory cell is done during the tE / W timing, during which time other commands cannot be received.) R / B display = HIGH: command standby state (Writing of data to the memory cell has been completed and the next command can be received.) SK Clock CS Write command DI HIGH-Z R/B tPD tOZ READY DO BUSY READY BUSY Fig.8 R / B status output timing 14 READY HIGH-Z BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs notes •(1)Operation Turning the power supply on and off 1) When the power supply is turned on and off, CS should be set to HIGH ( = VCC). 2) When CS is LOW, the command input reception state (active) is entered. If the power supply is turned on in this state, erroneous operations and erroneous writing can occur because of noise and other factors. To avoid this, make sure CS is set to HIGH ( = VCC) before turning on the power supply. (Good example) Here, the CS pin is pulled up to VCC. When turning off the power supply, wait at least 10msec before turning it on again. Failing to observe this condition can result in the internal circuit failing to be reset when the power supply is turned on. (Bad example) CS is LOW when the power supply is turned on or off In this case, because CS remains LOW, the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors. ∗ Please be aware that the case shown in this example can also occur if CS input is HIGH-Z. VCC VCC GND VCC CS GND Good example Bad example (2) Noise countermeasures 1) SKnoise If noise occurs at the rise of the SK clock input, the clock is assumed to be excessive, and this can cause malfunction because the bits are out of alignment. 2) WC noise During a writing operation, noise at the WC pin can be erroneously judged to be data, and this can cause writing to be forcibly interrupted. 3) VCC noise Noise and surges on the power supply line can cause malfunction. We recommend installing a bypass capacitor between the power supply and ground to eliminate this problem. 15 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs (3) Canceling modes 1) Read commands SK 32 Clock CS Start bit DI Operating code 4 bits Address 4 bits 8 bits 16 bits DO DO Data D15 Cancel can be performed for the entire read mode space WC H or L Cancellation method: CS HIGH 2) Write commands SK 32 clock CS DI Start bit Operating code Address DO 4 bits 4 bits 8 bits Data D15 16 bits tE / W R/B a b c d WC Canceling methods a: Canceled by setting CS HIGH. The WC pin is not involved. b: If the WC pin goes HIGH for even a second, writing is forcibly interrupted. Cancellation occurs even if the CS pin is HIGH. At this point, data has not been written to the memory, so the data in the designated address has not yet been changed. c: The operation is forcibly canceled by setting the WC pin to HIGH or turning off the power supply (although we do not recommend using this method). The data in the designated address is not guaranteed and should be written once again. d: If CS is set to HIGH while the R / B signal is HIGH (following the tE / W timing), the IC is reset internally, and waits for the next command to be input. 16 BR9010 / BR9010F / BR9010FV / BR9020 / BR9020F / BR9040 / BR9040F Memory ICs •External dimensions (Units: mm) 9.3 ± 0.3 1 4 3.0 ± 0.2 0.5 ± 0.1 2.54 0°~15° 5 1 4 4.4 ± 0.2 6.4 ± 0.3 0.3 ± 0.1 0.1 1.15 ± 0.1 3.2 ± 0.2 3.4 ± 0.3 0.51Min. 7.62 8 (0.52) 0.15 ± 0.1 5 6.5 ± 0.3 8 0.65 0.22 ± 0.1 0.3Min. 0.1 DIP8 SSOP-B8 1 4 0.11 1.27 0.15 ± 0.1 4.4 ± 0.2 5 1.5 ± 0.1 6.2 ± 0.3 5.0 ± 0.2 8 0.4 ± 0.1 0.3Min. 0.15 SOP8 17