™ Le79489 Subscriber Line Interface Circuit Ve580 Series DISTINCTIVE CHARACTERISTICS Low standby power (normal and reverse) On-chip ring and test relay drivers and relay snubber circuits Automatic on-chip battery switching Polarity reversal (full transmission) On-chip thermal management Loop and ground-key detector On-chip thermal shutdown Comparator for ring-trip detection –20 V to –60 V battery operation Ground-start capability Programmable current limit On-hook transmission Ideal for low power sensitive applications Programmable resistive feed Programmable loop-detect threshold Selectable overhead for metering applications Two-wire impedance set by single external impedance BLOCK DIAGRAM TMG DA DB Test Relay Driver A(TIP) Ring Relay Driver TESTOUT RINGOUT C1 Ring-Trip Comparator HPA Two-Wire Interface Ground-Key Detector HPB Loop Detector B(RING) Signal Transmission VBAT2 Power-Feed Controller VBAT1 Input Decoder and Control RSN RDC CAS OVH RFA BGND VCC E1 DET RD VTX Switch Control BSWOUT BSWEN BSWTH C2 C3 C4 AGND/DGND Document ID# 080201 Date: Sep 19, 2007 Rev: G Version: 3 Distribution: Public Document Le79489 Data Sheet ORDERING INFORMATION Standard Products Zarlink standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. D Le79489* J C TEMPERATURE RANGE C = Commercial (0°C to 70°C)* PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032) PACKAGING D = Green package DEVICE NUMBER/DESCRIPTION Le79489 Subscriber Line Interface Circuit PERFORMANCE GRADE OPTION Blank = No performance grade option –2 = 60 dB Longitudinal Balance, Polarity Reversal –3 = 52 dB Longitudinal Balance, No Polarity Reversal Valid Combinations Valid Combinations Le79489* (Blank) –2 –3 DJC1, 2 1. For delivery using a tape and reel packing system, add a "T" suffix to the OPN (Ordering Part Number) when placing an order. Valid Combinations list configurations planned to be supported in volume for this device. Contact Zarlink sales to confirm availability of specific valid combinations and to obtain additional data on Zarlink’s standard military–grade products. 2. The green package meets RoHS Directive 2002/95/EC of the European Council to minimize the environmental impact of electrical equipment. *Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix, until such time as all inventory bearing this mark has been depleted. It should be noted that parts marked with either the "Am" or the "Le" part number prefix are equivalent devices in terms of form, fit, and function. The only difference between the two is in the part number prefix appearing on the topside mark. 2 Zarlink Semiconductor Inc. Le79489 Data Sheet VBAT2 VCC BGND B(RING) A(TIP) 4 3 2 1 32 31 30 DB RINGOUT CONNECTION DIAGRAMS Top View TESTOUT 5 29 DA BSWOUT 6 28 RD TMG 7 27 HPB VBAT1 8 26 HPA C4 9 25 NC BSWEN 10 24 VTX C1 11 23 RSVD E1 12 22 RSN DET 13 21 AGND/DGND BSWTH 18 19 20 RDC C2 17 RFA 16 OVH 15 CAS 14 C3 32-Pin PLCC Notes: 1. Pin 1 is marked for orientation. 2. NC = No Connect 3. RSVD = Reserved. Do not connect to this pin. 3 Zarlink Semiconductor Inc. Le79489 Data Sheet PIN DESCRIPTIONS Pin Names Type Description AGND/DGND Gnd A(TIP) Output BGND Gnd B(RING) Output BSWEN — Battery Switch Control. Internally connected to automatic battery switch circuitry. BSWEN can be overridden by external logic. BSWEN Low connects VBAT1 to VBAT2. BSWEN High disconnects VBAT1 from VBAT2. BSWOUT Output Buffered Output. Internally connected to battery switch circuitry. The output is open-collector with a built-in pull-up resistor. BSWOUT Low indicates VBAT1 is connected to VBAT2. BSWOUT High indicates VBAT1 is disconnected from VBAT2. This output is valid only in the Active states. BSWTH Input Input for setting automatic battery switch threshold. Normally tied to Battery 2. Tie to ground for manual switching. C3–C1 Input Decoder. TTL compatible. C3 is MSB and C1 is LSB. C4 Input Test Relay Input – Active Low. 1 = Off. 0 = On. CAS Capacitor DA Input Ring-trip negative. Negative input to ring-trip comparator. DB Input Ring-trip positive. Positive input to ring-trip comparator. DET Output E1 Input HPA Capacitor High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor. HPB Capacitor High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor. NC — OVH Input Analog and Digital ground. Output of A(TIP) power amplifier. Battery (power) ground. Output of B(RING) power amplifier. Anti-sat pin for capacitor to filter reference voltage when operating in anti-sat region. Switchhook detector. When enabled, a logic Low indicates the selected detector is tripped. The detector is selected by the logic inputs (C3–C1). The output is open-collector with a built-in 15 kΩ pull-up resistor. Ground-Key Detect Select. E1 = 1 selects the hook switch detector. E1 = 0 selects the ground-key detector. In the Tip Open state, ground key is selected independent of E1. No connect. This pin not internally connected. Overhead Control. Logic High enables minimized nonmetering overhead. Logic Low enables 2.2 V metering DC overhead. TTL-compatible. RD Resistor Detector resistor. Detector threshold set and filter pin. RDC Resistor DC feed resistor. Connection point for the DC feed current programming network. The other end of the network connects to the receiver summing node (RSN). Connection point for the DC feed current programming network. The other end of the network connects to RSN. VRDC is negative for normal polarity and positive for reverse polarity. RFA — RINGOUT Output RSN Input Resistive feed adjust. Adjust the DC feed resistance gain coefficient, GDC, with external resistor connected to ground. Ring Relay Driver. Open-collector driver with emitter internally connected to BGND. Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 500 times the current into this pin. The networks that program receive gain, two-wire impedance, and feed current all connect to this node. RSVD — Reserved. These pins are reserved for Zarlink use. Make no connection to these pins. TESTOUT Output Test Relay Driver. Open collector driver with emitter internally connected to AGND. TMG — VBAT1 Battery VBAT2 Battery Battery supply for output power amplifiers. Switched to VBAT1 by BSWEN. VCC Power +5 V power supply. VTX Output Transmit Audio. This output is a 0.5066 unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. Exposed Pad Battery Thermal Management. External resistor connects this pin to VBAT2 to offload power dissipation from SLIC. Functions during normal polarity, Active state. Most negative battery supply and substrate connection. This must be electrically tied to VBAT1. 4 Zarlink Semiconductor Inc. Le79489 ABSOLUTE MAXIMUM RATINGS Data Sheet OPERATING RANGES Commercial (C) Devices Storage temperature. . . . . . . . . . . . . . . . . –55°C to +150°C With respect to AGND/DGND: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +7.0 V Ambient temperature . . . . . . . . . . . . . . . . –40°C to +85°C* VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V VBAT1 Continuous. . . . . . . . . . . . . . . . . . . . . . +0.4 V to –70 V 10 ms . . . . . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V BAT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40.5 V to –60 V BAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 V to BAT1 VBAT2 and BSWTH. . . . . . . . . . . . . . . . . . +0.4 V to VBAT1 AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V BGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3 V to –3 V BGND with respect to GND . . . . . . .–100 mV to +100 mV A(TIP) or B(RING) with respect to BGND: Continuous. . . . . . . . . . . . . . . . . . . . . . . .VBAT1 to +1 V 10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . . . . –70 V to +5 V 1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . . . . . –80 V to +8 V 250 ns (f = 0.1 Hz). . . . . . . . . . . . . . . . . –90 V to +12 V Load resistance on VTX to GND . . . . . . . . . . . .20 kΩ min Operating ranges define those limits over which the functionality of the device is guaranteed by production testing. *Zarlink guarantees the performance of this device over commercial (0 to 70°C) and industrial (-40 to 85 °C) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore TR-TSY-000357 Component Reliability Assurance Requirements for Telecommunications Equipment. Current from A(TIP) or B(RING) . . . . . . . . . . . . . ±150 mA TESTOUT/RINGOUT/current . . . . . . . . . . . . . . . . . 80 mA TESTOUT/RINGOUT/voltage . . . . . . . . . . BGND to +7 V TESTOUT/RINGOUT/transient . . . . . . . . BGND to +10 V DA and DB inputs Voltage on ring-trip inputs. . . . . . . . . . . . . VBAT1 to 0 V Current on ring-trip inputs. . . . . . . . . . . . . . . . . ±10 mA C4–C1, BSWEN, OVH, E1 Input voltage . . . . . . . . . . . . . . . –0.4 V to VCC + 0.4 V Maximum power dissipation, continuous* TA = 70°C, No heat sink (see note): In 32-pin PLCC package . . . . . . . . . . . . . . . . . . . .1.7 W Thermal data (θJA) In 32-pin PLCC package ..............................43°C/W typ ESD immunity (HBM) . . . . . . JESD22 Class 1C compliant * Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. Continuous operation above 145°C junction temperature may degrade device reliability. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Package Assembly Green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board 5 Zarlink Semiconductor Inc. Le79489 Data Sheet ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Min Typ Max Unit Note dB 4, 6 20 Ω 4 +50 mV Transmission Performance 2-wire return loss (See Test Circuit D) 200 Hz to 3.4 kHz 26 Analog output (VTX) impedance 3 Analog output (VTX) offset voltage Overload level, 2-wire THD, Total Harmonic Distortion THD, open loop –50 Active state 2.5 Vpk 0 dBm –64 –50 +7 dBm –55 –40 0 dBm, RLAC = 600 Ω dB –36 2a, 3 3 4 Longitudinal Capability (See Test Circuit C) 0°C to +70°C –40°C to +85°C –40°C to +85°C –3* –2 –2 –2 52 60 58 54 0°C to +70°C –40°C to +85°C –40°C to +85°C –3 –2 –2 –2 52 54 54 54 Longitudinal to metallic L-T 200 Hz to 1 kHz Normal polarity Normal polarity Normal polarity Reverse polarity Longitudinal to metallic L-T 1 kHz to 3.4 kHz Normal polarity Normal polarity Normal polarity Reverse polarity Longitudinal signal generation 4-L 200 Hz to 3.4 kHz 40 Longitudinal current per pin (A or B) Active state 15 Longitudinal impedance at A or B 0 to 100 Hz dB 8 dB 27 mArms Ω/pin 4 23 dBrnc 4 25 Longitudinal Induction 7 Idle Channel Noise C-message weighted noise RL = 600 Ω +7 +12 dBrnC 4, 8 Psophometric weighted noise RL = 600 Ω –83 –78 dBmp 8 Insertion Loss (See Test Circuits A and B) Gain, 4- to 2-wire Gain, 2- to 4-wire, 4-to-4-wire 0 dBm, 1 kHz 0 dBm, 1 kHz 0°C to 70°C –40°C to 85°C –0.15 0 +0.15 –0.20 0 +0.20 0°C to 70°C –40°C to 85°C –6.05 –5.90 –5.75 –6.10 –5.90 –5.70 Gain, 4- to 2-wire Open loop –0.35 +0.35 Gain, 2- to 4-wire, 4- to 4-wire Open loop –6.25 Gain over frequency 300 to 3.4 kHz, relative to 1 kHz –0.10 +0.10 Gain tracking +3 dBm to –55 dBm relative to 0 dBm –0.10 +0.10 Gain tracking open loop 0 dB to –15 dB –0.35 +0.35 Group delay 0 dBm, 1 kHz –5.90 4 Note: * P.G. = Performance Grade 6 Zarlink Semiconductor Inc. 4 4 dB –5.55 4 4 4 µs 4, 6 Le79489 Data Sheet ELECTRICAL CHARACTERISTICS (CONTINUED) Description Test Conditions (See Note 1) Min Typ Max Unit Note Line Characteristics IL, Active Short loop Medium loop Long loop RLDC = 250 Ω RLDC = 700 Ω RLDC = 2 kΩ 44.2 33.4 17.2 48.6 37.1 19.2 54.0 40.8 21.2 IL, Active Short loop Long loop RLDC = 250 Ω RLDC = 2 kΩ 44.2 16.0 48.6 18.0 54.0 20.0 0.7 IL IL 1.3 IL 18 30 IL, Accuracy, Standby state V BAT1 – 3 V I L = ---------------------------------R L + 400 TA = 25°C Current limited region IL, Loop current, Disconnect state RL = 0 ILLIM Active, A and B to GND 95 100 µA 135 mA 52 Vapparent VAB, Open loop voltage mA 40.3 39.8 37 Active, Normal Reverse Polarity OVH = 0 4 41.7 41.7 39 V BAT SW hysteresis 1150 mV BAT SW threshold (from VBAT1 to VBAT2) BAT2 + 8.5 V IA, Leakage, Tip Open state RL = 0 IB, Current, Tip Open state B to GND VA, Active RA to BAT1 = 7 kΩ, RB to GND = 100 Ω 18 30 –7.5 –5 100 µA 56 mA V 4 Power Supply Rejection Ratio (Vripple = 100 mVrms), Active Normal State VCC 50 Hz to 3.4 kHz 30 45 VBAT1 50 Hz to 3.4 kHz 28 50 VBAT2 50 Hz to 3.4 kHz 35 50 VBAT1, Open loop, RLAC = 600 Ω (Anti-sat region) 50 Hz 100 Hz 200 Hz 500 Hz to 3.4 kHz 8 15 20 28 14 22 29 40 Effective internal resistance CAS pin to GND 85 170 255 Open loop, Disconnect state 35 70 Open loop, Standby state 50 85 3 4 dB 4 kΩ 4 mW 9 Device Power Dissipation Open loop, Active state OVH = 1 150 250 Open loop, Active state OVH = 0 550 620 Off hook, Standby state RL = 600 Ω 1000 1300 Off hook, Active state RL = 250 Ω RL = 700 Ω 880 800 1200 1000 ICC, Open Loop VCC supply current Disconnect state Standby state Active state 2.5 3.0 6.3 4.5 4.5 9.5 IBAT1, Open Loop VBAT1 supply current Disconnect state Standby state Active state 0.5 0.7 2.8 1.0 1.5 4.8 Supply Currents, Battery 7 Zarlink Semiconductor Inc. mA Le79489 Data Sheet ELECTRICAL CHARACTERISTICS (CONTINUED) Description Test Conditions (See Note 1) Min Typ Max Unit Note 0.7 mVrms 4 RFI Rejection RFI rejection 100 kHz to 30 MHz (See Figure E) Logic Inputs (C4–C1, E1, BSWEN, OVH [–5, –6 only]) VIH, Input High voltage C3 C1, C2, C4, BSWEN, OVH, E1 2.5 2.0 V VIL, Input Low voltage 0.8 IIH, Input High current C4–C1, OVH, E1 –75 40 IIH, Input High current, BSWEN –75 1200 IIL, Input Low current, except C1 –400 IIL, Input Low current, C1 –600 µA –300 Logic Output (DET, BSWOUT) VOL, Output Low voltage IOUT = 0.3 mA VOH, Output High voltage IOUT = –0.05 mA 0.40 2.4 V Ring-Trip Comparator Input (DA, DB) Bias current Offset voltage Source resistance = 2 MΩ –500 –50 –50 0 nA +50 mV 5 Loop Detector IT, Loop-detect threshold tolerance Active state, Off-hook to On-hook RD = 35.4 kΩ, IT = 368/RD –15 +15 –20 +20 –15 +15 –20 +20 On-hook to Off-hook RD = 35.4 kΩ, IT = 414/RD Standby state, Off-hook to On-hook RD = 35.4 kΩ, IT = 425/RD % On-hook to Off-hook RD = 35.4 kΩ, IT = 471/RD Loop-detect threshold hysteresis Active state 1.3 Standby state IGK, GND key-detector threshold RL from BX to GND Active, Standby, and Tip Open states 5 4 mA 9 13 +0.3 +0.7 V 100 µA Relay Driver Output (RINGOUT/TESTOUT) On voltage IOL = 40 mA Off leakage VOH = +5 V Zener breakover IZ = 100 µA Zener On voltage IZ = 40 mA 6 7.5 7.9 8 Zarlink Semiconductor Inc. 10 V Le79489 Data Sheet RELAY DRIVER SCHEMATICS RINGOUT TESTOUT BGND BGND Notes: 1. Unless otherwise specified, test conditions are VCC = +5 V, BAT1 = –50 V, BAT2 = –34 V, RL = 600 Ω, RDC1 = RDC2 = 5.833 kΩ, RTMG = 570 Ω, RD = 35.4 kΩ, RFA = 0 Ω, no fuse resistors, CHP = 0.22 µF, CDC = 0.5 µF, CCAS = 0.33 µF, CVBAT12 = 220 nF, D1 = D2 = 1N400x, OVH = 1, two-wire AC input impedance is a 600 Ω resistance synthesized by the programming network shown below. VTX RT1 = 76 kΩ CT1 = 120 pF RT2 = 76 kΩ RSN RRX = 150 kΩ VRX 2. a. Overload level exists when THD = 1%. b. Overload level exists when THD = 1.5%. 3. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. 6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the DSLAC™ or QSLAC™ device. 7. Minimum current level is guaranteed not to cause a false Loop Detect. The SLIC must be functional in this condition. 8. Four-wire performance is 5–9 dB better than the specified two-wire values. 9. Open loop, Active state, Metering mode power dissipation may be reduced from a typical of 550 mW to a typical of 150 mW by connecting the DET pin to the OVH pin. This connection will force the SLIC into the nonmetering mode while on hook. With this connection, a metering signal sent after the SLIC goes on hook may be distorted on the 2W line because the SLIC is forced into the nonmetering mode. To eliminate this distortion, a delay can be added between the time the SLIC goes on hook and the time the SLIC switches to nonmetering mode by using an RC circuit for the DET pin to OVH pin connection. 9 Zarlink Semiconductor Inc. Le79489 Data Sheet Table 1. SLIC Decoding DET Output State C3 C2 C1 2-Wire Status E1 = 1 E1 = 0 0 0 0 0 Standby, Reverse Polarity Loop detector GK 1 0 0 1 Reserved X X 2 0 1 0 Active, Reverse Polarity Loop detector GK 3 0 1 1 Tip Open GK or loop detector GK 4 1 0 0 Disconnect Ring trip Ring trip 5 1 0 1 Ringing Ring trip Ring trip 6 1 1 0 Active, Normal Loop detector GK 7 1 1 1 Standby, Normal Loop detector GK Table 2. User-Programmable Components Z T = 253 ( Z 2WIN – 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired two-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. The internal amplifier pole is: 22 kHz • R LAC ------------------------------------600 Ω ± 10% ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. ZL is the 2-wire load impedance. ZL 500 ( Z T ) Z RX = ------------ • --------------------------------------------------G 42L Z T + 253 ( Z L + 2R F ) RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILIMIT is the desired loop current in the constant-current region. 625 ( GFA ) I LIMIT = --------------------------------R DC1 + R DC2 R DC1 + R DC2 R DC1 • R DC2 C DC = 1.5 ms • -------------------------------- ( RFA + 30.1 kΩ ) GFA = 0.99 • ------------------------------------------( RFA + 32 kΩ ) ( RFA + 60 kΩ ) RCL = 1.4 • ( R DC1 + R DC2 ) • -----------------------------------------( RFA + 100 kΩ ) 365 R D = --------- , IT RD and CD form the network connected from RD to AGND/DGND and IT is the threshold current between on hook and off hook in the Active state. msC D = 0.5 --------------- RD CCAS is the regulator filter capacitor and fc is the desired filter cutoff frequency. 1 C CAS = ----------------------------5 3.4 • 10 πf c V BAT1 – 3 V I S tan dby = ---------------------------------400 Ω + R L Standby loop current (resistive region). C BSWEN = 5 µmhos • T D ( ms ) CBSWEN is connected from BSWEN to GND for automatic switching. TD is the delay in switching from BAT1 to BAT2. The delay from BAT2 to BAT1 is about 0.1 TD. 10 Zarlink Semiconductor Inc. Le79489 Data Sheet Table 2. User-Programmable Components (continued) The DC feed resistance can be adjusted with a resistance (RFA) from the RFA pin to ground. R DC1 + R DC2 R FEED = 2 • R FUSE + --------------------------------- GDC 40 kΩ + RFA GDC = 47.9 ------------------------------------- 120 kΩ + RFA Thermal Management Equations (Active, Normal, and Reverse Polarity States) V BAT2 – 6 V R TMG ≥ ----------------------------------I LOOPmax (OVH = 1) V BAT2 – 7.5 V R TMG ≥ --------------------------------------I LOOPmax (OVH = 0) RTMG is connected from TMG to VBAT2 and is used to limit power dissipation within the SLIC in Active states only. Power dissipated in the thermal management resistor, RTMG, during the Active states. 2 P RTMG ( V BAT2 – 6 V – ( I L • R L ) ) ( R TMG ) = ------------------------------------------------------------------------------------------2 ( R TMG + 40 ) (OVH = 1) 2 ( V BAT2 – 7.5 V – ( I L • R L ) ) ( R TMG ) P RTMG = ----------------------------------------------------------------------------------------------2 ( R TMG + 40 ) (OVH = 0) Power dissipated in the SLIC while in the Active states. 2 P SLIC = ( V BAT2 • I L ) – P RTMG – R L • ( I L ) + 0.22 W 11 Zarlink Semiconductor Inc. Le79489 Data Sheet DC FEED CHARACTERISTICS RFA = 0 Ω RDC = RDC1 + RDC2 = 11.67 kΩ, No fuse resistors OVH = 1 BAT1 = –50 V 60 18.8 mA, 38.8 V 3 41.5 V 48.0 mA, 18.5 V VAB (Volts) 2 1 0 50.0 mA IL (mA) 0 Notes: Graph is for illustration only. 1. V AB = I LIMIT • RCL – I L • RCL RDC 2. V AB = 52 V – I L ------------- GDC 3a. RDC V AB = 0.8 V BAT1 + 2.2 – I L ------------------------ , OVH = 1 5 • GDC RDC 3b. V AB = 0.8 V BAT1 – 1.0 – I L ------------------------ , OVH = 0 5 • GDC a. Load Line (Typical) A a RL IL SLIC RSN RDC1 b RDC2 B RDC Feed current programmed by RDC1 and RDC2 b. Feed Programming Figure 1. DC Feed Characteristics 12 Zarlink Semiconductor Inc. CDC 60 Le79489 Data Sheet TEST CIRCUITS A(TIP) A(TIP) VTX RL VTX SLIC 2 SLIC AGND VL RT VAB RL VAB AGND RT RL RRX 2 RRX RSN RSN B(RING) VRX B(RING) IL2-4 = –20 log (VTX / VAB) IL4-2 = –20 log (VAB / VRX) B. Four- to Two-Wire Insertion Loss A. Two- to Four-Wire Insertion Loss 1 ωC << RL A(TIP) RL 2 S1 VTX SLIC C AGND VL VAB RT VL S2 RL 2 B(RING) S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) L-4 Long. Bal. = 20 log (VTX / VL) RRX RSN VRX S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX) C. Longitudinal Balance 13 Zarlink Semiconductor Inc. Le79489 Data Sheet TEST CIRCUITS (continued) ZD A(TIP) VTX SLIC R VS RT1 AGND VM CT1 R RT2 ZIN RSN B(RING) RRX ZD is the specified nominal input impedance. Return loss = –20 log (2 VM / VS) D. Two-Wire Return Loss Test Circuit L1 HF GEN 50 Ω C1 RF1 200 Ω 50 Ω 200 Ω 50 Ω C2 L2 RF2 CAX 33 nF CBX 33 nF A B VTX SLIC Under Test 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz E. RFI Test Circuit 14 Zarlink Semiconductor Inc. Le79489 Data Sheet TEST CIRCUITS (continued) +5 V DA VCC DB RD 2.2 nF A(TIP) A(TIP) HPA CHP RD VTX VTX RT HPB B(RING) CD (optional) B(RING) RRX RSN 2.2 nF VRX RDC2 TESTOUT RINGOUT BGND RDC RDC1 CDC AGND/ DGND RFA BSWOUT BAT2 BSWTH OVH VBAT2 BSWEN RFA C4 CVBAT12 C3 VBAT1 BAT1 D1 TMG RTMG (optional) BATTERY GROUND C2 C1 E1 DET ANALOG GROUND CAS CCAS F. Le79489 Test Circuit 15 Zarlink Semiconductor Inc. DIGITAL GROUND Le79489 Data Sheet PHYSICAL DIMENSIONS 32-Pin PLCC NOTES: 32-Pin PLCC JEDEC # MS-016 Min Nom Symbol A 0.125 -A1 0.075 0.090 D 0.485 0.490 D1 0.447 0.450 D2 0.205 REF E 0.585 0.590 E1 0.547 0.550 E2 0.255 REF Ԧ 0 deg -- 1 Dimensioning and tolerancing conform to ASME Y14,5M-1994. 2 To be measured at seating plan - C - contact point. 3 Dimensions “D1” and “E1” do not include mold protrusion. Allowable mold protrusion is 0.010 inch per side. Dimensions “D” and “E” include mold mismatch and determined at the parting line; that is “D1” and “E1” are measured at the extreme material condition at the upper or lower parting line. 0.595 0.553 4 Exact shape of this feature is optional. 10 deg 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 Max 0.140 0.095 0.495 0.453 32-Pin PLCC Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. 16 Zarlink Semiconductor Inc. Le79489 Data Sheet REVISION SUMMARY Revision C to Revision D • In the Electrical Characteristics table on page 8, some information was changed in the Test Conditions column in the Loop Detector section and the “Loop-detect threshold hysteresis” row was added to this section. Revision D to Revision E • The physical dimensions (PL032) were added to the Physical Dimensions section. • Updated the Pin Description table to correct inconsistencies. Revision E to Revision F • Updated OPN (Ordering Part Number) throughout document. • Absolute Maximum Ratings: Notes updated to standard. • Operating Ranges: Temperature statement updated to standard. • Updated "Sales Office Listing." • Updated physical dimension drawings. Revision F1 to G1 • Removed non-green OPNs from Ordering Information. • Removed all QFN package information throughout data sheet. • In Electrical Characteristics, removed specifications for polarity grade options, 1 and 4 - 6 Revision G1 to G2 • Added notes to Ordering Information on page 2. Revision G2 to G3 • Enhanced format of package drawing in Physical Dimensions • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 17 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. 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