™
Le75282
Dual Intelligent Line Card Access Switch
VE750 Series
APPLICATIONS
DESCRIPTION
The Le75282 Dual Intelligent Line Card Access Switch (LCAS)
device is a monolithic solid-state device that provides the
switching functionality of four 2 Form C relays in one
economical small package.
Central office
DLC
PBX
DAML
The Le75282 Dual LCAS device is designed to provide power
ringing access to a telephone loop in central office, digital loop
carrier, private branch exchange, digitally added main line, and
hybrid fiber coax/fiber-in-the-loop analog line card applications.
An additional pair of solid-state contacts provides access to the
telephone loop for line test access or message waiting in the
PBX application.
HFC/FITL
FEATURES
Small size/surface-mount packaging
5-V operation, very low power consumption
Monolithic IC reliability
Low impulse noise
Make-before-break, break-before-make operation
Clean, bounce-free switching
Low, matched ON-resistance
Built-in current limiting, thermal shutdown, and SLIC
device protection
Battery monitor, All Off state upon loss of battery
No EMI
Latched logic level inputs, no drive circuitry
BLOCK DIAGRAM
Only one external protector required per channel
RELATED LITERATURE
081065 Le79228 Quad ISLAC™ Device Data Sheet
VBH
FGND1
081190 Le792288 Octal ISLAC™ Device Data Sheet
081143 Le79232 Dual ISLIC™ Device Data Sheet
081144 Le79252 Dual ISLIC™ Device Data Sheet
Battery
Monitor
080923 Le792x2/Le79228 Chip Set User’s Guide
ASLIC1
SW1
BSLIC1
SW2
BLINE1
ALINE1
ORDERING INFORMATION
Device
Le75282BBVC
ARINGING1
Package Type1
44-pin TQFP (Green)
Packing2
SW4
SW3
BRINGING1
SW5
SW6
BTEST1
ATEST1
Tray
LD1
VDD
1.
2.
The green package meets RoHS Directive 2002/95/EC of the
European Council to minimize the environmental impact of
electrical equipment.
For delivery using a tape and reel packing system, add a "T" suffix
to the OPN (Ordering Part Number) when placing an order.
DGND
Control
Logic
CFG
CHANNEL 1
TSD1
OFF1
P1'-P3'
CHANNEL 2
Document ID# 081123 Date:
Rev:
E
Version:
Distribution:
Public Document
Sep 19, 2007
2
Le75282
Data Sheet
TABLE OF CONTENTS
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Zero Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Loss of Battery Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Impulse Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Integrated SLIC Device Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Diode Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Temperature Shutdown Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
External Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Test Access Switch Protection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
44-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision A1 to B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision B1 to C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision C1 to D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision D1 to E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision E1 to E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2
Zarlink Semiconductor Inc.
Le75282
Data Sheet
PRODUCT DESCRIPTION
The Le75282 Dual LCAS device has six operating states:
•
•
•
•
•
•
Idle/Talk — Line break switches closed, ringing and test access switches open.
Ringing — Ringing access switches closed, line break and test access switches open.
Test — Test access switches closed, line break and ringing access switches open.
Test/Monitor — Test access and line break switches closed, ringing access switches open.
Test Ringing — Test and ringing access switches closed, line break switches open.
All Off — Line break and ringing and test access switches open.
Control is provided by an Intelligent Subscriber Line Audio-processing Circuit (ISLAC), such as the Le79228 codec, or any
microcontroller. See Applications, on page 14 for proper connection of the control bus (P-bus).
The Le75282 Dual LCAS device offers break-before-make or make-before-break switching, with simple logic level input control.
Because of the solid-state construction, voltage transients generated when switching into an inductive ringing load during ring
cadence or ring trip are minimized, possibly eliminating the need for external zero cross switching circuitry. State control is via
logic level inputs so no additional driver circuitry is required.
The line break switch is a linear switch that has exceptionally low ON-resistance and an excellent ON-resistance matching
characteristic. The ringing access switch has a breakdown voltage rating > 320 V which is sufficiently high, with proper protection,
to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ringing generator).
Incorporated into the Le75282 Dual LCAS device is a diode bridge, current-limiting circuitry, and a thermal shutdown mechanism
to provide protection to the SLIC device and subsequent circuitry during fault conditions. Positive faults are directed to ground
and negative faults to battery. In either polarity, faults are reduced by the built-in current-limit and/or thermal shutdown
mechanisms.
To protect the Le75282 Dual LCAS device from an overvoltage fault condition, use of a secondary protector is required. The
secondary protector must limit the voltage seen at the A (Tip)/B (Ring) terminals to prevent the breakdown voltage of the switches
from being exceeded. To minimize stress on the solid-state contacts, use of a foldback- or crowbar- type secondary protector is
recommended. With proper choice of secondary protection, a line card using the Le75282 device will meet all relevant ITU-T,
LSSGR, FCC, or UL protection requirements.
The Le75282 Dual LCAS device provides extremely low idle and active power dissipation and allows use with virtually any range
of battery voltage. This makes the Le75282 Dual LCAS device especially appropriate for remote power applications such as
DAML or FOC/FITL or other Bellcore TA 909 applications where power dissipation is particularly critical.
Battery voltage is monitored by the control circuitry and used as a reference for the integrated protection circuit. The Le75282
device will enter an All Off state upon loss of battery.
During ringing, to turn on and maintain the ON state, the ringing access switch will draw a nominal 2 mA from the ring generator.
The Le75282 Dual LCAS device is packaged in a 44-pin TQFP package.
3
Zarlink Semiconductor Inc.
Le75282
Data Sheet
BLINE1
NC
ALINE1
ATEST1
ARINGING1
NC
ATEST2
ARINGING2
ALINE2
NC
BLINE2
CONNECTION DIAGRAM
44 43 42 41 40 39 38 37 36 35 34
BTEST2
1
33
BTEST1
NC
2
32
NC
NC
3
31
NC
BRINGING2
4
30
BRINGING1
29
NC
28
TSD1
NC
5
TSD2
6
FGND2
7
27
FGND1
44-pin TQFP
VBH
8
26
VBH
VDD
9
25
VDD
NC
10
24
CFG
DGND
11
23
DGND
BSLIC1
ASLIC1
OFF2
LD2
OFF1
LD1
P3'
P2'
P1'
ASLIC2
BSLIC2
12 13 14 15 16 17 18 19 20 21 22
Pin Descriptions
CH1
CH2
27
7
21
36
38
37
Description
CH1
CH2
Pin Name
Description
VBH
High-battery voltage. Used as a
reference for protection circuit.
12
BSLICx
Connect to B lead on SLIC side.
44
BLINEx
Connect to B lead on line side.
FGNDx
Fault ground.
13
ASLICx
Connect to A lead on SLIC side.
22
42
ALINEx
Connect to A lead on line side.
34
40
ARINGINGx
Connect to return ground of ringing
generator.
30
4
41
ATESTx
A lead test access.
33
1
BTESTx
VDD
5 V supply.
17
18
LDx
Data latch channel control, active low.
TSDx
Temperature shutdown flags. Read VDD
potential when device is in its
operational mode and 0 V when device
is in the thermal shutdown mode.
14
P1’
Logic level input switch control.
Connect to P-bus. See Applications, on
page 14 for proper connection.
DGND
Digital ground.
15
P2’
Logic level input switch control.
Connect to P-bus. See Applications, on
page 14 for proper connection.
OFFx*
All Off logic level input switch control. A
pull-down device is included, setting All
Off as the power-up default state. These
pins can also be used as a device reset.
If these pins are not to be used, they
must be tied to VDD.
16
P3’
Logic level input switch control.
Connect to P-bus. See Applications, on
page 14 for proper connection.
CFG
Operating states configuration. Tie to
DGND to select operating states as
defined in Table 9. Tie to VDD for
operating states as defined in Table 10.
9, 25
28
6
11, 23
19
Pin Name
20
2, 3, 5, 10, 29,
31, 32, 35, 39, NC
43
8, 26
No Connect. This pin is not internally
connected.
24
Notes:
"x" denotes channel number.
* Internal pull down on this node.
4
Zarlink Semiconductor Inc.
BRINGINGx Connect to ringing generator.
B lead test access.
Le75282
Data Sheet
ABSOLUTE MAXIMUM RATING
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability.
Parameter
Operating Temperature Range
Storage Temperature Range
Relative Humidity Range
Pin Soldering Temperature (t=10 s max)
5-V Power Supply
Battery Supply
Logic Input Voltage
Input-to-output Isolation
Pole-to-pole Isolation
ESD Immunity (Human Body Model)
Min
Max
Unit
–40
110
°C
–40
150
°C
5
95
%
—
260
°C
-0.3
7
V
—
–85
V
V
-0.3
VDD+0.3
—
330
V
—
330
V
JESD22 Class 1C compliant
Package Assembly
Green package devices are assembled with enhanced, environmental, compatible lead-free, halogen-free, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer leadfree board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile.
OPERATING RANGES
Environmental Ranges
Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment
.
0 to 70°C Commercial
Ambient Temperature
–40 to +85 °C extended temperature
Ambient Relative Humidity
15 to 85%
Electrical Ranges
VDD
+4.75 V to +5.25 V
VBH
–19 V to –72 V
5
Zarlink Semiconductor Inc.
Le75282
Data Sheet
ELECTRICAL CHARACTERISTICS
TA = –40 °C to +85 °C, unless otherwise specified.
Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are the result of
engineering evaluations. Typical values are for information purposes only and are not part of the testing requirements.
Table 1. Break Switches, SW1x (A lead) and SW2x (B lead) (Refer to Figure 2, on page 12)
Parameter
Test Condition
Measure
Min
Typ
Max
Unit
Iswitch
—
—
1
µA
Iswitch
—
—
1
µA
Iswitch
—
—
1
µA
∆ VON
∆ VON
∆ VON
—
—
—
19
—
14
—
31
—
Ω
Ω
Ω
—
0.02
1.0
Ω
OFF-state Leakage
Current:
+25 °C
Vswitch (differential) = –320 V to Gnd
Vswitch (differential) = –60 V to +260 V
+85 °C
Vswitch (differential) = –330 V to Gnd
Vswitch (differential) = –60 V to +270 V
–40 °C
Vswitch (differential) = –310 V to Gnd
Vswitch (differential) = –60 V to +250 V
ON-resistance:
ALINE = ±10 mA, ±40 mA, ASLIC = –2 V
BLINE = ±10 mA, ±40 mA, BSLIC = –2 V
+25 °C
+85 °C
–40 °C
ON-resistance Match
1
ON-state Voltage
DC Current Limit
Dynamic Current
2
Limit
(t = < 0.5 µs)
Per ON-resistance test
Magnitude
condition of SW1, SW2
RON SW1 – RON SW2
Maximum Differential Voltage (Vmax)
VON
—
—
320
Foldback Voltage Breakpoint 1 (V1)
VON
60
—
—
Foldback Voltage Breakpoint 2 (V2)
VON
V1 + 0.5
—
—
V
ILIM1
Iswitch
85
145
300
ILIM2
Iswitch
1
—
—
Break switches in ON state; ringing switches
off; apply ±1000 V (Source impedance 10 Ω)
unipolar double exponential 10/1000 µs pulse
with appropriate secondary protection in place
Iswitch
—
2.5
—
A
mA
Isolation:
+25 °C
Vswitch (both poles) = ±320 V, OFFx = 0
Iswitch
—
—
1
µA
+85 °C
Vswitch (both poles) = ±330 V, OFFx = 0
Iswitch
—
—
1
µA
–40 °C
Vswitch (both poles) = ±310 V, OFFx = 0
Iswitch
—
—
1
µA
—
—
—
200
—
V/µs
dV/dt Sensitivity3
1. Choice of secondary protector should ensure this rating is not exceeded.
2. This parameter is not tested in production.
3. Applied voltage is 100 Vp-p square wave at 100 Hz.
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Zarlink Semiconductor Inc.
Le75282
Data Sheet
Table 2. Ringing Return Switch, SW3x (Refer to Figure 2, on page 12)
Parameter
Test Condition
Measure
Min
Typ
Max
Unit
Iswitch
—
—
1
µA
Iswitch
—
—
1
µA
Iswitch
—
—
1
µA
∆ VON
—
26
110
Ω
OFF-state Leakage
Current:
+25 °C
Vswitch (differential) = –320 V to Gnd
+85 °C
Vswitch (differential) = –330 V to Gnd
Vswitch (differential) = –60 V to +260 V
Vswitch (differential) = –60 V to +270 V
–40 °C
Vswitch (differential) = –310 V to Gnd
Vswitch (differential) = –60 V to +250 V
ON-resistance
ON-state Voltage1
dc Current Limit
Iswitch (on) = ±0 mA, ±10 mA
Maximum Differential Voltage (Vmax)
VON
—
—
320
Foldback Voltage Breakpoint 1 (V1)
VON
200
—
—
Foldback Voltage Breakpoint 2 (V2)
VON
V1 + 0.5
—
—
V
ILIM1
Iswitch
70
—
—
ILIM2
Iswitch
1
—
—
Vswitch (both poles) = ±320 V, OFFx = 0
Vswitch (both poles) = ±330 V, OFFx = 0
Vswitch (both poles) = ±310 V, OFFx = 0
Iswitch
Iswitch
Iswitch
—
—
—
—
—
—
1
1
1
µA
µA
µA
—
—
—
200
—
V/µs
mA
Isolation:
+25 °C
+85 °C
–40 °C
dV/dt Sensitivity2
1. This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.
2. Applied voltage is 100 Vp-p square wave at 100 Hz.
Table 3. Ringing Access Switch, SW4x (Refer to Figure 3, on page 12)
Parameter
Test Condition
Measure
Min
Typ
Max
Unit
—
—
1
µA
—
—
1
µA
—
—
1
µA
OFF-state Leakage
Current (SW4):
Vswitch (differential) = –255 V to +210 V
+25 °C
+85 °C
–40 °C
Vswitch (differential) = +255 V to –210 V
Vswitch (differential) = –270 V to +210 V
Iswitch
Iswitch
Vswitch (differential) = +270 V to –210 V
Vswitch (differential) = –245 V to +210 V
Iswitch
Vswitch (differential) = +245 V to –210 V
ON-resistance
Iswitch (on) = ±70 mA, ±80 mA
∆ VON
—
6
20
Ω
Crossover Offset
Voltage
Iswitch (on) = ±1 mA
VOS
—
—
3
V
Ring Generator
Current During Ring
VCC = 5 V
IRINGSOURCE
—
2
—
mA
Steady-state Current1
—
—
—
—
150
mA
Surge Current1
Ringing access switch on; apply unipolar double
exponential 10/1000 µs pulse
—
—
—
2
A
Release Current
—
—
—
500
—
µA
Vswitch (both poles) = ±320 V, OFFx = 0
Vswitch (both poles) = ±330 V, OFFx = 0
Vswitch (both poles) = ±310 V, OFFx = 0
Iswitch
Iswitch
Iswitch
—
—
—
—
—
—
1
1
1
µA
µA
µA
—
—
—
200
—
V/µs
Isolation:
+25 °C
+85 °C
–40 °C
dV/dt Sensitivity2
1. This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.
2. Applied voltage is 100 Vp-p square wave at 100 Hz.
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Zarlink Semiconductor Inc.
Le75282
Data Sheet
Table 4. Test Access Switches, SW5x and SW6x (Refer to Figure 4, on page 13)
Parameter
Min
Typ
Max
Unit
—
—
1
µA
—
—
1
µA
Iswitch
—
—
1
µA
Iswitch (on) = ±10 mA, ±40 mA
Iswitch (on) = ±10 mA, ±40 mA
Iswitch (on) = ±10 mA, ±40 mA
∆ VON
∆ VON
∆ VON
—
—
—
34
—
24
—
77
—
Ω
Ω
Ω
ON-state Voltage1
Iswitch = ILIMIT @ 50 Hz/60 Hz
VON
—
—
130
V
dc Current Limit:
ILIMIT:
—
OFF-state Leakage Current:
+25 °C
Test Condition
Measure
Vswitch (differential) = –320 V to Gnd
Iswitch
Vswitch (differential) = –60 V to +260 V
Vswitch (differential) = –330 V to Gnd
+85 °C
Iswitch
Vswitch (differential) = –60 V to +270 V
Vswitch (differential) = –310 V to Gnd
–40 °C
Vswitch (differential) = –60 V to +250 V
ON-resistance:
+25 °C
+85 °C
–40 °C
+85 °C
Vswitch (on) = ±20 V
Iswitch
–40 °C
Vswitch (on) = ±20 V
Iswitch
80
—
—
—
250
mA
mA
Vswitch (both poles) = ±320 V, OFFx = 0
Vswitch (both poles) = ±330 V, OFFx = 0
Vswitch (both poles) = ±310 V, OFFx = 0
Iswitch
Iswitch
Iswitch
—
—
—
—
—
—
1
1
1
µA
µA
µA
—
—
—
200
—
V/µs
Isolation:
+25 °C
+85 °C
–40 °C
dV/dt Sensitivity2
1. This parameter is not tested in production. Choice of secondary protector should ensure this rating is not exceeded.
2. Applied voltage is 100 Vp-p square wave at 100 Hz.
Table 5. Diode Bridge
Min
Typ
Max
Unit
Voltage Drop @ Continuous Current
(50 Hz/60 Hz)
Parameter
Apply ± DC current limit of
break switches
Test Condition
Forward
Voltage
Measure
—
—
3.5
V
Voltage Drop @ Surge Current
Apply ± dynamic current
limit of break switches
Forward
Voltage
—
5
—
V
.
Table 6. Additional Electrical Characteristics
Parameter
Test Condition
Measure
Min
Typ
Max
Unit
V
Digital Input Characteristics:
Input Low Voltage (P1’-P3’, OFFx, CFG)
—
—
—
—
0.8
Input Low Voltage (LDx)
—
—
—
—
0.6
Input High Voltage (P1’-P3’, OFFx)
—
—
2.0
—
—
V
Input High Voltage (CFG)
—
—
3.0
—
—
V
Input High Voltage (LDx)
—
—
1.1
—
—
V
Input Leakage Current (High):
VDD = 5.25 V, VBH = –72 V,
(OFFx)
Vlogic-in = 5 V
llogic-in
—
—
500
µA
Input Leakage Current (High):
VDD = 5.25 V, VBH = –72 V,
(P1’-P3’, LDx, CFG)
Vlogic-in = 5 V
llogic-in
—
—
20
µA
Input Leakage Current (Low):
VDD = 5.25 V, VBH = –72 V,
(P1’-P3’, LDx, OFFx, CFG)
Vlogic-in = 0 V
llogic-in
—
—
20
µA
8
Zarlink Semiconductor Inc.
Le75282
Data Sheet
Table 6. Additional Electrical Characteristics (Continued)
VDD = 5 V, VBH = –48 V,
Idle/Talk state
IDD, IVBH
—
—
10
mW
All Off state
IDD, IVBH
—
—
7.5
mW
IDD, IVBH
—
—
20
mW
IDD
—
—
2.0
mA
IDD
—
—
1.5
mA
Ringing or Test Access state
IDD
—
—
4.0
mA
VBH = –48 V, All states
IVBH
—
4
10
µA
Shutdown Activation Temperature
—
—
110
125
150
°C
Shutdown Circuit Hysteresis
—
—
10
—
25
°C
1
Power Requirements :
Power Dissipation
Ringing or Test Access state
VDD = 5 V,
Idle/Talk state
VDD Current
All Off state
VBH Current
2
Temperature Shutdown Requirements3:
Loss of Battery Detector Threshold:
Loss of Battery
—
—
–19
–12
–5
V
Resumption of Battery
—
—
–19
–14
–5
V
1. Combined power or current of both channels, both channels in same state.
2. Controlled via OFFx pin.
3. Temperature shutdown flag (TSDx) will be high during normal operation and low during temperature shutdown state.
ZERO CROSS CURRENT TURN OFF
The ringing access switch (SW4x) is designed to turn off on the next zero current crossing after application of the appropriate
logic input control. This switch requires a current zero cross to turn off. This switch, once on, will remain in the ON state
(regardless of logic input) until a current zero cross. Therefore, to ensure proper operation, this switch should be connected, via
proper impedance, to the ringing generator or some other ac source. Do not attempt to switch pure dc with the ringing access
switch.
SWITCHING BEHAVIOR
When switching from the Ringing state to the Idle/Talk state via simple logic level input control, the Le75282 device is able to
provide timing control when the ringing access contacts are released relative to the state of the line break contacts.
Make-before-break operation occurs when the line break switch contacts are closed (or made) before the ringing access switch
contact is opened (or broken). Break-before-make operation occurs when the ringing access contact is opened (broken) before
the line break switch contacts are closed (made).
Using the logic level input pins P1’ and P2’, either make-before-break or break-before-make operation of the Le75282 device is
easily achieved. The logic sequences are presented in Tables 7 and 8. See Table 9, Operating States: CFG = 0, on page 17
for an explanation of the logic states.
When using an Le75282 device in the make-before-break mode during the ring-to-idle transition, for a period of up to one-half
the ringing frequency, the B break switch and the pnpn-type ringing access switch can both be in the ON state. This is the
maximum time after the logic signal at RD2 has transitioned, where the ringing access switch is waiting to open at the next zero
current cross. During this interval, current that is limited to the DC break switch current-limit value will be sourced from the BD
node of the SLIC device.
Table 7. Make-Before-Break Operation
Break
Switches
1x & 2x
Ringing
Return
Switch
3x
Ringing
Access
Switch
4x
Test
Access
Switches
5x & 6x
CFG=0, RD3=0
RD2
RD1
OFFx
State
1
0
1
Ringing
—
OFF
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
Timing
0
0
1
Makebeforebreak
SW4 waiting for next zero current
crossing to turn off, maximum
time—one-half of ringing. In this
transition state, current that is
limited to the dc break switch
current-limit value will be sourced
from the BD node of the SLIC.
0
0
1
Idle/Talk
Zero cross current has occurred.
9
Zarlink Semiconductor Inc.
Le75282
Data Sheet
Table 8. Break-Before-Make Operation
Break
Switches
1x & 2x
Ringing
Return
Switch
3x
Ringing
Access
Switch
4x
Test
Access
Switches
5x & 6x
—
OFF
ON
ON
OFF
OFF
OFF
ON
OFF
CFG=0, RD3=0
RD2
RD1
OFFx
State
1
0
1
Ringing
Timing
X
X
0
All Off
Hold this state for 25 ms. SW4
waiting for zero current to turn off.
X
X
0
All Off
Zero current has occurred and
SW4 has opened.
OFF
OFF
OFF
OFF
0
0
1
Idle/Talk
Release break switches.
ON
OFF
OFF
OFF
POWER SUPPLIES
Both the VDD and battery supply are brought onto the Le75282 device. The Le75282 device requires only the VDD supply for
switch operation; that is, state control is powered exclusively off of the VDD supply. Because of this, the Le75282 device offers
extremely low power dissipation, both in the idle and active states.
LOSS OF BATTERY VOLTAGE
As an additional protection feature, the Le75282 device monitors the battery voltage. Upon loss of battery voltage, both channels
of the Le75282 device will automatically enter an All Off state and remain in that state until the battery voltage is restored. The
Le75282 device is designed such that the device will enter the All Off state if the battery rises above –12 V (typ.) and will remain
off until the battery drops below –14 V (typ.).
Monitoring the battery for the automatic shutdown feature will draw a small current from the battery, typically 4 µA. This will add
slightly to the overall power dissipation of the device.
IMPULSE NOISE
Using the Le75282 device will minimize and possibly eliminate the contribution to the overall system impulse noise that is
associated with ringing access switches. Because of this characteristic of the Le75282 device, it may not be necessary to
incorporate a zero cross switching scheme. This ultimately depends upon the characteristics of the individual system and is best
evaluated at the board level.
INTEGRATED SLIC DEVICE PROTECTION
Diode Bridge
Le75282 device protection to the SLIC device or other subsequent circuitry is provided by a combination of current-limited break
switches, a diode bridge, and a thermal shutdown mechanism.
During a positive lightning event, fault current is directed to ground via steering diodes in the diode bridge. Voltage is clamped to
a diode drop above ground. Negative lightning is directed to battery via steering diodes in the diode bridge.
For power cross and power induction faults, the positive cycle of the fault is clamped a diode drop above ground and fault currents
are steered to ground. The negative cycle of the power cross is steered to battery. Fault currents are limited by the current-limit
circuit.
Current Limiting
During a lightning event, the current that is passed through the Le75282 device is limited by the dynamic current-limit response
of the break switches (assuming Idle/Talk state). When the voltage seen at the ALINEx/BLINEx nodes is properly clamped by an
external secondary protector, upon application of a 1000 V 10 x 1000 pulse (LSSGR lightning), the current seen at the ASLICx/
BSLICx nodes will typically be a pulse of magnitude 2.5 A and duration less than 0.5 µs.
During a power cross event, the current that is passed through the Le75282 is limited by the dc current-limit response of the break
switches (assuming Idle/Talk state). The DC current limit is dependent on the switch differential voltage, as shown in Figure 2, on
page 12.
Note that the current-limit circuitry has a negative temperature coefficient. Thus, if the device is subjected to an extended power
cross, the value of current seen at ASLICx/BSLICx will decrease as the device heats due to the fault current. If sufficient heating
occurs, the temperature shutdown mechanism will activate and the device will enter an All Off state.
10
Zarlink Semiconductor Inc.
Le75282
Data Sheet
Temperature Shutdown Mechanism
When the device temperature reaches a minimum of 110 °C, the thermal shutdown mechanism will activate and force the device
into an All Off state, regardless of the logic input pins. Pin TSDx will read low (0 V) when the device is in the thermal shutdown
state and high (VDD) during normal operation. When the device comes out of thermal shutdown and the TSDx output returns high,
the Le75282 device returns to its previously programmed RD1-RD3 state.
During a lightning event, due to the relatively short duration, the thermal shutdown will not typically activate.
During an extended power cross, the device temperature will rise and cause the device to enter the thermal shutdown state. This
forces an All Off state, and the current seen at ASLICx/BSLICx drops to zero. Once in the thermal shutdown state, the device will
cool and exit the thermal shutdown state, thus re-entering the state it was in prior to thermal shutdown. Current, limited to the dc
current-limit value, will again begin to flow and device heating will begin again. This cycle of entering and exiting thermal
shutdown will last as long as the power-cross fault is present.
If the magnitude of power is great enough, the external secondary protector could trigger, thereby shunting all current to ground.
EXTERNAL SECONDARY PROTECTION
An overvoltage secondary protection device on the loop side of the Le75282 device is required. The purpose of this device is to
limit fault voltages seen by the Le75282 device so as not to exceed the breakdown voltage or input-output isolation rating of the
device. To minimize stress on the Le75282 device, use of a foldback- or crowbar-type device is recommended. Basic design
equations governing the choice of external secondary protector are given below:
•
•
•
|VBHmax| + |Vbreakovermax| < |Vbreakdownmin(break)|
|Vringingpeakmax| + |VBHmax| + |Vbreakovermax| < |Vbreakdownmin(ring)|
|Vringingpeakmax| + |VBHmax| < |Vbreakovermin|
where:
VBHmax—Maximum magnitude of battery voltage.
Vbreakovermax—Maximum magnitude breakover voltage of external secondary protector.
Vbreakovermin—Minimum magnitude breakover voltage of external secondary protector.
Vbreakdownmin(break)—Minimum magnitude breakdown voltage of Le75282 break switch.
Vbreakdownmin(ring)—Minimum magnitude breakdown voltage of Le75282 ringing access switch.
Vringingpeakmax—Maximum magnitude peak voltage of ringing signal.
Series current-limiting fused resistors or PTC’s should be chosen so as not to exceed the current rating of the external secondary
protector. Refer to the manufacturer’s data sheet for requirements.
Test Access Switch Protection Considerations
The most robust design has proper capacitive termination of the test access switches. For a 24 or 32 channel test bus, when all
the test leads are tied together, the overall capacitance of the test bus provides adequate termination for the test access switches.
For a test bus with less than 24 channels, tie all the leads together and add a single test bus capacitor on ATESTx to ground and
on BTESTx to ground with a value of 32 pF for each channel less than 24. For any termination scheme, capacitance to ground
on the test nodes should be kept less than 10 nF.
Systems that do not use the test access switch functionality must also add capacitance to the test switch node or short the test
switches. If the test access switches are not to be used, ATEST1 and ATEST2 can be tied together with a 1 nF, 100 V capacitor
on this node to ground. Likewise, tie BTEST1 and BTEST2 together with a 1 nF, 100 V capacitor on this node to ground.
Alternatively, the test access switches can be shorted out. ATESTx can be shorted to ALINEx and BTESTx shorted to BLINEx.
Note, with the test switches shorted, test switch state becomes irrelevant.
In addition, using a low voltage secondary protector on A lead and an asymmetrical protector on B lead (with respect to positive
and negative voltage) is recommended. Refer to the Le79232 ISLIC data sheet for protection values.
11
Zarlink Semiconductor Inc.
Le75282
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 1. Protection Circuit
dc CURRENT-LIMIT
BREAK SWITCHES
VBH – 3
VBH
<1 µA
3V
dc CURRENT LIMIT
(OF BREAK SWITCHES)
Figure 2.
Switches 1 – 3, Break Switches and Ringing Return Switch
ISW
ILIM1
2/3 RON
–VMAX –V2 –V1
–1.5
1.5
–ILIM2
ILIM2
RON
V1
V2 VMAX
–ILIM1
Figure 3.
Switch 4, Ringing Access Switch
+I
RON
–VOS
–V
+VOS
–I
12
Zarlink Semiconductor Inc.
+V
VSW
Le75282
Figure 4.
Data Sheet
Switches 5, 6, Test Access Switches
ILIMIT
CURRENT
LIMITING
+I
2/3 RON
RON
–1.5 V
–V
1.5 V
RON
2/3 RON
CURRENT
LIMITING
ILIMIT
–I
13
Zarlink Semiconductor Inc.
+V
Le75282
Data Sheet
APPLICATIONS
Figure 6, on page 16 illustrates the internal functionality of the Le75282 device.
There are numerous ways to control the Le75282 LCAS device using the P1’-P3’/LDx and OFFx inputs. A one-to-one wiring of
SLAC P1 to LCAS P1’, SLAC P2 to LCAS P2’, and SLAC P3 to LCAS P3’, is usually not the desired connection. When using the
Le79Q224x/Le79228 SLAC as the controller, wiring of the control port varies dependent upon the desired operating states. P1,
P2, and P3 control lines are used to control the ISLIC device and the LCAS device. When LDx is high, the P-bus controls the
operating states of the ISLIC via C1, C2, and C3. When LDx is low, the P-bus controls the relay drivers and the test load in the
ISLIC device as well as the operating states of the LCAS device via RD1, RD2, and RD3. So functionality between the ISLIC
device and the LCAS device needs to be coordinated in order to provide the desired performance.
Figure 5. ISLIC Device and LCAS Control
Le79232 ISLIC
Standby (scan)
TIP Open
OHT
Disconnect
Active High Battery
Active Low Battery
D
E
C
O
D
E
R
R1 (Relay Driver)
Test (Load) Switch
Le75282 LCAS
Switch
Control
VCC
RD1-RD3 controlled by SLAC I/O Register
C
1
C
2
C
3
R
D
1
R
D
2
D
E
M
U
X
P1
P1
P2
P2
P3
P3
Le79228
SLAC
LD1
LD1
VDD
R
D
1
R
D
2
R
D
3
P1'
L
A
T
C
H
P2'
Re-wiring as
necessary
P3'
LD1
Connections are shown for channel one only
Control and wiring scenarios for the ISLIC device and LCAS device follows.
The following LCAS operating state options are available through P-bus control:
1. Idle/Talk, Ringing, Test, Test/Monitor
2. Idle/Talk, Ringing, Test/Monitor, Test Ringing
3. Idle/Talk, Ringing, Test, All Off
4. Idle/Talk, Ringing, Test, Test/Monitor, Test Ringing
5. Idle/Talk, Ringing, Test, Test/Monitor, Test Ringing, All Off
Note, for all five states, the All Off operating state can be asserted by driving the OFFx pin Low.
For option 1, LCAS CFG = 0 and LCAS P3’ = 0, wire SLAC P1 to LCAS P2’, and wire SLAC P3 to LCAS P1’, do not wire SLAC
P2 to the LCAS. The test load (if enabled) can then be applied independent of the LCAS operating state. When SLAC P1 = 1, the
Ringing and Test/Monitor state will be activated when the external ringing signal is at zero cross (assuming CCR4 RMODE is set
for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0)). For the Ringing state this is the desired
operation. For the Test/Monitor state, the delay in activation needs to be considered in the firmware.
For option 2, LCAS CFG = 0 or 1 and LCAS P3’ = 1, wire SLAC P1 to LCAS P2’, and wire SLAC P3 to LCAS P1’, do not wire
SLAC P2 to the LCAS. The test load (if enabled) can then be applied independent of the LCAS operating state. When SLAC P1
= 1, the Ringing and Test Ringing state will be activated when the external ringing signal is at zero cross (assuming CCR4 RMODE
is set for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0)). This is desired operation.
14
Zarlink Semiconductor Inc.
Le75282
Data Sheet
For option 3, LCAS CFG = 1 and LCAS P3’ = 0, wire SLAC P1 to LCAS P2’, and wire SLAC P3 to LCAS P1’, do not wire SLAC
P2 to the LCAS device. The test load (if enabled) can then be applied independent of the LCAS operating state. When SLAC P1
= 1, the Ringing and All Off state will be activated when the external ringing signal is at zero cross (assuming CCR4 RMODE is
set for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0)). For the Ringing state this is the desired
operation. For the All Off state, the delay in activation needs to be considered in the firmware. An immediate All Off state can
always be asserted by controlling OFFx or by writing the ZXR bit to disable zero cross ringing relay operation prior to writing the
All Off state.
For option 4, LCAS CFG = 0, wire SLAC P1 to LCAS P2’, wire SLAC P2 to LCAS P1’, and wire SLAC P3 to LCAS P3’. The test
load (if enabled) will be applied when the LCAS device is in the Test, Test/Monitor, and Test Ringing states. When SLAC P1 =
1, the Ringing, Test Ringing, and Test/Monitor state will be activated when the external ringing signal is at zero cross (assuming
CCR4 RMODE is set for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0)). For the Ringing
and Test Ringing state this is the desired operation. For the Test/Monitor state, the delay in activation needs to be considered in
the firmware. An immediate Test/Monitor state can always be asserted by writing the ZXR bit to disable zero cross ringing relay
operation prior to writing the Test/Monitor state.
For option 5, LCAS CFG = 1, wire SLAC P1 to LCAS P2’, wire SLAC P2 to LCAS P1’, and wire SLAC P3 to LCAS P3’. The test
load (if enabled) will be applied when the LCAS device is in the Test, All Off, Test/Monitor, and Test Ringing states. When SLAC
P1 = 1, the Ringing, Test Ringing, and All Off states will be activated when the external ringing signal is at zero cross (assuming
CCR4 RMODE is set for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0)). For the Ringing
and Test Ringing state this is the desired operation. For the All Off state, the delay in activation needs to be considered in the
firmware. An immediate All Off state can always be asserted by controlling OFFx or by writing the ZXR bit to disable zero cross
ringing relay operation prior to writing the All Off state.
A sixth option is to use the option 4 states but use the P1 relay driver in the ISLIC device to drive an electromechanical DPDT
test-out relay. The relay would be wired between the protection and the ALINE/BLINE LCAS device pins. The relay, when
actuated, would disconnect the LCAS device and apply an alternate test bus to the loop. For this option, LCAS CFG = 0, wire
SLAC P1 to LCAS P3’, wire SLAC P2 to LCAS P2’, and wire SLAC P3 to LCAS P1’. The R1 relay driver drives the test-out
electromechanical relay. When SLAC P1 = 0 the loop is connected, Idle/Talk, Test, Ringing, and Test/Monitor states are available.
When SLAC P1 = 1 the loop is disconnected, and Idle/Talk, Test/Monitor, Ringing, and Test Ringing states are available. When
SLAC P2 = 1, the Ringing, Test Ringing, and Test/Monitor states are activated when the external ringing signal is at zero crossing
(assuming CCR4 RMODE is set for external ringing (1) and ZXR is set for enable zero cross ringing relay operation (0) and I/O
Register RD2IO (Le792284 only) is set to automatically set and clear RD2 during external ringing). For the Ringing and Test
Ringing state this is the desired operation. For the Test/Monitor state, the delay in activation needs to be considered in the
firmware. An immediate Test/Monitor state can always be asserted by writing the ZXR bit to disable zero cross ringing relay
operation prior to writing the Test/Monitor state. Since SLAC P1 is used to drive the electromechanical test-out relay, and SLAC
P2 is used to activate the LCAS device ringing states at zero crossing, the per-channel test load is not used with this scenario.
Reset
There are two possible ways to control reset of the Le75282 device.
If the OFFx pin is used, it can provide a power-up reset and an active device reset. When using a SLAC with the general purpose
I/O pins, the I/O pins can be used to control OFFx. At power-up the I/O pins default to high impedance inputs. The internal pulldown in the OFFx pin will clear the P1’-P3’ inputs and set the Le75282 device into its All Off state at power-up. After the I/O pins
are configured as outputs, they can be set high to allow programming of the Le75282 device. During operation, the RD1-RD3
control data can be cleared by bringing OFFx low.
If OFFx is not used, a power-up reset can be achieved by placing a 0.1 µf capacitor on each TSDx pin to ground. The Le75282
device will then power-up in the All Off state and remain in that state until an operating state is programmed.
15
Zarlink Semiconductor Inc.
Le75282
Data Sheet
Figure 6. Le75282 Device Application, Idle/Talk State Shown
VDD
9, 25
A1
Fuse
37
ATEST1
38
ARINGING1
Test
Access
SW3 1
36
ALINE1
Ringing
Return
SW5 1
SW1 1
Secondary
Protection
Ringing
Access
BLINE1
Fuse
SW4 1
30
BRINGING1
33
BTEST1
8, 26
A2
Fuse
SW2 1
Break
ATEST2
40
ARINGING2
22
BSLIC1
SW6 1
Le75282
Dual LCAS
Test
Access
Le79232
Dual SLIC
Battery
Monitor
VBH
41
SW3 2
42
27
FGND1
B1
34
21
ASLIC1
Break
SW5 2
ALINE2
13
ASLIC2
SW1 2
7
Secondary
Protection
SW2 2
BLINE2
Fuse
SW4 2
4
1
12
BSLIC2
SW6 2
RD11
RD21
BRINGING2
RD31
RD12
BTEST2
Latch
RD22
Switch
Control
Logic
RD32
DGND
44
CFG
B2
FGND2
24
11, 23
16
Zarlink Semiconductor Inc.
P1'
14
P2'
15
P3'
16
LD1
17
LD2
18
TSD1
28
TSD2
6
OFF1
19
OFF2
20
Le75282
Data Sheet
Table 9. Operating States: CFG = 0
Operating State
Break Switches
Ringing Switches
Test Switches
RD31
RD21
RD11
OFFx1
Idle/Talk
ON
OFF
OFF
0
0
0
1
Test
OFF
OFF
ON
0
0
1
1
Ringing
OFF
ON
OFF
0
1
0
1
1
Test/Monitor
ON
OFF
ON
0
1
1
Idle/Talk
ON
OFF
OFF
1
0
0
1
Test/Monitor
ON
OFF
ON
1
0
1
1
Ringing
OFF
ON
OFF
1
1
0
1
Test Ringing
OFF
ON
ON
1
1
1
1
All Off
OFF
OFF
OFF
X
X
X
02
Notes:
1.
RD1, RD2, and RD3 data input values are directed to a given channel when the respective LDx logic signal is set to 0. OFFx
is a per-channel control.
2.
A 0 on OFFx resets the Le75282 device, the device will remain in the All Off state until OFFx is returned to 1 and the next
LDx signal is applied.
Table 10.
Operating State
Operating States: CFG = 1
Break Switches
Ringing Switches
Test Switches
RD31
RD21
RD11
OFFx1
Idle/Talk
ON
OFF
OFF
0
0
0
1
Test
OFF
OFF
ON
0
0
1
1
Ringing
OFF
ON
OFF
0
1
0
1
All Off
OFF
OFF
OFF
0
1
1
1
Idle/Talk
ON
OFF
OFF
1
0
0
1
Test/Monitor
ON
OFF
ON
1
0
1
1
Ringing
OFF
ON
OFF
1
1
0
1
Test Ringing
OFF
ON
ON
1
1
1
1
All Off
OFF
OFF
OFF
X
X
X
02
Notes:
1.
RD1, RD2, and RD3 data input values are directed to a given channel when the respective LDx logic signal is set to 0. OFFx
and TSDx are per-channel controls.
2.
A 0 on OFFx resets the Le75282 device, the device will remain in the All Off state until OFFx is returned to 1 and the next
LDx signal is applied.
A parallel-in/parallel-out data latch is integrated into the Le75282 device. Operation of the data latch is controlled by the LDx pins.
The data inputs to the latch are the P1’-P3’ logic level pins; the output of the data latch respectively is RD1-RD3 used for state
control.
When the LDx control pin for a given channel is at logic 1 or VREF (of an Le79228 SLAC device), changes on the data inputs
will be ignored.
When the LDx control pin for a given channel is at logic 0, the latch is transparent and changes on the data inputs is passed
directly through as state control. Any changes in the data inputs will be reflected in the state of the switches. When the LDx control
pin returns to logic 1 or VREF, the state of the switches becomes latched; that is, the state of the switches will remain until another
logic 0 transition occurs.
Note in Figure 6, on page 16 that the OFFx and TSDx are not tied to the data latch. OFFx and TSDx are not affected by the LD
input. The OFFx and TSDx (in thermal shutdown state) will override the RD1-RD3 state control for that channel.
OFFx pins have internal pull-down resistors which set the Le75282 device into the All Off state at power-up.
CFG is intended to be fixed at VDD or DGND, if CFG switches states when VDD is applied, the change will be recognized by a
given channel after an LD low transition is applied to that channel.
17
Zarlink Semiconductor Inc.
Le75282
Data Sheet
PHYSICAL DIMENSIONS
44-Pin TQFP
Min
Nom
Max
Symbol
A
1.20
A1
0.05
0.15
A2
0.95
1.00
1.05
D
12 BSC
D1
10 BSC
E
12 BSC
E1
10 BSC
L
0.45
0.60
0.75
N
44
e
0.80 BSC
b
0.30
0.37
0.45
b1
0.30
0.35
0.40
ccc
0.10
ddd
0.20
aaa
0.20
JEDEC #: MS-026 (C) ACB
Notes:
1. All dimensions and toleerances conform to ANSI Y14.5-1982.
2. Datum plane -H- is located at the mold parting line and is coincident
with the bottom of the lead where the lead exits the plastic body.
3. Dimensions “D1” and “E1” do not include mold protrusion. Allowable
protrusion is 0.254mm per side. Dimensions “D1” and “E1” include
mold mismatch and are determined at Datum plane -H- .
4. Dimension “B” does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08mm total in excess of the “b” dimension at
maximum material condition. Dambar can not be located on the lower
radius or the foot.
5. Controlling dimensions: Millimeter.
6. Dimensions “D” and “E” are measured from both innermost and
outermost points.
7. Deviation from lead-tip true position shall be within ±0.076mm for pitch
!PPDQGZLWKLQIRUSLWFKPP
8. Lead coplanarity shall be within: (Refer to 06-500)
1- 0.10mm for devices with lead pitch of 0.65-0.80mm.
2- 0.076mm for devices with lead pitch of 0.50mm.
Coplanarity is measured per specification 06-500.
9. Half span (center of package to lead tip) shall be
15.30 ± 0.165mm {.602”±.0065”}.
10. “N” is the total number of terminals.
11. The top of package is smaller than the bottom of the package by 0.15mm.
12. This outline conforms to Jedec publication 95 registration MS-026
13. The 160 lead is a compliant depopulation of the 176 lead MS-026
variation BGA.
44-Pin TQFP
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
18
Zarlink Semiconductor Inc.
Le75282
Data Sheet
REVISION HISTORY
Revision A1 to B1
•
•
•
•
•
•
•
•
•
OFFx and TSDx designations changed.
P1-P3 pins changed to P1’-P3’.
Loss of Battery Detector Threshold specification added.
Table 1, ON-state Voltage not tested in production note removed.
Table 4, Test Access Switches, dc Current Limit Test Condition changed from 10 V to 20 V.
Table 5, Additional Electrical Characteristics, Loss of Battery Detector Threshold, Loss of Battery limits changed from -16 V
min and -8 V max to -19 V min and -5 V max, Resumption of Battery limits changed from -18 V min and -10 V max to -19 V
min and -5 V max.
Table 6 and 7 modified, P1 changed to RD2, P3 changed to RD1.
Application section enhanced, figure 5 added.
Table 9 and 10 modified, P3 changed to RD3, P2 changed to RD2, and P1 changed to RD1.
Revision B1 to C1
•
•
•
•
Added green package OPN to Ordering Information, on page 1
In Product Description, on page 3, changed breakdown voltage rating from > 480 V to > 320 V.
In Electrical Characteristics, changed all ON-resistance and current limit typical values to reflect actual values.
Added Package Assembly, on page 5
Revision C1 to D1
•
•
•
•
Removed Le75282BVC package option in Ordering Information, on page 1.
Added notes to table in Ordering Information, on page 1.
Diode Bridge, Electrical Specifications table moved to page 8.
Test Switch Protection Considerations section added to page 11.
Revision D1 to E1
•
•
•
•
Table 1, test condition wording for Dynamic Current Limit modified.
Table 3, test conditions for Surge Current added.
Test Switch Protection Considerations section modified.
Minor text edits.
Revision E1 to E2
•
•
Enhanced format of package drawings in Physical Dimensions, on page 18
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
19
Zarlink Semiconductor Inc.
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