DS3104DK Demo Kit Evaluates: DS3104 Timing IC

Data Sheet
May 2012
DS3104DK Demo Kit
Evaluates: DS3104 Timing IC
General Description
The DS3104DK is an easy-to-use demo and
evaluation kit for the DS3104-SE line card timing IC.
A surface-mounted DS3104-SE and careful layout
provide maximum signal integrity. An on-board 8051compatible microcontroller and included software
give point-and-click access to configuration and
status registers from a Windows®-based PC. LEDs
on the board indicate interrupt, power-supply
function, and lock status. Single-ended and
differential clocks are accessed via SMB connectors.
All LEDs and connectors are clearly labeled with
silkscreening to identify associated signals.
Windows is a registered trademark of Microsoft Corp.
Demo Kit Contents
DS3104DK Board
CD-ROM Includes:
DS3104-SE Software
DS3104-SE Initialization File
DS3104DK Data Sheet
DS3104-SE Data Sheet/Errata Sheet
Features
♦
Soldered DS3104-SE for Best Signal Integrity
♦
SMB Connectors and Termination Ease
Connectivity
♦
Careful Layout for Analog Signal Paths
♦
On-Board Stratum 3 Oscillator with Footprints
for Stratum 3E and Stratum 4 Oscillators
♦
On-Board Microcontroller and Included
Software Provide Point-and-Click Access to
the DS3104-SE Register Set
♦
LEDs for Interrupt, Power Supplies, and Lock
Status
♦
Banana Jack VDD and GND Connectors
Support Use of Lab Power Supplies
♦
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
♦
Software Provides GUI Fields for Most
Commonly Used Features Plus Full
Read/Write Access to the Entire Register Set
♦
Software Support for Creating and Running
Configuration Scripts Saves Time During
Evaluation
Minimum System Requirements
♦
PC Running Windows XP or Windows 2000
♦
Display with 1024 x 768 Resolution or Higher
♦
Available USB or Serial (COM) Port
♦
USB Cable or DB-9 Serial Cable
Ordering Information
PART
DS3104DK
DESCRIPTION
Demo kit for DS3104-SE
1
_________________________________________________________________________________________ DS3104DK
Table of Contents
1.
BOARD FLOORPLAN .................................................................................................................. 4
INPUT AND OUTPUT CLOCKS ......................................................................................................... 5
JUMPERS, HEADERS, AND SWITCH SETTINGS ................................................................................. 5
MICROCONTROLLER ..................................................................................................................... 5
POWER-SUPPLY CONNECTORS ..................................................................................................... 5
1.1
1.2
1.3
1.4
2.
BASIC HARDWARE SETUP ......................................................................................................... 6
2.1
USB DRIVER INSTALLATION .......................................................................................................... 6
INSTALLING AND RUNNING THE SOFTWARE .......................................................................... 7
3.1
COMMAND LINE OPTIONS.............................................................................................................. 7
3.
4.
OVERVIEW OF THE SOFTWARE INTERFACE ........................................................................... 8
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
GLOBAL CONFIGURATION.............................................................................................................. 8
INPUT CLOCK MONITOR, DIVIDER, AND SELECTOR ......................................................................... 8
T0 DPLL ....................................................................................................................................10
T4 DPLL ....................................................................................................................................12
T0 APLL AND T0 APLL2 .............................................................................................................13
T4 APLL.....................................................................................................................................13
OUTPUT CLOCKS.........................................................................................................................14
DPLL FREQUENCY LIMITS, PHASE DETECTORS, DPLL LOCK CRITERIA ..........................................15
REFCLK CALIBRATION ................................................................................................................15
PROGRAMMABLE DFS ..............................................................................................................15
I/O PINS ..................................................................................................................................17
REGISTER VIEW W INDOW .........................................................................................................17
CONFIGURATION SCRIPTS AND LOG FILE ...................................................................................19
4.13.1
4.13.2
Configuration Log File .......................................................................................................................... 19
Configuration Scripts ............................................................................................................................ 19
5.
APPENDIX 1: HARDWARE COMPONENTS ...............................................................................20
6.
SCHEMATICS ..............................................................................................................................22
7.
DOCUMENT REVISION HISTORY ..............................................................................................22
2
_________________________________________________________________________________________ DS3104DK
List of Figures
Figure 1-1. DS3104DK Board Floorplan .......................................................................................................................4
Figure 4-1. Software Main Screen ................................................................................................................................8
Figure 4-2. Software Input Clock Window ....................................................................................................................9
Figure 4-3. Software T0 DPLL Window ..................................................................................................................... 11
Figure 4-4. Software T4 DPLL Software .................................................................................................................... 12
Figure 4-5. Software-Programmable DFS Window ................................................................................................... 16
Figure 4-6. Software I/O Pins Window ...................................................................................................................... 17
Figure 4-7. Software Register View Window ............................................................................................................. 18
List of Tables
Table 4-1. Mapping Between Input Clock Software Fields and DS3104-SE Register Fields ................................... 10
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3104-SE Register Fields ....................................... 11
Table 4-3. Mapping Between T4 DPLL Software Fields and DS3104-SE Register Fields ....................................... 12
Table 4-4. Mapping Between T0 APLL Software Fields and DS3104-SE Register Fields ....................................... 13
Table 4-5. Mapping Between T4 APLL Software Fields and DS3104-SE Register Fields ....................................... 13
Table 4-6. Mapping Between Output Clock Software Fields and DS3104-SE Register Fields ................................ 14
Table 4-7. Mapping Between DPLL Software Fields and DS3104-SE Register Fields ............................................ 15
Table 4-8. Mapping Between REFCLK Software Fields and DS3104-SE Register Fields ....................................... 15
Table 4-9. Mapping Between I/O Pins Software Fields and DS3104-SE Register Fields......................................... 17
3
_________________________________________________________________________________________ DS3104DK
1.
Board Floorplan
Figure 1-1 shows the DS3104DK floorplan. The DS3104-SE is in the center of the board, input clock SMB
connectors are along the left edge of the board, and output clock connectors are on the right edge. Between the
input clock connectors and the DS3104-SE, land patterns are provided for several different types of local
oscillators, ranging from inexpensive XOs to higher performance TCXOs. The top edge contains, from left to right,
power-supply connectors, DC-DC converters and power-indicator LEDs, reset pushbutton, serial connector, and
USB connector. An on-board DS87C520 microcontroller is located near the USB connector. The bottom edge of
the board is occupied by a JTAG connector and LED indicators.
See Appendix 1: Hardware Components for a complete component list. Complete board schematics follow in
Section 7.
Figure 1-1. DS3104DK Board Floorplan
4
_________________________________________________________________________________________ DS3104DK
1.1
Input and Output Clocks
There are seven SMB connectors at the left of the board labeled IC3, IC4, IC7, IC8, and SYNC1–SYNC3 that
provide a single-ended clock input to the DS3104-SE. All single-ended clock inputs are connected to the
DS3104-SE with a 50Ω characteristic impedance trace and terminated with 50Ω at the device (SYNC1–SYNC3
require a jumper in the TERM position to terminate due to dual functionality). Eight additional SMB connectors
labeled IC1P, IC1N, IC2P, IC2N, IC5P, IC5N, IC6P, and IC6N provide differential clock inputs to the DS3104-SE.
These differential inputs have 50Ω trace impedance, test points, and 50Ω termination at the device (i.e., 100Ω
differential).
On the other side of the PCB are 12 SMB clock output connectors labeled OC1–OC5, OC1B–OC5B, FSYNC, and
MFSYNC. All single-ended clock outputs are buffered at the DS3104-SE and connected to the SMB connector via
a 50Ω characteristic impedance trace. Cables attached to the single-ended output connectors must have 50Ω
termination and characteristic impedance for proper operation. Eight additional SMB connectors labeled OC4P,
OC4N, OC5P, OC5N, OC6P, OC6N, OC7P, and OC7N provide connections to the differential outputs from the
DS3104-SE.
1.2
Jumpers, Headers, and Switch Settings
Jumpers JMP9–JMP12 and JMP16 (lower right of board) provide the means to pull up or pull down the TEST,
SRFAIL, LOCK, SRCSW, and SONSDH pins of the DS3104-SE. (Note that some of these jumpers only make
sense for other DS310x products where the pin has a different function.) Labels specify which position is used to
pull each pin to a 1 or a 0 (if jumper is not installed, pin is left to float to accommodate a pin’s output function).
Jumpers JMP1–JMP4 (middle right of board) provide access to the SYNC1–SYNC3 and IC9 pins of the
DS3104-SE. Labels specify the position to install the jumper to pull the pin up (signified by “1”) or pull it down
through a 50Ω resistor (signified by “TERM\0”). The 50Ω resistor is used as a termination resistor when the pin is
used as a input clock signal. Jumper JMP6 (labeled VDDIOB) is used to set the VDDIOB supply voltage for output
clock pins OC1B–OC5B. The options are labeled for 2.5V or 3.3V. Jumpers JMP62 and JMP63 select the
computer interface to be USB or RS-232. Jumper JMP5 (upper-left) selects whether the board should be powered
from the USB connector or from the power-supply jacks (J3 or J13/J19). LEDs DS1–DS4 (upper-left) indicate the
labeled power supply is operational. LED DS16 (upper-right) indicates that the microprocessor is operational. LEDs
DS5, DS6, and DS10 (lower middle) indicate the status of the SRFAIL, LOCK, and INTREQ pins, respectively.
Switch SW1 is used to select a squaring circuit to accommodate a sinusoidal input on IC3. Header J51 provides
access to the JTAG port of the DS3104-SE. Test points are provided for differential inputs and outputs, the
watchdog timer pin, SPI port pins, and ground plane connection.
1.3
Microcontroller
The DS87C520 microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware
translates memory access requests from the RS-232 serial port or USB port into register accesses on the
DS3104-SE. When the microcontroller starts up it turns on DS16 to indicate that the controller is working correctly.
A pushbutton switch labeled RESET near the RS-232 connector resets the microcontroller as well as the
DS3104-SE.
1.4
Power-Supply Connectors
A 5V lab power supply can be connected across the red (J13) and black (J19) banana jacks. Optionally, the board
can be powered from the USB connector by placing jumper JMP5 in the USB position. The 5V input from either of
these sources is then regulated to 3.3V, 2.5V, and 1.8V, and distributed to board components.
Note that the board cannot be USB powered through some USB hubs. Before trying to power the board through a
USB hub, check the voltage at JMP5 to ensure the board is getting 5V from the hub.
5
_________________________________________________________________________________________ DS3104DK
2.
Basic Hardware Setup
The following steps provide a quick start to using the DS3104DK.
1) To communicate with the board using a USB cable:
a) Configure the board for USB communication by placing jumpers to connect the middle and right pins of
JMP62 and JMP63 (i.e., place the jumpers toward the “USB” silkscreen).
b) Connect a USB cable between the USB connector on the DS3104DK and an available USB port on the
host computer.
2) To communicate with the board using a serial (RS-232) cable:
a) Configure the board for serial communication by placing jumpers to connect the left and middle pins of
JMP62 and JMP63 (i.e., place the jumpers toward the “RS232” silkscreen).
b) Connect a standard DB-9 serial cable between the serial port connector on the DS3104DK and an
available serial port on the host computer. (Be sure the cable is a standard straight-through cable
rather than a null-modem cable. Null-modem cables prevent proper operation.)
3) To power the board from a lab power supply, place the POWER jumper (JMP5) in the PS position and
connect a 5V supply across the J13 and J19 connectors.
4) To power the board from the USB port, place the POWER jumper (JMP5) in the USB position.
At this point the power indicator LEDs DS1–DS4 should be lit. Microcontroller status LED DS16 (to the right of the
USB connector) should also be lit.
2.1
USB Driver Installation
When the DS3104DK is first connected to the PC using a USB cable, an on-board USB-to-serial converter IC is
automatically detected by Windows and the Found New Hardware Wizard is automatically started. Follow these
steps to install the drivers:
1) In the first screen of this wizard, select “Install from a list or specific location” and click “Next”.
2) In the second screen, select “Search for the best driver in these locations”, check “Include this location in
the search,” and browse to the “USB” directory in the DS3104DK CD-ROM or downloaded ZIP file. Click
“Next”.
3) Click “Finished”.
4) Repeats steps 1 to 3 the second time the Found New Hardware Wizard starts.
After the drivers are installed, whenever the DS3104DK board is connected to a USB port on the PC, the Windows
operating system will see the USB-to-serial converter IC as an additional COM port. The DS3104DK software will
automatically list the additional COM port in the PORT selection combo box in the upper-left corner of the main
window.
6
_________________________________________________________________________________________ DS3104DK
3.
Installing and Running the Software
At this time the DS3104-SE demo kit software only runs on Windows 2000 or Windows XP operating systems.
To install the demo kit software, run SETUP.EXE from the disk included in the DS3104DK box or from the zip file
downloadable on the Microsemi website or from Microsemi timing products technical support.
After software installation is complete, set up the hardware as described above and run the software by doubleclicking the DS3104 Demo Kit icon on the Windows desktop or by selecting Start→Programs→Microsemi→
DS3104 Demo Kit. When the main window appears, select the correct serial port in the box in the upper-left
corner. When communication has been properly established between the software and the hardware, the ID field in
the upper-left corner should indicate 3104 rev x, where x = 0 for a revision A1 device, and x = 1 for a revision A2
device.
The demo kit software always starts in demo mode (with the DEMO MODE checkbox in the upper-left corner
checked) to allow a user to look at the software without having the DK hardware connected to the PC. To connect
the software with the demo kit hardware, uncheck the DEMO MODE box. The software optionally initializes the
DS3104-SE device and then reads the state of the device to get ready for use.
3.1
Command Line Options
The demo kit software has these command line options:
-l <filepath>
-p[port#]
specifies an alternate log file
sets the serial (COM) port number
example: “DS3104DK.exe –l mylog.mfg
example: “DS3104DK.exe –p2” sets COM2
To add command line options to the DS3104-SE demo kit shortcut that the installer adds to the desktop, right-click
on the shortcut and select Properties. In the Shortcut tab, at the end of the text in the Target textbox, add a
space followed by the command line option.
7
_________________________________________________________________________________________ DS3104DK
4.
Overview of the Software Interface
Figure 4-1. Software Main Screen
4.1
Global Configuration
In the upper-left corner of the main window are several global status and configuration fields. The ID field displays
the device part number and revision. The PORT field shows the COM port to which the DK board is connected.
The DEMO MODE check box, which is checked by default, must be unchecked to enable the software to
communicate with the DK board. The ENABLE POLLING checkbox, also checked by default, controls software
polling of the device. The RESET checkbox controls MCR1:RESET in the device. Finally, the SDH and SONET
radio buttons (which control device register field MCR3:SONSDH) specify whether 1.544MHz (SON) or 2.048MHz
(SDH) is an available frequency option for input clocks IC1–IC9.
4.2
Input Clock Monitor, Divider, and Selector
This box occupying the left-center section of the main window contains the most frequently used configuration and
status associated with input clocks IC1–IC6, IC8, and IC9. Note that the device does not have an IC7 input clock.
Just to the right of the input clock numbers are software LEDs that indicate the state of each input as reported by
its input monitor. These LEDs are red in the absence of any other condition. When a clock of the correct frequency
is applied to an input, the associated LED turns green when activity is detected. If an input is disqualified by one of
the DPLLs because the DPLL could not lock to it, the LED turns magenta.
8
_________________________________________________________________________________________ DS3104DK
In the middle of the box, the FREQ and LK MODE fields configure the frequency and lock mode (direct-lock, DIVN,
LOCK8K, or alternate direct-lock) for each input clock. At the bottom is a field to configure the DIVN divider used
for inputs configured for DIVN mode.
All the fields in the box containing the PRIORITY fields display information about either the T0 DPLL or the T4
DPLL, depending on which of two radio buttons is selected at the top of the box. The PRIORITY fields configure
the input clock priorities for the selected DPLL (1 highest, 15 lowest, 0 disabled). The SEL REF field shows the
selected reference for the DPLL, while the REF 1, REF 2, and REF 3 fields display the three highest priority valid
inputs for the DPLL. The FREQ and PHASE fields show the real-time frequency and phase reported by the DPLL.
Clicking the More button opens another window (Figure 4-2) with additional input clock configuration and status
fields. See Figure 4-1 and Table 4-1 for further details.
Figure 4-2. Software Input Clock Window
9
_________________________________________________________________________________________ DS3104DK
Table 4-1. Mapping Between Input Clock Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
MAIN WINDOW
FREQ 1 to 9
LK MODE 1 to 9
PRIORITY 1 to 9
SEL REF
REF 1
REF 2
REF 3
FREQ (ppm)
PHASE (deg)
ISR1–ISR5 registers
LED red when ACT = 1, LOCK = 0
LED green when ACT = 0, LOCK = 0
LED magenta when LOCK = 1
ICR1 to ICR9:FREQ[3:0]
ICR1 to ICR9:LOCK8K, and DIVN
IPR1 to IPR5
PTAB1:SELREF
PTAB1:REF1
PTAB2:REF2
PTAB3:REF3
FREQ1, FREQ2, and FREQ3 registers concatenated
PHASE1 and PHASE2 register concatenated
Act 1 to 9
Lock 1 to 9
Valid 1 to 9
Enable 1 to 9
Bucket 1 to 9
PHLKTO and PHLKTOM
Alarm Timeout
External Switching
Ultra-Fast Switching
Freq Range Enable
8K Polarity
Leaky Bucket Settings
ISR1 to ISR5:ACT
ISR1 to ISR5:LOCK
VALSR1, VALSR2
VALCR1, VALCR2
ICR1 to ICR9:BUCKET
PHLKTO
MCR3:LKATO
MCR10:EXTSW
MCR10:UFSW
MCR1:FREN
TEST1:8KPOL
LBxU, LBxL, BLxS, LBxD (x = 1 to 4)
Input Clock Status LEDs 1 to 9
SUBWINDOW
4.3
T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE textbox. The STATE, SRFAIL,
and PHMON buttons represent latched status bits in the device. When the button is red, the corresponding latched
status bit has been set in the DS3104-SE. Pressing the button clears the latched status bit and changes the color
of the button back to green. The STATE button indicates the state of the T0 DPLL has changed since the last time
the button was pressed. SRFAIL indicates the selected reference has failed since the last time the button was
pressed. PHMON indicates the phase monitor limit (set by PMLIM) has been exceeded since the last time the
button was pressed.
The state of the T0 DPLL can be forced using the combo box to the left of the STATE textbox, and the selected
reference can be forced using the CLK SEL field. Below the CLK SEL field is a field that configures the T0 DPLL for
revertive or nonrevertive input reference switching.
The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3104-SE T0 DPLL). The
acquisition and locked bandwidths are set by the ABW and LBW fields, respectively, and the damping factor is set
by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0
DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of
the main window), the SOFTLIM LED turns red.
The PALARM status LED and the PHASE MONITOR and BUILDOUT fields are advanced topics. See Table 4-2
and the DS3104-SE data sheet for more details. Clicking the More button opens another window (see Figure 4-3)
with additional T0 DPLL configuration and status fields.
10
_________________________________________________________________________________________ DS3104DK
Figure 4-3. Software T0 DPLL Window
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
STATE combo box
STATE status box
CLK SEL
Revertive/Nonrevertive
FREQ
ABW
LBW
DAMP
STATE latched status button
SRFAIL
PALARM
SOFTLIM
AUTOBW
LIMINT
PBOEN
PBOFRZ
RECAL
MANUAL PBO
MCR1:T0STATE
OPSTATE:T0STATE
MCR2:T0FORCE
MCR3:REVERT
Fixed by T0 DPLL architecture
T0ABW
T0LBW
T0CR2:DAMP
MSR2:STATE
MSR2:SRFAIL
TEST1:PALARM
OPSTATE:T0SOFT
MCR9:AUTOBW
MCR9:LIMINT
MCR10:PBOEN
MCR10:PBOFRZ
FSCR3:RECAL
OFFSET1 and OFFSET2
Freerun Holdover
Holdover Type
HO Ready
SYNC2K Mode
MONLIM
AEFSEN
EFSEN
INDEP
OCN
FSMON
SYNC1 Source
SYNC1 Phase
SYNC2 Source
SYNC2 Phase
SYNC3 Source
SYNC3 Phase
PD2 Enable
PD2G
PD2G8K
APBO OFFSET
MCR3:FRUNHO
HOCR3:AVG
VALSR2:HORDY
FSCR3:SOURCE, FSCR1:SYNCSRC
FSCR3:MONLIM
MCR3:AEFSEN
MCR3:EFSEN
FSCR2:INDEP
FSCR2:OCN
OPSTATE:FSMON
Derived by software from SYNC2K Mode
FSCR2:PHASE1
Derived by software from SYNC2K Mode
FSCR2:PHASE2
Derived by software from SYNC2K Mode
FSCR2:PHASE3
T0CR3:PD2EN
T0CR3:PD2G
T0CR2:PD2G8K
PBOFF
MAIN WINDOW
SUBWINDOW
11
_________________________________________________________________________________________ DS3104DK
4.4
T4 DPLL
The state of the T4 DPLL (locked or not locked) is shown in the STATE field. The LOCK and NO INPUT buttons
represent latched status bits in the device. When the button is red, the corresponding latched status bit has been
set in the DS3104-SE. Pressing the button clears the latched status bit and changes the color of the button back to
green. LOCK indicates the state of the T4 DPLL has changed since the last time the button was pressed. NO
INPUT means the T4 DPLL has no valid inputs available. The selected reference for the T4 DPLL can be forced
using the CLK SEL field.
The frequency of the T4 DPLL is displayed in the FREQ field. When the FREQ field is changed, if the SRC DPLL
field in the T4 APLL box is set to T4 then the Input Freq and Output Freq fields in the T4 APLL box change to
match the new T4 DPLL frequency, and all the T4 options in the OC1–OC7 output clock combo boxes also change
to frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3104-SE.
The bandwidth of the T4 DPLL is set by the BW field, while the damping factor is set by the DAMP field. If the
frequency of the T4 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY
LIMITS box at the top of the window), the SOFTLIM LED turns red.
The LKT4T0 and T4MT0 fields are advanced topics. See Table 4-3 and the DS3104-SE data sheet for more
details. Clicking the More button opens another window (Figure 4-4) with additional T4 DPLL configuration and
status fields.
Figure 4-4. Software T4 DPLL Software
Table 4-3. Mapping Between T4 DPLL Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
STATE
CLK SEL
FREQ
BW
DAMP
LOCK
NO INPUT
SOFTLIM
LKT4T0
T4MT0
OPSTATE:T4LOCK
MCR4:T4FORCE
T4CR1:T4FREQ
T4BW
T4CR2:DAMP
MSR3:T4LOCK
MSR3:T4NOIN
OPSTATE:T4SOFT
MCR4:LKT4T0
T0CR1:T4MT0
PD2 Enable
PD2G
PD2G8K
T4CR3:PD2EN
T4CR3:PD2G
T4CR2:PD2G8K
MAIN WINDOW
SUBWINDOW
12
_________________________________________________________________________________________ DS3104DK
4.5
T0 APLL and T0 APLL2
The Input Freq field configures the frequency of the T0 APLL DFS (refer to the DS3104-SE data sheet for details).
The APLL output frequency is always four times the input frequency. When the Input Freq field is changed, the
Output Freq field changes to match, and all the T0 options in the OC1–OC7 output clock combo boxes also change
to frequencies derived from the new T0 APLL frequency. These changes match what happens in the DS3104-SE.
In normal operation the T0 APLL2 has a fixed output frequency of 312.5MHz (twice the standard XGMII clock rate).
The rate is displayed in the T0 APLL2 Output Freq textbox.
Whenever the T0 APLL DFS or the T0 APLL2 DFS are configured for programmable DFS operation (see section
4.10) their respective Input Freq and Output Freq fields specify their frequencies with a “P” prefix to indicate that
programmable DFS mode is enabled.
Table 4-4. Mapping Between T0 APLL Software Fields and DS3104-SE Register Fields
4.6
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
Input Freq
Output Freq
T0CR1:T0FREQ
Derived by software from Input Freq
T4 APLL
The T4 APLL can be connected to the output of the T4 DPLL or to the output of the T0 DPLL as specified by the
SRC DPLL field. When SRC DPLL is set to T4, the Input Freq field follows the T4 DPLL FREQ field. When SRC
DPLL is set to T0, several frequency options are available in the Input Freq field.
The Input Freq field configures the Frequency of the T4 APLL DFS (refer to the DS3104-SE data sheet for details).
The APLL output frequency is always four times the input frequency. When the Input Freq field is changed, the
Output Freq field changes to match, and all the T4 options in the OC1–OC7 output clock combo boxes also change
to frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3104-SE.
Similarly, when the FREQ field is changed in the T4 DPLL box, if the SRC DPLL field in the T4 APLL box is set to
T4 then the Input Freq and Output Freq fields in the T4 APLL box change to match the new T4 DPLL frequency,
and all the T4 options in the OC1–OC7 output clock combo boxes also change to frequencies derived from the new
T4 APLL frequency.
Whenever the T4 APLL DFS is configured for programmable DFS operation (see Section 4.10) the Input Freq and
Output Freq fields specify their frequencies with a “P” prefix to indicate that programmable DFS mode is enabled
for the T4 APLL DFS.
Table 4-5. Mapping Between T4 APLL Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
SRC DPLL
Input Freq
Output Freq
T0CR1:T4APT0
T0CR1:T0FT4
Derived by software from Input Freq
13
_________________________________________________________________________________________ DS3104DK
4.7
Output Clocks
The fields in this box configure the DS3104-SE’s output clocks. The 2K8K SOURCE field specifies the source (T0
or T4) for the 2kHz and 8kHz clock options for output clocks OC1–OC7. Similarly, the DIG1 SOURCE, DIG2
SOURCE, DIG1, and DIG2 fields configure the Digital1 and Digital2 frequency options for OC1–OC7 (refer to the
DS3104-SE data sheet for details).
The OC1–OC7 fields specify the output frequencies for outputs OC1–OC7. Note that when the T0 APLL setting is
changed, the frequencies of all the T0 options in the OC1–OC7 fields automatically change to frequencies derived
from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the frequencies of all the T4
options in the OC1–OC7 fields automatically change to frequencies derived from the new T4 APLL frequency.
These changes match what happens in the DS3104-SE.
Whenever the T0 APLL DFS, T4 APLL DFS, or T0 APLL2 DFS are configured for programmable DFS operation
(see Section 4.10) the T0, T4 and T02 options, respectively, in the OC1–OC7 fields change to frequencies derived
from the programmable DFS settings. These options all have a “P” prefix, for example, “PT0” or “PT4” to indicate
they are controlled by the programmable DFS mode. Similarly, whenever the DIG1 DFS or the DIG2 DFS are
configured for programmable DFS operation, the DIG1 and DIG2 fields change to display the programmable DFS
frequency with a “P” prefix.
FSYNC is an 8kHz output that can be configured as a 50% duty cycle clock or a frame pulse and can optionally be
inverted. MFSYNC is a 2kHz output that can be similarly configured.
Table 4-6. Mapping Between Output Clock Software Fields and DS3104-SE Register
Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
2K8K SOURCE
DIG1 SOURCE
DIG2 SOURCE
DIG1
DIG2
OC1 to OC7
FSYNC
MFSYNC
FSCR1:2K8KSRC
MCR7:DIG1SRC
MCR7:DIG2SRC
MCR6:DIG1SS, MCR7:DIG1F
MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF
OCR1 to OCR5
OCR4:FSEN, FSCR1:8KPUL, FSCR1:8KINV
OCR4:MFSEN, FSCR1:2KPUL, FSCR1:2KINV
14
_________________________________________________________________________________________ DS3104DK
4.8
DPLL Frequency Limits, Phase Detectors, DPLL Lock Criteria
The DPLL frequency limits specify the hard and soft limits of the DPLL frequency range. When the selected
reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is
not disqualified. If the FLLOL (frequency limit loss of lock) box is checked in the DPLL Lock Criteria box, when the
selected reference for a DPLL exceeds the hard limit the DPLL will lose lock (T4 transitions to Not Locked state,
and T0 transitions to LOL state).
The remaining fields are advanced topics. See Table 4-7 and the DS3104-SE data sheet for more details.
Table 4-7. Mapping Between DPLL Software Fields and DS3104-SE Register Fields
4.9
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
MCPDEN
USEMCPD
D180
COURSELIM
FINELIM
FLEN
CLEN
FLLOL
NALOL
HARD LIMIT
SOFT LIMIT
PHLIM2:MCPDEN
PHLIM2:USEMCPD
TEST1:D180
PHLIM2:COARSELIM
PHLIM1:FINELIM
PHLIM1:FLEN
PHLIM2:CLEN
DLIMIT3:FLLOL
PHLIM1:NALOL
HARDLIM[9:0] in DLIMIT1 and DLIMIT2
DLIMIT3:SOFTLIM
REFCLK Calibration
Any known frequency error in the local oscillator can be calibrated out inside the DS3104-SE by setting the ppm
value in the REFCLK box. Also, the significant edge of the REFCLK signal can be selected in XOEDGE field.
Table 4-8. Mapping Between REFCLK Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
REFCLK slider/textbox
XOEDGE
MCLKFREQ[15:0] in MCLK1 and MCLK2
MCR3:XOEDGE
4.10 Programmable DFS
When the Programmable DFS button in the upper-right corner of the main window is pressed, the Programmable
DFS window appears (Figure 4-5). In this window one or more of the output DFS engines in the DS3104-SE can be
configured to synthesize a custom frequency that is a multiple of 2kHz (f < 77.76MHz) or a multiple of 8kHz (f ≤
311.04MHz). The desired frequency can be entered in the Target Output Clock Frequency box at the top of the
window, and the software will perform the necessary computations to fill in the other numerical fields in window.
The programmable DFS configuration can be applied to one or more DFS engines as specified in the Use
Programmable DFS box. Frequencies below 77.76MHz are typically synthesized by the DIG1 or DIG2 DFS engine
and brought out on CMOS/TTL output clock pin(s) by selecting DIG1 or DIG2 in the appropriate output clock
configuration field in the main window of the software. Frequencies of 77.76MHz or above must be synthesized
using an APLL DFS and its associated APLL and are typically brought out on differential output clock pin(s).
If a group of custom clock rates that are related to one another by factors of 1, 2, 4, 6, 8, 10, 12, 16, 20, 48, or 64
are needed, often the highest frequency clock can be produced through one of the APLL DFS blocks and then
various lower rate clocks can be selected on one or more of the output pins. Refer to the OCR1–OCR4 registers in
the DS3104-SE data sheet for details.
15
_________________________________________________________________________________________ DS3104DK
If the software-computed values for DFS Frequency, DIG1, DIG2 & APLL Input Frequency, or APLL Multiplier are
manually overridden, the user must manually ensure that the DFS Frequency falls within its allowed range and that
the APLL VCO Frequency falls within its allowed range. Note that the APL VCO Frequency does not need to be
within its allowed range if none of the APLL DFS blocks are selected for use.
The Register Configuration section of the Programmable DFS window show the values that are written to the
DFSC1–DFSC15 registers to get the configuration specified in the upper part of the window. DFSC1–DFSC15 are
located at device addresses 1E0h–1EEh, respectively.
Figure 4-5. Software-Programmable DFS Window
16
_________________________________________________________________________________________ DS3104DK
4.11 I/O Pins
The fields in this window configure the general-purpose I/O available on the DS3104-SE. See Figure 4-6,
Table 4-9, and the DS3104-SE data sheet for details.
Figure 4-6. Software I/O Pins Window
Table 4-9. Mapping Between I/O Pins Software Fields and DS3104-SE Register Fields
SOFTWARE FIELD
DS3104-SE REGISTER FIELDS
GPIO1 to GPIO4 Config
GPIO1 to GPIO4 Status
INTREQ Mode
INTREQ Polarity
INTREQ Open-Drain Enable
LOCK Pin Enable
SRFAIL Pin Enable
OC1B to OC5 Enable
OC4POS/NEG to OC7POS/NEG format
GPCR:GPIOxD and GPIOxO
GPSR:GPIOx
INTCR:LOS, GPO
INTCR:POL
INTCR:OD
MCR1:LOCKPIN
MCR10:SRFPIN
OCR6:OCxEN
MCR8:OC4SF to OC7SF
4.12 Register View Window
When the Register View button in the upper-right corner of the main window is pressed, the Register View window
appears (Figure 4-7). In this window the DS3104-SE’s entire register set can be viewed and manually written as
needed.
The large grid that takes up most of the window displays the DS3104-SE register map. For each register, its
hexadecimal address in square brackets is followed by its register name and its contents in two-digit hex format.
When a register is clicked in the main register grid, its register description and fields are displayed at the bottom of
the window. Due to the limited speed of the serial port, the demo kit software does not continually poll every
register and does not make real-time updates to the data displayed on the Register View screen. Registers can be
manually read as described below.
17
_________________________________________________________________________________________ DS3104DK
The Register View window supports the following actions:
•
•
•
•
•
•
Read a register. Select the register in the register map.
Read a register field. Select the register in the map or the register field at the bottom of the window.
Read all registers. Press the Read All button.
Write a register. Double-click the register name in the register map and enter the value to be written.
Write a register field. Select the register, double-click the field, and enter the value to be written.
Write a multiregister field. Double-click one of the register names and enter the value for the field.
Figure 4-7. Software Register View Window
18
_________________________________________________________________________________________ DS3104DK
4.13 Configuration Scripts and Log File
4.13.1 Configuration Log File
Every write command issued by the software to the DS3104DK board is logged in file DS3104DKLog.mfg located
in the same directory as the software executable. This file can be viewed in Notepad by pressing the Log File
button in the upper-right corner of the main window. Command line option "-l <filepath>" can be used to cause the
software to write to a file other than DS3104DKLog.mfg.
4.13.2 Configuration Scripts
All or part of the text in the Configuration Log File can be copied to a text file with a .mfg file extension for use as a
configuration script. Configuration scripts are useful for quickly configuring the DS3104-SE without having to
remember all the required settings.
Two types of configuration scripts are possible: full and partial. A full configuration script can start with the
DS3104-SE in its power-on default state and configure every aspect of the device to bring it to a desired state. To
make a full configuration script, run the software, uncheck the Demo Mode checkbox, initialize the device,
configure the device using the DK software fields, press the Log File button, and use File→Save As in Notepad to
save a copy of the entire log file to a different file name.
A partial configuration file only affects a subset of the DS3104-SE device settings. To make a partial configuration
script, press the Log File button to view the Log File, press Ctrl-End to jump to the end of the file, and add to the
end of the file a carriage return or comment line (starting with a semicolon) to delimit the start of the desired
configuration. Then save and exit the Log File. Next, configure the device using the DK software fields. Finally,
view the log file again, jump to the end, and copy everything from the delimiter to the end of the file into a new .mfg
file.
To run a configuration script, press the Config Script button in the upper-right corner of the main window. In the
script window, type the path to the file or press the Browse button to navigate to the file.
Note that when the Demo Mode checkbox is unchecked, during the "Initializing the DS3104" step, the software
runs configuration script startup.mfg located in the same directory as the software executable. The startup.mfg file
can be edited or replaced as needed to change the initial configuration of the device. Be aware, however, that the
section of the startup.mfg file labeled “Required Initialization” must be executed after device power-up or reset for
the DS3104 to operate correctly.
19
_________________________________________________________________________________________ DS3104DK
5.
Appendix 1: Hardware Components
DESIGNATION
C1, C2, C5, C6,
C9–C12, C15, C42,
C59–C138, C140,
C142, C143, C145,
C147, C151, C155,
C163–C166, C168,
C169
C3, C13 ,C14, C16,
C41
C4, C17, C18, C20
C7
QTY
DESCRIPTION
SUPPLIER
PART
103
0.1µF ±20% 16V X7R ceramic capacitors (0603)
AVX
0603YC104MAT
5
4.7µF ±10%, 25V X5R ceramic capacitors (1206)
PAN
ECJ-3YB1E475K
4
6.8µF ±10%, 6.3V X5R ceramic capacitors (1206)
PAN
ECJ-3YB0J685K
1
68µF ±20%, 16V tantalum capacitor (D case)
PAN
ECS-T1CD686R
C8
1
0.01µF ±10%, 50V X7R ceramic capacitor (0603)
AVX
06035C103KAT
C19
C34–C38, C51–C58,
C139, C141, C153,
C154
C39, C40
1
100µF ±20%, 4V ceramic capacitor (1206)
TAI
AMK316BJ107ML-T
17
10µF ±20%, 10V ceramic capacitors (1206)
PAN
ECJ-3YB1A106M
2
22pF ±10%, 100V ceramic capacitors (1206)
AVX
12061A220KAT2A
C43
D1
1
1
1µF ±10%, 16V ceramic capacitor (1206)
DIODE 1A 50V GEN PURPOSE SILICON
PAN
GEN
ECJ-3YB1C105K
1N4001
D2, D7
DS1–DS4, DS6
2
5
SCHOTTKY DIODE, 1 AMP 40 VOLT
SMD green LEDs
IRF
PAN
10BQ040
LN1351C
DS5, DS10
DS16
J1, J2, J4–J12,
J15–J18, J20–J31,
J34–J41
2
1
SMD red LEDs
SMD green LED
PAN
PAN
LN1251C
LN1351C
35
CONNECTOR, SMB, 50 OHM VERTICAL, 5PIN
AMP
413990-1
J3
1
CONN 2.1MM/5.5MM PWRJACK RT ANGLE PCB,
closed frame, high current [email protected]
CUI, INC
PJ-002AH
J13
1
SOCKET, BANANA PLUG, HORIZONTAL, RED
MSR
164-6219
J14
1
CONNECTOR, SMB, 50 OHM VERTICAL, 5PIN,
DO NOT POPULATE
AMP
413990-1
J19
1
SOCKET, BANANA PLUG, HORIZONTAL, BLACK
MSR
164-6218
J50
1
CONN, DB9 RA, LONG CASE
AMP
747459-1
J51
1
TERMINAL STRIP, 10 PIN, DUAL ROW, VERT
J54
1
CONN, USB, TYPE B SINGLE RT ANGLE, BLACK
MOL
67068-0000
11
L_HEADER, 3-PIN, .100 CENTERS, VERTICAL
STC
TSW-103-07-T-S
4
L_2 PIN HEADER, .100 CENTERS, VERTICAL
STC
TSW-102-07-T-S
3
DO NOT PLACE, SHORTED 2PIN TH JUMPER
NA
2
L_3 PIN HEADER, .100 CENTERS, VERTICAL
STC
JMP1–JMP6,
JMP9–JMP12,
JMP16
JMP7, JMP8,
JMP36, JMP37
JMP13, JMP14,
JMP15
JMP62, JMP63
NA
NA
NA
TSW-103-07-T-S
20
_________________________________________________________________________________________ DS3104DK
DESIGNATION
R1–R4, R17, R19,
R20, R25–R27, R33,
R34, R41, R43, R45,
R47–R63, R111,
R112, R117, R118
R5, R11, R13, R15,
R21–R24, R29–R32,
R65–R68
R6
R7, R9, R10, R12,
R14, R84, R110,
R113, R115, R116,
R120–R123
R8, R16, R18, R46,
R64, R83, R100,
R101, R102
R28
QTY
DESCRIPTION
SUPPLIER
PART
36
L_RES 0603 0 Ohm 1/16W 1%
AVX
CJ10-000F
16
L_RES 0603 51.1 Ohm 1/16W 1%
PAN
ERJ-3EKF51R1V
1
RES 0603 100K Ohm 1/16W 5%
PAN
ERJ-3GEYJ104V
14
L_RES 0603 10K Ohm 1/16W 5%
PAN
ERJ-3GEYJ103V
9
RES 0603 DO NOT POPULATE
NA
1
RES 0603 33.2 Ohm 1/16W 1%
PAN
ERJ-3EKF33R2V
R35–R40, R42, R44,
R94, R108
10
L_RES 0603 330 Ohm 1/16W 5%
PAN
ERJ-3GEYJ331V
R97
1
RES 0603 20K Ohm 1/16W 5%
PAN
ERJ-3GEYJ203V
SW1
SW5
TP1–TP22,
TP49–TP60,
TP65–TP84
1
1
SWITCH DPDT SLIDE 6PIN TH
SWITCH MOM 4PIN SINGLE POLE
TYC
PAN
SSA22
EVQPAE04M
54
Test Points, 1 PLATED HOLE, DO NOT STUFF
NA
NA
U1, U2, U5, U9–U24,
U27, U28, U30–U34
26
L_TINYLOGIC HIGH SPEED 2-INPUT OR GATE,
5 PIN SOT23
FAI
NC7SZ32M5
U3
1
IC, LINE CARD TIMING, -40°C to +85°C, 64 PIN
QFP, DO NOT POPULATE
DAL
NOT POPULATED
U4, U6
2
LINEAR REGULATOR, 3.3V, 16 PIN TSSOP-EP
MAX
MAX1793EUE-33
U7, U25
2
L_TINYLOGIC HIGH SPEED 2-INPUT XOR
GATE, 5 PIN SOT23
U8
1
LINEAR REGULATOR, 1.8V, 16 PIN TSSOP-EP
MAX
MAX1793EUE-18
U26
1
IC, LINEAR REGULATOR, 1.5W, 2.5V OR ADJ,
1A, 16 PIN TSSOP-EP
MAX
MAX1793EUE-25
U29
1
IC, TCXO, 12.8MHz, 0°C to +70°C, 16-PIN SOIC
DAL
DS4026+BCC
U35
1
DAL
DS3104-SE
U41
1
DAL
DS232AS
U42
1
DAL
DS87C520-ECL
U44
1
MAX
MAX811TEUS-T
U45
1
MAX
MAX812MEUS-T
U46
1
IC, LINE CARD TIMING WITH SYNCHRONOUS
ETHERNET SUPPORT, -40 TO 85C, 81 PIN BGA
DUAL RS-232 XMITR/RCVR 16 PIN SOIC (300
MIL)
HIGH SPEED MICRO 44-PIN TQFP 0°C to +70°C
MICROPROCESSOR VOLTAGE MONITOR,
3.08V RESET, 4PIN SOT143
MICROPROCESSOR VOLTAGE MONITOR,
4.38V RESET, 4PIN SOT143
IC, SINGLE-CHIP USB TO UART BRIDGE, 28 PIN
QFN
FAI
SIL
NA
NC7SZ86M5
CP2101
21
_________________________________________________________________________________________ DS3104DK
6.
DESIGNATION
QTY
Y1
1
Y2
1
Y3
1
Y4
1
Y7
1
DESCRIPTION
OSCILLATOR, CRYSTAL CLOCK, 3.3V 12.8MHz
OSCILLATOR, RAKON TCXO, 3.3V, 12.8MHz, 4
PIN SMD
OSCILLATOR, CRYSTAL CLOCK XO 1613,
3.3V CMOS, LOW JITTER-12.8MHz, 4-PIN
SMD, DO NOT POPULATE
OSCILLATOR, CRYSTAL CLOCK XO 1633,
3.3V CMOS, LOW JITTER-12.8MHz, 4-PIN
SMD, DO NOT POPULATE
XTAL, LOW PROFILE, 11.0592MHz
SUPPLIER
PART
SAR
NTH069A3-12.8
RAK
E4837LF
SAR
S1613A-12.8000
SAR
S1633A-12.8000
PLE
LP49-33-11.0592M
Schematics
The schematics are featured in the following pages.
7.
Document Revision History
REVISION
DATE
061107
071607
092107
101607
112007
DESCRIPTION
Initial release.
Removed reference to definition files under Demo Kit Contents (rather, software is included);
added that a USB or serial COM is available to the Minimum System Requirements (third
bullet) section.
In Section 4.13.2, fourth paragraph, deleted last two sentences; in the fifth paragraph, added
new last sentence.
In Appendix 1, component U3, changed Part to “Not Populated.”
Removed references to “included international power supply.” Not shipping power supply
because the board can be USB powered.
In Section 1.1, added a sentence indicating that cables connected to single-ended outputs
must have 50Ω termination.
In Appendix 1, changed component Y2 to Rakon TCXO E4837LF.
2012-05
Reformatted for Microsemi. No content change.
22
A
8
C163.1UF
1
1
2
1
2
B
C164.1UF
1
2
7
SYNC1
SYNC2
SYNC3
IC1NEG
IC1POS
IC2NEG
IC2POS
IC3
IC4
IC5POS
IC5NEG
IC6POS
IC6NEG
IC8
IC9
IC8
IC9
F9
G9
SYNC3
IC6NEG
J6
G8
IC6POS
H6
SYNC2
IC5NEG
J4
SYNC1
IC5POS
H4
H9
IC4
J9
H8
IC2POS
IC3
J8
IC2NEG
H7
J7
VDD2
INTREQ/SRFAIL
VDD1
WDT
JTRST
JTCLK
JTDI
JTMS
JTDO
JTDO
JTCLK
JTDI
JTRST*
F8
A9
A8
E9
C8
JTMS
GPIO4/SONSDH
6
BGA
OR DS3102
DS3104_U1
U35
NA
VDD_OC45
VSS1
IC1POS
VSS2
H5
VSS3
IC1NEG
VDDIO1
VSS4
J5
VDDIO2
SRFAIL
SRCSW
RST*
REFCLK
TEST
E3
G5
VDD_OC67
DUT33
5
VDDIOB
VSS_OC45
DUT18
AVDD_PLL1
VSS_OC67
5
DUT18
AVDD_PLL2
AVSS_PLL1
6
VDDIO3
VSS5
C
C165.1UF
VPLL1
VPLL2
VPLL3
VPLL4
C166.1UF
2
AVDD_PLL3
AVSS_PLL2
C5
E6
G6
VDD3
LOCK
A2
C1
B9
B3
G1
F7
D8
B1
G7
TEST
REFCLK
PORNOT
SONSDH
SRCSW
SRFAIL
WDT
INTREQ
LOCK
AVDD_PLL4
AVSS_PLL3
C4
D6
F6
G3
VDDIO4
VSS6
D4
D5
E4
E5
F4
F5
D2
A4
B6
E1
E2
J2
H2
J3
H3
OC4POS
OC5
OC5B
OC5NEG
OC5POS
OC6NEG
OC6POS
OC7NEG
OC7POS
4
D1
OC4B
OC4NEG
E7
D7
CPOL
C9
CPHA
E8
SDI
SCLK
C7
A6
OC4
SDO
A3
D9
B5
OC3B/GPIO3
CS*
B7
OC3
H1
A5
OC2B/GPIO2
J1
A7
OC2
MFSYNC
B4
OC1B/GPIO1
FSYNC
B8
OC1
4
NA
1
3
SCLK
CPHA
CPOL
CS
SDO
1
SDI
R34
0.0
2
OC3B
OC4
OC4B
OC4NEG
OC4POS
OC5
OC5B
OC5NEG
OC5POS
OC6NEG
OC6POS
OC7NEG
OC7POS
FSYNC
MFSYNC
ENGINEER:
TITLE:
3
OC1 TP20
NA
OC1B
OC2 TP21
NA
OC2B
TP22
OC3
1
C6
VDDIOB
R25
VPLL1
B21
2 0.0
VPLL2 R26
C2
1
2
0.0
R27
VPLL3
F2
1
2 0.0
R33
VPLL4
F3
1
2 0.0
D3
G4
AVSS_PLL4
A1
C3
F1
G2
1
DS6
SONSDH
SRFAIL
LOCK
TEST
SRCSW
JML
2
1
1
1
1
1
DS10
RED GREEN
DS3104DK01B0
DS5
2
INTREQ
2
SRFAIL
2
R35
1
1
330
R40
2
7
R42
330
RED
NA
TP16
3
3
3
3
3
2
1
LOCK
2
1
1
2
330
2
1
D
8
VCC
WDT
NA
TP17
VCC
1
VCC
JMP10
JMP11
JMP12
JMP16
NA
NA
NA
JMP9NA
NA
PAGE:
DATE:
1
1 OF 12
013007
Wed May 30 13:54:19 2007
1
R94
1
1
2
330
2
2
2
2
2
R97
C8
R44
20K
.01UF
330
1
2
2
1
2
R8
DNP
1
CPHA
2
R10
10K
1
1
2
R83
DNP
1
CPOL
2
R84
10K
1
A
B
C
D
A
B
8
7
JTMS
JTDO
50
6
REFCLK
6
SONSDH 64
TEST 2
PORNOT 48
INTREQ 5
SRCSW 13
SRCSW
QFP
OR DS3106
DS3105_U2
U3
DS3105-SE
NA
I26
5
VDDIO2
VDD4
VSS4
VDD3
VSS3
VDD2
VSS2
VDD1
VSS1
27
39
57
58
INTREQ/SRFAIL
RST*
TEST
GPIO4/SONSDH
SYNC2
SYNC1
IC9
34
SYNC1 28
SYNC2 33
IC6POS
IC6NEG
IC5NEG
24
26
IC5POS
25
IC4
30
23
IC3
REFCLK
JTDI
41
29
JTCLK
51
IC3
IC4
IC5POS
IC5NEG
IC6POS
IC6NEG
IC9
JTRST*
VSS5
37
VDD_OC6
VSS6
49
VSS7
JTRST
JTCLK
JTDI
JTMS
JTDO
VSS_PLL1
22
59
AVDD_DL
DUT33
VDD_PLL1
VSS_PLL2
DUT18
5
VDD_PLL2
6
VDDIO1
VSS8
1
15
16
31
40
53
60
62
VSS_OC6
C
7
VDDIO3
AVSS_DL
21
55
4
VDD_PLL3
VSS_PLL3
D
8
14
32
54
61
VDDIO4
VPLL1
VPLL2
VPLL3
VPLL4
4
7
9
11
VDD_PLL4
VSS_PLL4
4
3
8
10
12
46
O6F1/GPIO2
18
52
43
SDO
SDI
CS*
CPHA
SCLK
FSYNC
MFSYNC
SDO
SDI
47 SCLK
42 CPHA
44 CS
17
FSYNC
MFSYNC
O6F2/GPIO3
45
O6F0/GPIO1
OC1B
OC2B
63 OC3B
38
O3F2/LOCK
35
O3F0/SYNC3
O3F1/SRFAIL
SYNC3
SRFAIL
36 LOCK
20
OC6POS
56
OC3
OC6NEG
OC3
OC6NEG
19 OC6POS
3
3
ENGINEER:
TITLE:
JML
2
DS3104DK01B0
2
PAGE:
DATE:
1
2 OF 12
013007
Wed May 30 13:54:21 2007
1
A
B
C
D
A
B
C
R101 DNP
2
2
DNP
8
GND
1
OUT
VCC
GND
VC
GNDA
GND
1
11
14
VCCD
VOSC
VCC
VREF
FOUT
DS4026_U
GNDD
GNDOSC
SCL
13
5
SDA
12
VS
RF_OUT
U29
12.8MHZ
2
1
Y2
OSC_TCXO
5
8
12.8MHZ_3.3V
Y1
OSC
OSC33
2
12.8MHZ_3.3V
4
1
DNP
R18
3
4
7
16
4
3
2
15
1
1
1
R46
33.2
R28
2
2
2
R5
.1UF
C1
REFCLK
2
6
1
4
1
4
1
B
A
U25
C
U7
B
A
C
100K
2
4
4
OUT
VCC
5
8
GND
1
OSC
Y4
OUT
VCC
5
OSC33
5
8
12.8MHZ_3.3V_XO
GND
1
OSC
Y3
12.8MHZ_3.3V_XO
1
R6
NC7SZ86
2
1
NC7SZ86
2
VCC 1
2
1
5
R64
SW1
DPDT
5
4
6
3
1
REFCLK
2
J12
J11
J10
J9
J8
J7
4
1
1
1
1
1
1
4
3
3
ENGINEER:
TITLE:
JML
2
DS3104DK01B0
2
1
1
R9
10K
R32
51.1
1
R12 10K
1
1
1
VCC
2
2
R11
51.1
VCC
2
2
2
VCC
R13
51.1
2
2
R15
51.1
R14 10K
1
VCC
2
JMP1
R7
10K
1
PAGE:
DATE:
1
3 OF 12
013007
Wed May 30 13:54:19 2007
2
2
SYNC3
SYNC1
2
SYNC2
2
IC9
1
IC8
IC4
IC3
JMP4
INPUT CLOCKS
OSC33 1
1
R100
NA
TP18
R16
1
51.1
THE INVERTERS THAT
CAN BE SWITCHED INTO
IC3 PATH ARE USED
TO SQUARE A CLOCK
THAT IS SINUSOIDAL
DNP
1 1
2
1
J14
11
1
J6
1
C5
C2
2
1
100UF
2
1
2
.1UF
.1UF
1
C11 .1UF
2
NA
TP19
D
C12 .1UF
1
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE
6
.1UF
R29
R30
R31
51.1
51.1
51.1
2
1
2
1
2
1
7
C10
1
3
1
3
1
3
1
8
C15 .1UF
1
2
1
2
R102
C19
DNP
2
JMP3
3
DNP
2
JMP2
DNP
A
B
C
D
INPUT CLOCKS
7
6
TP11
TP12
TP7
TP8
1
1
5
IC2NEG
2
4
J37
J36
IC2POS
JMP8
J35
J34
IC1NEG
2
JMP7
IC1POS
4
1
1
1
1
TP51
TP52
TP49
TP50
3
TITLE:
DS3104DK01B0
TP55
TP56
TP53
TP54
2
1
1
8
3
ENGINEER:
JML
2
PAGE:
DATE:
1
4 OF 12
013007
Wed May 30 13:54:20 2007
IC6NEG
2
JMP37
IC6POS
IC5NEG
2
JMP36
IC5POS
1
C
D
A
TP9
TP10
TP5
TP6
5
A
1
1
1
1
2
B
J31
J30
J29
J28
6
2
B
C
D
7
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE
8
1
1
1
1
1
1
1
1
R21
R22
R23
R24
2 1
1
51.1
51.1
51.1
51.1
2
2 1
1
1
1
1
1
1
1
1
1
R65
R66
R67
R68
2 1
1
51.1
51.1
51.1
51.1
2
2 1
1
A
B
C
D
OC5B
OC5
OC4
OC3
OC2
OC1
8
OUTPUT CLOCKS
8
1
1
1
1
1
1
0.0
R51
0.0
R49
0.0
R47
0.0
R45
0.0
R43
0.0
R41
B
A
C
4
U9
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
7
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
4
U20
4
U19
4
U18
4
U17
4
U16
4
U15
4
U14
4
U13
4
U12
4
U11
4
NC7SZ32 U10
2
2 1
7
1
1
1
1
1
1
0.0
R50
0.0
R57
0.0
R56
0.0
R54
0.0
R52
0.0
R48
2
2
2
2
2
2
6
6
1
1
1
1
1
1
J25
J24
J23
J22
J21
J20
5
5
OC4B
4
OC3B
OC2B
OC1B
MFSYNC
FSYNC
4
1
1
1
1
1
1
0.0
R20
0.0
R19
0.0
R17
0.0
R1
0.0
R55
0.0
R53
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
B
A
C
C
4
U27
B
C
B
A
C
B
A
C
B
A
C
B
A
C
U31
4
U34
4
U33
U32
4
4
4
U2
U1
U24
U23
U22
U21
ENGINEER:
TITLE:
3
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
A
B
A
4
4
4
4
4
4
NC7SZ32
U30
1
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
NC7SZ32
2
1
NC7SZ32
2
2 1
3
1
1
1
1
1
0.0
R62
0.0
R61
0.0
R60
0.0
R59
0.0
R58
0.0
R63
2
2
2
2
2
2
JML
2
DS3104DK01B0
1
2
J18
J17
J16
J1
J27
J26
PAGE:
DATE:
1
5 OF 12
013007
Wed May 30 13:54:20 2007
1
1
1
1
1
1
1
A
B
C
D
7
6
5
J15
J5
J4
J2
4
4
OC7NEG
OC7POS
OC6NEG
OC6POS
TP58
TP57
TP60
TP59
3
TITLE:
DS3104DK01B0
2
J39
J38
J41
J40
8
3
ENGINEER:
JML
2
PAGE:
DATE:
1
6 OF 12
013007
Thu Feb 15 16:29:11 2007
1
1
1
1
1
C
D
A
1
1
1
1
5
A
OUTPUT CLOCKS
TP4
TP3
TP2
TP1
6
B
OC5NEG
OC5POS
OC4NEG
OC4POS
7
B
C
D
8
1
1
1
1
1
1
1
1
3
6
5
4
3
ENGINEER:
TITLE:
JML
2
DS3104DK01B0
2
Wed Feb 21 13:57:17 2007
1
C
D
PAGE:
DATE:
1
7 OF 12
013007
A
7
4
A
8
5
INTENTIONALLY LEFT BLANK
6
B
7
B
C
D
8
A
B
8
7
1
3
1
C34
2
GND
T2IN
T1IN
R2IN
R1IN
C1NEG
TXD0
J
H
G
F
E
D
C
B
A
J50
6
C38
1
TX232
5
4
1
RXD0
JMP633
10UF
TX232
3 RX232
2
1
CONN_DB9P
9
8
7
6
7
14
9
12
5
4 2
15
16
USB_RXD
T2OUT
T1OUT
R2OUT
R1OUT
C2NEG
C2POS
VNEG
C1POS
VCC
VPOS
U41
DS232A
USB_TXD
JMP623
10
11
8
13
10UF
1 1
10UF
RX232
2 C37
C35
12
10UF
2 C36
16
2
2
V5_0
2
RS232
5
5
4
4
SDI
330
R108
P2_3
P2_2
P2_1
P2_0
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
XTAL1
XTAL2
GND<2-0>
8
9
10
11
12
13
14
11.0592MHZ 15
1
Y7
2
RXD0
TXD0
INTREQ
18
19
20
21
22
23
24
25
26
27
29
30
3
ENGINEER:
TITLE:
V5_0
VCC
2
JML
2
DS3104DK01B0
DS87C520_TQFP
P2_4
P2_5
P2_6
P2_7
PSEN
ALE
EA
AD7
AD6
7
32
AD5
31
33
AD4
5
2
TP13
POR
0.0
RST
34
AD3
4
1
R4
2
TP14
P1_7
35
AD2
P1_6
36
AD1
3
37
AD0
2
38
VCC
P1_5
P1_2
42
1
DS16
2
1
P1_1
41
2
P1_4
P1_0
40
U42
14
44
2
TP15
C
U5
NC7SZ32
B
A
GREEN
P1_3
0.0
0.0
1
2
NA
3
43
1
SCLK R31
CS
R2
22PF
6
22PF C40
C
7
FIRMWARE V2.28
D
8
1
C39
2
1
1
1
1
2
2
1
10UF
PAGE:
DATE:
1
8 OF 12
013007
Wed May 30 13:54:18 2007
R110
10K
1
A
B
C
D
A
B
8
4
3
2
SW5
1
3
1
9
7
5
3
1
8
MR*
GND
7
10
8
6
4
2
CONN_10P
10
7
9
6
4
3
5
2
1
RESET*
VCC
MAX811_U
U44
3.08V
JTCLK
JTDO
JTMS
JTRST
JTDI
2
4
1
0.0
R111
VCC
2
3
GND
MR*
6
PORNOT
1
RESET
VCC
U45
MAX812_U
4.38V
2
4
1
5
0.0
R112
V5_0
2
POR
VDD
DATDAT+
GND
SH
J54
USB
C
1
2
3
4
1
4
2
1
1
2
2
R115
10K
USBPWR
C43
NA
5
J51
C42
.1UF
1
2
10K
VCC
12
11
7
9
8
4
5
SUSPEND_HIGH
ENGINEER:
TITLE:
3
U46
NA
CP2101_U1
SUSPEND_LOW*
REGIN
RST*
VBUS
USBDP
USBDM
18
NC7
19
20
21
22
NC8
NC9
NC10
NC11
RI*
1 1
2 1
JML
28 1
27 1
25 1
24 1
23 1
2
R117
0.0
2
2
2
R121
10K
R122
10K
R123
10K
1
PAGE:
DATE:
1
9 OF 12
013007
Wed May 30 13:54:19 2007
2
2
2
TP84
R120
10K
USB_RXD
USB_TXD
TP83
R118 0.0
26 1
DCD*
DSR*
DTR*
CTS*
RTS*
RXD
TXD
2
DS3104DK01B0
GND
2
10K
3
NC1
3
4
NC2
R113
5
2
1
6
VDD
NC3
1
6
NC4
7
NC5
D
8
NC6
10
13
14
15
16
17
1UF R116
4.7UF
C41
A
B
C
D
A
B
C
8
B
A
1
2
B
A
C
41
U28
NA
DUT331
OSC331
1
330
R39
330
R38
330
R37
330
R36
V5_0
1
2
1
2 1
DS4
2 1
DS3
2 1
DS2
2 1
DS1
V5_0
1
2
CONN_BANANA_2P
J19
J3
2.1MM/5.5MM
NC7SZ32
2
DUT18 1
B
A
CONN_BANANA_2P
J13
2
USBPWR 3 JMP5 1
1
7
2
2
2
2
2
68UF
C7
2
6
1
2
V5_0
V5_0
V5_0
V5_0
10
GND
IN2
IN3
IN4
SHDN*
3
4
5
7
11
10
GND
6
RST*
SET
15
14
13
12
OUT4
OUT3
OUT2
OUT1
IN2
IN3
IN4
3
4
5
GND
SET
RST*
OUT4
OUT3
OUT2
OUT1
10
11
6
15
14
13
12
5
MAX1793_U2
SHDN*
IN1
2
MAX1793_U2
U8
IN1
2
7
11
6
RST*
SET
15
14
13
12
OUT4
OUT3
OUT2
OUT1
MAX1793_U2
U6
SHDN*
7
IN3
4
IN4
IN2
5
IN1
3
U4
2
5
1
JMP13
4
1
1
4
JMP15
D7
JMP14
2
2
2
DUT18
1 AMP
OSC33
DUT33
VCC
3
C3
3
ENGINEER:
TITLE:
IN3
IN4
4
5
JML
10
GND
2
D2
DUT33
1
JMP6
3
VDDIOB
1 AMP
1
PAGE:
DATE:
1
10 OF 12
013007
Wed May 30 13:54:20 2007
11
6
15
14
13
12
SET
RST*
OUT4
OUT3
OUT2
OUT1
MAX1793
SHDN*
IN2
3
7
IN1
2
U26
2.5 VOLT REGULATOR
C4
2
DS3104DK01B0
V5_0
4.7UF
D
6
1
2
1
1
2
7
6.8UF
1
2
1
2
2
8
C13
C14
C16
4.7UF
4.7UF
4.7UF
C17
C18
C20
1
2
1
2
1
2
6.8UF
6.8UF
6.8UF
2
1
2
D1
A
B
C
D
A
B
C52
C51
8
1
2
VCC
VCC
C56 10UF
1
GND
DUT18
2
2
1
2
1
C63
TP65
1
1
2
.1UF
1
C67 .1UF
1
2
1
C71 .1UF
1
2
1
C75 .1UF
1
2
1
7
TP68
TP69
C79 .1UF
2
1
2
1
2
1
2
1
2
1
2
1
1
C83 .1UF
1
C87 .1UF
1
C91 .1UF
1
C95 .1UF
1
C99 .1UF
1
6
TP74
C103 .1UF
2
1
2
1
2
1
2
1
1
6
C107 .1UF
1
C111 .1UF
1
C115 .1UF
1
C119 .1UF
1
2
1
TP79
C123 .1UF
5
2
1
2
1
2
1
2
1
1
C127 .1UF
1
C131 .1UF
5
1
1
.1UF
7
1
1
1
1
1
1
C132 .1UF
2
2
.1UF
1
C55 10UF
C59 10UF
1
C64 .1UF
2
1
C72 .1UF
2
1
C80 .1UF
1
C84 .1UF
2
1
C92 .1UF
2
1
C100 .1UF
1
C104 .1UF
2
1
C112 .1UF
2
1
C120 .1UF
1
C124 .1UF
2
2
1
1
2
C60 10UF
2
1
2
1
2
2
1
2
1
2
2
1
2
1
2
2
1
C128 .1UF
1
C133 .1UF
C136 .1UF
C137 .1UF
VCC
DUT33
1
1
C61 10UF
1
C65 .1UF
2
C68 .1UF
1
C73 .1UF
2
C76 .1UF
1
C81 .1UF
1
C85 .1UF
2
C88 .1UF
1
C93 .1UF
2
C96 .1UF
1
C101 .1UF
1
C105 .1UF
2
C108 .1UF
1
C113 .1UF
2
C116 .1UF
1
C121 .1UF
1
C125 .1UF
2
2
2
C
C53
2
C57 10UF
2
2
1
2
1
2
2
1
2
1
2
2
1
2
1
2
2
1
1
2
.1UF
8
1
1
C62 10UF
1
C66 .1UF
C69 .1UF
1
C74 .1UF
C77 .1UF
1
C82 .1UF
1
C86 .1UF
C89 .1UF
1
C94 .1UF
C97 .1UF
1
C102 .1UF
1
C106 .1UF
C109 .1UF
1
C114 .1UF
C117 .1UF
1
C122 .1UF
1
C126 .1UF
C129 .1UF
1
C134 .1UF
2
C138 .1UF
D
C54
2
C58 10UF
2
2
2
C70 .1UF
2
2
C78 .1UF
2
2
2
C90 .1UF
2
2
C98 .1UF
2
2
2
C110 .1UF
2
2
C118 .1UF
2
2
2
C130 .1UF
2
1
2
TP66
TP67
TP73 TP71 TP70
TP72
TP77 TP75
TP76
TP78
TP81
TP82
TP80
1
C135 .1UF
1
.1UF
4
4
C6
C153
1
2
C139
1
2
OSC33
10UF
C154
2
1
1
10UF
C141
2
1
V5_0
1
10UF
C155
2
V5_0
VDDIOB
2
.1UF
C9
2
.1UF
10UF
C143
1
2
.1UF
C168
2
1
.1UF
C145
1
2
1
.1UF
C147
3
ENGINEER:
TITLE:
1
3
.1UF
C169
2
2
.1UF
1
.1UF
C151
2
1
.1UF
C140
JML
1
1
.1UF
2
2
DS3104DK01B0
2
.1UF
C142
2
PAGE:
DATE:
1
11 OF 12
013007
Wed May 30 13:54:21 2007
1
A
B
C
D
8
7
6
-
5
4
3
ENGINEER:
TITLE:
FIXED USBPWR NET, FIXED SILKSCREEN BELOW SONSDH HEADER
GENERAL CLEANUP, RELEASE TO DATASHEET,
DS3104DK01B0
2
Tue May 29 13:45:02 2007
1
C
D
JML
2
PAGE:
DATE:
1
12 OF 12
013007
A
052907
-
ON DS OSC, OTHER CHANGES MADE PER DESIGN REVIEW
-
3
ADDED SPI TESTPOINTS, CHANGED 4.7UF TO 100 UF
ADDED TWO FOOTPRINTS FOR SMD STRATUM 4 OSC,
RELEASE FOR REVIEW
4
-
-
-
5
A
-
B0
051707
030907
021907
6
B
-
-
02
A0
-
01
REVISION HISTORY -
7
B
C
D
8
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.