M61251AFP Single-chip NTSC TV signal processor REJ03F0078-0100Z Rev.1.0 Sep.22.2003 Description The M61251AFP is a single-chip TV-signal processor IC for the NTSC format and is ideal for use in combination with a microcomputer. Processing circuits for all signals, including intermediate-frequency video and audio, video, color, the on-screen display of characters, and the deflection system are all included, and various functions are controllable via an I2C bus. Furthermore, a reset circuit, clock circuit, and regulator are included for use with microcomputers. Features • • • • • • • • • • • • • • Handling of VIF does not require a VCO coil Adjustment-free audio demodulator PLL-SPLIT SIF system with FM radio function Supports component video-signal input Fsc output available ACL or ABCL is selectable Built-in horizontal oscillator Built-in sawtooth waveform generator for vertical sync Self-diagnostic function Built-in black-peak hold, AFC2, color killer filter Horizontal / vertical pulse output for OSD Built-in microcomputer reset circuit Built-in microcomputer clock output Built-in 5- and 8-V regulators Rev.1.0, Sep.22.2003, page 1 of 15 M61251AFP Block diagram Rev.1.0, Sep.22.2003, page 2 of 15 M61251AFP 5.7V REG OUT INTERCARRIER OUT AUDIO OUT AUDIO BYPASS EXT AUDIO IN 53 52 51 50 49 SIF GND 55 VIF VCO FEED BACK 54 FM DIRECT OUT VIDEO OUT VIF GND RF AGC OUT 59 58 57 56 64 VIF IN(2) 63 VIF IN(1) 62 VIF AGC FILTER1 61 VIF AGC FILTER2 60 VIF APC FILTER Pin configuration V RAMP CAP 1 48 LIMITER IN AFT OUT 2 47 8.7V REG OUT VIF Vcc 3 4 5 6 46 Cr IN VREG Vcc TV/Y IN 40 VIDEO/CHROMA Vcc 39 DRIVE Vcc MCU 5.7V REG OUT 31 32 Y SW OUT 30 FSC OUT1 MCU RESET P-ON CONTROL 16 26 27 28 29 B OUT AUDIO ATT FILTER 35 DRIVE GND 34 X-TAL 3.58 33 ACL/ABCL SDA SCL 15 CLOCK CONTROL G OUT FAST BLK 13 14 22 23 24 25 NC R OUT Cb IN Hi Vcc 38 EXT/C IN 37 CHROMA APC FILTER 36 VIDEO/CHROMA GND R IN 12 20 DEF Vcc 21 10 11 B IN G IN H OUT FBP IN 45 44 43 42 41 M61251AFP INVERTED FBP OUT V PULSE OUT LOGIC GND 17 DEF GND 7 8 9 18 19 V RAMP F/B AFC FILTER HVCO FEED BACK RAMP OUT INTELLIGENT MONITOR SIF Vcc Absolute maximum, ratings Symbol Parameter Ratings Unit Vcc Pd Kt Topr Tstg Supply voltage Power dissipation Thermal derating Operating temperature Storage temperature 6.0, 10.0 1325 10.6 –20 to + 65 –40 to +150 V mW mW / °C °C °C Recommended operating conditions Supply-voltage terminals Blocks Pins 3 and 4 VIF / SIF Voltage 5.0 V Pins 39 and 40 Pin 12 Pin 44 Pin 42 Video, chroma Deflection/CMOS (start - up Vcc) SIF/ATT, deflection, RGB Power supply 5.0 V 8.0 V 8.0 V 8.7 V GND terminals Blocks Pins 56 and 57 Pins 35 and 36 Pins 8 and 9 VIF / SIF Video, chroma Deflection, CMOS Rev.1.0, Sep.22.2003, page 3 of 15 M61251AFP Electrical characteristics Function Block Parameter Specification (typ.) Pin no. VIF IF amplifier Gain-control range Input impedance 45 to 108dBµ 2 kΩ, 5pF 63.64 Video detector Video output level I2C video-output gain range 1.2 Vpp + / – 0.1 Vpp 58 Video S / N Video frequency response 54 dB 6 MHz DG / DP Intermodulation 3% / 3deg 50 dB Frequency IIC “VIF VCO ADJ” Range 45.75 / 58.75 MHz + / –4 MHz – Capture range IF AGC range Output range I2C RF delay adj. range Output range Sensitivity 2 I C output + / –2 MHz 45 to 107 dBµ 0.3 to 4.7 V 60 to 110 dBµ 0.3 to 4.7 V 10 mV / KHz Below 100 kHz Between 100 kHz and f0 Between f0 and +100 kHz Over +100 kHz 43 dBµ 4.5 MHz +/ –1.0 MHz – – 59 54 VCO PLL IF AGC RF AGC AFT SIF Limiter FM detector Limiting sensitivity PLL capture range AF amplifier FM Direct output level (TV) 500 mVrms AF S/N AMR Distortion (T.H.D) 60 dB 55 dB 1% Control range TV / EXT crosstalk –70 to 0 dB –70 dB Audio ATT Rev.1.0, Sep.22.2003, page 4 of 15 Condition Negative sync. I2C: 3 bits –3dB I2C: 6bit I2C: 7bit 2 – I2C “AFTO / AFT1” 48 – 51 Input 4.5 MHz / 25 KHz 100dBµ M61251AFP Electrical characteristics (cont) Function Block Parameter Specification (typ.) Pin no. Condition Video Video switch Chroma trap TV / EXT crosstalk Center frequency –55dB 3.58 MHz 31 – at 5 MHz Suppression at subcarrier frequency (fsc) Suppression at fsc+/-100 kHz Suppression at fsc+/-500 kHz –30dB –25dB –10dB I2C: 2bits Trap fine adjustment Video tone Delay time Peak frequency for emphasis Control range Delay-time adjustment Delay fine adjustment Start Point End Stop Max. effect Gain Y SW LPF cut-off frequency 125 ns 2.5 MHz –2.5 to +10dB 125 / 250 / 400 / 550nsec 0 / 80nsec 60 I RE 8 IRE 6dB (25 IRE) 6dB 700 KHz – Video mute Mute suppression (Y) –45dB 14. 15. 16 Chroma BPF Center frequency 2 - MHz suppression ACC range Overload fo 3.58 MHz –22 dB +6 to –22 dB chroma 169% 3.579545 MHz – fsc out 1 level - 1 1Vpp fsc out 1 level - 2 OFF APC Pull - IN + / –600 Hz 14, 15, 16 Color killer detector Color killer level Suppression Tint control –45dB –40dB +/- 45deg – Demodulation angle 103deg / 95deg Carrier leakage –40dB Demodulation ratio (B - Y) : (R –Y) = 1:0.55 Delay line Black stretch Y SW OUT Chroma ACC VCXO Demodulator Rev.1.0, Sep.22.2003, page 5 of 15 – I2C: 6 bits I2C: 2 bits I2C: 1 bit – 31 I2C “Y SW LPF” : 1 – 14, 15, 16 29 Pin25 CLK CONT : High Pin25 CLK CONT : Low – APC Filter 1µF+4.7K//0.015µF I2 C 7bit I2 C”C Angle 95” M61251AFP Electrical characteristics (cont) Function Block Parameter RGB Matrix Color control Max. attenuation External RGB MCU reset Power supply Specification (typ.) Pin no. Condition 14, 15, 16 I2C: 7 bits B / W mode at I2C data = 0 21, 22, 23 I2C Analog OSD” –45dB Input level Digital: 1 Vp-p Analog: 0.7 Vp-p OSD speed (rise) OSD speed (fall) 0.02µs 0.02µs Contrast control Range of control Brightness control Range of control –40 to 3dB External control –0.85 to + 0.85 V External control 14, 15, 16 33 14, 15, 16 33 I2C: 7 bits Decoupling 0.1 µF I2C: 8 bits De-coupling 0.1 µF Drive control Range of control + / -3dB (R / B) 14, 16 I2C: 7 bits Cut-off RGB OUT Range of control Output pedestal voltage +0.9 to –0.9 V 2.4 V 14, 15, 16 Distribution of output voltage Less than 300 mW Clamp ability 100% Output blanking voltage 0.3 V Pin 32 voltage detection 4.2 V Reset polarity Low reset Maximum sink current Supply voltage (P-ON) 4 mA Reset VREG Vcc 42 32 Output voltage 5.7 V Maximum output current 2.5 mA 5.7 V REGOUT Output voltage 5.7 V Maximum output current 5 mA Output voltage 1 8.7 V Output voltage 2 0V Maximum output current 1 mA Rev.1.0, Sep.22.2003, page 6 of 15 Open emitter output 30 8.7 V MCU 5.7 V REGOUT 8.7 REGOUT 14, 15, 16 49 Pin 28 (Power on control) = 5V Pin 28 (Power on control) = 5V 47 Pin 28 (Power on control) = 0V M61251AFP Electrical characteristics (cont) Function Block Parameter Specification (typ.) Pin no. Condition Deflection Sync. separation Slice level 50% / 25% – I2C ”S SiliceDown1” Horizontal VCO Horizontal VCO free-running frequency 50% / 45% 15.734 KHz Horizontal phase I2C bus 11 2 I C: 3 bits fH+ / –500 KHz Horizontal VCO adjustment AFCI I2C ”S SiliceDown2” Horizontal pull-in range Range of control +/–500 Hz (normal) 11 Filter 1uF 6.2 K / 0.01 uF +/–800 Hz (fast) +/–1.6µs 11 I2C: 5 bits Horizontal pulse timing 8.5µs Horizontal pulse width 25µs Inverter FBP OUT Output range 0.1 to 5.0 V 19 Vertical count down Vertical freerunning frequency 60 Hz 5 Vertical pull - in range 55 to 67 Hz Vertical position adjustment 8 Positions Vertical position step 2Horizontal Line / Step V-ramp variable range 2 Vpp +/- 0.8Vpp V-pulse width (pulse mode) 0.5ms V-BLK width (pulse mode) 1.5ms Acknowledge current 5 mA SCL/SDA Vth (high) 0.75 V SCL/SDA Vth (low) Clock frequency 4.25 V I2C bus 2 I C: 3 bits 2 I C: 7 bits 26, 27 100 KHz Bus table Slave address = BAH (write), BBH (read) A6 A5 A4 A3 A2 A1 A0 R/W 1 0 1 1 1 1 1 1/0 Rev.1.0, Sep.22.2003, page 7 of 15 M61251AFP Write table (input bytes) DATA SUB ADDRESS HEX BIN D7 D6 D5 D4 D3 (inhibited) 00H 00000000 0 1 (inhibited) 01H 02H 00000001 0 0 0 0 Audio EXT 0 0 00000011 00000100 1 C. Clip level 0 0 Black Stre. Off Take Off 0 0 0 0 00H 0 0 0 00H V0 V0 V0 20H V0 V0 40H 0 0 0 0 Video Tone 0 V1 V0 V0 Contrast Control V1 1 00000111 V0 0 0 V0 V0 V0 Y/C EXT Y DL Fine Adj V0 V0 0 0 0 80H V0 Tint Control V0 V1 0 V0 V0 V0 V0 40H V0 V0 40H 1 0 0 04H V0 V0 V0 80H 0 0 0 40H 0 0 0 40H 0 0 0 80H 0 0 0 80H 0 0 80H Blue Back 08H 00001000 00001001 Y DL Time Adj Color Control V0 V1 HV BLK OFF 09H 20H 0 ABCL VIF Defeat 07H 40H 0 0 0 V0 00000110 0 Video T Sharp VIF Video Out Gain 06H 0 0 AFT Defeat 0 00000101 0 TRAP Off EXTRGB C. Clip 05H INITIAL Audio ATT 0 ABCL Gain 04H D0 VIF VCD ADJ Audio Mute 03H D1 0 VIFFreq5875 Video Mute 00000010 D2 RF Felay Adj V0 VOUT STOP 0 V0 FSC FREE 0 V0 V0 HTONE SW 0 (inhibited) 0 0 Brightness Control 0AH 00001010 V1 V0 V0 V0 V0 (inhibited) 0BH 00001011 DRIVE (R) 0 1 0 0 0 (inhibited) 0CH 00001100 DRIVE (B) 0 1 0 0 0 Cut Off (R) 0DH 00001101 1 0 0 0 0 Cut Off (G) 0EH 00001110 1 0 0 0 0 Cut Off (B) 0FH 10H 00001111 1 0 White Back V-free 0 0 00010000 0 0 0 1 H VCO Adj 0 0 (inhibited) 11H 00010001 0 00010010 0 0 1 0 H-free 13H 00010011 V. 1Windows 0 0 15H 00010100 0 0 0 16H 0 0 0 AFC2 Gain OSD level 0 0 00010110 1 0 Service SW 0 0 VSYNCDET Auto Slice down 0 H Start 00010111 0 00011000 0 V1 0 19H 00011001 0 00011010 0 0 V0 0 0 0 0 0 00H 0 00H 1 03H (inhibited) 1 0 Killer level 0 0 00H 0 0 0 90H V0 V0 V0 40H 0 0 0 00H 0 0 0 00H 0 0 0 0 00H 0 0 0 0 00H 0 0 0 0 00H AFC2 H Phase 1 0 V0 Baseband Tint Control V0 0 0 0 Test2 0 0 20H US/JPN SW (inhibited) 0 0 0 Test3 1AH 0 TRAP Fine Adj (inhibited) 0 BGPFBP OFF 0 0 0 Test1 18H 0 S.Slice Down2 S.Slice Down1 FBP Vth L 0 0 24H V Shift Analog OSD YUV SW 17H 0 0 0 Black Strech Charge AFC1 Gain 00010101 0 Gamma Control YSW LPF Black Strech Discharge 14H 1 V-Size Monitoring 12H 0 (inhibited) (inhibited) 0 0 0 (inhibited) 1BH 00011011 0 0 0 0 (inhibited) 1CH 00011100 0 0 0 0 NOTE: V0/V1 ==> V–LATCH BIT Read table (output bytes) SUB ADDRESS 00H 00000000 D7 KILLERB D6 (not assigned) Rev.1.0, Sep.22.2003, page 8 of 15 D5 STPETB D4 VCOINB D3 AFT 0 D2 AFT 1 D1 HCOINB D0 (not assigned) M61251AFP Bus table Write Function Bit Subaddress Data Description Initial value 7 00H D0 to D6 RF AGC delay point adjustment 40H 6 10H D0 to D5 VIF VCO free-run frequency adjustment (VIF defeat = 1, AFT output: center) 20H VIF frequency 58, 75 1 01H D6 IF output at 45.75 / 58.75 MHz. 0: 45.75 MHz, 1: 58.75 MHz 0 VIF video out gain AFT defeat 3 06H D5 – D7 Adjustment of output level for VIF-demodulated video waveform on pin 58 80H 1 04H D6 AFT output on / off (defeat). 0: AFT on (non defeat), 1: defeat 0 VIF defeat 1 07H D7 VIF gain normal/minimum. 0: AGC function, 1: defeat (minimum gain) 0 S Audio I attenuation F Audio EXT 7 03H D0 to D6 Pin 51 audio-output level adjustment 00H 1 02H D6 Switches between the internal and externalinput audio signals. 0: internal, 1: external 0 Audio mute 1 03H D7 Pin 54 audio direct output on / off (mute). 0: audio on (no mute), 1: mute 0 V RF delay I adjustment F VIF VCO adjustment Rev.1.0, Sep.22.2003, page 9 of 15 Note M61251AFP Write (Cont) V I D E O C H R O M A Function Bit Subaddress Data Description Initial value Note Video tone Contrast control 6 7 04H 05H D0 to D5 D0 to D6 Sharpness level control Contrast level control 20H 40H V Latch V Latch EXTRGB contrast clip C. clip level 1 05H D7 EXT RGB contrast lower limit clipping on/off. 0: clipping on, 1: clipping off 0 V Latch 1 02H D5 EXT RGB contrast lower-limit clipping level. 0: low (20H), 1: high (40H) 0 Y delay time adjustment 2 06H D0 to D1 Y signal delay adjustment X0H Y delay fine adjustment EXT 1 06H D2 Y signal delay fine adjustment 0 1 06H D3 Selects video input on pin 41 or 38. 0: pin 41, 1: pin 38 0 V Latch Y/C 1 06H D4 Selects composite input or YC on pin 38 or 41. 0: composite, 1: Y / C mode 0 V Latch Y SW LPF 1 13H D5 Pin 31 (Y SW OUT) output frequency characteristic. 0: flat, 1: LPF (fc = 700 kHz) 0 Video tone sharpness Video mute 1 02H D3 Selects one of two video-tone levels (sharp or soft). 0: standard, 1: sharp 0 1 02H D7 Y-signal output on / off (video mute). 0: mute off, 1: mute 0 TRAP off 1 02H D4 Y-signal chroma trapping on / off. 0: trapping on, 1: trapping off 0 TRAP fine adjustment Black stretch off 2 12H D0 – D1 X0H 1 02H D1 Chroma-trapping frequency fine adjustment Black - stretch circuit on / off. 1: on, 1: off Black stretch charge Discharge 2 14H D4 – D5 Adjustment of charge - time - constant for black stretch 0XH 2 14H D6 to D7 0XH Gamma control 2 12H D2 to D3 Adjustment of discharge – time - constant for black stretch Gamma-level adjustment X0H Tint control 7 07H D0 to D6 Hue control 40H V Latch Baseband tint control 7 17H D0 to D6 YUV input hue control 40H V Latch YUV SW 1 17H D7 Switches between YUV and other input mode 0 Color control 7 08H D0 to D6 Color level control 40H Take off 1 02H D0 Chroma BPF take-off on / off, 0: BPF, 1: take-off 0 JS / JPN / SW 1 15H D1 to D3 US / JPN modes, 100: US mode, 011: JPN mode 0 0 Killer level 1 15H D0 Color killer sensitivity, 0: 43 dB, 1: 45 dB 0 Fsc free 1 09H D5 Crystal oscillator circuit forced free-running mode. 0: off, 1: free-running 0 Rev.1.0, Sep.22.2003, page 10 of 15 V Latch M61251AFP Write (Cont) Function Bit Subaddress Data Description Initial value Note 8 0AH D0 to D7 Brightness level control 80H V Latch 7 0BH D0 to D6 Red-output level control 40H 7 0CH D0 to D6 Blue-output level control 40H Cut-off (red) 8 0CH D0 to D7 Red-output DC-level control 80H Cut-off (green) 8 0EH D0 to D7 Green-output DC-level control 80H R Brightness control G Drive (red) B Drive (blue) Cut-off (blue) 8 0FH D0 to D7 Blue-output DC-level control 80H Blue background 1 08H D7 Blue-background screen on / off. 1: off, 1: blue background 0 White background 1 10H D7 White background on / off, 1: off, 1: white background 0 ABCL 1 02H D2 ABCL on/off. 0: off, 1: ABCL on 0 ABCL gain 1 04H D7 ABCL sensitivity low / high. 0: low, 1: high 0 On-screen display level 1 15H D5 On-screen display level (70 / 90%). 0: 70%, 1: 90% 0 Halftone SW 1 09H D4 Halftone on / off. 0: off, 1: on 0 Analog on-screen display 1 15H D4 On-screen display digital / analog input. 0: digital, 1: analog 0 Rev.1.0, Sep.22.2003, page 11 of 15 M61251AFP Write (Cont) Function Bit Subaddress Data Description Initial value 5 16H D0 to D4 Adjustment of horizontal phase of display 90H 1 09H D6 Pin 5 VOUT (ramp / pulse) forcible stop mode (when stopped, pin 5 is at ground level). 0: VOUT, 1: stopped 0 Service switch 1 13H D3 Vertical output on / off, 0: vertical output on, 1: vertical output off 0 Horizontal start 1 13H D4 Horizontal output out / stopped. 0: stopped, 1: H OUT 0 AFC1 gain 1 15H D7 Horizontal AFC gain high / low. 0: low, 1: high 0 AFC2 gain 1 15H D6 Horizontal AFC2 gain high/low. 0: high, 1: low 0 Horizontal VCO adjustment 3 10H D0 to D2 Adjustment of horizontal VCO freerunning frequency 24H Vertical shift 3 13H D0 to D2 Adjustment of vertical ramp start timing X0H Vertical size 6 11H D0 to D5 Adjustment of vertical ramp amplitude 20H Horizontal free 1 13H D7 Horizontal output forced free-run mode on/off. 0: off, 1: horizontal free-run 0 Vertical free 1 10H D6 Vertical output forced free-run mode on/off. 0: off, 1: vertical free-run 0 S slice down 1 1 14H D2 Sync detection slice level (50 / 30%). 0: 50%, 1: 30% 0 S slice down 2 1 14H D3 Sync detection slice level (50 / 40%), 0: 50%, 1: 40% 0 Auto slice down 1 16H D6 Synchronous detection slice level during video period, 0: Slice level remains constant, 1: slice level decreased during video period 0 FBP Vth L 1 16H D5 Pin 10 (FBP in) FBP slice level. 0: Vth = 2 V (HBLK width: narrow), 1: Vth = 1 V (HBLK width: wide) 0 HV BLK OFF 1 09H D7 Horizontal / vertical blanking. 0: blanking ON, 1: blanking OFF 0 Vertical sync. detection 1 16H D7 Minimum width for vertical sync detection. 0: synchronous detection width = 18 us, 1: synchronous detection width = 14 us 90H One window 1 13H D6 Minimum width for vertical sync detection (1 / 2 windows). 0: 2 windows, 1: 1 window 0 BGPFBP off 1 19H D7 Internal BGP on / off when there is no FBP input. 0: BGP on, 1: BGP off 0 AFC2 horizontal D phase E Ramp stop F Rev.1.0, Sep.22.2003, page 12 of 15 Note M61251AFP Write (Cont) Function Bit Subaddress Data Description Initial value Monitoring 4 12H D4 to D7 Pin 18 intelligent monitoring mode switch 0XH Test 1 1 18H D6 to D7 Reserved (test bit) 0 Test 2 2 19H D6 Reserved (test bit) 0 Test 3 2 1AH D6 to D7 Reserved (test bit) 0 Rev.1.0, Sep.22.2003, page 13 of 15 Note M61251AFP Read: KILLERB 1 00H D7 Color killer information output; 1 when killer is off. AFTO 1 00H D3 AFT information output (note 1) AFT1 1 00H D2 AFT information output (note 1) HCOINB 1 00H D1 Horizontal sync detection, not synchronized = 1 VCOINB 1 00H D5 Vertical sync detection, not detected = 1 STDETB 1 00H D4 Station detection in TV mode, not detected = 1 Note 1: AFT0 / AFT1, read byte: AFT OUTPUT AFT0/AFT1 <READ BYTE: AFT OUTPUT> fo –100kHz +100kHz IF AFT0 1 0 0 1 AFT1 1 1 0 0 Intelligent monitor (1) Sub-address: 12H D4 to D7 (4 bits) (2) Output pin: pin 18 (3) Specifications Decimal Hexad ecimal Binary D7 D6 D5 D4 Output signal Vcc voltage Specifications AC / DC 0 1 2 0X 1X 2X 0 0 0 0 0 0 0 0 1 0 1 0 Composite sync AFT OUT (pin2) RF AGC OUT (pin59) 8V 5V 5V 0/5V Positive sync. AC DC DC 5 6 7 8 9 10 11 12 5X 6X 7X 8X 9X AX BX CX 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 TV / Y IN (pin41) G OUT (pin15) R OUT (pin14) B OUT (pin16) ACL (pin33) HOUT VIF VCC (pin10) VIF VCC (pin 3,4) 5V 8V 8V 8V 5V 5V 8V 5V 1 Vp-p (typ.) 1/2 1/2 1/2 0 dB 0/4V 0 / 4.75 V AC AC AC AC DC AC AC AC 13 DX 1 1 0 1 START UP VCC (pin 12) 8V 1/3 14 EX 1 1 1 0 VIDEO / CROMA VCC (pin 39 40) 5V 15 FX 1 1 1 1 HI VCC (pin44) 8V Rev.1.0, Sep.22.2003, page 14 of 15 95 / 100 Positive sync. DC DC 1/3 DC 16 1 17 64 e y D HD b JEDEC Code — x 32 49 48 Weight(g) M 33 F HE EIAJ Package Code LQFP64-P-1414-0.8 Detail F Lp Lead Material Cu Alloy L L1 A b2 I2 MD ME x y A3 A A1 A2 b c D E e HD HE L L1 Lp Symbol Dimension in Millimeters Min Nom Max — — 1.7 0.1 0.2 0 — — 1.4 0.32 0.37 0.45 0.105 0.125 0.175 13.9 14.1 14.0 13.9 14.1 14.0 0.8 — — 16.0 15.8 16.2 15.8 16.2 16.0 0.3 0.5 0.7 1.0 — — 0.45 0.6 0.75 — 0.25 — — — 0.2 0.1 — — 0° 8° — 0.5 — — — — 0.95 — 14.4 — — — 14.4 Recommended Mount Pad l2 MD Plastic 64pin 14 14mm body LQFP e b2 MMP E Rev.1.0, Sep.22.2003, page 15 of 15 A2 A1 ME 64P6U-A M61251AFP Package Dimensions c A3 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0