Preliminary Datasheet LP6205S High Efficiency Boost DC/DC Regulator General Description Features The LP6205 is a current mode boost DC-DC converter. Its PWM circuitry with built-in 0.3Ω,24V,1.5A Current power MOSFET makes this converter highly power efficiently. Selectable high switching frequency allows faster loop response and easy filtering with a low noise output. The non-inverting input its error amplifier is connected to an internal 1.25V precision reference voltage. Soft-Start time can be programmed with an external capacitor, which sets the input current ramp rate. Current mode control and external compensation network make it easy and flexible to stabilize the system. 1.3V Start-up Input Voltage Output up to 1.5A Zero Shutdown Mode Supply Current 94% Efficiency Up to 1.2MHz Switching Frequency Using Internal Power Switches Small SOT23-6 Package Typical Application Circuit Vin(3.6-5V) Vout_5V 10uH SS24 + 22uF 1uF + Cout 22uF*3 Ordering Information LP6205S - □ □ R1 100K □ 1uF 5 2 SW VDD 22pF 6 ON/OFF F: Pb-Free LP6205sB6F EN R1 1M PGND FB GND 1 3 4 22pF Package Type B6: SOT23-6 Pin Configurations Applications AlK. Battery Products Li-ion Battery Products Host/OTG 5V output HDMI Power Supply Marking Information Please see website:www.lowpowersemi.com. LP6205S–00 Ver. 1.0 Datasheet Jul.-2013 R1 110K TOP View SOT23-6 www.lowpowersemi.com Page 1 of 5 R2 33K Preliminary Datasheet LP6205S Functional Pin Description Pin Number 1 2 3 4 5 6 Pin Name SOT23-6 GND SW GND FB VDD EN Function Ground. Switch pin. Ground. Feedback Power pin. Enable pin Function Block Diagram LP6205S–00 Ver. 1.0 Datasheet Jul.-2013 www.lowpowersemi.com Page 2 of 5 Preliminary Datasheet LP6205S Absolute Maximum Ratings Supply Input Voltage------------------------------------------------------------------------------------------------------6V SW Pin Switch Voltage--------------------------------------------------------------------------------−0.3V to (Vout + 0.8V) Other I/O Pin Voltages---------------------------------------------------------------------------------- −0.3V to (Vout + 0.3V) SW Pin Switch Current -----------------------------------------------------------------------------------------------------1.5A SW Pin Voltage(max) -----------------------------------------------------------------------------------------------------30V Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------------260°C Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility HBM (Human Body Mode) ----------------------------------------------------------------------------------------------------2kV MM(Machine-Mode)-----------------------------------------------------------------------------------------------------------200V Recommended Operating Conditions Operation Ambient Temperature Range------------------------------------------------------------------ −40°C to 85°C Electrical Characteristics (VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25°C, unless otherwise specified) Parameter Test Conditions Start-UP Voltage IL = 1mA Operating VDD Range VDD pin voltage No Load Current I (VIN) VIN = 2V, VOUT = 6V Feedback Reference Voltage Min Typ Max 2.5 2.5 Units V 6.5 V 26 μA Close Loop, VDD = 3.3V 1.25 V Switching Frequency VDD = 3.3V 1200 KHz Maximum Duty VDD = 3.3V 95 % SW ON Resistance VDD = 3.3V 200 mΩ Current Limit Setting VDD = 3.3V 1.5 A Line Regulation VIN = 1.5 ~ 2.5V, IL = 1mA 55 mV/V Load Regulation VIN = 2.5V, IL = 1 ~ 100mA 0.2 mV/mA 50 ppm/℃ 165 ℃ 10 ℃ 145 mV Temperature Stability for VOUT Thermal Shutdown Thermal Shutdown Hysterises Maximum VRS LP6205S–00 Ver. 1.0 Datasheet VRS Jul.-2013 www.lowpowersemi.com Page 3 of 5 Preliminary Datasheet LP6205S Application Information Referring to Typical application circuits, the output proper value capacitor between FB pin and GND pin is voltage of the switching regulator(Vout) can be set with suggested. An empirical suggestion is around 220pF. Equation(1): PCB Layout Guide PCB Layout shall follow these guidelines for better Vout=(1+R1/R2) X 1.25 V system stability: 1. A full GND plane without any gap break. 2. VDD to GND bypass Cap-The 1uF MLCC noise Feedback Loop Design Referring to the typical application circuits, the selection of R1 and R2 based on the trade-off between quiescent current consumption and interference immunity is stated below: lower values of R1 and R2 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1 and R2 are needed. Such high impedance, which careful PCB connections. 3. Vin to GND bypass Cap-Add a Cap close to the inductor when Vin is not an idea voltage source. 4. Minimize the FB node copper area and keep it far For applications without standby or suspend modes, requires bypass cap pin4 shall have short and wide layout and avoid away from noise sources. 5. I follow Equation(1) 6. I Higher R reduces the quiescent current(Path current=1.25V/R2),however resistors beyond 5M/W are not recommended. any interference. Especially to FB pin. To improve the system stability a LP6205S–00 Ver. 1.0 Datasheet Jul.-2013 www.lowpowersemi.com Page 4 of 5 Preliminary Datasheet LP6205S Packaging Information SOT23-6 LP6205S–00 Ver. 1.0 Datasheet Jul.-2013 www.lowpowersemi.com Page 5 of 5