US2066-Revision 0_10t

US2066
100 x 32
OLED/PLED Segment/Common Driver with Controller
For 20x4 Characters
US2066
1 General Description
US2066 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic
display. It consists of 100 segments and 34 commons while it can display 1, 2, 3, or 4 lines with 5x8 or 6x8 dots format. This
IC is designed for Common Cathode type OLED/PLED panel.
US2066 displays character directly from its internal 10,240 bits (256 characters x 5 x 8 dots) Character Generator ROM
(CGROM). All the character codes are stored in the 640 bits (80 characters) Data Display RAM (DDRAM). User defined character can be loaded via 512 bits (8 characters) Character Generator RAM (CGRAM). Data/Commands are sent from general
MCU through software selectable 4-/8-bit 68XX/80XX series compatible Parallel Interface, I2C interface or Serial Peripheral
Interfaces.
The contrast control and oscillator which embedded in US2066 reduce the number of external components. With the special
design on minimizing power consumption, US2066 is suitable for portable applications requiring a compact size.
2 Features
•
•
•
•
•
•
Resolution: 100 x 32 dot matrix panel
Power supply (2 options selected
configuration):
[Low voltage I/O application]
o VDDIO = 2.4V to 3.6V
(MCU interface logic level)
o VDD = 2.4V to VDDIO
(Low voltage power supply)
o VCC = 8.0V to 15.0V
(Panel driving power supply)
by
hardware
[5V I/O application]
o VDDIO = 4.4V to 5.5V
(MCU interface logic level)
o VDD is internally regulated, a stabilizing
capacitor is needed
o VCC = 8.0V to 15.0V
(Panel driving power supply)
Segment maximum source current: 450uA
Common maximum sink current: 45mA
256-step Contrast Control
Pin selectable MCU Interfaces:
o 4 / 8-bit 6800/8080-series parallel interface
o Serial Peripheral Interface
o I2C Interface (Up to 400kbit/s)
2.1 5-dot / 6-dot font width
Display Line
Numbers
Duty Ratio
2
1/16
4
1/32
1
3
1/8
1/24
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-Chip Memories
o Character Generator ROM (CGROM):
10,240 bits (256 characters x 5 x 8 dot)
o Character Generator RAM (CGRAM):
64 x 8 bits (8 characters)
o Display Data RAM (DDRAM):
80 x 8 bits (80 characters max.)
Selectable duty cycle: 1/8, 1/16, 1/24, 1/32
1, 2, 3 or 4 lines with 5x8 or 6x8 dots format display
3 sets of CGROM (ROM A / B / C – hardware pin
selectable)
Row Re-mapping and Column Re-mapping
Double-height Font characters
Bi-direction shift function
All character reverse display
Display shift per line
Automatic power on reset
Screen saving continuous scrolling function in
horizontal direction (character by character)
Screen saving fade in / out feature
Programmable Frame Frequency
Smart Cross-talk compensation scheme
On-Chip Oscillator
Chip layout for COG
Wide range of operating temperatures: -40°C to 85°C
Table 2-1: 5-dot / 6-dot font width
5-dot font width
6-dot font width
Displayable Characters
Displayable Characters
2 lines of 20 characters
2 lines of 16 characters
1 lines of 20 characters
3 lines of 20 characters
4 lines of 20 characters
1 lines of 16 characters
3 lines of 16 characters
4 lines of 16 characters
1
3
Block Diagram
VDDIO
5V I/O
Regulator
FR
Display Timing
Generator
Character
Generator RAM
(CGRAM)
8 char max.
SEG/COM
Driving
Block
Character
Generator ROM
A,B,C (CGROM)
256 char max.
Display Data
RAM
(DDRAM)
80 char max.
Display Controller
Segment Drivers
Common Drivers
……………………………………
Segment Drivers
……………………………………
SEG49
SEG48
｜
｜
｜
｜
｜
SEG1
SEG0
C0
COM0
COM1
｜
｜
｜
｜
COM30
COM31
C1
SEG50
SEG51
｜
｜
｜
｜
｜
SEG98
SEG99
2
US2066
……………………………………
Figure 3-1: US2066 Block Diagram
Oscillator
VSL
BGGND
VDD
REGVDD
MCU interface
Busy
Flag
CL
CLS
VCOMH
IREF
RES#
CS#
D/C#
E(RD#)
R/W#(WR#)
BS0
BS1
BS2
ROM0
ROM1
D7
D6
D5
D4
D3
D2
D1
D0
VCC
VSS
VLSS
GPIO
SHLC
SHLS
OPR0
OPR1
Command Decoder
US2066
4 Pin Descriptions
Key:
Pin Name
VDD
I = Input
O =Output
I/O = Bi-directional (input/output)
P = Power pin
NC = Not Connected
Pull LOW= connect to Ground
Pull HIGH= connect to VDDIO
Table 4-1 : US2066 Pin Description
Pin Type Description
P
Power supply for core logic operation.
VDD can be supplied externally or regulated internally.
In LV IO application (internal VDD is disabled), this is a power input pin.
In 5V IO application (internal VDD is enabled), VDD is regulated internally from VDDIO.
A capacitor should be connected between VDD and VSS under all circumstances.
VDDIO
P
Low voltage power supply and power supply for interface logic level in both Low Voltage I/O
and 5V I/O application. It should match with the MCU interface voltage level and must be
connected to external source.
VCC
P
Power supply for panel driving voltage. This is also the most positive power voltage supply
pin. It is supplied by external high voltage source.
VSS
P
Ground pin. It must be connected to external ground.
VLSS
P
Analog system ground pin. It must be connected to external ground.
VCOMH
P
COM signal deselected voltage level.
A capacitor should be connected between this pin and VSS.
No external power supply is allowed to connect to this pin.
IREF
I
This pin is the segment output current reference pin.
IREF is supplied externally.
A resistor should be connected between this pin and VSS to maintain current of around 15uA.
BS[2:0]
I
MCU bus interface selection pins. Select appropriate logic setting as described in the
following table. BS2, BS1 and BS0 are pin select.
Table 4-2 : Bus Interface selection
BS[2:0]
000
001
010
011
100
101
110
111
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
Interface
Serial Interface
Invalid
I2C
Invalid
8-bit 6800 parallel
4-bit 6800 parallel
8-bit 8080 parallel
4-bit 8080 parallel
3
US2066
Pin Name
BGGND
REGVDD
Pin Type Description
P
Reserved pin. It should be connected to ground.
I
Internal VDD regulator selection pin in 5V I/O application mode.
When this pin is pulled HIGH, internal VDD regulator is enabled (5V I/O application).
When this pin is pulled LOW, internal VDD regulator is disabled (Low voltage I/O application).
Under 5V I/O application mode, internal VDD regulator can also be disabled by extended
command 71h “Function Selection A” for power saving; details refer to
Table 6-2.
SHLC
I
This pin is used to determine the Common output scanning direction.
Table 4-3 : COM scan direction
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
SHLS
I
SHLC
1
0
COM scan direction
COM0 to COM31 (Normal)
COM31 to COM0 (Reverse)
This pin is used to change the mapping between the display data column address and the
Segment driver. Refer to Table 6-4 for details.
Table 4-4 : SEG scan direction
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
ROM[1:0]
I
SHLS
1
0
SEG direction
SEG0 to SEG99 (Normal)
SEG99 to SEG0 (Reverse)
These pins are used to select Character ROM; select appropriate logic setting as described in
the following table. ROM1 and ROM0 are pin select as shown in below table:
Table 4-5 : Character ROM selection
ROM1
0
0
1
1
ROM0
0
1
0
1
ROM
A
B
C
S/W selectable (3)
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
(3)
S/W selectable by extended command 72h “Function Selection B”; details refer to
Table 6-2.
OPR[1:0]
I
This pin is used to select the character number of character generator. Refer to Table 5-4 for
details. OPR1 and OPR0 are pin select such that
Table 4-6 : Character RAM selection
OPR1
1
0
1
0
Note
(1)
0 is connected to VSS
(2)
1 is connected to VDDIO
OPR0
1
1
0
0
CGROM
256
248
250
240
CGRAM
0
8
6
8
4
US2066
Pin Name
GPIO
VSL
Pin Type Description
I/O
P
It is a GPIO pin. Details refer to OLED command DCh.
This is segment voltage (output low level) reference pin.
When external VSL is not used, this pin should be left open.
When external VSL is used, connect with resistor and diode to ground (details depend on
application).
CL
I
External clock input pin.
When internal clock is enable (i.e. pull HIGH in CLS pin), this pin is not used and should be
connected to Ground.
When internal clock is disable (i.e. pull LOW is CLS pin), this pin is the external clock source
input pin.
CLS
I
Internal clock selection pin.
When this pin is pulled HIGH, internal oscillator is enabled (normal operation).
When this pin is pulled LOW, an external clock signal should be connected to CL.
CS#
I
This pin is the chip select input connecting to the MCU.
The chip is enabled for MCU communication only when CS# is pulled LOW (active LOW).
In I2C mode, this pin must connect to VSS.
RES#
I
This pin is reset signal input.
When the pin is pulled LOW, initialization of the chip is executed.
Keep this pin pull HIGH during normal operation.
D/C#
I
This pin is Data/Command control pin connecting to the MCU.
When the pin is pulled HIGH, the data at D[7:0] will be interpreted as data.
When the pin is pulled LOW, the data at D[7:0] will be transferred to a command register.
In I2C mode, this pin acts as SA0 for slave address selection.
When serial interface is selected, this pin must be connected to VSS.
R/W# (WR#)
I
This pin is read / write control input pin connecting to the MCU interface.
When 6800 interface mode is selected, this pin will be used as Read/Write (R/W#) selection
input. Read mode will be carried out when this pin is pulled HIGH and write mode when
LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write
operation is initiated when this pin is pulled LOW and the chip is selected.
When serial or I2C interface is selected, this pin must be connected to VSS.
E (RD#)
I
This pin is MCU interface input.
When 6800 interface mode is selected, this pin will be used as the Enable (E) signal.
Read/write operation is initiated when this pin is pulled HIGH and the chip is selected.
When 8080 interface mode is selected, this pin receives the Read (RD#) signal. Read
operation is initiated when this pin is pulled LOW and the chip is selected.
When serial or I2C interface is selected, this pin must be connected to VSS.
5
US2066
Pin Name
D[7:0]
Pin Type Description
I/O
These pins are bi-directional data bus connecting to the MCU data bus.
Unused pins are recommended to tie LOW.
When serial interface mode is selected, D0 will be the serial clock input: SCLK; D1 will be the
serial data input: SID and D2 will be the serial data output: SOD.
When I2C mode is selected, D2, D1 should be tied together and serve as SDAout, SDAin in
application and D0 is the serial clock input, SCL.
FR
O
This pin outputs RAM write synchronization signal. Proper timing between MCU data writing
and frame display timing can be achieved to prevent tearing effect.
It should be kept NC if it is not used.
Refer to Section 5.4 for details.
SEG0 ~
SEG99
O
These pins provide the OLED segment driving signals. These pins are VSS state when display
is OFF.
COM0 ~
COM31
O
These pins provide the Common switch signals to the OLED panel. These pins are in high
impedance state when display is OFF.
C[1:0]
-
These pins are reserved. Nothing should be connected to these pins, nor are they connected
together.
TR[9:0]
-
These pins are reserved. Nothing should be connected to these pins, nor are they connected
together.
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US2066
5 Functional Block Descriptions
5.1 MCU Interface selection
US2066 has all four kinds of interface type with MCU: I2C, serial, 4-bit bus and 8-bit bus. Different MCU modes can be set by
hardware selection on BS[2:0] pins; refer to Table 4-2 for BS[2:0] setting. This chip MCU interface consists of 8 data pins and 5
control pins. The pin assignment at different interface mode is summarized in Table 5-1.
Pin Name
Bus
Interface
4-bit 6800
4-bit 8080
8-bit 6800
8-bit 8080
Serial Interface
I2C
5.1.1
Table 5-1 : MCU interface assignment under different bus interface mode
Data/Command Interface
D7
D6
D5
D[7:4]
D[7:4]
D4
Tie LOW
Tie LOW
Control Signal
D3
D2
D1
Tie LOW
Tie LOW
D[7:0]
D[7:0]
SOD
SID
SDAOUT SDAIN
D0
E
R/W#
E
R/W#
RD# WR#
E
R/W#
RD# WR#
Tie LOW
Tie LOW
SCLK
SCL
CS# D/C#
CS# D/C#
CS# D/C#
CS# D/C#
CS# D/C#
CS# Tie LOW
SA0
RES#
RES#
RES#
RES#
RES#
RES#
RES#
MCU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E signal.
Table 5-2 : Control pins of 6800 interface
Function
E
Write command
↓
Read status
Write data
Read data
↓
↓
↓
R/W
#
CS#
D/C#
L
L
L
L
L
H
H
L
H
L
L
H
Note
(1)
↓ stands for falling edge of signal
H stands for HIGH in signal
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally
performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 5-1.
Figure 5-1: Data read back procedure - insertion of dummy read
R/W#
E
Databus
N
Write column
address
Dummy read
n
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
7
US2066
In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data.
When interfacing data length is 4-bit, only 4 ports, D[7:4], are used as data bus; the unused 4 ports, D[3:0] are recommended to
tie to GND.
At first higher 4-bit (in case of 8-bit bus mode, the contents of D4 - D7) are transferred, and then lower 4-bit (in case of 8-bit bus
mode, the contents of D0 - D3) are transferred. So transfer is performed by two times.
When interfacing data length is 8-bit, transfer is performed at a time through 8 ports, from D[7:0].
5.1.2
MCU Parallel 8080-series Interface
The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
CS#
Figure 5-2: Example of Write procedure in 8080 parallel interface mode
WR#
D[7:0]
D/C#
RD#
CS#
high
low
Figure 5-3: Example of Read procedure in 8080 parallel interface mode
RD#
D[7:0]
D/C#
WR#
high
low
Table 5-3 : Control pins of 8080 interface
Function
Note
(1)
↑ stands for rising edge of signal
(2)
H stands for HIGH in signal
Write command
Read status
Write data
Read data
RD#
H
↑
H
↑
WR#
↑
H
↑
H
CS#
L
L
L
L
D/C#
L
L
H
H
8
US2066
(3)
L stands for LOW in signal
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally
performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 5-4.
Figure 5-4: Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
Write column
address
5.1.3
Dummy read
n
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
Serial Interface
When serial interface mode is started, all the three ports, SCLK (synchronizing transfer clock; i.e. D0), SID (serial input data; i.e.
D1), and SOD (serial output data; i.e. D2), are used. If US2066 is used with other chips, chip select port (CS#) can be used.
By setting CS# to "Low", US2066 can receive SCLK input. If CS# is set to "High", US2066 resets the internal transfer counter.
Before transfer real data, start byte has to be transferred. It is composed of succeeding five "High" bits, read write control bit
(R/W), register selection bit (DC) and end bit that indicates the end of start byte. Whenever succeeding five "High" bits are
detected by US2066, it makes serial transfer counter reset and ready to receive next information.
The next input data are register selection bit that determine which register will be used, and read write control bit that determine
the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte. (Refer to Figure 5-5
and Figure 5-6).
5.1.3.1
Write Operation (R/W = 0)
5.1.3.2
Read Operation (R/W = 1)
After start byte is transferred from MPU to US2066, 8-bit data is transferred which is divided into 2 bytes, each byte has four bit's
real data and four bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred data
becomes "1011 0000 0001 0000" where the 2nd and the 4th four bits must be "0000" for safe transfer. To transfer several bytes
continuously without changing D/C bit and R/W bit, start byte transfer is needed only at first starting time. Namely, after first start
byte is transferred, real data can be transferred succeeding.
After start byte is transferred to US2066, MPU can receive 8-bit data through the SOD port at a time from the LSB. Wait time is
needed to insert between start byte and data reading, because internal reading from RAM requires some delay. Continuous data
reading is possible like serial write operation. It also needs only one start byte, only if some delay between reading
operations of each byte is inserted. During the reading operation, US2066 observes succeeding five "High" from MPU. If it is
detected, US2066 restarts serial operation at once and ready to receive DC bit. So in continuous reading operation, SID port must
be "Low".
9
US2066
Figure 5-5: Timing Diagram of Serial Data Transfer
Figure 5-6: Timing Diagram of Continuous Data Transfer
Continuous Write Operation
SCLK
Wait
SID
Start Byte
1st Byte
Wait
2nd Byte
1st Byte
Instruction1
2nd Byte
1st Byte
Instruction2
2nd Byte
Instruction3
Instruction1
Execution Time
Instruction2
Execution Time
Instruction3
Execution Time
Continuous Read Operation
SCLK
SID
Wait
Wait
Wait
Start Byte
SOD
Data Read1
Instruction1
Execution Time
5.1.4
MCU I2C Interface
a)
Slave address bit (SA0)
Data Read2
Instruction2
Execution Time
Data Read3
Instruction3
Execution Time
The I2C communication interface consists of slave address bit SA0, I2C-bus data signal SDA (SDAOUT/D2 for output and SDAIN/D1 for
input) and I2C-bus clock signal SCL (D0). Both the data and clock signals must be connected to pull-up resistors. RES# is used for
the initialization of device.
10
US2066
US2066 has to recognize the slave address before transmitting or receiving any information by the I2C-bus. The device
will respond to the slave address following by the slave address bit (“SA0” bit) and the read/write select bit (“R/W#” bit)
with the following byte format,
b7 b6 b5 b4 b3 b2 b1
b0
0 1 1 1 1 0 SA0 R/W#
“SA0” bit provides an extension bit for the slave address. Either “0111100” or “0111101” can be selected as the slave
address of US2066. D/C# pin acts as SA0 for slave address selection.
“R/W#” bit is used to determine the operation mode of the I2C-bus interface. R/W#=1, it is in read mode. R/W#=0, it is
in write mode.
b)
I2C-bus data signal (SDA)
SDA acts as a communication channel between the transmitter and the receiver. The data and the acknowledgement are
sent through the SDA.
It should be noticed that the ITO track resistance and the pulled-up resistance at “SDA” pin becomes a voltage potential
divider. As a result, the acknowledgement would not be possible to attain a valid logic 0 level in “SDA”.
“SDAIN” and “SDAOUT” are tied together and serve as SDA. The “SDAIN” pin must be connected to act as SDA. The
“SDAOUT” pin may be disconnected. When “SDAOUT” pin is disconnected, the acknowledgement signal will be ignored in the
I2C-bus.
c)
5.1.4.1
I2C-bus clock signal (SCL)
The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of data bit is taken place
during a single clock period of SCL.
I2C-bus Write data
The I2C-bus interface gives access to write data and command into the device. Please refer to Figure 5-7 for the write mode of I2Cbus in chronological order.
Figure 5-7 : I2C-bus data format
Note:
Write Mode
1 byte
D a t a B y t e
- - - - - - - -
P
ACK
m ≧ 0 words
0 0 0 0 0 0
ACK
D a t a B y t e
- - - - - - - -
D/C#
Co
ACK
0 0 0 0 0 0
ACK
Slave address
D/C#
Co
ACK
R/W#
SA0
S 0 1 1 1 1 0
Co – Continuation bit
D/C# – Data / Command Selection bit
ACK – Acknowledgement
SA0 – Slave address bit
R/W# – Read / Write Selection bit
S – Start Condition
P – Stop Condition
n ≧ 0 bytes
MSB………LSB
R/W#
SA0
0 1 1 1 1 0
US2066
Slave address
ACK
D/C#
Co
0 0 0 0 0 0
Control Byte
11
US2066
5.1.4.2
1)
2)
3)
4)
5)
6)
7)
Write mode for I2C
The master device initiates the data communication by a start condition. The definition of the start condition is shown in
Figure 5-8. The start condition is established by pulling the SDA from HIGH to LOW while the SCL stays HIGH.
The slave address is following the start condition for recognition use. For the US2066, the slave address is either
“b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as SA0).
The write mode is established by setting the R/W# bit to logic “0”.
An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W#
bit. Please refer to the Figure 5-9 for the graphical representation of the acknowledge signal. The acknowledge bit is
defined as the SDA line is pulled down during the HIGH period of the acknowledgement related clock pulse.
After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA. A control
byte mainly consists of Co and D/C# bits following by six “0”’s.
a. If the Co bit is set as logic “0”, the transmission of the following information will contain data bytes only.
b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is set to logic “0”,
it defines the following data byte as a command. If the D/C# bit is set to logic “1”, it defines the following data
byte as a data which will be stored at the DDRAM. The DDRAM address counter will be increased by one
automatically after each data write.
Acknowledge bit will be generated after receiving each control byte or data byte.
The write mode will be finished when a stop condition is applied. The stop condition is also defined in Figure 5-8. The stop
condition is established by pulling the “SDA in” from LOW to HIGH while the “SCL” stays HIGH.
Figure 5-8 : Definition of the Start and Stop Condition
tHSTART
TSSTOP
SDA
SCL
S
p
START condition
STOP condition
Figure 5-9 : Definition of the acknowledgement condition
DATA OUTPUT
BY TRANSMITTER
Non-acknowledge
DATA OUTPUT
BY RECEIVER
Acknowledge
SCL FROM
MASTER
1
S
START Condition
2
8
9
Clock pulse for acknowledge
Please be noted that the transmission of the data bit has some limitations.
1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “HIGH” period of the clock
pulse. Please refer to the Figure 5-10 for graphical representations. Except in start or stop conditions, the data line can be
switched only when the SCL is LOW.
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US2066
2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors.
Figure 5-10 : Definition of the data transfer condition
SDA
SCL
Data line is
stable
Change of
data
5.2 Command Decoder
This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of the
D/C# pin.
If D/C# pin is HIGH, D[7:0] is interpreted as display data written to Character Generator RAM (CGRAM) or Display Data RAM
(DDRAM). If it is LOW, the input at D[7:0] is interpreted as a command. Then data input will be decoded and written to the
corresponding command register.
5.3 Oscillator Circuit and Display Time Generator
Figure 5-11 : Oscillator Circuit and Display Time Generator
Internal
Oscillator
Fosc
CL
M
U
X
CLK
Divider
DCLK
Display
Clock
CLS
This module is an on-chip LOW power RC oscillator circuitry. The operation clock (CLK) can be generated either from internal
oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is pulled HIGH, internal oscillator is chosen and
CL should be connected to VSS. Pulling CLS pin LOW disables internal oscillator and external clock must be connected to CL pins
for proper operation. When the internal oscillator is selected, its output frequency Fosc can be changed by command D5h A[7:4].
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D” can be programmed from 1
to 16 by command D5h
DCLK = FOSC / D
The frame frequency of display is determined by the following formula.
FFRM =
, where
Fosc
D × K × 1 Duty Ratio
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•
•
•
•
D stands for clock divide ratio. It is set by command D5h A[3:0]. The divide ratio has the range from 1 to 16.
K is the number of display clocks per row. The value is derived by
K = Phase 1 period + Phase 2 period + Ko
= 18 + 7 + 126 = 151 at power on reset (that is Ko is a constant that equals to 126)
(Please refer to Section 5.5 “Segment Drivers / Common Drivers” for the details of the “Phase”)
Duty Ratio depends on display line number and segment-icon mode status. Refer to Table 2-1 for details.
FOSC is the oscillator frequency. It can be changed by OLED command D5h A[7:4]. The higher the register setting results in
higher frequency.
5.4 FR Synchronization
FR synchronization signal can be used to prevent tearing effect.
One frame
FR
100%
Memory
Access
Process
0%
Time
Fast write MCU
Slow write MCU
US2066 displaying memory updates to OLED screen
The starting time to write a new image to OLED driver is depended on the MCU writing speed. If MCU can finish writing a frame
image within one frame period, it is classified as fast write MCU. For MCU needs longer writing time to complete (more than one
frame but within two frames), it is a slow write one.
For fast write MCU: MCU should start to write new frame of ram data just after rising edge of FR pulse and should be finished
well before the rising edge of the next FR pulse.
For slow write MCU: MCU should start to write new frame ram data after the falling edge of the 1st FR pulse and must be
finished before the rising edge of the 3rd FR pulse.
5.5 Segment Drivers / Common Drivers
Segment drivers deliver 100 current sources to drive the OLED panel. The driving current can be adjusted from 0 to 450uA with
256 steps. Common drivers generate voltage-scanning pulses.
The segment driving waveform is divided into three phases:
1. In phase 1, the OLED pixel charges of previous image are discharged in order to prepare for next image content display.
2. In phase 2, the OLED pixel is driven to the targeted voltage. The pixel is driven to attain the corresponding voltage level
from VSS. The period of phase 2 can be programmed in length from 1 to 15 DCLKs. If the capacitance value of the pixel
of OLED panel is larger, a longer period is required to charge up the capacitor to reach the desired voltage.
3. In phase 3, the OLED driver switches to use current source to drive the OLED pixels and this is the current drive stage.
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Figure 5-12 : Segment Output Waveform in three phases
Segment
VSS
Phase: 1 2
Time
3
After finishing phase 3, the driver IC will go back to phase 1 to display the next row image data. This three-step cycle is run
continuously to refresh image display on OLED panel.
5.6 SEG/COM Driving Block
This block is used to derive the incoming power sources into the different levels of internal use voltage and current.
• VCC is the most positive voltage supply.
• VCOMH is the Common deselected level. It is internally regulated.
• VLSS is the ground path of the analog and panel current.
• IREF is a reference current source for segment current drivers ISEG. The relationship between reference current and
segment current of a color is:
ISEG = (Contrast+1) / 8 x IREF
in which the contrast (0~255) is set by OLED command “Set Contrast” 81h
The magnitude of IREF is controlled by the value of resistor, which is connected between IREF pin and VSS as shown in
Figure 5-13. It is recommended to set IREF to 15 ± 2uA so as to achieve ISEG = 450uA at maximum contrast 255.
Figure 5-13 : IREF Current Setting by Resistor Value
US2066
IREF (voltage at
this pin = VCC –
4.5V)
IREF ~ 15uA
R1
VSS
Since the voltage at IREF pin is VCC –4.5V, the value of resistor R1 can be found as below:
For IREF = 15uA, VCC =15V:
R1 = (Voltage at IREF – VSS) / IREF
= (15 – 4.5) / 15uA
= 700kΩ
5.7 Power ON and OFF Sequence
The following figures illustrate the recommended power ON and power OFF sequence of US2066:
When LV I/O mode is chosen:
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Power ON sequence:
1. Power ON VDDIO, VDD
2. After VDDIO, VDD become stable, set RES# pin LOW (logic low) for at least 3us (t1) (4) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 100us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send fundamental command 0Ch (for RE=0b, SD=0b) for display ON. SEG/COM will be ON after
100ms (tAF).
Figure 5-14 : The Power ON sequence.
ON VDDIO, VDD RES#
ON VCC
VDDIO, VDD
OFF
t0
RES#
Send 0Ch command for
Display ON
t1
GND
t2
VCC
OFF
tAF
SEG/COM
ON
OFF
Power OFF sequence:
1. Send fundamental command 08h (for RE=0b, SD=0b) for display OFF.
2. Power OFF VCC.(1), (2), (3)
3. Power OFF VDDIO, VDD after tOFF. (5) (where Minimum tOFF=0ms (5), Typical tOFF=100ms)
Figure 5-15 : The Power OFF sequence
Send 08h command for Display OFF
OFF VCC
OFF VDDIO, V
VCC
OFF
tOFF
VDDIO, VDD
OFF
Note:
(1)
Since an ESD protection circuit is connected between VDDIO, VDD and VCC, VCC becomes lower than VDDIO, VDD whenever VDDIO, VDD
is ON and VCC is OFF as shown in the dotted line of VCC in Figure 5-14 and Figure 5-15.
(2)
VCC should be kept float (i.e. disable) when it is OFF.
(3)
Power Pins (VDDIO, VDD, VCC) can never be pulled to ground under any circumstance.
(4)
The register values are reset after t1.
(5)
VDDIO, VDD should not be Power OFF before VCC Power OFF.
When 5V I/O mode is chosen:
Power ON sequence:
1. Power ON VDDIO
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2. After VDDIO becomes stable, set wait time at least 1ms (t0) for internal VDD become stable. Then set RES# pin LOW (logic low)
for at least 3us (t1) (4) and then HIGH (logic high).
3. After set RES# pin LOW (logic low), wait for at least 100us (t2). Then Power ON VCC.(1)
4. After VCC become stable, send fundamental command 0Ch (for RE=0b, SD=0b) for display ON. SEG/COM will be ON after
200ms (tAF).
Figure 5-16 : The Power ON sequence.
ON VDDIO RES#
VDDIO
ON VCC
Send 0Ch command for
Display ON
t0
OFF
t0
RES#
t1
GND
t2
VCC
OFF
tAF
SEG/COM
ON
OFF
Power OFF sequence:
1. Send fundamental command 08h (for RE=0b, SD=0b) for display OFF.
2. Power OFF VCC.(1), (2), (3)
3. Power OFF VDDIO after tOFF. (5) (where Minimum tOFF=0ms (5), Typical tOFF=100ms)
Figure 5-17 : The Power OFF sequence
Send 08h command for Display OFF
OFF VCC
OFF VDDIO, V
VCC
OFF
tOFF
VDDIO, VDD
OFF
Note:
(1)
Since an ESD protection circuit is connected between VDDIO, VDD and VCC, VCC becomes lower than VDDIO, VDD whenever VDDIO, VDD
is ON and VCC is OFF as shown in the dotted line of VCC in Figure 5-16 and Figure 5-17.
(2)
VCC should be kept float (i.e. disable) when it is OFF.
(3)
Power Pins (VDDIO, VDD, and VCC) can never be pulled to ground under any circumstance.
(4)
The register values are reset after t1.
(5)
VDDIO, VDD should not be Power OFF before VCC Power OFF.
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5.8 Busy Flag (BF)
When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction
cannot be accepted. BF can be read, when D/C# = Low and R/W# (WR#) = High (Read Instruction Operation), through
D7. Before executing the next instruction, be sure that BF is not high.
5.9 Address Counter (AC)
Address Counter (AC) stores DDRAM and CGRAM address, transferred from Command Decoder After writing into
(reading from) DDRAM and CGRAM, AC is automatically increased (decreased) by 1. In parallel and serial mode, when
D/C# = "Low" and R/W# (WR#) = "High", AC can be read through D[6:0].
5.10
Cursor/Blink Control Circuit
5.11
Display Data Ram (DDRAM)
It controls cursor/blink ON/OFF and black/white inversion at cursor position.
DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address counter (AC)
as a hexadecimal number. (Refer to Figure 5-18)
Figure 5-18: DDRAM Address
MSB
AC6
AC5
AC4
AC3
AC2
AC1
LSB
AC0
Display of 5-Dot Font Width Character
5-dot 1-line Display
In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-4FH (Refer to Figure 5-19)
Figure 5-19: 1-line x 20ch. Display (5-dot Font Width)
Display Position
COM0
COM7
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
SEG0
SEG99
DDRAM Address
COM0
COM7
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
COM0
COM7
4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
(After Shift Left)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
(After Shift Right)
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5-dot 2-line Display
In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 5-20).
Figure 5-20: 2-line x 20ch. Display (5-dot Font Width)
Display Position
COM0
COM7
COM8
COM15
COM0
COM7
COM8
COM15
COM0
COM7
COM8
COM15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
SEG0
SEG99
DDRAM Address
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54
(After Shift Left)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
(After Shift Right)
5-dot 3-line Display
In case of 3-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H (refer to Figure 5-21).
Figure 5-21: 3-line x 20ch. Display (5-dot Font Width)
Display Position
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
COM0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
COM7
COM8 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
COM15
COM16
COM23 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
SEG0
1
DDRAM Address
2
3
4
5
6
7
8
SEG99
9 10 11 12 13 14 15 16 17 18 19 20
COM0 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00
COM7
COM8
COM15 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20
COM16
COM23 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40
(After Shift Left)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
COM0 13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
COM7
COM8 33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
COM15
COM16
COM23 53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
(After Shift Right)
5-dot 4-line Display
In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H (refer to
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Figure 5-22).
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
Figure 5-22: 4-line x 20ch. Display (5-dot Font Width)
Display Position
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
DDRAM Address
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
SEG0
SEG99
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00
21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20
41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40
61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60
(After Shift Left)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32
53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72
(After Shift Right)
DISPLAY OF 6-DOT FONT WIDTH CHARACTER
When the device is used in 6-dot font width mode, SEG96, SEG97, SEG98 and SEG99 must be opened.
6-dot 1-line Display
In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-4FH (refer to Figure 5-23).
Figure 5-23: 1-line x 16ch. Display (6-dot Font Width)
Display Position
COM0
COM7
COM0
COM7
COM0
COM7
1
2
00 01
SEG0
1
2
3
02
4
03
5
04
6
05
7
06
3
4
5
6
7
02
03
04
05
06
07
1
2
3
4
5
6
7
00
9
08
10
09
11
0A
12
0B
13
14
0C 0D
15
0E
DDRAM Address
01
4F
8
07
01
02
03
04
05
8
9
10
11
0F
SEG95
08
09
0A
0B
0C
0D 0E
13
14
15
16
8
9
10
11
12
13
14
15
16
(After Shift Left)
06
07
08
09
(After Shift Right)
12
16
0A
0B
0C
0F
0D
10
0E
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6-dot 2-line Display
In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 5-24).
Figure 5-24: 2-line x 16ch. Display (6-dot Font Width)
Display Position
COM0
COM7
COM8
COM15
COM0
COM7
COM8
COM15
COM0
COM7
COM8
COM15
1
00
2
01
40 41
SEG0
1
01
41
1
27
67
2
02
42
2
00
40
3
02
42
4
03
43
5
04
44
6
05
45
7
06
46
8
07
47
9
08
48
10
09
49
11
0A
4A
12
0B
4B
13 14
0C 0D
4C 4D
15
0E
4E
DDRAM Address
3
03
43
3
01
41
4
04
44
4
02
42
5
05
45
5
03
43
6
06
46
6
04
44
7
07
47
7
05
45
8
08
48
9
09
49
10
0A
4A
11
0B
4B
(After Shift Left)
8
06
46
9
07
47
10
08
48
11
09
49
(After Shift Right)
16
0F
4F
SEG95
12 13
0C 0D
14
0E
15
0F
16
10
12
0A
14
0C
15
0D
16
0E
4C 4D
4A
13
0B
4B
4E
4C
4F
4D
50
4E
6-dot 3-line Display
In case of 3-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H (refer to Figure 5-25).
Figure 5-25: 3-line x 16ch. Display (6-dot Font Width)
Display Position
COM0
COM7
COM8
COM15
COM16
COM23
COM0
COM7
COM8
COM15
COM16
COM23
COM0
COM7
COM8
COM15
COM16
COM23
1
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
11
0A
12
0B
13 14
0C 0D
15
0E
16
0F
40 41
SEG0
42
43
44
45
46
47
48
49
4A
4B
4C 4D
4E
4F
SEG95
20
21
22
23
24
25
26
27
28
29
2A
2B
2C 2D
2E
DDRAM Address
2F
1
01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
9
09
10
0A
11
0B
12 13
0C 0D
14
0E
15
0F
16
10
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D
4E
4F
50
21
22
23
24
25
26
27
1
13
2
00
3
01
4
02
5
03
6
04
7
05
53
40
41
42
43
44
45
33
20
21
22
23
24
25
28
29
2A
2B
(After Shift Left)
2C 2D
2E
2F
30
8
06
9
07
10
08
11
09
12
0A
13
0B
14
0C
15
0D
16
0E
46
47
48
49
4A
4B
4C
4D
4E
26
27
28
29
(After Shift Right)
2A
2B
2C
2D
2E
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6-dot 4-line Display
In case of 4-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H (refer to
Figure 5-26).
Figure 5-26 : 4-line x 16ch. Display (6-dot Font Width)
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
COM0
COM7
COM8
COM15
COM16
COM23
COM24
COM31
5.12
1
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
11
0A
12
0B
13 14
0C 0D
15
0E
16
0F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D
4E
4F
20
21
60 61
SEG0
22
62
23
63
24
64
25
65
26
66
27
67
28
68
29
69
2A
6A
2B
6B
2C 2D
6C 6D
2E
2F
6E
6F
SEG95
1
01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
9
09
10
0A
11
0B
12 13
0C 0D
14
0E
15
0F
16
10
41
42
43
44
45
46
47
48
49
4A
4B
4C 4D
4E
4F
50
21
61
22
62
23
63
24
64
25
65
26
66
27
67
28
68
29
69
2A
2B
2C 2D
6A 6B 6C 6D
(After Shift Left)
2E
6E
2F
6F
70
2
00
3
01
4
02
5
03
6
04
7
05
8
06
9
07
10
08
11
09
12
0A
13
0B
14
0C
15
0D
16
0E
53
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
73
20
60
21
61
22
62
23
63
24
64
25
65
26
66
27
67
28
29
2A
2B
2C
68 69 6A 6B 6C
(After Shift Right)
2D
6D
DDRAM Address
30
1
13
33
Display Position
2E
6E
CGROM (Character Generator ROM)
There are 3 optional CGROM’s in US2066 (details refer to Section 12), which is selected by ROM0 and ROM1 pins (by
extension command 72h under appropriate H/W pin setting; refer to Table 4-5 and
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Table 6-2 for details), while each CGROM has 5 x 8 dots 256 Character Pattern.
5.13
CGRAM (Character Generator RAM)
CGRAM has up to 8 characters of 5 x 8 dots, selectable by OPR0 and OPR1 pins (refer to Table 4-6).
(OPR1, OPR0) = (0, 0)
Table 5-4: CGRAM and CGROM arrangement with
(OPR1, OPR0) = (0, 1)
(OPR1, OPR0) = (1, 0)
(OPR1, OPR0) = (1, 1)
By writing font data to CGRAM, user defined character can be used (refer to Table 5-5).
Table 5-5: Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
5x8 dots Character Pattern
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Character Code (DDRAM Data)
CGRAM Address
CGRAM Daata
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0
0
0
0
x
0
0
0
0
0
0
0
0
0 B1 B0 x
0
1
1
1
0
0
0
1
1
0
0
0
1
.
0
1
0
1
0
0
0
1
.
.
0
1
1
.
1
1
1
1
1
.
.
1
0
0
.
1
0
0
0
1
.
.
1
0
1
.
1
0
0
0
1
1
1
0
.
1
0
0
0
1
1
1
1
0
0
0
0
0
.
.
.
.
.
.
.
.
0
0
0
0
x
1
1
1
1
1
1
0
0
0 B1 B0 x
1
0
0
0
1
0
0
1
1
0
0
0
1
.
.
0
1
0
.
1
0
0
0
1
.
.
0
1
1
.
1
1
1
1
1
.
.
1
0
0
.
1
0
0
0
1
.
.
1
0
1
.
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
0
Pattern
Number
Pattern1
.
.
Pattern8
6 x 8 Dots Character Pattern
Character Code (DDRAM Data)
CGRAM Address
CGRAM Daata
D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0
0
0
0
0
x
0
0
0
0
0
0
0
0
0 B1 B0 0
0
1
1
1
0
0
0
1
0
1
0
0
0
1
.
0
1
0
0
1
0
0
0
1
.
.
0
1
1
.
0
1
1
1
1
1
.
.
1
0
0
.
0
1
0
0
0
1
.
.
1
0
1
.
0
1
0
0
0
1
1
1
0
.
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
.
.
.
.
.
.
.
.
0
0
0
0
x
1
1
1
1
1
1
0
0
0 B1 B0 0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
.
.
0
1
0
.
0
1
0
0
0
1
.
.
0
1
1
.
0
1
1
1
1
1
.
.
1
0
0
.
0
1
0
0
0
1
.
.
1
0
1
.
0
1
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
Pattern
Number
Pattern1
.
.
Pattern8
Notes:
(1)
When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.
In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1", enabled dots
of P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.
In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled dots
of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.
(2)
"X": Don't care
5.14
5V I/O regulator
US2066 accepts two low voltage power supply ranges:
• 2.4-3.6V [Low Voltage I/O Application] and
• 4.4-5.5V [5V I/O Application]
5V IO Regulator is enabled to regulate internal VDD for power supply of internal circuit blocks (core logic operation).
24
US2066
Table 5-6 summarizes the input / output connection of 5V IO regulator in normal application.
Table 5-6: 5V IO regulator pin description
Pin Name
Low Voltage I/O Application
5V I/O Application
REGVDD
LOW, disable 5V I/O regulator
HIGH, enable 5V I/O regulator
VDD
2.4 - VDDIO
NC with stabilizing capacitor
It is internally regulated
VDDIO
2.4V -3.6V
4.4V -5.5V
25
US2066
6 Command Table
There are three sets of command set in US2066: Fundamental Command Set, Extended Command Set and OLED Command Set.
These three command sets can be selected by setting logic bits IS, RE and SD accordingly.
Table 6-1: Fundamental Command Table
1. Fundamental Command Set
Command
Clear Display
Return Home
IS RE SD
X
X
X
0
0
0
Instruction Code
D/C#
R/W#
(WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
*
Description
Write "20H" to DDRAM and set DDRAM
address to "00H" from AC.
Set DDRAM address to "00H" from AC and
return cursor to its original position if
shifted. The contents of DDRAM are not
changed.
Assign cursor / blink moving direction with
DDRAM address.
I/D = "1": cursor/ blink moves to right and
DDRAM address is increased by 1 (POR)
I/D = "0": cursor/ blink moves to left and
DDRAM address is decreased by 1
X
0
0
0
0
0
0
0
0
0
1
I/D
S
Assign display shift with DDRAM address.
S = "1": make display shift of the enabled
lines by the DS4 to DS1 bits in the shift
enable instruction. Left/ right direction
depends on I/D bit selection.
Entry Mode
Set
S = "0": display shift disable (POR)
Common bi-direction function.
BDC = "0": COM31 -> COM0
BDC = "1": COM0 -> COM31
X
1
0
0
0
0
0
0
0
0
1
BDC
BDS Segment bi-direction function.
BDS = "0": SEG99 -> SEG0,
BDS = "1": SEG0 -> SEG99
Set display/cursor/blink ON/OFF
D = "1": display ON,
D = "0": display OFF (POR),
Display ON /
OFF Control
X
0
0
0
0
0
0
0
0
1
D
C
B
C = "1": cursor ON,
C = "0": cursor OFF (POR),
B = "1": blink ON,
B = "0": blink OFF (POR).
Assign font width, black/white inverting of
cursor, and 4-line display mode control bit.
Extended
Function Set
X
1
0
0
0
0
0
0
0
1
FW
B/W
FW = "1": 6-dot font width,
NW FW = "0": 5-dot font width (POR),
B/W = "1": black/white inverting of cursor
enable,
B/W = "0": black/white inverting of cursor
26
US2066
1. Fundamental Command Set
Command
IS RE SD
R/W#
D/C#
(WR#)
D7
Instruction Code
D6
D5
D4
D3
D2
D1
D0
Description
disable (POR)
NW = "1": 3-line or 4-line display mode
NW = "0": 1-line or 2-line display mode
Set cursor moving and display shift control
bit, and the direction, without changing
DDRAM data.
Cursor or
Display Shift
Double
Height (4line) /
Display-dot
shift
0
0
0
0
0
0
0
0
1
S/C
R/L
*
*
S/C = "1": display shift,
S/C = "0": cursor shift,
R/L = "1": shift to right,
R/L = "0": shift to left
0
1
0
0
0
0
0
0
1
UD2
UD1
*
DH’
UD2~1: Assign different doubt height
format (POR=11b)
Refer to Table 7-2 for details
DH’ = "1": display shift enable
DH’ = "0": dot scroll enable (POR)
DS[4:1]=1111b (POR) when DH’ = 1b
Determine the line for display shift.
Shift Enable
1
1
0
0
0
0
0
0
1
DS4
DS3
DS2
DS1 = "1/0": 1st line display shift
enable/disable
DS2 = "1/0": 2nd line display shift
DS1
enable/disable
DS3 = "1/0": 3rd line display shift
enable/disable
DS4 = "1/0": 4th line display shift
enable/disable.
HS[4:1]=1111b (POR) when DH’ = 0b
Determine the line for horizontal smooth
scroll.
Scroll Enable
1
1
0
0
0
0
0
0
1
HS4
HS3
HS2
HS1 = "1/0": 1st line dot scroll
enable/disable
HS1 HS2 = "1/0": 2nd line dot scroll
enable/disable
HS3 = "1/0": 3rd line dot scroll
enable/disable
HS4 = "1/0": 4th line dot scroll
enable/disable.
Numbers of display line, N
when N = "1":
2-line (NW=0b) / 4-line (NW=1b),
when N = "0":
1-line (NW=0b) / 3-line (NW=1b)
Function Set
X
0
0
0
0
0
0
1
*
N
DH
RE
(0)
IS
DH = “ 1/0”: Double height font control for
2-line mode enable/ disable (POR=0)
Extension register, RE ("0")
Extension register, IS
27
US2066
1. Fundamental Command Set
Command
IS RE SD
X
Set CGRAM
address
Set DDRAM
Address
Set Scroll
Quantity
Read Busy
Flag and
Address/
Part ID
Write data
Read data
0
X
X
X
X
X
1
0
0
1
X
X
X
0
0
0
0
0
0
0
R/W#
D/C#
(WR#)
0
0
0
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
*
N
BE
RE
(1)
REV
0
0
0
0
1
0
1
0
1
Instruction Code
1
BF
D7
D7
1
AC6
*
AC6
/
ID6
D6
D6
AC5
AC5
SQ5
AC5
/
ID5
D5
D5
AC4
AC4
SQ4
AC4
/
ID4
D4
D4
AC3
AC3
SQ3
AC3
/
ID3
D3
D3
AC2
AC2
SQ2
AC2
/
ID2
D2
D2
AC1
AC0
Description
CGRAM blink enable
BE = 1b: CGRAM blink enable
BE = 0b: CGRAM blink disable (POR)
Extension register, RE ("1")
Reverse bit
REV = "1": reverse display,
REV = "0": normal display (POR)
Set CGRAM address in address counter.
(POR=00 0000)
Set DDRAM address in address counter.
(POR=000 0000)
AC1
AC0
SQ1
Set the quantity of horizontal dot scroll.
(POR=00 0000)
SQ0 Valid up to SQ[5:0] = 110000b
AC1
/
ID1
Can be known whether during internal
operation or not by reading BF. The
contents of address counter or the part ID
can also be read. When it is read the first
time, the address counter can be read.
AC0
When it is read the second time, the part
/
ID can be read.
ID0
D1
D1
BF = "1": busy state
BF = "0": ready state
D0
D0
Write data into internal RAM
(DDRAM / CGRAM).
Read data from internal RAM
(DDRAM / CGRAM).
Notes
(1)
POR stands for Power on Reset Values.
(2)
“*” and “X” stand for “Don’t care”.
28
US2066
Table 6-2: Extended Command Table
2. Extended Command Set
Command
IS RE SD
Function
Selection A
X 1 0
X 1 0
X 1 0
X 1 0
R/W#
D/C#
(WR#)
Instruction Code
Hex
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
71
A[7:0]
0
A7
1
A6
1
A5
1
A4
0
0
72
0
1
1
1
1
0
*
*
*
Function
Selection B
0
A3
0
A2
0
A1
Description
1 A[7:0] = 00h, Disable internal VDD
regulator at 5V I/O application mode
A0
A[7:0] = 5Ch, Enable internal VDD
regulator at 5V I/O application mode
(POR)
0
0
1
0 OPR[1:0]: Select the character no. of
ROMROM OPR OPR character generator
*
1
0
1
0
OPR[1:
CGRAM
CGROM
0]
00b
240
8
01b
248
8
10b
250
6
11b
256
0
ROM[1:0]: Select character ROM
RO[1:0]
00b
01b
10b
11b
X 1 X
0
0
OLED
Characterization
78 / 79
0
1
1
1
1
0
0
ROM
A
B
C
Invalid
SD Extension register, SD
SD = 0b: OLED command set is
disabled (POR)
SD = 1b: OLED command set is
enabled
Details refer to Table 6-3.
Notes
(1)
POR stands for Power on Reset Values.
(2)
“*” and “X” stand for “Don’t care”.
29
US2066
Table 6-3: OLED Command Table
3. OLED Command Set
Command IS RE SD
Set Contrast
Control
Instruction Code
Description
D/C# R/W#
Hex D7 D6 D5 D4 D3 D2 D1 D0
(WR#)
X 1 1
0
0
81
1
0
0
0
0
0
0
1 Double byte command to select 1 out of
X 1 1
0
0
A[7:0] A7 A6 A5 A4 A3 A2 A1 A0 256 contrast steps. Contrast increases
as the value increases.
(POR = 7Fh )
X 1 1
X 1 1
0
0
0
0
D5
1
A[7:0] A7
1
A6
0
A5
1
A4
0
A3
1
A2
0
A1
1 A[3:0]: Define the divide ratio (D) of
the display clocks (DCLK):
A0
divide ratio = A[3:0] + 1
(POR=0000b)
A[7:4]: Set the Oscillator Frequency,
FOSC. Oscillator Frequency
increases with the value of
A[7:4] and vice versa.
(POR=0111b)
Set Display
Clock Divide
Ratio/Oscillator
Frequency
Range:0000b~1111b
Frequency increases as setting value
increases.
X 1 1
X 1 1
0
0
0
0
D9
1
A[7:0] A7
1
A6
0
A5
1
A4
1
A3
0
A2
0
A1
Set Phase
Length
1 A[3:0]: Phase 1 period of up to 32
DCLK; clock 0 is an valid entry
A0
with 2 DCLK (POR=1000b)
A[7:4]: Phase 2 period of up to 15
DCLK; clock 0 is invalid entry
(POR=0111b)
X 1 1
X 1 1
0
0
0
0
DA
A[5:4]
1
0
1
0
0
A5
1
A4
1
0
0
0
1
0
Set SEG Pins
Hardware
Configuration
0 A[4]=0b, Sequential SEG pin
0 configuration
A[4]=1b (POR), Alternative (odd/even)
SEG pin configuration
A[5]=0b (POR), Disable SEG Left/Right
remap
A[5]=1b, Enable SEG Left/Right remap
Refer to Table 6-4 for details
X 1 1
X 1 1
Set VCOMH
Deselect Level
0
0
0
0
DB
A[6:4]
1
0
1
A6
0
A5
1
A4
1
0
0
0
1
0
1
0
A[6:4]
000b
001b
010b
011b
100b
Hex V COMH deselect level
code
00h ~ 0.65 x VCC
10h ~ 0.71 x VCC
20h ~ 0.77 x VCC (POR)
30h ~ 0.83 x VCC
40h 1 x VCC
30
US2066
3. OLED Command Set
Command IS RE SD
Instruction Code
Description
D/C# R/W#
Hex D7 D6 D5 D4 D3 D2 D1 D0
(WR#)
X 1 1
0
0
DC
1
1
0
1
1
1
0
0 Set VSL & GPIO
X 1 1
0
0
A[7:0] A7
0
0
0
0
0
A1 A0
Set VSL:
A[7] = 0b: Internal VSL (POR)
A[7] = 1b: Enable external VSL
Set GPIO:
A[1:0]= 00b represents GPIO pin HiZ,
input disabled (always read as
low)
A[1:0]= 01b represents GPIO pin HiZ,
input enabled
A[1:0]= 10b represents GPIO pin
output Low (RESET)
A[1:0]= 11b represents GPIO pin
output High
Function
Selection C
X 1 1
X 1 1
0
0
0
0
23
A[5:0]
0
*
0
*
1
A5
0
A4
0
A3
0
A2
1
A1
1 A[5:4] = 00b Disable Fade Out /
A0 Blinking Mode[RESET]
A[5:4] = 10b Enable Fade Out mode.
Once Fade Mode is enabled, contrast
decrease gradually to all pixels OFF.
Output follows RAM content when Fade
mode is disabled.
Set Fade Out
and Blinking
A[5:4] = 11b Enable Blinking mode.
Once Blinking Mode is enabled, contrast
decrease gradually to all pixels OFF and
than contrast increase gradually to
normal display. This process loop
continuously until the Blinking mode is
disabled.
A[3:0] : Set time interval for each fade
step
A[3:0]
0000b
0001b
0010b
:
1110b
1111b
Time interval
for each fade step
8 Frames
16 Frames
24 Frames
:
120 Frames
128 Frames
Note
(1)
POR stands for Power on Reset Values.
(2)
“*” and “X” stand for “Don’t care”.
(3)
The locked OLED driver IC MCU interface prohibits all commands access except logic bit SD is set to 1b.
(4)
Refer to Table 6-1 and
31
US2066
Table 6-2 for the details of logic bits IS, RE and SD.
32
US2066
Table 6-4 : SEG Pins Hardware Configuration
SEG Odd / Even (Left / Right) and Top / Bottom connections are software selectable, thus there are total of 8 cases and they
are shown on the followings:
SEG Remap (Fundamental)
Command Control bit: BDS;
or by H/W setting: SHLS
1
1
0
0
1
1
0
0
Left / Right Swap
OLED Command :
DAh -> A[5]
0
1
0
1
0
1
0
1
COL99
COL99
COL98
COL98
.
.
.
.
.
COL50
COL50
COL48
.
.
..
.
COL1
.
COL0
COL0
Default
…
0…49
31...0 0…
US2066
SSD1311Z
SEG
SEG
(1) Sequential SEG
99 …50
…
SEG
SEG
US2066
SSD1311Z
SEG
SEG
0…
31...0 0…49
(2) Sequential SEG & left / right
COL0
COL1
COL0
.
.
.
.
COL1
.
COL49
COL49
COL50
.
.
.
.
COL98
COL99
COL99
(3) Sequential SEG & SEG remap
99 …50
…
SEG
SEG
SSD1311Z
US2066
SEG
SEG
COM
COM
0…
…
31...0 0…49
0…
…
31...0 0…49
US2066
SSD1311Z
SEG
SEG
COL50
.
COM
COM
COL51
99 …
…50
Remark
COL49
COL49
COM
COM
SEG
SEG
99 …
…50
SEG
SEG
1
2
3
4
5
6
7
8
Oddeven (1) / Sequential (0)
OLED Command :
DAh -> A[4]
0
0
0
0
1
1
1
1
COM
COM
Case no.
(4) Sequential SEG & SEG remap & left / right
33
US2066
COL99
COL99
.
COL98
COL98
.
.
.
.
COL97
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
COL3
.
.
.
COL2
COL2
COL0
COL0
COL1
COL1
(5) Odd / even SEG
COM
US2066
SSD1311Z
(6) Odd / even SEG & left / right
COL0
COL0
COL1
.
.
COL2
COL2
.
.
.
.
COL3
.
.
..
..
.
.
.
.
.
.
.
.
.
.
.
.
.
.
COL97
COL98
COL1
COL98
.
COL99
COL99
COM
US2066
SSD1311Z
SEG
SEG
COM
(7) Odd / even SEG & SEG remap
SEG
US2066
SSD1311Z
127…64
…64 31…0
…49
99…50
38?
31...0 00…63
SEG
COM
SEG
SEG
COM
SEG
127…64
…64 31…0
…49
99…50
38?
31...0 00…63
SEG
SEG
SEG
COM
SEG
US2066
SSD1311Z
127…64
…64 31…0
…49
99…50
38?
31...0 00…63
SEG
COM
SEG
SEG
COM
SEG
SEG
127…64
…64 31…0
…49
99…50
38?
31...0 00…63
(8) Odd / even SEG & SEG remap & left / right
Note:
(1)
The above eight figures are all with bump pads being faced up.
34
US2066
7
Command Descriptions
7.1 Fundamental Command Set
7.1.1
Clear Display (IS= X, RE = X, SD = 0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
1
Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address
counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode
increment (I/D = "1").
7.1.2
Return Home (IS= X, RE = 0, SD = 0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
X
Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original
site and return display to its original status, if shifted. Contents of DDRAM do not change.
7.1.3
Entry Mode Set (IS= X, RE = 0 or 1, SD = 0)
When RE = 0
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
0
0
0
0
0
0
0
Set the moving direction of cursor and display.
I/D: Increment/decrement of DDRAM address (cursor or blink)
When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.
When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.
- CGRAM operates the same as DDRAM, when read from or write to CGRAM.
D2
1
D1
I/D
D0
S
When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the command “Shift Enable” is shifted to the
right (I/D = "0") or to the left (I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or
CGRAM read/write operation, shift of display like this function is not performed.
When RE = 1
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
1
Set the data shift direction of segment in the application set.
BDS: Data shift direction of segment
When BDS = "Low", segment data shift direction is set to reverse from SEG99 to SEG0.
When BDS = "High", segment data shift direction is set to normal order from SEG0 to SEG99.
D1
BDC
D0
BDS
D1
C
D0
B
BDC: Data shift direction of common
When BDC = "Low", common data shift direction is set to reverse from COM31 to COM0.
When BDC = "High", common data shift direction is set to normal order from COM0 to COM31.
The BDC, BDS setting is recommended to be set at the same time as the command “Function set”.
7.1.4
Display ON/OFF Control (IS= X, RE = 0, SD = 0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
0
0
0
0
0
0
1
Control display/cursor/blink ON/OFF 1 bit register.
D: Display ON/OFF control bit
When D = "High", entire display is turned ON.
When D = "Low", display is turned OFF, but display data is remained in DDRAM.
D2
D
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US2066
C:
B:
Cursor ON/OFF control bit
When C = "High", cursor is turned ON.
When C = "Low", cursor is disappeared in current display, but I/D register remains its data.
Cursor Blink ON/OFF control bit
When B = "High", cursor blink is ON, that performs alternate between all the high data and display character at the cursor
position.
When B = "Low", blink is OFF.
7.1.5
Extended Function Set (IS= X, RE = 1, SD = 0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
FW
B/W
NW
FW: Font Width control
When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than that of 5dot font width.
The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0, including the leftmost space bit of
CGRAM. (refer to Figure 7-1)
When FW = "Low", 5-dot font width is set.
B/W: Black/White Inversion enable bit
When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit in the command “Display
ON/OFF Control” becomes don't care condition.
NW: 4 Line mode enable bit
When NW = "High", 3 or 4 line display mode is set. In this case, N bit in the command “Function set” becomes don't care
condition.
When NW = "Low", 1 or 2 line display mode is set. In this case, N bit in the command “Function set” becomes don't care
condition.
Figure 7-1 : 6-dot Font Width CGROM/CGRAM
6-bit
s
p
a
c
e
CGROM
Character
Font
(5-dot)
6-bit
8-bit
CGROM
7.1.6
CGRAM
Character
Font
(6-dot)
8-bit
CGRAM
Cursor or Display Shift (IS = 0, RE = 0, SD=0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
S/C
R/L
X
X
Shift right / left cursor position or display, without writing or reading of display data. This command is used to correct or search
display data (refer to Table 7-1). During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. When 4-line
mode, cursor moves to the next line, only after every 20th digit of the current line. Note that display shift is performed
simultaneously in all the line enabled by DS1-DS4 in the command “Shift Enable”. When displayed data is shifted repeatedly, each
line shifted individually. When display shift is performed, the contents of address counter are not changed.
S/C
0
0
1
1
R/L
0
1
0
1
Table 7-1: Shift patterns According to S/C and R/L Bits
Operation
Shift cursor to the left, address counter is decreased by 1.
Shift cursor to the right, address counter is increased by 1
Shift all the display to the left, cursor moves according to the display. No change in address counter.
Shift all the display to the right, cursor moves according to the display. No change in address counter.
36
US 2 0 6 6
7.1.7
Double Height (4-line) / Display-dot shift (IS = 0, RE = 1, SD = 0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
UD2
UD1
X
DH’
UD2, UD1: Assign different double height formats, they are applicable to different line display modes when DH bit in command
“Function Set” =1.
Note that UD1=0 and UD2=0 are forbidden in 2-line display
mode, while UD1=0 is forbidden in 3-line display mode.
Table 7-2: Double Height Display According to UD2 andUD1 Bit
UD2
UD1
0
0
0
1
1
0
1
1
s (when DH=1)
Character Displays
DH’: Display shift enable selection bit.
When DH’ = “High”, display shift per line enabled.
When DH’ = “Low”, smooth dot scroll enabled.
7.1.8
Shift/Scroll Enable (IS =1, RE = 1, SD=0)
Shift Enable - DH’ = 1
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
DS4
DS3
DS2
DS1
DS: Display shift per line enable this instruction selects shifting line to be shifted according to each line mode in display shift
right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each
line.
st
line and 2 nd line are shifted. If all the DS bits (DS1 to DS4) are
If DS1 and DS2 are set to “High” (enable) in 2 line mode, 1
set to “Low” (disable), no shift is observed on the display.
Scroll Enable - DH’ = 0
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
HS4
HS3
HS2
HS1
HS: Horizontal scroll per line enable
This command makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and
each scroll is performed individually in each line.
If scroll the line in 1-line display mode, set HS1 to “High”.
If the 2 nd line scroll is needed in 2-line mode, set HS2 to “High” (refer to Table 7-3).
Note: DH’ bit is in command “Double Height (4-line) / Display-dot shift”
37
US 2 0 6 6
Table 7-3: Relationship between DS and COM signal
Enable Bit
HS1 / DS1
HS2 / DS2
HS3 / DS3
HS4 / DS4
7.1.9
Enabled Common Signals During Shift
COM0 – COM7
COM8 – COM15
COM16 – COM23
COM24 – COM31
Description
The part of display line that corresponds to enabled common
signal can be shifted.
Function Set (IS = X, RE = 0 or 1, SD = 0)
RE = 0
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
0
0
0
0
1
X
N
N: Display line number control bit
When N = “Low”, 1-line display mode (for NW=0), or 3-line display mode (for NW=1).
When N = “High”, 2-line display mode is set (for NW=0), or 4-line display mode (for NW=1).
DH: When DH= “High”, UD2=1 and UD1=1 Double height font type control bit for 2 line mode:
D2
DH
D1
RE(0)
D0
IS
Table 7-4: Double Height display when DH=1, UD2=1 and UD1=1
NW
N
DH
Display
lines
Character
font
0
0
0
1
5x8
0
0
1
1
0
1
0
2
5x8
0
1
1
2
5 x 16
Character Displays
Forbidden
When DH= “Low”, Double height font type control is disabled.
RE: Extended function registers enable bit
At this instruction, RE must be “Low”.
IS: Special registers enable bit
RE = 1
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
X
N
BE
RE(1)
REV
N: Display line number control bit
When N = “Low”, 1-line display mode (for NW=0), or 3-line display mode (for NW=1).
When N = “High”, 2-line display mode is set (for NW=0), or 4-line display mode (for NW=1).
BE: CGRAM data blink enable bit
If BE is “High”, it makes user font of CGRAM blink. The quantity of blink is assigned at the highest 2 bit of CGRAM. If BE is
“Low” CGRAM blink is disabled.
RE: Extended function registers enable bit
At this instruction, RE must be “High”.
When RE = “High”, the following control bits / commands can be accessed:
- BDC/ BDS control bits of Entry Mode Set command,
- HS / DS control bits of Shift / Scroll enable commands,
- UD2/UD1/DH’ control bits of Double height (4-line) / Display-dot Shift command,
- SQ control bits of Set Scroll Quantity command, and
- BE / REV control bits of function set register can be accessed.
REV: Reverse enable bit
When REV = “High”, all the display data are reversed. Namely, all the white dots become black and black dots become white.
When REV = “Low”, the display mode set normal display.
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US2066
7.1.10 Set CGRAM Address (IS = 0, RE = 0, SD=0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
0
0
0
1
AC5
AC4
Set CGRAM address to AC. This command makes CGRAM data available from MPU.
D3
AC3
D2
AC2
D1
AC1
D0
AC0
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
0
0
1
AC6
AC5
AC4
AC3
Set DDRAM address to AC. This command makes DDRAM data available from MPU.
D2
AC2
D1
AC1
D0
AC0
7.1.11 Set DDRAM Address (IS = X, RE = 0, SD=0)
• In 1-line display mode (N = 0, NW = 0), DDRAM address is from “00H” to “4FH”.
• In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from “00H” – “27H”, and DDRAM address in the 2nd
line is from “40H” – “67H”.
• In 3-line display mode (N=0, NW = 1), DDRAM address is from “00H” – “13H” in the 1st line, from “20H” to “33H” in the 2nd
line and from “40H” – “53H” in the 3rd line.
• In 4-line display mode (N=1, NW = 1), DDRAM address is from “00H” – “13H” in the 1st line, from “20H” to “33H” in the 2nd
line, from “40H” – “53H” in the 3rd line and from “60H” – “73H” in the 4th line.
Details refer to Section 5.11.
7.1.12 Set Scroll Quantity (IS = X, RE = 1, SD=0)
D/C#
0
R/W# (WR#)
0
D7
1
D6
X
D5
SQ5
D4
SQ4
D3
SQ3
D2
SQ2
D1
SQ1
D0
SQ0
As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (Refer to Table 7-5). In this case
US2066 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.
SQ5
0
0
0
0
.
.
.
1
1
SQ4
0
0
0
0
.
.
.
0
1
SQ3
0
0
0
0
.
.
.
1
X
Table 7-5: Scroll Quantity According to HDS Bits
SQ2
0
0
0
0
.
.
.
1
X
SQ1
0
0
1
1
.
.
.
1
X
SQ0
0
1
0
1
.
.
.
1
X
No shift
Shift left
Shift left
Shift left
.
.
.
Shift left
Shift left
Function
by 1-dot
by 2-dot
by 3-dot
by 47-dot
by 48-dot
7.1.13 Read Busy Flag & Address (IS = X, RE = X, SD=0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
BF
AC6/ID6
AC5/ID5
AC4/ID4
AC3/ID3
AC2/ID2
AC1/ID1
AC0/ID0
This command shows whether US2066 is in internal operation or not. If the resultant BF is High, it means the internal operation is
in progress . Then wait until BF is Low before the next instruction can be performed.
The value of address counter or the part ID can be read through this command. When first time run this command, the address
counter can be read. When this command is run for second time, the part ID can be read (refer to Figure 7-2).
Part Number
US2066
Part ID
0100001b
39
US2066
Figure 7-2: Read Busy Flag & Address/Part ID (6800 – parallel interface)
D/C#
R/W#
CS#
E
D7
Data
Busy
Busy
Not Busy
Data
D[6:0]
Data
AC[6:0]
ID[6:0]
AC[6:0]
Data
Read first time
Read again
Address counter is read
Address counter is read
Read second time
Part ID is read
7.1.14 Write Data to RAM (IS = X, RE = X, SD=0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM or CGRAM is set by the previous address setting
command: “Set DDRAM address” or “Set CGRAM address”. RAM set instruction can also determine the AC direction to RAM. After
write operation, the address is automatically increased / decreased by 1, according to the entry mode.
7.1.15 Read Data from RAM (IS = X, RE = X, SD=0)
D/C#
R/W# (WR#)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address set instruction. If address set
instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not
determined.
If RAM data is read several times without RAM address set instruction before read operation, correct RAM data can be got from the
second, but the first data would be incorrect, because there is no time margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction: it also transfer
RAM data to output data register. After read operation, address counter is automatically increased/decreased by 1 according to the
entry mode. After CGRAM read operation, display shift may not be executed correctly.
In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next
address position, but only the previous data can be read by read instruction.
In order to match the operating frequency of the DDRAM with that of the MCU, some pipeline processing is internally performed
which requires the insertion of a dummy read before the first actual display data read.
40
US2066
7.2 Extended Command Set
7.2.1
Function Selection A [71h] (IS = X, RE = 1, SD=0)
7.2.2
Function Selection B [72h] (IS = X, RE = 1, SD=0)
This double byte command enable or disable the internal VDD regulator at 5V I/O application mode.
The internal VDD is enabled as default by data 5Ch, whereas it is disabled if the data sequence is set as 00h.
Beside using ROM[1:0] and OPR[1:0] hardware pins, the character number of the Character Generator RAM and the character
ROM can be selected through this command, details refer to
41
US2066
Table 6-2.
7.2.3
OLED Characterization [78H/ 79h] (IS = X, RE = 1, SD= 0 or 1)
This single byte command is used to select the OLED command set. When SD is set to 0b , OLED command set is disabled. When
SD is set to 1b, OLED command set is enabled.
42
US 2 0 6 6
7.3 OLED Command Set
7.3.1
Set Contrast Control (81h)
This command sets the Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh. The segment output
current increases as the contrast step value increases.
7.3.2
Set Display Clock Divide Ratio/ Oscillator Frequency (D5h)
This command consists of two functions:
•
Display Clock Divide Ratio (D)(A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16, with reset value = 1.
Please refer to section 5.3 for the details relationship of DCLK and CLK.
•
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc that is the source of CLK if CLS pin is pulled high. The 4-bit value results in 16
different frequency settings. The default setting is 0111b.
7.3.3
Set Phase Length (D9h)
This double byte command sets the length of phase 1 and 2 of segment waveform of the driver.
•
Phase 1 (A[3:0]): Set the period from 2 to 32 in the unit of DCLKs.
•
7.3.4
Phase 2 (A[7:4]): Set the period from 1 to 15 in the unit of DCLKs.
Set SEG Pins Hardware Configuration (DAh)
This double byte command changes the mapping between the display data column address and the segment driver. It allows
flexibility in OLED module design. Please refer to Table 6-4.
This command only affects subsequent data input. Data already stored in DDRAM will have no changes.
7.3.5
Set V
COMH
Deselect Level (DBh)
This command adjusts the VCOMH regulator output.
7.3.6
Set VSL / GPIO (DCh)
This double byte command consists of two functions:
•
Set VSL (A[7])
External VSL is enabled when A[7] is set to 1b, whereas it is set to internal VSL as default at A[7] = 0b.
•
Set the states of GPIO (A[1:0])
The state of GPIO can be defined by control bits A[1:0]; refer to Table 6-3 for details.
7.3.7
Set fade Out Blinking (23h)
This command allows to set the fade mode and adjust the time interval for each fade step. Below figures show the example of
Fade Out mode and Blinking mode.
Figure 7-3 : Example of Fade Out mode
43
US 2 0 6 6
Figure 7-4 : Example of Blinking mode
44
US2066
8 Maximum Ratings
Table 8-1 : Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDDIO
VDD
VCC
VSEG
VCOM
Vin
TA
Tstg
Parameter
Supply Voltage
SEG output voltage
COM output voltage
Input voltage
Operating Temperature
Storage Temperature Range
Value
-0.3 to +6
-0.3 to +6
0 to 16
0 to VCC
0 to 0.9*VCC
VSS-0.3 to VDD+0.3
-40 to +85
-65 to +150
Unit
V
V
V
V
V
V
ºC
ºC
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be restricted to
the limits in the Electrical Characteristics tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than masimum rated voltages to this high
impedance circuit. Reliability of operation is enhanced if unused input is connected to an appropriate logic voltage level (e.g.
either VSS or VDDIO). Unused outputs must be left open.
This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal
operation. This device is not radiation protected.
45
US2066
9 DC CHARACTERISTICS
Condition (Unless otherwise specified):
Voltage referenced to VSS,
VDDIO = 2.4V to 3.6V,
TA = 25°C
Symbol
Parameter
VCC
Operating Voltage
Low voltage power supply, power
VDDIO
supply for I/O pins
VDD
Logic Supply Voltage
VOH
VOL
VIH
VIL
High Logic Output Level
Low Logic Output Level
High Logic Input Level
Low Logic Input Level
ISLP_VDD
VDD Sleep mode Current
ISLP_VDDIO
ISLP_VCC
ICC
IDDIO
IDD
ISEG
VDDIO Sleep mode Current
VCC Sleep mode Current
Table 9-1 : DC Characteristics
Test Condition
Low Voltage I/O Application
5V I/O Application
Low Voltage I/O Application
5V I/O Application (VDD as output)
IOUT = 100uA, 3.3MHz
IOUT = 100uA, 3.3MHz
VDDIO = 3.3V, VCC = OFF
VDD (external: LV I/O mode) = 3.3V,
Display OFF, No panel attached
VDDIO = 3.3V,
VCC =OFF
Ext VDD = 3.3V
Display OFF,
No panel attached
Enable Internal VDD
VDDIO = 5V,
during Sleep mode
(at 5V I/O mode)
VCC =OFF
Display OFF,
Disable Internal VDD
No panel attached during Sleep mode
(Deep Sleep mode)
VCC = 8~15V
VDDIO = 3.3V, VDD (external) = 3.3V,
or
VDDIO = 5V, VDD (internal)
Display OFF, No panel attached
VCC Supply Current
VDDIO = VDD = 3.3V, VCC =12, Contrast = FFh,
IREF =15uA, No loading, Display ON, All ON
VDDIO = VDD = 3.3V
VDDIO Supply Current
VCC = 12, Contrast = FFh,
(Low Voltage I/O Application)
IREF = 15uA , No loading, Display
VDDIO = 5V (Internal VDD)
ON, All ON
(5V I/O Application)
VDD Supply Current
VDDIO = VDD = 3.3V (Low Voltage I/O Application),
VCC = 12, Contrast = FFh,
IREF = 15uA , No loading, Display ON, All ON
Segment Output Current,
VDDIO = VDD =3.3V (LV I/O)
or
VDDIO = 5V (5V I/O),
VCC = 12V, IREF = 15uA,
Display ON
Dev
Segment output current uniformity
Adj. Dev
Adjacent pin output current
uniformity (contrast setting = FFh)
Contrast=FFh
Min
8
2.4
4.4
2.4
0.9 x VDDIO
0.8 x VDDIO
-
Typ
-
-
-
10
uA
-
-
10
uA
-
60
TBD
uA
-
-
10
uA
-
-
10
uA
-
560
670
uA
-
2
5
uA
-
130
160
uA
-
90
110
uA
-
450
550
225
-
Contrast=AFh
-
340
Contrast=3Fh
-
112
Contrast=7Fh
Contrast=0Fh
Dev = (ISEG – IMID)/IMID
IMID = (IMAX + IMIN)/2
ISEG[0:99] = Segment current
at contrast setting = FFh
Adj Dev = (I[n]-I[n+1]) / (I[n]+I[n+1])
Max
Unit
15
V
3.6
V
5.5
V
3.6
V
V
V
0.1 x VDDIO V
V
0.2 x VDDIO V
-
-
-
-
uA
56
-
-3
-
3
%
-2
-
2
%
46
US2066
10 AC Characteristics
10.1
AC Characteristics
Conditions:
Voltage referenced to VSS
VDDIO = 2.4 to 3.6V (Low Voltage I/O Application) or VDDIO = 4.4V to 5.5V (5V I/O Application)
TA = 25°C
Symbol
FOSC (1)
FFRM
tRES
Parameter
Oscillation Frequency of
Display Timing Generator
Table 10-1 : AC Characteristics
Test Condition
VDD = 3.3V or Internal VDD
100x32 4-line Character Display
Mode, Display ON,
Internal Oscillator Enabled
Reset low pulse width (RES#) -
Frame Frequency for 32 MUX
Mode
Min.
Typ.
Max.
Unit
-
FOSC * 1 / (D * K * 32)(2)
-
Hz
2000
-
-
ns
454
505
556
kHz
Note
(1)
FOSC stands for the frequency value of the internal oscillator and the value is measured when command B3h A[7:4] is in default
value.
(2)
D: Divide ratio
K: Phase 1 period + Phase 2 period + Ko, where Ko = 126
Default K is 18 + 7 + 126 = 151
47
US2066
10.2
6800-Series MCU Parallel Interface Timing Characteristics
Table 10-2: 6800-Series MCU Parallel Timing Characteristics
(TA = 25 C, VDDIO = 2.4-3.6 / 4.5-5.5V, VSS =0V)
Symbol Parameter
tcycle
Clock Cycle Time (write cycle)
tAS
Address Setup Time
tAH
Address Hold Time
tCS
Chip Select Time
tCH
Chip Select Hold Time
tDSW
Write Data Setup Time
tDHW
Write Data Hold Time
tDHR
Read Data Hold Time
tOH
Output Disable Time
tACC
Access Time (RAM)
Access Time (command)
PWCSL
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
PWCSH
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
tR
Rise Time
tF
Fall Time
o
Min
400
13
17
0
0
35
18
13
10
Typ
-
Max
90
250
250
50
155
55
-
-
15
15
-
-
125
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
(1)
All timings are based on 20% to 80% of VDDIO-VSS
Figure 10-1: 6800-series parallel interface characteristics (Form 1: CS# low pulse width > E high pulse width)
D/C#
tAS
R/W#
tAH
tCS
tCH
CS#
E
D[7:0] (Write)
D[7:0] (Read)
tR
tcycle
PWCSH
tDSW
tACC
tF
PWCSL
tDHW
Valid Data
tDHR
Valid Data
tOH
48
US2066
Figure 10-2: 6800-series parallel interface characteristics (Form 2: CS# low pulse width < E high pulse width)
D/C#
tAS
R/W#
tCS
CS#
E
D[7:0] (Write)
D[7:0] (Read)
tAH
tCH
PWCSH
PWCSL
tcycle
tR
tDSW
tACC
tDHW
Valid Data
tF
tDHR
Valid Data
tOH
49
US2066
10.3
8080-Series MCU Parallel Interface Timing Characteristics
(TA = 25 C,
Symbol
tcycle
tAS
tAH
tCS
tCSH
tCSF
tDSW
tDHW
tDHR
tOH
tACC
o
PWCSL
PWCSH
tR
tF
Table 10-3 : 8080-Series MCU Parallel Interface Timing Characteristics
VDDIO = 2.4-3.6 / 4.5-5.5V, VSS =0V)
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Chip Select Time
Chip select hold time to read signal
Chip select hold time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM) - tPWLR
Chip Select Low Pulse Width (read Command) - tPWLR
Chip Select Low Pulse Width (write) - tPWLW
Chip Select High Pulse Width (read) - tPWHR
Chip Select High Pulse Width (write) - tPWHW
Rise Time
Fall Time
Min
400
13
17
0
0
0
35
18
13
10
Typ
-
Max
70
250
250
50
155
55
-
-
15
15
-
-
125
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 10-3 : 8080-series parallel interface characteristics
Write cycle
Read Cycle
50
US2066
10.4
Serial Interface Timing Characteristics
Table 10-4 : Serial Timing Characteristics
(TA = 25 C, VDDIO = 2.4-3.6 / 4.5-5.5V, VSS =0V)
Symbol Parameter
tc
Serial clock cycle time
tr, tf
Serial clock rise/fall time
tw
Serial clock width (high, low)
tsu1
Chip select setup time
th1
Chip select hold time
tsu2
Serial input data setup time
th2
Serial input data hold time
tD
Serial output data delay time
tDH
Serial output data hold time
Note: All timings are based on 20% to 80% of VDDIO-VSS
o
Min
1
400
60
20
200
TBD
10
Typ
-
Max
20
15
TBD
-
Unit
us
ns
ns
ns
ns
ns
ns
ns
ns
Figure 10-4 : Serial Timing Characteristics
CS#
tcycle
VIL1
tsu1
SCLK
tR
VIH1
VIL1
tsu2
tW
VIH1
VIL1
th2
VIH1
VIL1
tF
tW
VIL1
th1
VIH1
VIL1
SID
tD
SOD
tDH
VOH1
VOL1
51
US2066
10.5
I2C Timing Characteristics
Table 10-5 : I2C Timing Characteristics
(TA = 25oC, VDDIO = 2.4-3.6 / 4.5-5.5V, VSS =0V)
Symbol
tcycle
tHSTART
tHD
Parameter
Min
Typ
Max
Unit
Start condition Hold Time
0.6
-
-
us
2.5
Clock Cycle Time
Data Hold Time (for “SDAOUT” pin)
5
Data Hold Time (for “SDAIN” pin)
300
tSSTART
Start condition Setup Time (Only relevant for a repeated Start condition)
0.6
tR
Rise Time for data and clock pin
tIDLE
Idle Time before a new transmission can start
tSD
tSSTOP
tF
Data Setup Time
Stop condition Setup Time
Fall Time for data and clock pin
Note: All timings are based on 20% to 80% of VDDIO-VSS
100
-
-
-
-
-
0.6
-
-
-
-
1.3
-
-
-
-
-
us
ns
ns
ns
us
-
us
300
ns
-
300
-
-
ns
us
Figure 10-5 : I2C Timing Characteristics
52
US2066
11 Application Example
Figure 11-1 : Application Example of US2066
The configuration for I2C interface mode is shown in the following diagram:
(VDDIO=VDD=3.3V, VCC =12V, IREF=15uA)
SEG1
SEG3
:
:
SEG97
SEG99
SEG98
SEG96
:
:
SEG2
SEG0
COM0
COM1
.
.
.
.
..
.
.
.
.
COM30
COM31
CHAR DISPLAY PANEL
20 x 4
US2066
VLSS
VCC VCOMH IREF D2 D1
C2
RES#
VDDIO
VDD
R1
VSS
VLSS
C4
C1
VCC
D0
RP
SDA
C3
RP
SCL
RES#
VDDIO
GND
Pin connected to MCU interface: D[2:0], RES#
Pin internally connected to VSS: D[7:3], BS0, BS2, E, R/W#, CS#, CL, OPR0, OPR1
Pin internally connected to VDD: BS1, CLS, SHLC, SHLS, ROM0, ROM1
TR[9:0] should be left open.
(3)
D/C# acts as SA0 for slave address selection
C1, C2: 4.7uF (1)
C3, C4: 1.0uF (1) place close to IC VDDIO / VDD and VSS pins on PCB
RP : Pull up resistor
Voltage at IREF = VCC – 4.5V. For VCC = 12V, IREF = 15uA:
R1 = (Voltage at IREF - VSS) / IREF
≈ (12-4.5)V / 15uA
= 500KΩ
Note
(1)
The capacitor value is recommended value. Select appropriate value against module application.
(2)
Die gold bump face down.
(3)
Refer to Section 5.1.4 for details.
(4)
It is recommended to tie VLSS and VSS at one common ground point to minimize circulating ground noise.
53
US2066
12 US2066 CGROM Character Code
12.1
ROM A ( ROM[1:0] = [0:0] )
Language: English, Irish, Spanish, Dutch (2), Danish, Norwegian, Swedish, Finnish, Czech (7), Slovene, Hungarian (2), Turkish (1)
The number in the parentheses is showing how many letters might be needed to build and define additionally. The darker
background is showing the maximum addresses those could be allocated by OPR[1:0] setting.
54
US2066
12.2
ROM B ( ROM[1:0] = [0:1] )
Language: English, Irish, Portuguese, Spanish, French (1), Italian, German, Dutch (2), Icelandic, Danish, Norwegian, Swedish, Polish (8),
Czech (8), Hungarian (2), Romanian (5), Turkish, Vietnamese (6), Russian (Small Letters)
The number in the parentheses is showing how many letters might be needed to build and define additionally. The darker
background is showing the maximum addresses those could be allocated by OPR[1:0] setting.
55
US2066
12.3
ROM C ( ROM[1:0] = [1:0] )
Language: English, Dutch (2), Japanese, Greek (Small Letters)
The number in the parentheses is showing how many letters might be needed to build and define additionally. The darker
background is showing the maximum addresses those could be allocated by OPR[1:0] setting.
56