HX8238-D - Orient Display

( DOC No. HX8238-D-DS )
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
Preliminary version 01 November, 2007
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.1October, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
List of Contents
November, 2007
1. General Description..................................................................................................................................... 6
2. Features ........................................................................................................................................................ 6
3. Block Diagram .............................................................................................................................................. 7
4. PAD Assignment .......................................................................................................................................... 8
5. Pin Description ............................................................................................................................................ 9
6. Block Function Description...................................................................................................................... 12
6.1 S ERIAL INTERFACE ................................................................................................................................... 12
6.2 DATA CONTROL ........................................................................................................................................ 13
6.3 GAMMA/GRAYSCALE V OLTAGE GENERATOR .............................................................................................. 13
6.4 B OOST AND REGULATOR CIRCUIT ............................................................................................................. 13
6.5 PWM B OOST C ONVERTER ....................................................................................................................... 13
6.6 S HIFT REGISTER ...................................................................................................................................... 14
6.7 DATA LATCHES ......................................................................................................................................... 14
6.8 AGING MODE ........................................................................................................................................... 14
6.9 RESET CIRCUIT ........................................................................................................................................ 14
7 3-Wire Serial Port Interface ........................................................................................................................ 15
7.1 P RIMARY REGISTER COMMAND TABLE ...................................................................................................... 15
7.2 P RIMARY REGISTER DEFAULT VALUE ........................................................................................................ 16
7.3 P RIMARY REGISTER COMMAND D ESCRIPTION ........................................................................................... 17
7.4 S ECONDARY R EGISTER COMMAND TABLE ................................................................................................. 31
7.5 S ECONDARY R EGISTER DEFAULT VALUE ................................................................................................... 32
7.6 S ECONDARY R EGSITER COMMAND DESCRIPTION ...................................................................................... 33
7.7 P OWER UP /DOWN S EQUENCE OF THE S ECONDARY REGISTER COMMAND .................................................. 42
8. OTP Programming ..................................................................................................................................... 44
9. Gamma Adjustment Function................................................................................................................... 45
9.1 S TRUCTURE OF GRAYSCALE A MPLIFIER .................................................................................................... 46
9.2 GAMMA A DJUSTMENT REGISTER ............................................................................................................... 48
9.2.1 Gradient Adjusting Register ........................................................................................................... 48
9.2.2 Amplitude Adjusting Register ......................................................................................................... 48
9.2.3 Micro Adjusting Register ................................................................................................................ 48
9.3 L ADDER RESISTOR / 8 TO 1 S ELECTOR...................................................................................................... 49
10. Maximum Rating ...................................................................................................................................... 53
11. DC Characteristics................................................................................................................................... 54
12. AC Characteristics................................................................................................................................... 55
13. HX8238-D Output Voltage Relationship................................................................................................. 67
14. Application Circuit................................................................................................................................... 68
15. Revision History....................................................................................................................................... 71
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.1November, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
List of Figures
November, 2007
Figure 6. 1 SPI Timing.................................................................................................................... 12
Figure 6. 2 ...................................................................................................................................... 13
Figure 7. 1 Status Read ................................................................................................................ 17
Figure 7. 2 Driver Output Control ............................................................................................... 17
Figure 7. 3 Scan Direction & Display.......................................................................................... 18
Figure 7. 4 LCD-Driving-Waveform Control............................................................................... 19
Figure 7. 5 Power Control 1......................................................................................................... 19
Figure 7. 6 Input Data and Color Filter Control ......................................................................... 20
Figure 7. 7 PWM for External LED driver Control ..................................................................... 22
Figure 7. 8 Contrast/Brightness Control.................................................................................... 23
Figure 7. 9 Power Control 2......................................................................................................... 23
Figure 7. 10 Power Control 3 ....................................................................................................... 25
Figure 7. 11 Gate Scan Position.................................................................................................. 25
Figure 7. 12 Gate Scan Display Position.................................................................................... 25
Figure 7. 13 Horizontal Porch...................................................................................................... 26
Figure 7. 14 Vertical Porch .......................................................................................................... 27
Figure 7. 15 No. of Clock Cycle of Clock ................................................................................... 27
Figure 7. 16 No. of Clock Cycle of HSYNC................................................................................. 28
Figure 7. 17 Power Control 4 ....................................................................................................... 29
Figure 7. 18 Gamma Control 1 .................................................................................................... 30
Figure 7. 19 Gamma Control 2 .................................................................................................... 30
Figure 7. 20 Display Interface Control Instruction .................................................................... 33
Figure 7. 21 Entr y Mode Instruction ........................................................................................... 34
Figure 7. 22 Display Direction According To SS, RGB ............................................................. 35
Figure 7. 23 Gate Control1 Instruction ....................................................................................... 36
Figure 7. 24 CLW Bits ................................................................................................................... 36
Figure 7. 25 Gate Control2 Instruction ....................................................................................... 37
Figure 7. 26 Display Control1 Instruction .................................................................................. 37
Figure 7. 27 Display Control2 Instruction .................................................................................. 38
Figure 7. 28 Power Control1 Instruction .................................................................................... 39
Figure 7. 29 Power Control.......................................................................................................... 40
Figure 7. 30 Gamma Control 1 .................................................................................................... 41
Figure 7. 31 Gamma Control 2 .................................................................................................... 41
Figure 7. 32 Power Up Sequence when SPSW connect to VSS (CPE = VSS) ........................ 42
Figure 7. 33 Power Down Sequence when SPSW connect to VSS (CPE = VSS)................... 43
Figure 8. 1 OTP Read Table........................................................................................................... 44
Figure 8. 2 OTP Programming Circuitry......................................................................................... 44
Figure 9. 1
Figure 9. 2
Figure 9. 3
Figure 9. 4
Grayscale Control Block ..............................................................................................
Grayscale Amplifier......................................................................................................
Resistor Ladder for Gamma Voltages Generation.......................................................
Gamma Adjustment Function ......................................................................................
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
45
46
47
48
-P.2November, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
List of Figures
November, 2007
Figure 12. 1 Pixel Timing................................................................................................................ 55
Figure 12. 2 Data Transaction Timing in Parallel RGB (24 bit) Interface (SYNC Mode) ............... 56
Figure 12. 3 Data Transaction Timing in Serial RGB (8 bit) Interface (SYNC Mode) .................... 57
Figure 12. 4 Signal Timing in DE Mode ......................................................................................... 58
Figure 12. 5 Color Mode Conversion Timing ................................................................................. 58
Figure 12. 6 CCIR601 Horizontal Timing ....................................................................................... 59
Figure 12. 7 CCIR601 Vertical Timing............................................................................................ 60
Figure 12. 8 CCIR656 Horizontal Timing ....................................................................................... 61
Figure 12. 9 CCIR656 Vertical Timing ............................................................................................ 62
Figure 12. 10 Power Up Sequence ................................................................................................ 63
Figure 12. 11 Power Down Sequence............................................................................................ 64
Figure 12. 12 (a) SPI interface Timing Diagram & Write SPI Example.......................................... 65
Figure 12. 13 (b) SPI interface Timing Diagram & Read SPI Example ......................................... 66
Figure 12. 14 Rising/Falling time.................................................................................................... 66
Figure 13. 1 LCD Driving Voltage Relationship ............................................................................. 67
Figure 14. 1 Booster Capacitors .................................................................................................... 68
Figure 14. 2 Power Supply Pins Connections................................................................................ 68
Figure 14. 3 Filtering and Charge Sharing Capacitors................................................................... 69
Figure 14. 4 Panel and FPC Connection ....................................................................................... 69
Figure 14. 5 Panel Connection Example........................................................................................ 70
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.3November, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
List of Tables
November, 2007
Table 7. 1 Command Table (Primary Register Map) .................................................................. 15
Table 7. 2 Registers Default Value(Primary Register Map) ...................................................... 16
Table 7. 3 Source Output Level ................................................................................................... 17
Table 7. 4 Step-up Cycle .............................................................................................................. 19
Table 7. 5 VGH and VGL Booster Ratio ...................................................................................... 19
Table 7. 6 Step-up Cycle .............................................................................................................. 20
Table 7. 7 Op-amp Power............................................................................................................. 20
Table 7. 8 Color Filter Type.......................................................................................................... 21
Table 7. 9 Interface Type .............................................................................................................. 21
Table 7. 10 LED Driver Control Signal Frequency..................................................................... 22
Table 7. 11 VLCD63 Voltage ......................................................................................................... 24
Table 7. 12 VCOM Amplitude ....................................................................................................... 25
Table 7. 13 No. of Pixel Per Line ................................................................................................. 26
Table 7. 14 No. of Clock Cycle of Clock ..................................................................................... 27
Table 7. 15 No. of Clock Cycle of HSYNC .................................................................................. 28
Table 7. 16 VCOMH....................................................................................................................... 29
Table 7. 17 Command Table ........................................................................................................ 31
Table 7. 18 Registers Default Value(Secondary Register Map) ............................................... 32
Table 7. 19 REV Bit And Source Output Level Of Displayed Area........................................... 33
Table 7. 20 CLW Bits Setting ....................................................................................................... 36
Table 7. 21 SAP Bits Setting ........................................................................................................ 39
Table 7. 22 VCOM Amplitude ....................................................................................................... 40
Table 7. 23 VCOMH....................................................................................................................... 40
Table 8. 1 OTP Programming Sequence ....................................................................................... 44
Table 9. 1 PRP(N) ......................................................................................................................... 49
Table 9. 2 VRP(N)0 ........................................................................................................................ 49
Table 9. 3 VRP(N)1 ........................................................................................................................ 49
Table 9. 4 PKP and PKN ................................................................................................................ 49
Table 9. 5 Grayscale Voltages Formulas ....................................................................................... 50
Table 9. 6 Reference Voltages of Positive Polarity ........................................................................ 51
Table 9. 7 Reference Voltages of Negative Polarity....................................................................... 52
Table 10. 1 Maximum Ratings ........................................................................................................ 53
Table 11. 1 DC Characteristics ....................................................................................................... 54
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.4November, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
List of Tables
November, 2007
Table 12. 1 Pixel Timing ................................................................................................................. 55
Table 12. 2 Data Transaction Timing in Normal Operating Mode .................................................. 56
Table 12. 3 Power Up Sequence.................................................................................................... 63
Table 12. 4 Power Down Sequence ............................................................................................... 64
Table 12. 5 SPI Timing ................................................................................................................... 66
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.5November, 2007
HX8238-D
960 x 240 TFT LCD Single Chip
Digital Driver
Preliminary Version 01
November, 2007
1. General Description
The HX8238-D is a single chip controller and driver LSI that integrates the power
circuit. It can drive a maximum 960x240 dot graphics on a-TFT panel displays in
262K colors.
The HX8238-D has a low-voltage operation, 1.8 min voltage. In addition, The
HX8238-D is equipped with a DC-DC converter control circuit that generates the
supply voltage for source and gate drivers with minimum external components. A
common voltage generation circuit is included to drive the TFT-display counter
electrode. An integrated gamma control circuit is also included that can be adjusted
by software commands to provide maximum flexibility and optimal display quality.
The HX8238-D is suitable for any medium-sized or small portable battery-driven
product requiring long-term driving capabilities, such as Digital Still Cameras.
2. Features
 960
x 240 graphics display a-TFT panel controller/driver for 262K colors.
 Support digital 8-bits serial/24-bits parallel RGB and CCIR601/656 input mode.
 Power supply:
 VDD = 1.8V to 2.5V (non-regulated input for logic)
 VDDIO = 1.8V to 3.6V (regulated input for logic)
 VCI = 2.5V to 3.6V (power supply for internal analog circuit)
 Maximum gate driving output voltage: 30Vp-p
 Source driving output voltage: 0V to 5V
 Low current sleep mode and 8-color display mode for power saving.
 Display size: 960 x 240.
 Support Line and Frame inversion.
 Support Contrast/Brightness control
 Source and gate scan direction control.
 On-chip voltage generator.
 On-chip DC-DC converter up to 6x / -6x.
 Programmable gamma correction curve.
 Non-Volatile Memory (OTP) for VCOM calibration
 Programmable common electrode voltage amplitude and level for Cs on common
structure only
 PWM function to generate power for backlight control
 COG package
Himax Confidential
This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.6November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
3. Block Diagram
VCOM
G0-G239
S0 – S959
RESB
Source
Driver
CPE
VDD /VDDIO
Register
Circuit
REGVDD
SHUT
Gamma /
Grayscale
Voltage
REV
Switches
Network
Generator
VCI / VCIP
CXN
CXP
CYN
Booster
Circuit
Register
Circuit
VLCD 63
Data
Latches
CYP
CN
CP
C 1N
C 1P
C 2N
C2 P
Shift
Register
VG
H
VGL
C 3N
C 3P
Gate Driver
VSS/ VSSRC /
AVSS / VCHS
PWM
Shift Registers
Serial
Interface
Data Control
POL
PINV
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
QXH
B GR
CM
RL
VSYNC
H SYNC
D OTC LK
D EN
B B[7:0 ]
GG[7:0]
R R[7:0 ]
SWD[2: 0]
SEL[ 2:0]
SDO
SDI
SCL
C SB
SPS W
TB
DRV
VF B
Himax Confidential
-P.7November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
4. PAD Assignment
DUMMY (1)
DUMMY (1)
DUMMY (1)
DUMMY (2)
G1
G3
G5
G7
G235
G237
G237
G239
DUMMY (6)
S0
S1
S2
S3
S955
S956
S957
S958
S959
DUMMY (9)
G238
G236
G234
G232
G6
G4
G2
G0
DUMMY (2)
DUMMY (1)
DUMMY (1)
DUMMY (1)
DRV (2)
VFB (2)
DUMMY (1)
VCHS (10)
VSSRC (8)
VCOM (4)
VCOMH (4)
VCOML (4)
VCOMR (2)
TEST16 (1)
TEST17 (1)
VGH (5)
C3P (3)
C3N (3)
C2P (3)
C2N (3)
VGL (5)
CP (3)
CN (3)
DUMMY (1)
VDD (6)
VCI (10)
VCIP (4)
VDDIO (6)
CXP (6)
CXN (6)
CYP (6)
CYN (6)
VCIX2 (6)
VCIX2J (6)
VLCD63 (6)
C1N (5)
C1P (5)
VCIM (5)
DUMMY (1)
PINV (1)
CPE (1)
VSS (1)
SWD2 (1)
VDDIO (1)
SWD1 (1)
VSS (1)
SWD0 (1)
VDDIO (1)
SEL2 (1)
SEL1 (1)
SEL0 (1)
VSS (1)
BGR (1)
VDDIO (1)
CM (1)
VSS (1)
RL (1)
VDDIO (1)
REGVDD (1)
VSS (1)
REV (1)
VDDIO (1)
TB (1)
VSS (1)
SHUT (2)
DOTCLK (2)
VSYNC (2)
HSYNC (2)
DEN (2)
RR7 (2)
RR6 (2)
RR5 (2)
RR4 (2)
RR3 (2)
RR2 (2)
RR1 (2)
RR0 (2)
GG7 (2)
GG6 (2)
GG5 (2)
GG4 (2)
GG3 (2)
GG2 (2)
GG1 (2)
GG0 (2)
BB7 (2)
BB6 (2)
BB5 (2)
BB4 (2)
BB3 (2)
BB2 (2)
BB1 (2)
BB0 (2)
SDI (2)
SCK (2)
CSB (2)
RESB (2)
SDO (2)
POL (1)
QXH (1)
DUMMY (1)
TEST4 (1)
TEST5 (1)
TEST6 (1)
TEST7 (1)
TEST8 (1)
TEST9 (1)
TEST10 (1)
TEST11 (1)
TEST12 (1)
TEST13 (1)
TEST14 (1)
TEST15 (1)
SPSW (1)
VSS (8)
EXVR (4)
AVSS (10)
DUMMY (1)
VCOM (4)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.8November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
5. Pin Description
Name
I/O
CM
Input
RR [7:0]
GG [7:0]
BB [7:0]
Input
DEN
VSYNC
Input
HSYNC
DOTCLK
SHUT
Input
RL
TB
BGR
Input
REV
SWD[2:0]
SEL[2:0]
CPE
QXH
Function
Data sequence control pin, this pin toggle each line under delta
panel.
Polarity signal to monitor VCOM signal
Output
POL
PINV
Input
Description
Input pin to select 262k-color or 8-color display mode. After entered
8-color display mode, the driver will switch to Frame-Inversion-Mode,
Logic Control and only MSB of the data Red, Green and Blue will be considered.
- Connect to VDDIO for 8-color display mode
- Connect to VSS for 262k-color display mode
Graphic Data Input Pins. Internal pull low.
- RR [7:0]: Red Data - 8-bits
Graphic Display - GG [7:0]: Green Data - 8-bits
Data
- BB [7:0]: Blue Data - 8-bits
For 8 bit interface, only RR[7:0] are used. For unused pins, please
connect to VSS or floating.
Display enable pin from controller. Internal pull high.
Connect to VDDIO or floating if not used.
Frame synchronization signal. Internal pull high.
Display Timing - Fixed to VDDIO or floating if not used.
Signals
Line synchronization signal. Internal pull high.
- Fixed to VDDIO or floating if not used
Dot-clock signal and oscillator source. A non-stop external clock must be
provided to that pin even at front or black porch non-display period.
Display shut down pin to put the driver into sleep mode. A sharp falling
edge must be provided to such pin when IC power on. Internal pull low.
Logic Control - Connect to VDDIO for sleep mode
- Connect to VSS for normal operating mode
(Refer to Power Up Sequence)
Input pin to select the Source driver data shift direction.
- Connect to VDDIO for display first RGB data at S0-S2
- Connect to VSS for display first RGB data at S959-S957
Input pin to select the Gate driver scan direction.
- Connect to VSS for Gate scan from G239 to G0 (reverse scan)
- Connect to VDDIO for Gate scan from G0 to G239 (normal scan)
Input pin to select the color mapping.
- Connect to VDDIO for Blue-Green-Red mapping
- Connect to VSS for Red-Green-Blue mapping
(See S0-S959 pin description for details)
Input pin to select the display reversion.
- Connect to VDDIO mapping data ‘0’to maximum pixel voltage for
Panel Mapping normally white panel
- Connect to VSS for mapping data ‘0’to minimum pixel voltage for
Control
normally black panel
Input pin to define color filter type. References register R04h.
Input pin to select input interface mode. References register R04h.
These pins are internal pull low.
Input pin to enable internal charge pump circuit. Internal pull high.
- Connect to VDDIO to enable internal charge pump VCIM, VGH, VGL,
VCIX2 and VCOM.
- Connect to VSS to disable internal charge pump VGH, VGL, VCIX2
and VCOM.
POL Control
Control the polarity of POL signal. Internal pull low.
- Connect to VDDIO, POL phase is reversed with internal VCOM signal
- Connect to VSS, POL phase is same with internal VCOM signal
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.9November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Name
I/O
REGVDD
Input
RESB
Input
SPSW
Input
CSB
SCK
Input
SDI
SDO
Output
VDDIO
Power
VDD
VSS
AVSS
Power
VSSRC
VCHS
VCI
Power
VCIP
VCIM
Output
VCIX2
VCIX2J
Power
EXVR
Input
VCOMR
VCOMH
Output
VCOML
Function
Description
Input pin to enable internal voltage regulation.
-Connect to VDDIO if System Vdd > 2.5V
Logic Control
-Connect to VSS if 2.5V ≧ System Vdd ≧ 1.8V, internal regulator will
be disabled
System reset pin. Internal pull high.
System Reset
- Connect to VDDIO when not used (Refer to Power Up Sequence)
SPI table select.
SPI Select
- Connect to VSS for Secondary SPI Register.
- Connect to VDDIO for Primary SPI Register.
Chip select pin of serial interface. Internal pull high.
- Leave it OPEN when not used (Refer to Serial Interface block)
Clock pin of serial interface. Internal pull high.
- Leave it OPEN when not used (Refer to Serial Interface block)
Serial Interface
Data input pin in serial mode. Internal pull high.
- Leave it OPEN when not used (Refer to Serial Interface block)
Data output pin in serial mode.
- Leave it OPEN when not used (Refer to Serial Interface block)
Voltage input pin for I/O logic.
- Connect to system Vdd
Voltage input pin for internal logic.
(a) REGVDD = VDDIO
Power Supply for
Internal regulator will be on for 3.6V ≧ System Vdd ≧ 2.5V
Logic Circuits
VDD ~2V.
(b) REGVDD = VSS
Internal regulator will be off for 2.5V ≧ System Vdd ≧ 1.8V
VDD = System Vdd
System ground pin of the IC.
- Connect to system ground
Grounding for analog circuit.
- Connect to system ground
Ground of the
Grounding for analog circuit. This pin requires a noise free path for
Power Supply
providing accurate LCD driving voltages.
- Connect to system ground.
Grounding for booster circuit.
- Connect to system ground.
Booster input voltage pin.
- Connect to voltage source between 2.5V to 3.6V
Power Supply for
Voltage supply pin for analog circuit. This pin requires a noise free path
Analog Circuits
for providing accurate LCD driving voltages.
- Connect to same source of VCI
Negative voltage of VCI.
- Connect a capacitor for stabilization
Booster Voltages
Equals to 2 x VCI.
- Connect a capacitor for stabilization
Voltage for
This is the power supply used by on chip analog blocks and VGH/VGL
Analog
dcdc.
External reference of internal Gamma resistor.
- Connect to VSS
External
This pin provides voltage reference for internal voltage regulator when
Reference
register VDV[6:0] of Power Control 3 set to “01111XX”.
- Connect to an external voltage source for reference
This pin indicates a HIGH level of VCOM generated in driving the VCOM
alternation.
Voltages for
- Connect a capacitor for stabilization
VCOM Signal This pin indicates a LOW level of VCOM generated in driving the VCOM
alternation.
- Connect a capacitor for stabilization
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.10November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Name
I/O
VLCD63
VGH
Output
VGL
CP
CXP
CYP
C1P
C2P
C3P
CN
CXN
CYN
C1N
C2N
C3N
DRV
Output
VFB
Input
TEST4~5
TEST6~17
VCOM
G0-G239
Input
Output
Input
Output
S0-S959
DUMMY
Function
Description
Internal generated power for source driver
- Connect a capacitor for stabilization
LCD Driving
A positive power output pin for gate driver.
Voltages
- Connect a capacitor for stabilization
A negative power output pin for gate driver.
- Connect a capacitor for stabilization
- Connect a capacitor to CN
- Connect a capacitor to CXN
- Connect a capacitor to CYN
- Connect a capacitor to C1N
- Connect a capacitor to C2N
Booster and
- Connect a capacitor to C3N
Stabilization
- Connect a capacitor to CP
Capacitors
- Connect a capacitor to CXP
- Connect a capacitor to CYP
- Connect a capacitor to C1P
- Connect a capacitor to C2P
- Connect a capacitor to C3P
Power transistor gate signal for the boost converter
Main boost regulator feedback input. Connect feedback resistive divider
PWM control
to GND.
FB threshold is 0.6 V nominal
IC Testing Signal Test pin of the internal circuit. Leave it connect to ground.
IC Testing Signal Test pin of the internal circuit. Leave it OPEN.
A power supply for the TFT-display common electrode.
Gate driver output pins. These pins output VGH, VGL level.
LCD Driving
Source driver output pins.
Signals
S (3n): display Red if BGR = LOW, Blue if BGR = HIGH.
S (3n+1): display Green.
S (3n+2): display Blue if BGR = LOW, Red if BGR = HIGH.
Floating pins and no connection inside the IC. These pins can be
shorted together or connect to any signal.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.11November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
6. Block Function Description
6.1 Serial Interface
The SPI is available through the chip select line (CSB), serial transfer clock line
(SCK), serial data input (SDI), and serial data output (SDO).
The Driver IC recognizes the start of data transfer at the falling edge of CSB input to
initiate the transfer of start byte. It recognizes the end of data transfer at the rising
edge of CSB input. The Driver IC is selected when the 6-bit chip address in the start
byte transferred from the transmission device and the 6-bit device identification code
assigned to the Driver IC are compared and both 6-bit data correspond. The
identification code must be 011100(Primary SPI Register) or 011101(Secondary SPI
Register). Two different chip addresses must be assigned to the Driver IC because
the seventh bit of the start byte is assigned to a register select bit (RS). When RS = 0,
index register write or status read is executed. When the RS = 1, instruction write.
The eighth bit of the start byte is to specify read or write (R/W bit). The data are
received when the R/W bit is 0, and are transmitted when the R/W bit is 1.
After receiving the start byte, the Driver IC starts to transmit or receive data by byte.
The data transmission adopts a format by which the MSB is first transmitted (9th SCK
started). All Driver IC instructions consist of 16 bits and they are executed internally
after two bytes are transmitted with the MSB first (IB15 to 0---9th ~24th SCK).
Transfer starts
Transfer ends
CSB
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
MSB
SDI
0
1
1
1
0
0
RS RW DB DB DB DB
15 14 13 12
Device ID
SDO
LSB
DB DB DB
11 10 9
DB DB DB DB DB DB DB DB DB
7
5 4 3 2 1 0
8
6
Index register setting/Instruction
DB DB DB DB
15 14 13 12
DB DB DB
11 10 9
DB DB DB DB DB DB DB DB DB
7
5 4 3 2 1 0
8
6
Status read
Figure 6. 1 SPI Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.12November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
6.2 Data Control
The display data and frame position information from the controller is synchronized
with the Gate Drive circuit and shift registered for the Source Driver circuit.
6.3 Gamma/Grayscale Voltage Generator
The grayscale voltage circuit generates a LCD driver circuit that corresponds to the
grayscale levels as specified in the grayscale gamma-adjusting resistor. 262K possible
colors can be displayed.
6.4 Boost and Regulator Circuit
These two functional blocks generate the voltage of VGH, VGL, VCOMH, VCOML and
VLCD63, which are necessary for operating a TFT LCD.
6.5 PWM Boost Converter
VCC
L1
VO
D1
DRV
PWM
Controller
R1
VFB
+
-
C2
0 .6V
R2
PWM Boost Converter
Figure 6. 2
When set PWMS=0, internal PWM function is enabled. The internal reference voltage is
adjustable by FB[2:0] in R05h. By adjusting the voltage, you can get different VO to
meet your system application.
When set PWMS=1, HX8238D will send the enable signal from DRV pin to control
external LED driver. The enable control signal can be adjusted the duty cycle by
DUTY[7:0] in R08h, the duty cycle range is from 1/256 to 256/256. And it also can be
adjustable the frequency by PWMF[3:0] in R08h, the frequency range is from 100Hz to
100 KHz.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.13November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
6.6 Shift Register
The shift registers control the direction of line scanning of source.
6.7 Data Latches
This block is a series of latches carrying the display signal information. These latches
hold the data, which will be fed to the Source Driver to output the required voltage level.
6.8 Aging Mode
If only DOTCLK is sent into driver IC without VSYNC, HSYNC, and DEN signals,
HX8238-D will enter Aging Mode after power on. In Aging Mode, the display will show
Black, White, Red, Green, and Blue images in series automatically.
6.9 Reset Circuit
This block is integrated into the Interface Logic which includes Power on Reset circuitry
and the hardware reset pin, /RES. Both of these having the same reset function. Once
the /RES pin receives a negative reset pulse, all internal circuitry will start to initialize.
The minimum pulse width for completing the reset sequence is 10us. The status of the
chip after reset is given by:
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.14November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7 3-Wire Serial Port Interface
7.1 Primary Register Command Table
Reg#
SR
R27h
R28h
R29h
R2Bh
Register
Status Read
Driver output
control
LCD driver
AC control
Power
control (1)
Data and
color filter
control
Reserved
LED
control
Contrast/
Brightness
control
Power
control (2 )
Power
control (3 )
Gate scan
starting
Position
Horizontal
Porch
Vertical
Porch
Power
control (4 )
Reserved
Reserved
Reserved
Reserved
R30h
γ control (1)
0
1
0
0
0
0
0
R31h
γ control (2)
0
1
0
0
0
0
0
R32h
γ control (3)
0
1
0
0
0
0
0
R33h
γ control (4)
0
1
0
0
0
0
0
R34h
γ control (5)
0
1
0
0
0
0
0
R35h
γ control (6)
0
1
0
0
0
0
0
R36h
γ control (7)
0
1
0
0
0
0
0
R37h
γ control (8)
0
1
0
0
0
R01h
R02h
R03h
R04h
R06h
R08h
R0Ah
R0Dh
R0Eh
R0Fh
R16h
R17h
R1Eh
R/W R/S
1
0
IB15
L7
IB14
L6
IB13
L5
IB12
L4
IB11
L3
IB10
L2
IB9
L1
IB8
L0
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
0
1
0
RL
REV
PINV
BGR
SM
TB
CPE
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
B/C
0
0
0
0
0
0
0
0
0
0
1
DCT3
DCT2
DCT1
DCT0
BTF
BT2
BT1
BT0
DC3
DC2
DC1
DC0
AP2
AP1
AP0
0
0
1
0
0
0
0
0
PALM
BLT1
BLT0
0
0
SEL2
SEL1
SEL0
SWD2
SWD1 SWD0
0
1
0
0
0
DUTY5
DUTY4
DUTY3
DUTY2
DUTY1
DUTY0
0
1
0
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0
0
0
CON4
CON3
CON2
CON1
CON0
0
1
0
VRC2
VRC1
VRC0
0
0
VDS1
VDS0
0
0
VRH5
VRH4
VRH3
VRH2
VRH1
VRH0
0
1
0
0
1
VDV6
VDV5
VDV4
VDV3
VDV2
VDV1
VDV0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
SCN7
SCN6
SCN5
SCN4
SCN3
SCN2
SCN1
SCN0
0
1
XLIM8 XLIM7 XLIM6 XLIM5 XLIM4 XLIM3 XLIM2 XLIM1 XLIM0
0
0
0
0
0
0
0
0
1
STH1
STH0
HBP6
HBP5
HBP4
HBP3
HBP2
HBP1
HBP0
VBP6
VBP5
VBP4
VBP3
VBP2
VBP1
VBP0
0
1
0
0
0
0
0
0
0
0
nOTP
VCM6 VCM5
VCM4
VCM3
VCM2
VCM1
VCM0
PKP
02
PKP
22
PKP
42
PRP
02
PKN
02
PKN
22
PKN
42
PRN
02
VRP
02
VRN
02
PKP
01
PKP
21
PKP
41
PRP
01
PKN
01
PKN
21
PKN
41
PRN
01
VRP
01
VRN
01
PKP
00
PKP
20
PKP
40
PRP
00
PKN
00
PKN
20
PKN
40
PRN
00
VRP
00
VRN
00
Reserved
R3Ah
γ control (9)
0
1
0
0
0
R3Bh
γ control (10)
0
1
0
0
0
PWMS PWMF3 PWMF2 PWMF1 PWMF0 DUTY7 DUTY6
0
0
VRP
14
VRN
14
VRP
13
VRN
13
PKP
12
PKP
32
PKP
52
PRP
12
PKN
12
PKN
32
PKN
52
PRN
12
VRP
12
VRN
12
Reserved
Reserved
Reserved
Reserved
PKP
PKP
11
10
PKP
PKP
31
30
PKP
PKP
51
50
PRP
PRP
11
10
PKN
PKN
11
10
PKN
PKN
31
30
PKN
PKN
51
50
PRN
PRN
11
10
VRP
VRP
11
10
VRN
VRN
11
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VRP
03
VRN
03
Note: * means don’t care
Software settings will override hardware pin (eg, BGR bits override BGR pin definition)
Table 7. 1 Command Table (Primary Register Map)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.15November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.2 Primary Register Default Value
Reg#
R01h
R02h
R03h
R04h
R08h
R0Ah
R0Dh
R0Eh
R0Fh
R16h
R17h
R1Eh
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R3Ah
R3Bh
Hex Code
XX00
0200
6464
04XX
06FF
4008
3229
1200
0000
9F80
005F
0000
0407
0202
0000
0505
0003
0707
0000
0904
0904
Register Bit Value
RL=X, REV=X, PINV=X, BGR=X, SM=“0”, TB=X, CPE=X
B/C=“1”
DCT=“0110”, BT=“100”, BTF=“0”, DC=“0110”, AP=“010”
PALM=“1”, BLT=”00”, SEL= X, SWD=X
PWMS=”0”, PWMF=”0110”, DUTY=”11111111”
BR=“1000000”, CON=“01000”
VRC=“011”, VDS=“10”, VRH=“101001”
VDV=“1001000”
SCN=“00000000”
XLIM=“100111111”
STH=“00”, HBP=Note(2), VBP=Note(2)
nOTP=“0”, VCM=“1011111”
PKP1=“000”, PKP0=“000”
PKP3=“100”, PKP2=“111”
PKP5=“010”, PKP4=“010”
PRP1=“000”, PRP0=“000”
PKN1=“101”, PKN0=“101”
PKN3=“000”, PKN2=“011”
PKN5=“111”, PKN4=“111”
PRN1=“000”, PRN0=“000”
VRP1=“01001”, VRP0=“0100”
VRN1=“01001”, VRN0=“0100”
Note: (1) X means the bit is refer to the logic stage of the corresponding hardware pin
(2) The default values of the VSP、HBP、VBP are automatically set by SEL
Table 7. 2 Registers Default Value(Primary Register Map)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.16November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.3 Primary Register Command Description
Status Read
R/W
R
RS
0
IB15
L7
IB14
L6
IB13
L5
IB12
L4
IB11
L3
IB10
L2
IB9
L1
IB8
L0
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 1 Status Read
The status read instruction reads the internal status of the HX8238-D.
L7–0: Indicate the driving raster-row position where the liquid crystal display is being
driven.
Driver Output Control (R01h)
R/W
W
RS
1
IB15
0
IB14
R L
IB13
REV
IB12
PINV
IB11
BGR
IB10
S M
IB9
T B
IB8
CPE
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 2 Driver Output Control
CPE: When CPE=0, Vcim is not shut down, but VGH, VGL, VCOM and Vcix2 are
shut down. When CPE=1, internal charge pump Vcim, VGH, VGL, VCOM and
Vcix2 are enabled.
REV: Displays all character and graphics display sections with reversal when
REV=“0”. Since the grayscale level can be reversed, display of the same data
is enabled on normally white and normally black panels. Source output level is
indicated below.
REV
1
0
RGB data
00000H
:
3FFFFH
00000H
:
3FFFFH
Table 7.
Source output level
VCOM = ”L”
VCOM = ”H”
V0
V63
:
:
V63
V0
V63
V0
:
:
V0
V63
3 Source Output Level
PINV: When PINV=0, POL output is same phase with internal VCOM signal. When
PINV=1, POL output phase is reversed with VCOM signal.
BGR: Selects the <R><G><B> arrangement. When BGR=“0” <R><G><B> color is
assigned from S0.When BGR=“1” <B><G><R> color is assigned from S0.
SM: Change the division of gate driver. When SM = “0”, odd/even division (interlace
mode) is selected. When SM=“1”, upper/lower division is selected. Select the
division mode according to the mounting method.
TB: Selects the output shift direction of the gate driver. When TB=“1”, G0 shifts to
G239. When TB = “0”, G239 shifts to G0.
RL: Selects the output shift direction of the source driver. When RL=“1”, S0 shifts to
S959 and <R><G><B> color is assigned from S0. When RL=“0”, S959 shifts to
S0 and <R><G><B> color is assigned from S959. Set RL bit and BGR bit when
changing the dot order of R, G and B.
Note: The default setting of register bits REV, BGR, TB and RL are defined by the logic stage of corresponding
hardware pins. These bits will override the hardware setting once software command was sent to set the bits.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.17November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
SM = 0
SM = 1
G0
G2
G4
G0
G1
G2
G3
G4
G5
G 236
G 238
G1
G3
G5
TB = 1
RL = 1
G236
G 237
G238
G 239
S0
G 237
G 239
S0
S959
S959
G0
G1
G0
G2
G4
G2
G3
G4
G5
G236
G238
G1
G3
G5
TB = 0
RL = 1
G236
G 237
G238
G 239
S0
G 237
G 239
S959
S0
S959
G0
G1
G0
G2
G4
G2
G3
G4
G5
G236
G238
G1
G3
G5
TB = 1
RL = 0
G 236
G237
G 238
G239
S0
G237
G239
S0
S959
S959
G0
G1
G0
G2
G4
G2
G3
G4
G5
G 236
G 238
TB = 0
G1
G3
G5
RL = 0
G 236
G 237
G 238
G 239
S0
G 237
G 239
S959
S0
S 959
Figure 7. 3 Scan Direction & Display
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.18November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
LCD-Driving-Waveform Control (R02h)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
B/C
IB8
0
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 4 LCD-Driving-Waveform Control
B/C: When B/C = 0, frame inversion of the LCD driving signal is enabled. When B/C =
1, line inversion waveform is generated
Power control 1 (R03h)
R/W
W
RS
1
IB15
DCT3
IB14
DCT2
IB13
DCT1
IB12
DCT0
IB11
BT F
IB10
BT2
IB9
BT1
IB8
BT0
IB7
DC3
IB6
DC2
IB5
DC1
IB4
DC0
IB3
AP2
IB2
AP1
IB1
AP0
IB0
0
Figure 7. 5 Power Control 1
DCT3-0: Set the step-up cycle of the step-up circuit for 8-color mode (CM = VDDIO).
When the cycle is accelerated, the Vcim and Vcix2 driving ability of the
step-up circuit increase, but their current consumption increase, too. Adjust
the cycle taking into account the display quality and power consumption.
VGH and VGL are always fixed at the step-up cycle of Fline x 0.5.
DCT3
DCT2
DCT1
DCT0
Step-up cycle
0
0
0
0
Fline x 14
0
0
0
1
Fline x 12
0
0
1
0
Fline x 10
0
0
1
1
Fline x 8
0
1
0
0
Fline x 7
0
1
0
1
Fline x 6
0
1
1
0
Fline x 5
0
1
1
1
Fline x 4
1
0
0
0
Fline x 3
1
0
0
1
Fline x 2
1
0
1
0
Fline x 1
1
0
1
1
Fline x 0.5
1
1
0
0
Fline x 0.25
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
* Fline = horizontal frequency (Fline Typ. 15KHz)
Table 7. 4 Step-up Cycle
BT2-0 & BTF: Control the step-up factor of the step-up circuit. Adjust the step-up
factor according to the power supply voltage to be used.
BTF
0
0
0
0
0
0
0
0
1
BT2
0
0
0
0
1
1
1
1
X
BT1
0
0
1
1
0
0
1
1
X
BT0
0
1
0
1
0
1
0
1
X
VGH output
VCIX2j X 3
VCIX2j X 3
VCIX2 j X 3
VCIX2j X 2 + VCI
VCIX2j X 2 + VCI
VCIX2j X 2 + VCI
VCIX2j X 2
VCIX2j X 2
VCIX2j X 3
VGL output
- (VCIX2j X 3) + VCI
- (VCIX2j X 2)
- (VCIX2j X 3)
- (VCIX2j X 2) - VCI
- (VCIX2j X 2)
- (VCIX2j X 2) + VCI
- (VCIX2j X 2)
- (VCIX2j X 2) + VCI
- VCIX2j
Table 7. 5 VGH and VGL Booster Ratio
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.19November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
DC3-0: Set the step-up cycle of the step-up circuit for 262k-color mode (CM=VSS).
When the cycle is accelerated, the Vcim and Vcix2 driving ability of the
step-up circuit increase, but their current consumption increase, too. Adjust
the cycle taking into account the display quality and power consumption.
VGH and VGL are always fixed at the step-up cycle of Fline x 0.5.
DC3
DC2
DC1
DC0
Step-up cycle
0
0
0
0
Fline x 14
Fline x 12
0
0
0
1
0
0
1
0
Fline x 10
Fline x 8
0
0
1
1
Fline x 7
0
1
0
0
0
1
0
1
Fline x 6
Fline x 5
0
1
1
0
Fline x 4
0
1
1
1
1
0
0
0
Fline x 3
Fline x 2
1
0
0
1
Fline x 1
1
0
1
0
1
0
1
1
Fline x 0.5
Fline x 0.25
1
1
0
0
Reserved
1
1
0
1
1
1
1
0
Reserved
Reserved
1
1
1
1
Note: Fline = horizontal frequency (Fline Typ. 15KHz)
Table 7. 6 Step-up Cycle
AP2-0: Adjust the amount of current from the stable-current source in the internal
operational amplifier circuit. When the amount of current becomes large, the
driving ability of the operational-amplifier circuits increase. Adjust the current
taking into account the power consumption. During times when there is no
display, such as when the system is in a sleep mode, set AP2-0 = “000” to halt
the operational amplifier circuit and the step-up circuits to reduce current
consumption.
AP2
0
0
0
0
1
1
1
1
AP1
0
0
1
1
0
0
1
1
AP0
0
1
0
1
0
1
0
1
Op-amp power
Least
Small
Small to medium
Medium
Medium to large
Large
Large to Maximum
Maximum
Table 7. 7 Op-amp Power
Input Data and Color Filter Control (R04h)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
PALM
IB9
BLT1
IB8
BLT0
IB7
0
IB6
0
IB5
SEL2
IB4
SEL1
IB3
SEL0
IB2
SWD2
IB1
SWD1
IB0
SWD0
Figure 7. 6 Input Data and Color Filter Control
SWD2-0: Control and switch the relationship between the R, G, B data and color filter
type.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.20November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
SWD[2:0]= 000
G1
G2
G3
G4
G
B
R
G
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
B
R
G
B
QXH
L
H
L
H
B
R
G
B
R
G
B
R
G
B
R
G
B
R
B
R
G
B
G
B
SWD[2:0]= 100
R
G1
G2
G3
G4
G
G
B
R
G
B
R
G
B
R
G
B
R
B
R
G
R
G
B
B
R
G237
G238
G239
G240
QXH
L
H
L
H
G1
G2
G3
G4
B
R
G
B
R
G
B
R
G
B
R
G
B
B
R
SWD [2:0]=111
R
R
R
R
G1
G2
G3
G4
G
G
G
G
B
B
B
B
R
R
R
R
G
G
G
G
B
B
B
B
L
H
L
H
23 4L ines
24 0L ines
R
R
R
R
G
G
G
G
B
B
B
B
R
G
R
G
B
R
B
R
G
B
G
B
R
G
B
R
G
B
G
R
G
B
R
B
B
R
G
B
G
B
R
G
R
G
B
R
G
B
R
G
R
G
B
R
B
R
R
G
B
G
B
R
R
G
G
B
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
R
G
R
G
B
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
G
B
R
G
G237
G238
G239
G240
QXH
L
H
L
H
G1
G2
G3
G4
R
G
B
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
B
R
R
G
B
R
G
B
R
G
B
R
G
B
B
R
G
R
G
G
B
R
L
H
L
H
G
SWD[2:0]= 110
L
H
L
H
QXH
L
H
L
H
…
…
L
H
L
H
…
…
G237
G238
G239
G240
G1
G2
G3
G4
B
R
G
G
B
QXH
L
H
L
H
…
…
G237
G238
G239
G240
B
R
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
G
B
L
H
L
H
QXH
L
L
L
L
Note：The QXH is used to control the input data sequence.
…
…
G237
G238
G239
G240
B
R
B
SWD [2:0]=01X
QXH
L
H
L
H
23 4L in es
G
B
R
G
G
G
24 0L in es
G
B
R
G
B
23 4L in es
R
G
R
G
R
R
SWD [2:0]= 101
24 0L in es
23 4Lin es
24 0Lin es
G237
G238
G239
G240
B
B
B
…
…
L
H
L
H
…
…
G
G
2 34 Lin es
G
R
G
R
2 40 Lin es
B
R
B
2 34 Line s
G
G1
G2
G3
G4
2 40 Line s
2 34 Lin es
2 40 Lin es
…
…
G237
G238
G239
G240
SWD [2:0]= 001
R
R
R
R
G
G
G
G
B
B
B
B
L
L
L
L
Table 7. 8 Color Filter Type
SEL2-0: Define the input interface mode.
SEL2
SEL1 SEL0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Input format
YUV mode
Format
Parallel-RGB data format
(only support stripe type color filter)
Serial-RGB data format
CCIR 656 data format (640RGB)
CCIR 656 data format (720RGB)
YUV mode A data format (Cr-Y-Cb-Y)
YUV mode A data format (Cr-Y-Cb-Y)
YUV mode B data format (Cb-Y-Cr-Y)
YUV mode B data format (Cb-Y-Cr-Y)
DOTCLK Freq (MHz)
24.54
27
Display Data
640
720
Operating Frequency
6.5MHz
19.5MHz
24.54MHz
27MHz
24.54MHz
27MHz
27MHz
24.54MHz
Active Area (DOTCLK)
1280
1440
Table 7. 9 Interface Type
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.21November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
BLT[1:0]: Set the initial power on black image insertion time.
00: 10 fields
01: 20 fields
10: 40 fields
11: 80 fields
PALM: Set the input data line number in PAL mode
0: 280 lines
1: 288 lines
PWM Control (R08h)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
PWMS
IB11
PWMF3
IB10
PWMF2
IB9
PWMF1
IB8
PWMF0
IB7
DUTY7
IB6
DUTY6
IB5
DUTY5
IB4
DUTY4
IB3
DUTY3
IB2
DUTY2
IB1
DUTY1
IB0
DUTY0
Figure 7. 7 PWM for External LED driver Control
PWMS: Select PWM function.
When PWMS=0, use internal PWM circuit. (Default)
When PWMS=1, use external LED driver, DRV pin outputs control signal.
PWMF3-0: Select control signal frequency when set PWMS=1. Adjust range from
100Hz to 100KHz. Default value = 0110.
PWMF3
PWMF2
PWMF1
PWMF0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Parallel RGB
6.5MHz
8
DCLK / 2
8
DCLK / 2
8
DCLK / 2
9
DCLK / 2
10
DCLK / 2
11
DCLK / 2
12
DCLK / 2
13
DCLK / 2
14
DCLK / 2
15
DCLK / 2
16
DCLK / 2
Reserved
Reserved
Reserved
Reserved
Reserved
Enable signal frequency
Serial RGB
19.5MHz
8
DCLK / 3 / 2
8
DCLK / 3 / 2
8
DCLK / 3 / 2
9
DCLK / 3 / 2
10
DCLK / 3 / 2
11
DCLK / 3 / 2
12
DCLK / 3 / 2
13
DCLK / 3 /2
14
DCLK / 3 / 2
15
DCLK / 3 / 2
16
DCLK / 3 / 2
Reserved
Reserved
Reserved
Reserved
Reserved
YUV/CCIR656
24.54/27MHz
8
DCLK / 2
9
DCLK / 2
10
DCLK / 2
11
DCLK / 2
12
DCLK / 2
13
DCLK / 2
14
DCLK / 2
15
DCLK / 2
16
DCLK / 2
17
DCLK / 2
18
DCLK / 2
Reserved
Reserved
Reserved
Reserved
Reserved
Table 7. 10 LED Driver Control Signal Frequency
DUTY7-0: Select control signal duty cycle when set PWMS=1. Adjust range from
00h(duty cycle=1/256) to FFh(duty cycle=256/256). Default value is FFh.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.22November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Contrast/Brightness Control (R0Ah)
R/W
W
RS
1
IB15
0
IB14
B R6
IB13
BR5
IB12
BR4
IB11
B R3
IB10
BR2
IB9
BR1
IB8
B R0
IB7
0
IB6
0
IB5
0
IB4
CON4
IB3
CON3
IB2
CON2
IB1
CON1
IB0
CON0
Figure 7. 8 Contrast/Brightness Control
CON4-0: Display Contrast level adjustment. (0.125/step) Adjust range from 00h
(level=0) to 1Fh (level=3.875). Default value is 08h (level=1).
BR6-0: Display Brightness level adjustment. (2/step) Adjust range from 00h
(level=-128) to 7Fh(level=+126). Default value is 40h(level=0).
Power Control 2 (R0Dh)
R/W
W
RS
1
IB15
0
IB14
VRC2
IB13
VRC1
IB12
VRC0
IB11
0
IB10
0
IB9
VDS1
IB8
VDS0
IB7
0
IB6
0
IB5
VRH5
IB4
VRH4
IB3
VRH3
IB2
VRH2
IB1
VRH1
IB0
VRH0
Figure 7. 9 Power Control 2
VRC[2:0]: Set the VCIX2 charge pump voltage clamp.
VRC[2:0]=000, 5.1V
VRC[2:0]=001, 5.3V
VRC[2:0]=010, 5.5V
VRC[2:0]=011, 5.7V
VRC[2:0]=100, 5.9V
VRC[2:0]=101, reserved
VRC[2:0]=110, reserved
VRC[2:0]=111, reserved
VDS[1:0]: Set the VDD regulator voltage if pin “REGVDD” is set to VDDIO.
VDS[1:0]=00, 1.8V
VDS[1:0]=01, 2V
VDS[1:0]=10, 2.2V
VDS[1:0]=11, 2.5V
VRH5-0: Set amplitude magnification of VLCD63. These bits amplify the VLCD63
voltage 2.464 to 4.456 times the Vref voltage set by VRH5-0.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.23November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
VRH5 VRH4 VRH3 VRH2 VRH1 VRH0 VLCD63Voltage
0
0
0
0
0
0
Vref x 2.456
0
0
0
0
0
1
Vref x 2.488
0
0
0
0
1
0
Vref x 2.520
0
0
0
0
1
1
Vref x 2.552
0
0
0
1
0
0
Vref x 2.584
0
0
0
1
0
1
Vref x 2.616
0
0
0
1
1
0
Vref x 2.648
0
0
0
1
1
1
Vref x 2.680
0
0
1
0
0
0
Vref x 2.712
0
0
1
0
0
1
Vref x 2.744
0
0
1
0
1
0
Vref x 2.776
0
0
1
0
1
1
Vref x 2.808
0
0
1
1
0
0
Vref x 2.840
0
0
1
1
0
1
Vref x 2.872
0
0
1
1
1
0
Vref x 2.904
0
0
1
1
1
1
Vref x 2.936
0
1
0
0
0
0
Vref x 2.968
0
1
0
0
0
1
Vref x 3.000
0
1
0
0
1
0
Vref x 3.032
0
1
0
0
1
1
Vref x 3.064
0
1
0
1
0
0
Vref x 3.096
0
1
0
1
0
1
Vref x 3.128
0
1
0
1
1
0
Vref x 3.160
0
1
0
1
1
1
Vref x 3.192
0
1
1
0
0
0
Vref x 3.224
0
1
1
0
0
1
Vref x 3.256
0
1
1
0
1
0
Vref x 3.288
0
1
1
0
1
1
Vref x 3.320
0
1
1
1
0
0
Vref x 3.352
0
1
1
1
0
1
Vref x 3.384
0
1
1
1
1
0
Vref x 3.416
0
1
1
1
1
1
Vref x 3.448
Note: Vref is the internal reference voltage equals to 1.25V.
VRH5 VRH4 VRH3 VRH2 VRH1 VRH0 VLCD63Voltage
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Vref x 3.480
Vref x 3.512
Vref x 3.544
Vref x 3.576
Vref x 3.608
Vref x 3.640
Vref x 3.672
Vref x 3.704
Vref x 3.736
Vref x 3.768
Vref x 3.800
Vref x 3.832
Vref x 3.864
Vref x 3.896
Vref x 3.928
Vref x 3.960
Vref x 3.992
Vref x 4.024
Vref x 4.056
Vref x 4.088
Vref x 4.120
Vref x 4.152
Vref x 4.184
Vref x 4.216
Vref x 4.248
Vref x 4.280
Vref x 4.312
Vref x 4.344
Vref x 4.376
Vref x 4.408
Vref x 4.440
Vref x 4.472
Table 7. 11 VLCD63 Voltage
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.24November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Power Control 3 (R0Eh)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
VDV6
IB11
VDV5
IB10
VDV4
IB9
VDV3
IB8
VDV2
IB7
VDV1
IB6
VDV0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 10 Power Control 3
VDV6-0: Set the alternating amplitudes of VCOM at the VCOM alternating drive.
These bits amplify VCOM amplitude 0.6 to 1.2525 times the VLCD63
voltage. External voltage at VCOMR is referenced when VDV=“01111xx”.
VDV6
0
0
0
0
0
VDV5
0
0
0
0
0
VDV4
0
0
0
0
0
VDV2
0
0
0
0
1
VDV1
0
0
1
1
0
VDV0
0
1
0
1
0
1
1
VDV3
0
0
0
0
0
:
:
:
1
1
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
*
*
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
*
0
0
:
:
:
1
1
1
*
0
0
1
*
1
1
*
*
0
1
*
*
VCOM Amplitude
VLCD63 x 0.6000
VLCD63 x 0.6075
VLCD63 x 0.6150
VLCD63 x 0.6225
VLCD63 x 0.6300
:
Step = 0.0075
:
VLCD63 x 1.0350
VLCD63 x 1.0425
Reference from
external voltage (VCOMR)
VLCD63 x 1.0500
VLCD63 x 1.0575
:
Step = 0.0075
:
VLCD63 x 1.2450
VLCD63 x 1.2525
Reserved
Reserved
Table 7. 12 VCOM Amplitude
Gate Scan Position (R0Fh)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
SCN7
IB6
SCN6
IB5
SCN5
IB4
SCN4
IB3
SCN3
IB2
SCN2
IB1
SCN1
IB0
SCN0
Figure 7. 11 Gate Scan Position
SCN8-0: Set the scanning starting position of the gate driver.
1 st line of data
G0
G0
TECHNOLOGIES
奇景光電
G30
1st line of data
HIMAX
TECHNOLOGIES
G239
奇景光電
SCN 7-0
=00000000
SCN 7-0
=00000000
G239
HIMAX
Figure 7. 12 Gate Scan Display Position
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.25November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Horizontal Porch (R16h)
R/W
W
RS
1
IB15
XLIM8
IB14
XLIM 7
IB13
XLIM6
IB12
XLIM5
IB11
XLIM4
IB10
XLIM3
IB9
XLIM2
IB8
XLIM1
IB7
XLIM0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 13 Horizontal Porch
XLIM8-0: Set the number of valid pixel per line.
XLIM8
0
0
0
XLIM7
0
0
0
XLIM6
0
0
0
XLIM5
0
0
0
1
1
1
1
0
0
0
1
0
0
1

1
1


XLIM4
0
0
0
:
:
：
1
1


XLIM3
0
0
0
XLIM2
0
0
0
XLIM1
0
0
1
XLIM0
0
1
0
1
1


1
1


1
1


0
1


No. of pixel per line
1
2
3
:
Step = 1
:
319
320
Reserved
Reserved
Table 7. 13 No. of Pixel Per Line
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.26November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Vertical Porch (R17h)
R/W
W
RS
1
IB15
STH1
IB14
STH0
IB13
HBP6
IB12
HBP5
IB11
HBP4
IB10
HBP3
IB9
HBP2
IB8
HBP1
IB7
HBP0
IB6
VBP6
IB5
VBP5
IB4
VBP4
IB3
VBP3
IB2
VBP2
IB1
VBP1
IB0
VBP0
Figure 7. 14 Vertical Porch
HBP6-0: Set the delay period from falling edge of HSYNC signal to first valid data.
The pixel data exceed the range set by XLIM8-0 and before the first valid
data will be treated as dummy data. The setting is only effective in SYNC
mode timing.
HBP6
0
0
0
0
0
0
0
0
0
0
HBP5
0
0
0
0
0
0
0
0
0
0
HBP4
0
0
0
0
0
0
0
0
0
0
HBP3
0
0
0
0
0
0
0
0
1
1
HBP2
0
0
0
0
1
1
1
1
0
0
HBP1
0
0
1
1
0
0
1
1
0
0
HBP0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
No. of Clock Cycle
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
9
:
Step = 1
:
126
127
Table 7. 14 No. of Clock Cycle of Clock
Cycle time of HSYNC
Set by XLIM8-0
Set by HBP6-0
HSYNC
Default 320 pixels per line
Pixel Data
Dummy
D0
D1
D2
D317 D318 D319
Dummy
DOTCLK
10 clock cycles of DOTCLK
HBP6-0 = 00001000
Figure 7. 15 No. of Clock Cycle of Clock
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.27November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
STH1-0: Adjust the first valid data by dot clock. This setting is not valid in parallel RGB
input interface.
STH = 00: +0 dot clock
STH = 01: +1 dot clock
STH = 10: +2 dot clock
STH = 11: +3 dot clock
VBP6-0: Set the delay period from falling edge of VSYNC to first valid line. The line data
within this delay period will be treated as dummy line. The setting is only
effective in SYNC mode timing.
VBP6
0
0
0
0
0
VBP5
0
0
0
0
0
VBP4
0
0
0
0
0
VBP3
0
0
0
0
0
VBP2
0
0
0
0
1
VBP1
0
0
1
1
0
VBP0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No. of clock cycle of HSYNC
Can’t set
Can’t set
2
3
4
:
Step = 1
:
124
125
126
127
Table 7. 15 No. of Clock Cycle of HSYNC
Cycle time of VSYNC
Set by VBP6-0
VSYNC
HSYNC
Dummy Lines
1st Line
Last Line
Dummy Lines
Figure 7. 16 No. of Clock Cycle of HSYNC
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.28November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Power Control 4 (R1Eh)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
nOTP
IB6
VCM6
IB5
VCM5
IB4
VCM4
IB3
VCM3
IB2
VCM2
IB1
VCM1
IB0
VCM0
Figure 7. 17 Power Control 4
nOTP: nOTP=0, VCOM6-0 value is controlled by OTP memory. (Default)
nOTP=1, VCOM6-0 value is controlled by SPI register.
VCM6-0: Set the VCOMH voltage if nOTP = “1”. These bits amplify the VCOMH voltage
0.36 to 0.995 times the VLCD63 voltage.
VCM6
0
0
0
0
0
VCM5
0
0
0
0
0
VCM4
0
0
0
0
0
VCM3
0
0
0
0
0
VCM2
0
0
0
0
1
VCM1
0
0
1
1
0
VCM0
0
1
0
1
0
:
:
1
1
1
1
0
0
1
1
0
1
0
1
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
Note: 2V < VCOMH < VLCD63
1
1
1
1
VCOMH
VLCD63 x 0.360
VLCD63 x 0.365
VLCD63 x 0.370
VLCD63 x 0.375
VLCD63 x 0.380
:
Step = 0.005
:
VLCD63 x 0.980
VLCD63 x 0.985
VLCD63 x 0.990
VLCD63 x 0.995
Table 7. 16 VCOMH
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.29November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Gamma Control 1 (R30h to R37h)
R/W
W
W
W
W
W
W
W
W
RS
1
1
1
1
1
1
1
1
IB15
0
0
0
0
0
0
0
0
IB14
0
0
0
0
0
0
0
0
IB13
0
0
0
0
0
0
0
0
IB12
0
0
0
0
0
0
0
0
IB11
0
0
0
0
0
0
0
0
IB10
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB9
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB8
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB7
0
0
0
0
0
0
0
0
IB6
0
0
0
0
0
0
0
0
IB5
0
0
0
0
0
0
0
0
IB4
0
0
0
0
0
0
0
0
IB3
0
0
0
0
0
0
0
0
IB2
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB1
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB0
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB1
VRP01
VRN01
IB0
V R P 00
VRN00
Figure 7. 18 Gamma Control 1
PKP52–00: Gamma micro adjustment registers for the positive polarity output.
PRP12-00: Gradient adjustment registers for the positive polarity output.
PKN52-00: Gamma micro adjustment registers for the negative polarity output.
PRN12-00: Gradient adjustment registers for the negative polarity output.
Gamma Control 2 (R3Ah to R3Bh)
R/W
W
W
RS
1
1
IB15
0
0
IB14
0
0
IB13
0
0
IB12
VRP14
VRN14
IB11
VRP13
VRN13
IB10
VRP12
VRN12
IB9
VRP11
VRN11
IB8
VRP10
VRN10
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
VRP03
VRN03
IB2
VRP02
VRN02
Figure 7. 19 Gamma Control 2
VRP14-00: Adjustment registers for amplification adjustment of the positive polarity
output.
VRN14-00: Adjustment registers for the amplification adjustment of the negative polarity
output.
(Refer to Gamma Adjustment Function for details)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.30November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.4 Secondary Register Command Table
Reg
No.
Register
DISPLAY
INTERFACE
DISPLAY DATA
02h
CONTROL
ENTER
03h
MODE
GATE
04h
CONTROL 1
GATE
05h
CONTROL 2
DISPLAY
06h
CONTROL 1
DISPLAY
07h
CONTROL 2
POWER
09h
CONTROL 1
POWER
0ah
CONTROL 2
GAMMA
10h
CONTROL(1)
GAMMA
11h
CONTROL(1)
GAMMA
12h
CONTROL(1)
GAMMA
13h
CONTROL(1)
GAMMA
14h
CONTROL(1)
GAMMA
15h
CONTROL(1)
GAMMA
16h
CONTROL(1)
GAMMA
17h
CONTROL(1)
GAMMA
18h
CONTROL(1)
GAMMA
19h
CONTROL(1)
01h
IB15
IB14
IB13
IB12
IB11
IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
IM
0
0
0
0
0
0
0
REV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VPL
HPL
DPL
EPL
0
0
0
SS
0
0
0
0
0
0
STB
0
0
0
CLW1
CLW0
0
0
0
0
0
0
GAON
0
0
0
0
0
0
NW
0
DSC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VBP7
VBP6
VBP5
VBP4
VBP3
VBP2
VBP1
VBP0
0
0
0
0
0
0
HBP9
HBP8
HBP7
HBP6
HBP5
HBP4
HBP3
HBP2
HBP1
HBP0
MSEL
EXM
0
0
GON
0
POC
0
0
SAP2
SAP1
SAP0
0
0
0
0
0
0
0
VDV4
VDV3
VDV2
VDV1
VDV0
0
0
0
VCM4
VCM3
VCM2
VCM1
VCM0
0
0
0
0
0
PRP12
PRP11 PRP10
0
0
0
0
0
PRP02 PRP01 PRP00
0
0
0
0
0
PRN12
PRN11 PRN10
0
0
0
0
0
PRN02 PRN01 PRN00
0
0
0
VRP14 VRP13 VRP12
VRP11 VRP10
0
0
0
0
VRP03 VRP02 VRP01 VRP00
0
0
0
VRN14 VRN13 VRN12
VRN11 VRN10
0
0
0
0
VRN03 VRN02 VRN01 VRN00
0
0
0
0
0
PKP12
PKP11 PKP10
0
0
0
0
0
PKP02 PKP01 PKP00
0
0
0
0
0
PKP32
PKP31 PKP30
0
0
0
0
0
PKP22 PKP21 PKP20
0
0
0
0
0
PKP52
PKP51 PKP50
0
0
0
0
0
PKP42 PKP41 PKP40
0
0
0
0
0
PKN12
PKN11 PKN10
0
0
0
0
0
PKN02 PKN01 PKN00
0
0
0
0
0
PKN32
PKN31 PKN30
0
0
0
0
0
PKN22 PKN21 PKN20
0
0
0
0
0
PKN52
PKN51 PKN50
0
0
0
0
0
PKN42 PKN41 PKN40
Table 7. 17 Command Table
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.31November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.5 Secondary Register Default Value
Reg No.
R01h
R02h
R03h
R04h
R05h
Hex Code
0000
0000
0100
3000
5000
R06h
000A
R07h
0021
R09h
0A00
R0Ah
040F
R10h
R11h
0000
0000
R12h
0904
R13h
0904
R14h
R15h
R16h
R17h
R18h
R19h
0000
0407
0202
0505
0003
0707
Register Bit Value
IM=“0”, REV=“0”
VPL=“0”, HPL=“0”, DPL=“0”, EPL=“0”, SS=“1”, STB=“0”
CLW1=“1”, CLW0=“1”, GAON=“0”
NW=“1”, DSC=“1”
VBP7=“0”, VBP6=“0”, VBP5=“0”, VBP4=“0”, VBP3=“1”, VBP2=“0”, VBP1=“1”,
VBP0=“0”
HBP9=“0”, HBP8=“0”, HBP7=“0”, HBP6=“0”, HBP5=“1”, HBP4=“0”, HBP3=“0”,
HBP2=“0”, HBP1=“0”, HBP0=“1”
MSEL=“0”, EXM=“0”, GON=“1”, POC=“1”, SAP2=“0”, SAP1=“0”, SAP0=“0”
VDV4=“0”, VDV3=“0”, VDV2=“1”, VDV1=“0”, VDV0=“0”,VCM4=“0”, VCM3=“1”,
VCM2=“1”, VCM1=“1”, VCM0=“1”
PRP12=“0”, PRP11=“0”, PRP10=“0”, PRP02=“0”, PRP01=“0”, PRP00=“0”
PRN12=“0”, PRN11=“0”, PRN10=“0”, PRN02=“0”, PRN01=“0”, PRN00=“0”
VRP14=“0”, VRP13=“1”, VRP12=“0”, VRP11=“0”, VRP10=“1”, VRP03=“0”,
VRP02=“1”, VRP01=“0”, VRP00=“0”
VRN14=“0”, VRN13=“1”, VRN12=“0”, VRN11=“0”, VRN10=“1”, VRN03=“0”,
VRN02=“1”, VRN01=“0”, VRN00=“0”
PKP12=“0”, PKP11=“0”, PKP10=“0”, PKP02=“0”, PKP01=“0”, PKP00=“0”
PKP32=“1”, PKP31=“0”, PKP30=“0”, PKP22=“1”, PKP21=“1”, PKP20=“1”
PKP52=“0”, PKP51=“1”, PKP50=“0”, PKP42=“0”, PKP41=“1”, PKP40=“0”
PKN12=“1”, PKN11=“0”, PKN10=“1”, PKN02=“1”, PKN01=“0”, PKN00=“1”
PKN32=“0”, PKN31=“0”, PKN30=“0”, PKN32=“0”, PKN31=“1”, PKN30=“1”
PKN52=“1”, PKN51=“1”, PKN50=“1”, PKN42=“0”, PKN41=“1”, PKN40=“1”
Table 7. 18 Registers Default Value(Secondary Register Map)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.32November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.6 Secondary Regsiter Command Description
DISPLAY INTERFACE CONTROL (R01H)
R/W
W
RS
1
IB15
I M
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
REV
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 20 Display Interface Control Instruction
IM: Specify the PD data weight.
IM=“0”: 24bits interface
IM=“1“: 8bits interface
REV: Reverses all character and graphics display sections.
REV=“0”: Normally White Panel
REV=“1”: Normally Black Panel
REV
0
1
Data
6’b000000
︰
︰
6’b111111
6’b000000
︰
︰
6’b111111
Source Output Level of Displayed Area
Positive Polarity
Negative Polarity
V0
V63
︰
︰
︰
︰
V63
V0
V63
V0
︰
︰
︰
︰
V0
V63
Table 7. 19 REV Bit And Source Output Level Of Displayed Area
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.33November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
ENTRY MODE (R03H)
R/W
W
RS
1
IB15
VPL
IB14
HPL
IB13
DPL
IB12
EPL
IB11
0
IB10
0
IB9
0
IB8
S S
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
STB
IB0
0
Figure 7. 21 Entry Mode Instruction
VPL: Reverses the polarity of the VSYNC signal.
VPL=“0”: VSYNC is low active.
VPL=“1”: VSYNC is high active.
HPL: Reverses the polarity of the HSYNC signal.
HPL=“0”: HSYNC is low active.
HPL=“1”: HSYNC is high active.
DPL: Reverses the polarity of the DOTCLK signal.
DPL=“0”: Display data is fetched at rising edge of DOTCLK.
DPL=“1”: Display data is fetched at falling edge of DOTCLK.
EPL: Set the polarity of ENABLE pin while using DE interface mode.
EPL=“0”: DE=L write data, DE=H won’t write data.
EPL=“1”: DE=H write data, DE=L won’t write data.
SS: Selects the output shift direction of the source driver.
SS=“0”: S960S1
SS=“1”: S1S960
STB: Standby mode
STB=“1”: Standby mode (SD/GD/TCON/VCOM disable)
STB=“0”: Standby mode cancel
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.34November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
B
R G
B
R
B
R
R G
B
S960
R G
S959
R
B
G R
B
G
R
S3
G
S2
S3
B
S1
S2
R
S960
S1
B G
S959
R
S958
G
B
B
G
R
SS=0,RGB=01
SS=1,RGB=01
B
R G
S960
B
S958
G
S959
R
S958
B
S3
R G
S2
S3
B
S1
S2
R G
S960
B
S959
G
SS=0,RGB=00
S958
R
S1
SS=1,RGB=00
B G
G
Figure 7. 22 Display Direction According To SS, RGB
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.35November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
GATE CONTROL 1 (R04H)
R/W
W
RS
1
IB15
0
IB14
0
IB13
CLW1
IB12
C LW0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
0
IB6
0
IB5
GAON
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 23 Gate Control1 Instruction
Figure 7. 24 CLW Bits
CLW2-0: Specify the pulse output timing of the CKV and CKVB signal.
CLW1
0
0
1
1
CLW0
0
1
0
1
OEV
1.5us
3.0us
4.5us
6.0us
Note: The values indicate the number of clocks after the falling edge of CKV & CKVB.
Table 7. 20 CLW Bits Setting
GAON: Gate all on.
GAON=”0”, Gate all on disable.
GAON=”1”, Gate all on enable.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.36November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
GATE CONTROL2 (R05H)
R/W
W
RS
1
IB15
0
IB14
NW
IB13
0
IB12
DSC
IB11
0
IB10
0
IB9
0
IB8
0
IB7
0
IB6
0
IB5
0
IB4
0
IB3
0
IB2
0
IB1
0
IB0
0
IB5
VBP5
IB4
VBP4
IB3
VBP3
IB2
VBP2
IB1
VBP1
IB0
V B P0
Figure 7. 25 Gate Control2 Instruction
NW: Frame or line inversion selection
NW = “0”: Frame inversion.
NW = “1”: Line inversion.
DSC: Specify state of gate driver output signal.
DSC=“0”: Gate output disable, GOUT=VGL.
DSC=“1”: Gate output enable.
DISPLAY CONTROL1 (R06H)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
VBP7
IB6
VBP6
Figure 7. 26 Display Control1 Instruction
VBP7-0: Vertical back porch. (4H < VBP < 255H)
VBP7
0
0
0
0
0
VBP6
0
0
0
0
0
VBP5
0
0
0
0
0
VBP4
0
0
0
0
0
VBP3
0
0
0
0
0
VBP2
0
0
0
0
1
VBP1
0
0
1
1
0
VBP0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No. of clock cycle of HSYNC
Can’t set
Can’t set
Can’t set
Can’t set
4
:
Step = 1
:
252
253
254
255
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.37November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
DISPLAY CONTROL2 (R07H)
R/W
W
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
HBP9
IB8
HBP8
IB7
H BP7
IB6
HBP6
IB5
HBP5
IB4
HBP4
IB3
HBP3
IB2
HBP2
IB1
H BP1
IB0
H BP0
Figure 7. 27 Display Control2 Instruction
HBP9-0: Horizontal back porch. (8clock < HBP < 1023clock)
8clock < HBP of the Parallel RGB < 255clock
8clock < HBP of the Serial RGB < 1023clock
HBP9
HBP8
HBP7
HBP6
HBP5
HBP4
HBP3
HBP2
HBP1
HBP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
No. of Clock
Cycle
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
Can’t set
8
9
:
Step = 1
:
1022
1023
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.38November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
POWER CONTROL 1 (R09H)
R/W
W
RS
1
IB15
MSEL
IB14
EXM
IB13
0
IB12
0
IB11
GON
IB10
0
IB9
POC
IB8
0
IB7
0
IB6
SAP2
IB5
SAP 1
IB4
SAP0
IB3
0
IB2
0
IB1
0
IB0
0
Figure 7. 28 Power Control1 Instruction
MSEL: Select the polarity of POL.
MSEL=”0”: POL is in phase with internal VCOM.
MSEL=”1”: POL is reverse with internal VCOM.
EXM: VCOM enable selection.
EXM = “0”: VCOM circuit enable.
EXM = “1”: VCOM circuit disable, VCOMOUT floating.
GON: VCOM enable selection.
GON= “0”: VCOM circuit disable, VCOMOUT floating.
GON= “1”: VCOM circuit enable.
POC: Power control.
POC=“0”: SD output the white pattern.
POC=“1”: SD output the normal display.
SAP2-0: Set current amount of SD/Power circuit
SAP2
0
0
0
0
1
1
1
1
SAP1
0
0
1
1
0
0
1
1
SAP0
0
1
0
1
0
1
0
1
Amount of Current in SD/Power circuit
Standby mode(default)
Small
Small or medium
Medium
Medium or large
Large
Setting Inhibited
Setting Inhibited
Table 7. 21 SAP Bits Setting
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.39November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Power Control(R0 Ah)
R/W
W
RS
1
IB 15
0
IB14
0
IB13
0
IB12
VDV4
IB11
VDV3
IB10
VDV2
IB9
VDV1
IB8
VDV0
IB7
0
IB6
0
IB5
0
IB4
VCM4
IB3
VCM3
IB2
VCM2
IB1
VCM1
IB0
VCM 0
Figure 7. 29 Power Control
VDV4-0: Set the alternating amplitudes of VCOM at the VCOM alternating drive.
These bits amplify VCOM amplitude 0.7875 to 1.2525 times the VLCD63
voltage. External voltage at VCOMR is referenced when VDV = “01111xx”.
VDV4
0
0
0
0
VDV3
0
0
0
0
VDV2
0
0
0
0
VDV1
0
0
1
1
VDV0
0
1
0
1
1
0
0
1
*
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
VCOM Amplitude
VLCD63 x 0.7875
VLCD63 x 0.8025
VLCD63 x 0.8175
VLCD63 x 0.8325
:
Step = 0.0150
:
Setting inhibited
:
Step = 0.0150
:
VLCD63 x 1.2225
VLCD63 x 1.2375
VLCD63 x 1.2525
Table 7. 22 VCOM Amplitude
VCM4-0: Set the VCOMH voltage if nOTP=“1”. These bits amplify the VCOMH
voltage 0.68 to 0.990 times the VLCD63 voltage.
VCM4
0
0
0
0
0
VCM3
0
0
0
0
0
VCM2
0
0
0
0
1
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
Note: 2V < VCOMH < VLCD63
VCM 1
0
0
1
1
0
VCM0
0
1
0
1
0
0
0
1
1
0
1
0
1
VCOMH
VLCD63 x 0.680
VLCD63 x 0.690
VLCD63 x 0.700
VLCD63 x 0.710
VLCD63 x 0.720
:
Step = 0.010
:
VLCD63 x 0.96 0
VLCD63 x 0.970
VLCD63 x 0.98 0
VLCD63 x 0.99 0
Table 7. 23 VCOMH
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.40November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Gamma Control 1 (R10h to R11h and R14h to R19h)
R/W
W
W
W
W
W
W
W
W
RS
1
1
1
1
1
1
1
1
IB15
0
0
0
0
0
0
0
0
IB14
0
0
0
0
0
0
0
0
IB13
0
0
0
0
0
0
0
0
IB12
0
0
0
0
0
0
0
0
IB11
0
0
0
0
0
0
0
0
IB10
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB9
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB8
PKP1
PKP3
PKP5
PRP1
PKN1
PKN3
PKN5
PRN1
IB7
0
0
0
0
0
0
0
0
IB6
0
0
0
0
0
0
0
0
IB5
0
0
0
0
0
0
0
0
IB4
0
0
0
0
0
0
0
0
IB3
0
0
0
0
0
0
0
0
IB2
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB1
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB0
PKP0
PKP2
PKP4
PRP0
PKN0
PKN2
PKN4
PRN0
IB2
VRP02
VRN02
IB1
VRP01
VRN01
IB0
VR P00
VR N 00
Figure 7. 30 Gamma Control 1
PKP52-00: Gamma micro adjustment registers for the positive polarity output
PRP12-00: Gradient adjustment registers for the positive polarity output
PKN52-00: Gamma micro adjustment registers for the negative polarity output
PRN12-00: Gradient adjustment registers for the negative polarity output
Gamma Control 2 (R12h to R13h)
R/W
W
W
RS
1
1
IB15
0
0
IB14
0
0
IB13
0
0
IB12
VRP14
VRN14
IB11
VRP13
VRN13
IB10
V RP12
VRN12
IB9
VRP11
VRN11
IB8
VRP10
VRN10
IB7
0
0
IB6
0
0
IB5
0
0
IB4
0
0
IB3
VRP03
VRN03
Figure 7. 31 Gamma Control 2
VRP14-00: Adjustment registers for amplification adjustment of the positive polarity
output.
VRN14-00: Adjustment registers for the amplification adjustment of the negative
polarity output.
(Refer to Gamma Adjustment Function for details)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.41November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
7.7 Power Up/Down Sequence of the Secondary Register Command
When set to Secondary Register command and CPE=VSS, the charge pump circuit
will not enable and the VCIX2, VGH, VGL need to external input.
VCOM can be selected to internal generation or external input by setting register
R09h EXM or GON, it needs set both EXM=0 and GON=1, VCOM will be internal
generated. If each EXM=1 or GON=0, then VCOM circuit will be disabled, and VCOM
need to be external input.
Please follow the recommend power up/down sequence as below steps:
(Set VCOM is external inputed.)
System Power On
At least 5ms
Power On Reset Display off State
R09
0000h
Power Setting Function 1
R09
R0A
4000h
2000h
Power Setting Function 2
R09
4055h
R01
R02
R03
R04
R05
R06
R07
R08
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
409Dh
0204h
0100h
3000h
4003h
000Ah
0021h
0C00h
0103h
0301h
1F0Fh
1F0Fh
0707h
0307h
0707h
0000h
0004h
0000h
More than 10ms
More than 50ms
Instruction Setting
Wait more than 2 Frames
R09
R05
4A55h
5003h
Display On Sequence
Display ON
Figure 7. 32 Power Up Sequence when SPSW connect to VSS (CPE = VSS)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.42November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Normal Display
Wait more than 2 Frames
<Display off sequence>
R09 ← 4055 h
R05 ← 4003 h
Power down setting 1
R0A ← 0000h
Wait at least 1ms
R09 ← 4000h
Power down setting 2
Power Off
Figure 7. 33 Power Down Sequence when SPSW connect to VSS (CPE = VSS)
When set to Secondary register command and CPE=VDDIO, the charge pump circuit
will enable and the VCIX2, VGH, VGL, VCOM will internal generation.
Please follow the power up/down sequence as Figure 12.10 and Figure 12.11.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.43November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
8. OTP Programming
OTP Write Sequence
Step
Operation
Power up the module. Set nOTP=1 and find out the appropriate value of VCM[6:0] and
1
power off the system
2
Power up the system with VDD=VDDIO=2.5V. If REGVDD=1, set R0Dh=16’h0324.
3
Set appropriate values found from step 1 to register of VCOM (R1Eh)
4
Set R06h=16’h2820 to stop VGH/VGL pumping. Wait 0.5s.
5
Set R60h=16’h8000
6
Set R60h=16’hC000
7
Connect 7.3V to VGH and 0V to VGL (Note1)
8
Set R60h=16’hC200
9
Set R60h=16’hC280
10
Wait 200us for completing this program
11
Set R60h=16’hC200
12
Remove 7.5V from VGH and 0V from VGL
13
Set R60h=16’h8200
14
Set R60h=16’h0200
15
Set R60h=16’h0040
16
Set R60h=16’h0000
Note1: VGH is connected to 7.1~7.4
Table 8. 1 OTP Programming Sequence
You can use above programming sequence to set VCM[6:0] value to OTP cell twice.
If you want to check if the OTP cell is still available for programming, you can read the
status from R61h shown below.
R/W
R
RS
1
IB15
0
IB14
0
IB13
0
IB12
0
IB11
0
IB10
0
IB9
0
IB8
0
IB7
IND
IB6
VCM6
IB5
VCM5
IB4
VCM4
IB3
VCM3
IB2
VCM2
IB1
VCM1
IB0
VCM 0
Figure 8. 1 OTP Read Table
You can check the IND bit to see if the VCM[6:0] is still programmable or not. If
IND=0, you can program new VCM[6:0] value to OTP. If IND=1, it means that the
OTP cell have already programmed twice and you can’t program it any more.
IB6~IB0 indicate the currently effective VCM[6:0] setting in OTP cell.
OTP Programming circuitry
Apply voltage at Step (7)
HX8238-D
V GH
V GL
+
GND
Note: C = 1uF
(built -in on the module)
C
+
-
-
GND
7.3 V
GND
Figure 8. 2 OTP Programming Circuitry
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.44November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
9. Gamma Adjustment Function
The HX8238-D incorporates gamma adjustment function for the 262K-color display.
Gamma adjustment is implemented by deciding the 8-grayscale levels with angle
adjustment and micro adjustment register. Also, angle adjustment and micro
adjustment is fixed for each of the internal positive and negative polarity. Set up by
the liquid crystal panel’s specification.
RGB Interface
Display Data
R5 R4 R3 R2 R1 R0 G5 G4G3G2 G1G0 B5 B4 B3 B2 B1 B0
PKP02 PKP01PKP00
Positive
polarity
register
PKP12 PKP11 PKP10
PKP22 PKP21 PKP20
PKP32 PKP31 PKP30
V0
PKP42 PKP41 PKP40
PKP52 PKP51 PKP50
PRP02PRP01PRP00
PRP12 PRP11PRP10
8-LEVELS
6-bits
64- LEVELS
Grayscale
amplifier
VRP03 VRP02 VRP01VRP00
VRP14VRP13 VRP12 VRP11VRP10
6-bits
6-bits
64 grayscale
Control<R>
64 grayscale
Control<R>
64 grayscale
Control<R>
LCD Driver
LCD Driver
LCD Driver
V63
PKN02 PKN01PKN00
Negative
polarity
register
PKN12 PKN11 PKN10
PKN22 PKN21PKN20
PKN32 PKN31PKN30
PKN42 PKN41PKN40
R
G
B
PKN52 PKN51PKN50
PRN02 PRN01 PRN00
LCD
PRN12 PRN11 PRN10
VRN03 VRN02 VRN01 VRN00
VRN14 VRN13 VRN12 VRN11 VRN10
Figure 9. 1 Grayscale Control Block
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.45November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
9.1 Structure of Grayscale Amplifier
Below figure indicates the structure of the grayscale amplifier. It determines 8 levels
(VIN0-VIN7) by the gradient adjuster and the micro adjustment register. Also, dividing
these levels with ladder resistors generates V0 to V63.
Gradient
Adjustment register
VLCD63
PRP0
3
PRP1
3
Micro adjustment register
PKP0 PKP1
3
3
PKP2
PKP3
3
Amplitude
Adjustment register
PKP4
PKP5
VRP0
3
3
4
3
VRP1
5
VINP0
V0
VINP1
8 to 1
selector
V1
:
V7
VINP2
Ladder res is tor
VINP3
8 to 1
selector
VINP4
8 to 1
selector
Gray scale Amplifier
8 to 1
selector
V8
:
V19
V20
:
V42
V43
:
V54
VINP5
8 to 1
selector
V55
:
V61
VINP6
8 to 1
selector
VINP7
*
V62
:
V63
Individual ladder resistors are used for positive and
negative polarity.
EXVR
Figure 9. 2 Grayscale Amplifier
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.46November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
VLCD63
VRP0[3:0]
0 to 30R
VRP0
VINP0
KVP0
5R
PKP0[2:0]
RP0
KVP1
KVP2
KVP3
KVP4
8 to 1
KVP5
selector
KVP6
KVP7
KVP8
RP1
RP2
RP3
RP4
RP5
RP6
RP7
4Rx7
0 to 28R
VRHP
PRP0[2:0]
VRN0[3:0]
0 to 30R
VRN0
5R
PKN0[2:0]
RN0
KVN1
KVN2
KVN3
KVN4
8 to 1
KVN5
selector
KVN6
KVN7
KVN8
RN1
RN2
RN3
RN4
RN5
RN6
RN7
VINP1
4Rx7
PKP1[2:0]
0 to 28R
VRHN
PRN0[2:0]
KVP9
RP8
RP9
1Rx7
5R
RN8
KVN10
RP10
KVP11
KVP12
RN9
RN10
KVN11
KVN12
RP11
RP12
KVP13
KVP14
RN11
RN12
KVN13
KVN14
RP13
KVP15
RP14
KVP16
8 to 1
VINP2
1R
selector
RN14
PKP2[2:0]
5R
16R
RP18
RP19
KVP20
PKN2 [2:0]
KVN17
8 to 1
VINP3
1Rx7
RN16
RN17
KVN18
KVN19
RN18
KVN20
RN19
RN20
KVN21
KVN22
RP20
RP21
KVP23
RN21
KVN23
RP22
KVP24
RN22
KVN24
selector
PKP3[2:0]
RP23
16R
1R x7
RP26
RP27
KVP28
RP28
RP29
RP30
5R
1R x7
0 to 28R
VRLP
RN26
KVN28
RN27
RN28
KVN29
KVN30
KVP31
RN29
KVN31
KVP32
RN30
KVN32
RP32
KVP33
KVP34
RP33
KVP35
RP34
RP35
KVP36
KVP37
RP36
KVP38
RP37
RP38
KVP39
KVP40
8 to 1
VINP4
1Rx7
selector
8 to 1
selector
PRP1[2:0]
VINP5
PKP5[2:0]
5R
1Rx7
0 to 28R
VRLN
4R x7
5R
0 to 31R
VRP1
8R
RN32
KVN33
KVN34
RN33
KVN35
RN34
RN35
KVN36
KVN37
RN36
KVN38
RN37
RN38
KVN39
KVN40
8 to 1
selector
PRN1[2:0]
VINN4
VINN5
PKN5 [2:0]
KVN41
KVP42
RN39
KVN42
RP41
KVP43
KVP44
RN40
RN41
KVN43
KVN44
RP42
RP43
KVP45
KVP46
RN42
RN43
KVN45
KVN46
RP44
KVP47
RN44
KVN47
RP45
KVP48
RN45
KVN48
8 to 1
VINP6
4Rx7
selector
RP46
VINP7
VRP 1[4:0]
R P4 7
8 to 1
selector
PKN4 [2:0]
RN31
KVP41
RP39
RP40
PKN3 [2:0]
KVN26
KVN27
PKP4[2:0]
RP31
VINN3
KVN25
RN24
RN25
KVP29
KVP30
8 to 1
selector
RN23
KVP25
KVP26
KVP27
VINN2
KVN16
KVP21
KVP22
RP24
RP25
8 to 1
selector
RN15
KVP17
1Rx7
PKN1 [2:0]
RN13
RP15
KVP18
KVP19
VINN1
KVN9
KVP10
RP16
RP1 7
VINN0
KVN 0
5R
0 to 31R
VRN1 8R
8 to 1
VINN6
selector
RN46
VINN7
VRN 1[4:0]
RN47
EXVR
Figure 9. 3 Resistor Ladder for Gamma Voltages Generation
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.47November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
9.2 Gamma Adjustment Register
This block is the register to set up the grayscale voltage adjusting to the gamma
specification of the LCD panel. This register can independent set up to
positive/negative polarities and there are three types of register groups to adjust
gradient, amplitude, and micro-adjustment on number of the grayscale,
characteristics of the grayscale voltage. (Use the same setting of Reference-value
and R.G. B.) Following graphics indicates the operation of each adjusting register.
Figure 9. 4 Gamma Adjustment Function
9.2.1 Gradient Adjusting Register
The gradient-adjusting resistor is to adjust around middle gradient, specification of
the grayscale number and the grayscale voltage without changing the dynamic range.
To accomplish the adjustment, it controls the variable resistors in the middle of the
ladder resistor by registers (PRP(N)0 / PRP(N)1) for the grayscale voltage generator.
Also, there is an independent resistor on the positive/negative polarities in order for
corresponding to asymmetry drive.
9.2.2 Amplitude Adjusting Register
The amplitude-adjusting resistor is to adjust amplitude of the grayscale voltage. To
accomplish the adjustment, it controls the variable resistors in the boundary of the
ladder resistor by registers (VRP(N)0 / VRP(N)1) for the grayscale voltage generator.
Also, there is an independent resistor on the positive/negative polarities as well as
the gradient-adjusting resistor.
9.2.3 Micro Adjusting Register
The micro-adjusting register is to make subtle adjustment of the grayscale voltage
level. To accomplish the adjustment, it controls each reference voltage level by the 8
to 1 selector towards the 8-level reference voltage generated from the ladder resistor.
Also, there is an independent resistor on the positive/negative polarities as well as
other adjusting resistors.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.48November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
9.3 Ladder Resistor / 8 to 1 Selector
This block outputs the reference voltage of the grayscale voltage. There are two
ladder resistors including the variable resistor and the 8 to 1 selector selecting
voltage generated by the ladder resistor. The gamma registers control the variable
resistors and 8 to 1 selector resistors. Also, there has pin (EXVR) that can be
connected to VSS or an external variable resistor for compensating the dispersion of
length between both panels.
Variable Resistor
There are 3 types of the variable resistors that are for the gradient and amplitude
adjustment. The resistance is set by the resistor (PRP(N)0 / PRP(N)1) and (VRP(N)0
/ VRP(N)1) as below.
PRP(N)[0:1]
000
001
010
011
100
101
110
111
Resistance
0R
4R
8R
12R
16R
20R
24R
28R
VRP(N)0
0000
0001
0010
Resistance
0R
2R
4R
VRP(N)1
00000
00001
00010
:
Step = 2R
:
1110
1111
Table 9. 1 PRP(N)
Resistance
0R
1R
2R
:
Step = 1R
:
11110
30R
11111
31R
28R
30R
Table 9. 2 VRP(N)0
Table 9. 3 VRP(N)1
8 to 1 Selector
In the 8 to 1 selector, a reference voltage VIN can be selected from the levels which
are generated by the ladder resistors. There are six types of reference voltage (VIN1
to VIN6) and totally 48 divided voltages can be selected in one ladder resistor.
Following figure explains the relationship between the micro adjusting register and
the selecting voltage.
Register
PKP[2:0]
000
001
010
011
100
101
110
111
Positive polarity
Selected voltage
VINP1
KVP1
KVP2
KVP3
KVP4
KVP5
KVP6
KVP7
KVP8
VINP2
KVP9
KVP10
KVP11
KVP12
KVP13
KVP14
KVP15
KVP16
VINP3
KVP17
KVP18
KVP19
KVP20
KVP21
KVP22
KVP23
KVP24
VINP4
KVP25
KVP26
KVP27
KVP28
KVP29
KVP30
KVP31
KVP32
VINP5
KVP33
KVP34
KVP35
KVP36
KVP37
KVP38
KVP39
KVP40
VINP6
KVP41
KVP42
KVP43
KVP44
KVP45
KVP46
KVP47
KVP48
Register
PKN[2:0]
000
001
010
011
100
101
110
111
Negative polarity
Selected voltage
VINN1
KVN1
KVN2
KVN3
KVN4
KVN5
KVN6
KVN7
KVN8
VINN2
KVN9
KVN10
KVN11
KVN12
KVN13
KVN14
KVN15
KVN16
VINN3
KVN17
KVN18
KVN19
KVN20
KVN21
KVN22
KVN23
KVN24
VINN4
KVN25
KVN26
KVN27
KVN28
KVN29
KVN30
KVN31
KVN32
VINN5
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
VINN6
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
Table 9. 4 PKP and PKN
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.49November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Grayscale
voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
V32
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
V43
V44
V45
V46
V47
V48
V49
V50
V51
V52
V53
V54
V55
V56
V57
V58
V59
V60
V61
V62
V63
Positive Polarity
Negative Polarity
VINP0
VINP1
V8+(V1-V8)*(2241/2703)
V8+(V1-V8)*(1671/2703)
V8+(V1-V8)*(1209/2703)
V8+(V1-V8)*(849/2703)
V8+(V1-V8)*(567/2703)
V8+(V1-V8)*(294/2703)
VINP2
V20+(V8-V20)*(1533/1767)
V20+(V8-V20)*(1356/1767)
V20+(V8-V20)*(1188/1767)
V20+(V8-V20)*(993/1767)
V20+(V8-V20)*(843/1767)
V20+(V8-V20)*(693/1767)
V20+(V8-V20)*(543/1767)
V20+(V8-V20)*(441/1767)
V20+(V8-V20)*(336/1767)
V20+(V8-V20)*(213/1767)
V20+(V8-V20)*(81/1767)
VINP3
V43+(V20-V43)*(1887/1965)
V43+(V20-V43)*(1779/1965)
V43+(V20-V43)*(1653/1965)
V43+(V20-V43)*(1536/1965)
V43+(V20-V43)*(1437/1965)
V43+(V20-V43)*(1362/1965)
V43+(V20-V43)*(1278/1965)
V43+(V20-V43)*(1191/1965)
V43+(V20-V43)*(1098/1965)
V43+(V20-V43)*(1008/1965)
V43+(V20-V43)*(927/1965)
V43+(V20-V43)*(843/1965)
V43+(V20-V43)*(750/1965)
V43+(V20-V43)*(678/1965)
V43+(V20-V43)*(612/1965)
V43+(V20-V43)*(528/1965)
V43+(V20-V43)*(450/1965)
V43+(V20-V43)*(375/1965)
V43+(V20-V43)*(303/1965)
V43+(V20-V43)*(222/1965)
V43+(V20-V43)*(147/1965)
V43+(V20-V43)*(87/1965)
VINP4
V55+(V43-V55)*(936/1014)
V55+(V43-V55)*(867/1014)
V55+(V43-V55)*(792/1014)
V55+(V43-V55)*(723/ 1014)
V55+(V43-V55)*(648/1014)
V55+(V43-V55)*(561/1014)
V55+(V43-V55)*(465/1014)
V55+(V43-V55)*(387/1014)
V55+(V43-V55)*(291/1014)
V55+(V43-V55)*(201/1014)
V55+(V43-V55)*(111/1014)
VINP5
V62+(V55-V62)*(1218/1317)
V62+(V55-V62)*(1092/1317)
V62+(V55-V62)*(936/1317)
V62+(V55-V62)*(774/1317)
V62+(V55-V62)*(579/1317)
V62+(V55-V62)*(324/1317)
VINP6
VINP7
VINN7
VINN6
V1+(V8-V1)*(462/2703)
V1+(V8-V1)*(1032/2703)
V1+(V8-V1)*(1494/2703)
V1+(V8-V1)*(1854/2703)
V1+(V8-V1)*(2136/2703)
V1+(V8-V1)*(2409/2703)
VINN5
V8+(V20-V8)*(234/1767)
V8+(V20-V8)*(411/1767)
V8+(V20-V8)*(579/1767)
V8+(V20-V8)*(774/1767)
V8+(V20-V8)*(924/1767)
V8+(V20-V8)*(1074/1767)
V8+(V20-V8)*(1224/1767)
V8+(V20-V8)*(1326/1767)
V8+(V20-V8)*(1431/1767)
V8+(V20-V8)*(1554/1767)
V8+(V20-V8)*(1686/1767)
VINN4
V20+(V43-V20)*(78/1965)
V20+(V43-V20)*(186/1965)
V20+(V43-V20)*(312/1965)
V20+(V43-V20)*(429/1965)
V20+(V43-V20)*(528/1965)
V20+(V43-V20)*(603/1965)
V20+(V43-V20)*(687/1965)
V20+(V43-V20)*(774/1965)
V20+(V43-V20)*(867/1965)
V20+(V43-V20)*(957/1965)
V20+(V43-V20)*(1038/1965)
V20+(V43-V20)*(1122/1965)
V20+(V43-V20)*(1215/1965)
V20+(V43-V20)*(1287/1965)
V20+(V43-V20)*(1353/1965)
V20+(V43-V20)*(1437/1965)
V20+(V43-V20)*(1515/1965)
V20+(V43-V20)*(1590/1965)
V20+(V43-V20)*(1662/1965)
V20+(V43-V20)*(1743/1965)
V20+(V43-V20)*(1818/1965)
V20+(V43-V20)*(1878/1965)
VINN3
V43+(V55-V43)*(78/1014)
V43+(V55-V43)*(147/1014)
V43+(V55-V43)*(222/1014)
V43+(V55-V43)*(291/1014)
V43+(V55-V43)*(366/1014)
V43+(V55-V43)*(453/1014)
V43+(V55-V43)*(549/1014)
V43+(V55-V43)*(627/1014)
V43+(V55-V43)*(723/1014)
V43+(V55-V43)*(813/1014)
V43+(V55-V43)*(903/1014)
VINN2
V55+(V62-V55)*(99/1317)
V55+(V62-V55)*(225/1317)
V55+(V62-V55)*(381/1317)
V55+(V62-V55)*(543/1317)
V55+(V62-V55)*(738/1317)
V55+(V62-V55)*(993/1317)
VINN1
VINN0
Table 9. 5 Grayscale Voltages Formulas
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.50November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Reference
Formula
Micro-adjusting
register
Reference voltage
KVP0
VLCD63 - Δ V x VRP0 / SUMRP
KVP1
VLCD63 - Δ V x (VRP0 + 5R) / SUMRP
PKP0[2:0] = ”000”
KVP2
VLCD63 - Δ V x (VRP0 + 9R) / SUMRP
PKP0[2:0] = ”001”
KVP3
VLCD63 - Δ V x (VRP0 + 13R) / SUMRP
PKP0[2:0] = ”010”
KVP4
VLCD63 - Δ V x (VRP0 + 17R) / SUMRP
PKP0[2:0] = ”011”
KVP5
VLCD63 - Δ V x (VRP0 + 21R) / SUMRP
PKP0[2:0] = ”100”
KVP6
VLCD63 - Δ V x (VRP0 + 25R) / SUMRP
PKP0[2:0] = ”101”
KVP7
VLCD63 - Δ V x (VRP0 + 29R) / SUMRP
PKP0[2:0] = ”110”
KVP8
VLCD63 - Δ V x (VRP0 + 33R) / SUMRP
PKP0[2:0] = ”111”
KVP9
VLCD63 - Δ V x (VRP0 + 33R + VRHP) / SUMRP
PKP1[2:0] = ”000”
KVP10
VLCD63 - Δ V x (VRP0 + 34R + VRHP) / SUMRP
PKP1[2:0] = ”001”
KVP11
VLCD63 - Δ V x (VRP0 + 35R + VRHP) / SUMRP
PKP1[2:0] = ”010”
KVP12
VLCD63 - Δ V x (VRP0 + 36R + VRHP) / SUMRP
PKP1[2:0] = ”011”
KVP13
VLCD63 - Δ V x (VRP0 + 37R + VRHP) / SUMRP
PKP1[2:0] = ”100”
KVP14
VLCD63 - Δ V x (VRP0 + 38R + VRHP) / SUMRP
PKP1[2:0] = ”101”
KVP15
VLCD63 - Δ V x (VRP0 + 39R + VRHP) / SUMRP
PKP1[2:0] = ”110”
KVP16
VLCD63 - Δ V x (VRP0 + 40R + VRHP) / SUMRP
PKP1[2:0] = ”111”
KVP17
VLCD63 - Δ V x (VRP0 + 45R + VRHP) / SUMRP
PKP2[2:0] = ”000”
KVP18
VLCD63 - Δ V x (VRP0 + 46R + VRHP) / SUMRP
PKP2[2:0] = ”001”
KVP19
VLCD63 - Δ V x (VRP0 + 47R + VRHP) / SUMRP
PKP2[2:0] = ”010”
KVP20
VLCD63 - Δ V x (VRP0 + 48R + VRHP) / SUMRP
PKP2[2:0] = ”011”
KVP21
VLCD63 - Δ V x (VRP0 + 49R + VRHP) / SUMRP
PKP2[2:0] = ”100”
KVP22
VLCD63 - Δ V x (VRP0 + 50R + VRHP) / SUMRP
PKP2[2:0] = ”101”
KVP23
VLCD63 - Δ V x (VRP0 + 51R + VRHP) / SUMRP
PKP2[2:0] = ”110”
KVP24
VLCD63 - Δ V x (VRP0 + 52R + VRHP) / SUMRP
PKP2[2:0] = ”111”
KVP25
VLCD63 - Δ V x (VRP0 + 68R + VRHP) / SUMRP
PKP3[2:0] = ”000”
KVP26
VLCD63 - Δ V x (VRP0 + 69R + VRHP) / SUMRP
PKP3[2:0] = ”001”
KVP27
VLCD63 - Δ V x (VRP0 + 70R + VRHP) / SUMRP
PKP3[2:0] = ”010”
KVP28
VLCD63 - Δ V x (VRP0 + 71R + VRHP) / SUMRP
PKP3[2:0] = ”011”
KVP29
VLCD63 - Δ V x (VRP0 + 72R + VRHP) / SUMRP
PKP3[2:0] = ”100”
KVP30
VLCD63 - Δ V x (VRP0 + 73R + VRHP) / SUMRP
PKP3[2:0] = ”101”
KVP31
VLCD63 - Δ V x (VRP0 + 74R + VRHP) / SUMRP
PKP3[2:0] = ”110”
KVP32
VLCD63 - Δ V x (VRP0 + 75R + VRHP) / SUMRP
PKP3[2:0] = ”111”
KVP33
VLCD63 - Δ V x (VRP0 + 80R + VRHP) / SUMRP
PKP4[2:0] = ”000”
KVP34
VLCD63 - Δ V x (VRP0 + 81R + VRHP) / SUMRP
PKP4[2:0] = ”001”
KVP35
VLCD63 - Δ V x (VRP0 + 82R + VRHP) / SUMRP
PKP4[2:0] = ”010”
KVP36
VLCD63 - Δ V x (VRP0 + 83R + VRHP) / SUMRP
PKP4[2:0] = ”011”
KVP37
VLCD63 - Δ V x (VRP0 + 84R + VRHP) / SUMRP
PKP4[2:0] = ”100”
KVP38
VLCD63 - Δ V x (VRP0 + 85R + VRHP) / SUMRP
PKP4[2:0] = ”101”
KVP39
VLCD63 - Δ V x (VRP0 + 86R + VRHP) / SUMRP
PKP4[2:0] = ”110”
KVP40
VLCD63 - Δ V x (VRP0 + 87R + VRHP) / SUMRP
PKP4[2:0] = ”111”
KVP41
VLCD63 - Δ V x (VRP0 + 87R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”000”
KVP42
VLCD63 - Δ V x (VRP0 + 91R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”001”
KVP43
VLCD63 - Δ V x (VRP0 + 95R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”010”
KVP44
VLCD63 - Δ V x (VRP0 + 99R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”011”
KVP45
VLCD63 - Δ V x (VRP0 + 103R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”100”
KVP46
VLCD63 - Δ V x (VRP0 + 107R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”101”
KVP47
VLCD63 - Δ V x (VRP0 + 111R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”110”
KVP48
VLCD63 - Δ V x (VRP0 + 115R + VRHP + VRLP) / SUMRP
PKP5[2:0] = ”111”
KVP49
VLCD63 - Δ V x (VRP0 + 120R + VRHP + VRLP) / SUMRP
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1
Δ V: Voltage difference between VLCD63 and of EXVR.
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
Table 9. 6 Reference Voltages of Positive Polarity
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.51November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Reference
KVN0
KVN1
KVN2
KVN3
KVN4
KVN5
KVN6
KVN7
KVN8
KVN9
KVN10
KVN11
KVN12
KVN13
KVN14
KVN15
KVN16
KVN17
KVN18
KVN19
KVN20
KVN21
KVN22
KVN23
KVN24
KVN25
KVN26
KVN27
KVN28
KVN29
KVN30
KVN31
KVN32
KVN33
KVN34
KVN35
KVN36
KVN37
KVN38
KVN39
KVN40
KVN41
KVN42
KVN43
KVN44
KVN45
KVN46
KVN47
KVN48
KVN49
Formula
VLCD63 - Δ V x VRN0 / SUMRN
VLCD63 - Δ V x (VRN0 + 5R) / SUMRN
VLCD63 - Δ V x (VRN0 + 9R) / SUMRN
VLCD63 - Δ V x (VRN0 + 13R) / SUMRN
VLCD63 - Δ V x (VRN0 + 17R) / SUMRN
VLCD63 - Δ V x (VRN0 + 21R) / SUMRN
VLCD63 - Δ V x (VRN0 + 25R) / SUMRN
VLCD63 - Δ V x (VRN0 + 29R) / SUMRN
VLCD63 - Δ V x (VRN0 + 33R) / SUMRN
VLCD63 - Δ V x (VRN0 + 33R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 34R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 35R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 36R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 37R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 38R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 39R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 40R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 45R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 46R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 47R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 48R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 49R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 50R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 51R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 52R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 68R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 69R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 70R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 71R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 72R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 73R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 74R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 75R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 80R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 81R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 82R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 83R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 84R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 85R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 86R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 87R + VRHN) / SUMRN
VLCD63 - Δ V x (VRN0 + 87R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 91R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 95R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 99R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 103R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 107R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 111R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 115R + VRHN + VRLN) / SUMRN
VLCD63 - Δ V x (VRN0 + 120R + VRHN + VRLN) / SUMRN
Micro-adjusting
register
Reference voltage
-
VINN0
PKN0[2:0] = ”000”
PKN0[2:0] = ”001”
PKN0[2:0] = ”010”
PKN0[2:0] = ”011”
PKN0[2:0] = ”100”
PKN0[2:0] = ”101”
PKN0[2:0] = ”110”
PKN0[2:0] = ”111”
PKN1[2:0] = ”000”
PKN1[2:0] = ”001”
PKN1[2:0] = ”010”
PKN1[2:0] = ”011”
PKN1[2:0] = ”100”
PKN1[2:0] = ”101”
PKN1[2:0] = ”110”
PKN1[2:0] = ”111”
PKN2[2:0] = ”000”
PKN2[2:0] = ”001”
PKN2[2:0] = ”010”
PKN2[2:0] = ”011”
PKN2[2:0] = ”100”
PKN2[2:0] = ”101”
PKN2[2:0] = ”110”
PKN2[2:0] = ”111”
PKN3[2:0] = ”000”
PKN3[2:0] = ”001”
PKN3[2:0] = ”010”
PKN3[2:0] = ”011”
PKN3[2:0] = ”100”
PKN3[2:0] = ”101”
PKN3[2:0] = ”110”
PKN3[2:0] = ”111”
PKN4[2:0] = ”000”
PKN4[2:0] = ”001”
PKN4[2:0] = ”010”
PKN4[2:0] = ”011”
PKN4[2:0] = ”100”
PKN4[2:0] = ”101”
PKN4[2:0] = ”110”
PKN4[2:0] = ”111”
PKN5[2:0] = ”000”
PKN5[2:0] = ”001”
PKN5[2:0] = ”010”
PKN5[2:0] = ”011”
PKN5[2:0] = ”100”
PKN5[2:0] = ”101”
PKN5[2:0] = ”110”
PKN5[2:0] = ”111”
-
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1
Δ V: Voltage difference between VLCD63 and of EXVR.
Table 9. 7 Reference Voltages of Negative Polarity
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.52November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
10. Maximum Rating
Maximum Ratings (Voltage Referenced to VSS)
Symbol
VDD
VDDIO
VCI
I
TA
Tstg
Ron
Parameter
Supply Voltage
Input Voltage
Current Drain Per Pin Excluding VDD and VSS
Operating Temperature
Storage Temperature
Input Resistance
Table 10. 1 Maximum Ratings
Value
-0.3 to +2.7
-0.3 to +4.0
VSS - 0.3 to 5.0
25
-30 to +85
-65 to +150
TBD
Unit
V
V
V
mA
℃
℃

Maximum ratings are those values beyond which damages to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Description section.
This device contains circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions to be taken
to avoid application of any voltage higher than maximum rated voltages to this high
impedance circuit. For proper operation it is recommended that VCI and VOUT be
constrained to the range VSS < VDDIO ≤
VCI < VOUT.
Reliability of operation is enhanced if unused input is connected to an appropriate
logic voltage level (e.g., either VSS or VDDIO).
Unused outputs must be left open. This device may be light sensitive. Caution should
be taken to avoid exposure of this device to any light source during normal operation.
This device is not radiation protected.
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.53November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
11. DC Characteristics
DC Characteristics
(Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 2.2V, TA = 25℃)
Symbol
VDD
VDDIO
VCI
Isleep
Idp
VCIM
VCIX2
Parameter
System power supply pins of the
logic block
Power supply pin of IO pins
Booster Reference Supply Voltage
Range
Sleep mode current
Operating mode current
Negative VCI Output Voltage
Test condition
Recommend Operating Voltage
Possible Operating Voltage
Recommend Operating Voltage
Possible Operating Voltage
Recommend Operating Voltage
Possible Operating Voltage
VCI=3.3V
No panel loading
No panel loading, ITO for VCIX2,
(1)
VCIX2 primary booster efficiency
VCI and V CHS = 10 Ohm
No panel loading; 4x booster;
ITO for CYP, CYN, VCIX2 , VCI and
VCHS = 10 Ohm
No panel loading; 5x booster;
Gate driver High Output Voltage
VGH
ITO for CYP, CYN, VCIX2 , VCI and
(2)
Booster efficiency
VCHS = 10 Ohm
No panel loading; 6x booster;
ITO for CYP, CYN, VCIX2 , VCI and
VCHS = 10 Ohm
VGL
Gate driver Low Output Voltage
VCOMH
VCOM High Output Voltage
VCOML
VCOM Low Output Voltage
VCOMA
VCOM Amplitude
VLCD63
VLCD63 Output Voltage
△VLCD63 Max. Source Voltage Variation
VOH1
Logic High Output Voltage
I out = -100μA
VVD
Source Output Voltage Deviation
VOS
Source Output Voltage Offset
VOL1
Logic Low Output Voltage
I out = 100μA
VIH1
Logic High Input voltage
VIL1
Logic Low Input voltage
IOH
Logic High Output Current Source V out = VDD – 0.4V
IOL
Logic Low Output Current Drain
V out = 0.4V
Logic Output Tri-state Current Drain IOZ
Source
IIL/I IH
Logic Input Current
CIN
Logic Pins Input Capacitance
RSON
Source drivers output resistance
RGON
Gate drivers output resistance
RCON
VCOM output resistance
Note : (1) VCIX2 efficiency = VCIX2 / (2 x VCI) x 100%
(2) VGH efficiency = VGH / (VCI x n) x 100% (where n = booster factor)
Min.
Typ.
Max.
Unit
1.8
-
2.50
V
1.8
-
3.6
V
2.5 or
VDDIO
-
3.6
V
- VCI
50
10
-
12
- VCI+0.7
μA
mA
V
83
90
-
％
84
89.5
-
％
80
88.5
-
％
72
80
-
％
- VGH
VCIM+0.5
-2
0.9V DDIO
0
0.8V DDIO
0
50
-
20
-
-5.1
5.54
6
5.57
2
VDD
30
0.1V DDIO
VDDIO
0.2V DDIO
-50
V
V
V
V
V
％
V
mV
mV
V
V
V
μA
μA
-1
-
1
μA
-1
-
5
1
500
200
1
7.5
-
μA
pF
kΩ
Ω
Ω
Table 11. 1 DC Characteristics
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.54November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
12. AC Characteristics
AC Characteristics
(Unless otherwise specified, Voltage Referenced to VSS, VDDIO = 2.2V, T A = 25 ℃)
tvsys
tvsyh
VSYNC
thsys
thsyh
HSYNC
thv
tDOTCLK
DOTCLK
tCKL
tCKH
tds
tdh
Pixel
data
Figure 12. 1 Pixel Timing
Characteristics
Symbol
Min.
24 bit
8 bit
100
33.3
20
10
20
10
20
10
20
10
Typ.
24 bit
6.5
154
-
8 bit
19.5
51.3
-
Max.
24 bit
8 bit
10
30
-
Unit
DOTCLK Frequency
fDOTCLK
MHz
DOTCLK Period
tDOTCLK
ns
Vertical Sync Setup Time
tvsys
ns
Vertical Sync Hold Time
tvsyh
ns
Horizontal Sync Setup Time
thsys
ns
Horizontal Sync Hold Time
thsyh
ns
Phase difference of Sync
thv
1
240
tDOTCLK
Signal Falling Edge
DOTCLK Low Period
tCKL
50
15
ns
DOTCLK High Period
tCKH
50
15
ns
Data Setup Time
tds
12
10
ns
Data hold Time
tdh
12
10
ns
Reset pulse width
tRES
10
us
Note: External clock source must be provided to DOTCLK pin of HX8238-D. The driver will not operate if absent of the
clocking signal.
Table 12. 1 Pixel Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.55November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
H
= 408
cycl
e
tHBP = 68
HDISP = 320
t HFP
=
20
DOTCLK
HSYNC
Pixe
l
Data
D0
Dummy
D1
----------
D 317 D318 D 319
Dummy
a ) Horizontal Data Transaction Timing
V
cycl
e
= 262
Line
s
tVBP = 18
VSYNC
VDISP = 240 Lines
t VFP = 4
HSYNC
Lin
0
e
b )
Lin
e
239
Vertical Data Transaction Timing
Figure 12. 2 Data Transaction Timing in Parallel RGB (24 bit) Interface (SYNC Mode)
Characteristics
Symbol
DOTCLK Frequency
DOTCLK Period
Horizontal Frequency (Line)
Vertical Frequency (Refresh)
Horizontal Back Porch
Horizontal Front Porch
Horizontal Data Start Point
Horizontal Blanking Period
Horizontal Display Area
Horizontal Cycle
Vertical Back Porch
Vertical Front Porch
Vertical Data Start Point
Vertical Blanking Period
NTSC
Vertical Display
Area
PAL
fDOTCLK
tDOTCLK
fH
fV
tHBP
tHFP
tHBP
tHBP + tHFP
HDISP
Hcycle
tVBP
tVFP
tVBP
tVBP + tVFP
Min24 bit
8 bit
100
33.3
-
VDISP
-
Vertical Cycle
NTSC
PAL
Vcycle
-
Typ.
24 bit
6.5
154
8 bit
19.5
51.3
14.9
60
68
20
68
88
320
408
204
60
204
264
960
1224
18
4
18
22
240
280(PALM=0)
288(PALM=1)
262
313
Max.
24 bit
8 bit
10
30
22.35
90
450
1350
-
MHz
ns
KHz
Hz
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
tDOTCLK
Lines
Lines
Lines
Lines
-
Lines
350
Lines
Unit
Table 12. 2 Data Transaction Timing in Normal Operating Mode
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.56November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
H cycle =1224
tHBP = 204
t HFP = 60
HDISP = 960
DOTCLK
HSYNC
Pixel
Data
D0
Dummy
D1
---------- D957 D958 D959
Dummy
a ) Horizontal Data Transaction Timing
V cycle = 262 Lines
t VBP = 18
VSYNC
VDISP = 240 Lines
t VFP = 4
HSYNC
Line 0
b )
Line 239
Vertical Data Transaction Timing
Figure 12. 3 Data Transaction Timing in Serial RGB (8 bit) Interface (SYNC Mode)
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.57November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
240H
1 Period (1 Frame)
Dummy Enable
(3H)
>2H
DOTCKL
DATA[23:0]
1 Horizontal Period
320 dotclk
31~80 dotclk
DOTCLK
DEN
DATA[23:0]
1
2
3
318 319
320
1
Valid Data transfer area
Figure 12. 4 Signal Timing in DE Mode
CM
HSYNC
VSYNC
Color
mode
262k color mode
8 color mode
262k color mode
Note: The color mode conversion starts at the first falling edge of VSYNC after stage change of CM.
Figure 12. 5 Color Mode Conversion Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.58November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
SEL[2:0] = 100, NTSC /PAL
H cycle= 1560
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cr1
Y1
Cb1
Y2
t HBP = HBP[6:0]*4+STP[1:0]
Cr320
Y639
Cb320
Y640
Invalid Data
Cr360
Y719
Cb360
Y720
Invalid Data
Cr360
Y719
Cb360
Y720
Invalid Data
Cb360
Y719
Cr360
Y720
Invalid Data
Cb360
Y719
Cr360
Y720
Invalid Data
Cb320
Y639
Cr320
Y640
Invalid Data
HDISP = 1280
SEL[2:0] = 101, NTSC
H cycle= 1716
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cr1
Y1
Cb1
Y2
t HBP = HBP[6:0]*4+STP[1:0]
HDISP = 1440
SEL[2:0] = 101, PAL
H cycle= 1728
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cr1
Y1
Cb1
Y2
t HBP = HBP[6:0]*4+STP[1:0]
HDISP = 1440
SEL[2:0] = 110, NTSC
H cycle= 1716
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cb1
Y1
Cr1
Y2
t HBP = HBP[6:0]*4+STP[1:0]
HDISP = 1440
SEL[2:0] = 110, PAL
H cycle= 1728
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cb1
Y1
Cr1
Y2
t HBP = HBP[6:0]*4+STP[1:0]
HDISP = 1440
SEL[2:0] = 111, NTSC /PAL
H cycle= 1560
HSYNC
DOTCLK
//
RR[7 :0 ]
//
Invalid Data
Cb1
t HBP = HBP[6:0]*4+STP[1:0]
Y1
Cr1
Y2
HDISP = 1280
Figure 12. 6 CCIR601 Horizontal Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.59November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Figure 12. 7 CCIR601 Vertical Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.60November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Figure 12. 8 CCIR656 Horizontal Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.61November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
SEL[2:0] = 010, 011, NTSC (F=0 è ODD field, F=1 è EVEN field)
H
523 524 525 1
2
3
4
…………
5
19 20 21 22 23 24 25 26
V
F
t VBP = VBP[6:0]
RR[7:0]
DL238 DL239 DL240
H
…………
261 262 263 264 265 266 267 268
282 283 284 285 286 287 288 289
V
F
t VBP = VBP[6:0]
RR[7:0]
DL 1DL 2DL3 DL4
DL239 DL240
SEL[2:0] = 010, 011, PAL, PALM=0 ( F=0 è ODD field, F=1 è EVEN field)
H
618 619 620 621 622 623 624 625
1
2
3
…………
21 22 23 24 25 26 27 28 29 30
V
F
RR[7:0]
t VBP = VBP[6:0]
DL278 DL280
H
305 306 307 308 309 310 311 312 313 314 315
…………
333 334 335 336 337 338 339 340 341 342
V
F
RR[7:0]
t VBP = VBP[6:0] + 1
DL279 DL280
DL1 DL2 DL3
SEL[2:0] = 010, 011, PAL, PALM=1 ( F=0 è ODD field, F=1 è EVEN field)
H
618 619 620 621 622 623 624 625
1
2
3
…………
21 22 23 24 25 26 27 28 29 30
V
F
t VBP = VBP[6:0]
RR[7:0]
DL283 DL284 DL285 DL286 DL287 DL288
H
305 306 307 308 309 310 311 312 313 314 315
…………
333 334 335 336 337 338 339 340 341 342
V
F
t VBP = VBP[6:0] + 1
RR[7:0]
DL283 DL284 DL285 DL286 DL287 DL288
Figure 12. 9 CCIR656 Vertical Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.62November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
VDDIO
VCI
>1ns
>10us
RESB
>10us
SPI
SPI accessing
SHUT
tp-shut
DOTCLK
Tclk-shut
HSYNC
VSYNC
1st
2nd
3rd
4th
5th
VCIX2
VLCD63
VCIM
VGH
VGL
Gate/POL/PWM (If PWM turn-on)
SOUT (S0~S959)
Tshut-on
Figure 12. 10 Power Up Sequence
Characteristics
VDDD / VDDIO on to falling edge of
SHUT
DOTCLK
Falling edge of SHUT to display start
- 1 line: 408 clk
- 1 frame: 262 line
-DOTCLK = 6.5MHz
Symbol
Min.
Typ.
Max.
Unit
tp-shut
1
-
-
us
tclk-shut
1
-
-
14
clk
frame
-
166
232.4
ms
tshut-on
Note: It is necessary to input DOTCLK before the falling edge of SHUT.
Display starts at 10th falling edge of VSTNC after the falling edge of SHUT.
Table 12. 3 Power Up Sequence
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.63November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
V DDIO
V CI
RESB
SPI
SPI accessing
SHUT
DOTCLK
HSYNC
VSYNC
1st
2nd
3rd
4th
5th
6th
VCIX2
Floating
VLCD63
Floating
VCIM
Floating
Floating
VGH
VGL
VGL discharge to ground
Gate/POL/PWM (If PWM turn-on)
SOUT
(S0~S959)
Tshut-off
Figure 12. 11 Power Down Sequence
Characteristics
Rising edge of SHUT to display off
- 1 line: 408 clk
- 1 frame: 262 line
- DOTCLK = 6.5MHz
Symbol
tshut-off
Min.
2
Typ.
-
Max.
-
Unit
frame
33.4
-
-
ms
Note: DOTCLK must be maintained at lease 2 frames after the rising edge of SHUT.
Display become off at the 2nd falling edge of VSTNC after the falling edge of SHUT.
If RESET signal is necessary for power down, provide it after the 2-frames-cycle of the SHUT period.
Table 12. 4 Power Down Sequence
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.64November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
 Write
SPI
Note: The example writes “0x1264h” to register R28h.
SPID connected to VSS.
Figure 12. 12 (a) SPI interface Timing Diagram & Write SPI Example
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.65November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
 Read
SPI
Note: The example Read “0x1264h” from register R28h.
Figure 12. 13 (b) SPI interface Timing Diagram & Read SPI Example
Figure 12. 14 Rising/Falling time
Characteristics
Serial Clock Frequency
Serial Clock Cycle Time
Clock Low Width
Clock High Width
Clock Rising Time
Clock Falling Time
Chip Select Hold Time
Chip Select High Delay Time
Data Setup Time
Data Hold Time
Symbol
fclk
tclk
tsl
tsh
trs
tfl
tcsh
tcsd
tds
tdh
Min.
50
25
25
10
20
5
10
Spec.
Typ.
-
Max.
20
30
30
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 12. 5 SPI Timing
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.66November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
13. HX8238-D Output Voltage Relationship
VGH(9.3~16.5V)
VCIX2
VLCD63 ( MAX 5.57V)
VCOMH ( MAX 5.54V)
VCI (2.5~3.6V)
VSS
VCOML
VCIM
VGL (-5.9~-15V)
Note: The above voltages level assumed 100% efficiency of the internal booster. There has no voltage drop due to
resistance from ITO trace of the panel.
Figure 13. 1 LCD Driving Voltage Relationship
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.67November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
14. Application Circuit
CXP
10 V
CXN
CYP
CYN
C1P
10 V
All capacitors
10 V
C1N
C2P
C2N
C3P
C3N
CP
are ceramic
0.1~0.33uF
25 V
25 V
25 V
CN
Figure 14. 1 Booster Capacitors
Figure 14. 2 Power Supply Pins Connections
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.68November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
Figure 14. 3 Filtering and Charge Sharing Capacitors
(1) Capacitors on VCI should be 4.7uF.
(2) Capacitors on VCIM should be 2.2uF
(3) Capacitors on VCIX2 should be 2.2~4.7uF
(4) Capacitors on VGH, VGL should be 1~4.7uF
(5) Other capacitors should be 1uF
* VCI should be separate with VCIP at ITO layout to provide noise free path
* VSS, VCHS, AVSS, and VSSRC should be separated at ITO layout to provide noise free path
Figure 14. 4 Panel and FPC Connection
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.69November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
960 X 240
TFT Panel
Cs on Common
240
960
QXH
POL
Output to control
Dump driver
Hardware Setting Pins
RR[7:0]
GG[7:0]
BB[7:0]
HSYNC
VSYNC
DOTCLK
DEN
SHUT
CM
BGR
REV
SWD
SEL
CPE
TB
RL
SPSW
MCU serial interface
and control
VCOM
RESB
CSB
SCK
SDI
SDO
External
Component
pins
S0-S959
Refer to
figure 16.1~16.4
Power/Ground
VCI/VCIP/VCIX2J
VSS/AVSS
VSSRC/VCHS
VDD/VDDIO
G0-G239
Figure 14. 5 Panel Connection Example
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.70November, 2007
HX8238-D
960x 240 TFT LCD Single Chip Digital Driver
DATA SHEET Preliminary V01
15. Revision History
Version
01
Date
2007/11/08
Description of Changes
New setup
Himax Confidential
This information contained herein is the exclusive property of Himax and shell not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.
-P.71November, 2007